Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.10 97.65 100.00 98.38 100.00 99.53


Total test records in report: 1222
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T1035 /workspace/coverage/default/39.uart_alert_test.2727846375 Jun 25 05:14:59 PM PDT 24 Jun 25 05:15:00 PM PDT 24 36642662 ps
T1036 /workspace/coverage/default/2.uart_stress_all_with_rand_reset.1742979771 Jun 25 05:12:34 PM PDT 24 Jun 25 05:29:25 PM PDT 24 84174126454 ps
T1037 /workspace/coverage/default/42.uart_loopback.334417470 Jun 25 05:15:11 PM PDT 24 Jun 25 05:15:15 PM PDT 24 2842085611 ps
T208 /workspace/coverage/default/68.uart_fifo_reset.549711439 Jun 25 05:15:54 PM PDT 24 Jun 25 05:16:35 PM PDT 24 102071202144 ps
T217 /workspace/coverage/default/18.uart_fifo_reset.2316721667 Jun 25 05:13:27 PM PDT 24 Jun 25 05:14:25 PM PDT 24 29915831801 ps
T1038 /workspace/coverage/default/35.uart_alert_test.2057648159 Jun 25 05:14:43 PM PDT 24 Jun 25 05:14:45 PM PDT 24 32700917 ps
T1039 /workspace/coverage/default/11.uart_rx_parity_err.3446760383 Jun 25 05:13:00 PM PDT 24 Jun 25 05:14:24 PM PDT 24 200757038500 ps
T1040 /workspace/coverage/default/35.uart_smoke.1301855477 Jun 25 05:14:43 PM PDT 24 Jun 25 05:14:47 PM PDT 24 250302933 ps
T1041 /workspace/coverage/default/2.uart_tx_rx.3558983750 Jun 25 05:12:43 PM PDT 24 Jun 25 05:12:56 PM PDT 24 12879735471 ps
T1042 /workspace/coverage/default/10.uart_rx_start_bit_filter.788806007 Jun 25 05:13:03 PM PDT 24 Jun 25 05:13:12 PM PDT 24 4670850705 ps
T1043 /workspace/coverage/default/12.uart_fifo_full.857512426 Jun 25 05:13:10 PM PDT 24 Jun 25 05:13:26 PM PDT 24 54129557576 ps
T1044 /workspace/coverage/default/6.uart_perf.2061366079 Jun 25 05:12:42 PM PDT 24 Jun 25 05:16:02 PM PDT 24 16737571111 ps
T1045 /workspace/coverage/default/20.uart_intr.1150706301 Jun 25 05:13:40 PM PDT 24 Jun 25 05:14:40 PM PDT 24 35529785271 ps
T1046 /workspace/coverage/default/38.uart_fifo_full.2852621396 Jun 25 05:14:51 PM PDT 24 Jun 25 05:15:58 PM PDT 24 187198899188 ps
T1047 /workspace/coverage/default/37.uart_stress_all_with_rand_reset.1081370988 Jun 25 05:14:50 PM PDT 24 Jun 25 05:51:10 PM PDT 24 125229439556 ps
T1048 /workspace/coverage/default/10.uart_long_xfer_wo_dly.1010366285 Jun 25 05:13:03 PM PDT 24 Jun 25 05:15:07 PM PDT 24 160111644722 ps
T1049 /workspace/coverage/default/66.uart_stress_all_with_rand_reset.751794214 Jun 25 05:15:55 PM PDT 24 Jun 25 05:23:51 PM PDT 24 280342641200 ps
T1050 /workspace/coverage/default/288.uart_fifo_reset.3918291758 Jun 25 05:17:25 PM PDT 24 Jun 25 05:18:44 PM PDT 24 47910770019 ps
T1051 /workspace/coverage/default/49.uart_intr.668129606 Jun 25 05:15:48 PM PDT 24 Jun 25 05:16:48 PM PDT 24 72071349758 ps
T1052 /workspace/coverage/default/13.uart_intr.1918030170 Jun 25 05:13:13 PM PDT 24 Jun 25 05:13:31 PM PDT 24 63585950338 ps
T1053 /workspace/coverage/default/19.uart_tx_ovrd.2146577184 Jun 25 05:13:38 PM PDT 24 Jun 25 05:13:42 PM PDT 24 1592026565 ps
T1054 /workspace/coverage/default/0.uart_stress_all.2937937459 Jun 25 05:12:24 PM PDT 24 Jun 25 05:13:47 PM PDT 24 85277707795 ps
T1055 /workspace/coverage/default/19.uart_fifo_reset.2765466180 Jun 25 05:13:38 PM PDT 24 Jun 25 05:15:34 PM PDT 24 78928636914 ps
T1056 /workspace/coverage/default/89.uart_fifo_reset.2475715859 Jun 25 05:16:10 PM PDT 24 Jun 25 05:16:34 PM PDT 24 15405132726 ps
T1057 /workspace/coverage/default/12.uart_rx_oversample.3754655108 Jun 25 05:13:10 PM PDT 24 Jun 25 05:13:37 PM PDT 24 3701213729 ps
T1058 /workspace/coverage/default/110.uart_fifo_reset.1109266384 Jun 25 05:16:21 PM PDT 24 Jun 25 05:19:23 PM PDT 24 181510036110 ps
T1059 /workspace/coverage/default/5.uart_intr.3769047552 Jun 25 05:12:42 PM PDT 24 Jun 25 05:12:51 PM PDT 24 5354117687 ps
T1060 /workspace/coverage/default/39.uart_stress_all_with_rand_reset.3963201234 Jun 25 05:15:03 PM PDT 24 Jun 25 05:16:37 PM PDT 24 21250346903 ps
T234 /workspace/coverage/default/197.uart_fifo_reset.2356836734 Jun 25 05:16:46 PM PDT 24 Jun 25 05:18:43 PM PDT 24 121662382809 ps
T1061 /workspace/coverage/default/17.uart_perf.764436075 Jun 25 05:13:30 PM PDT 24 Jun 25 05:20:11 PM PDT 24 14866272768 ps
T1062 /workspace/coverage/default/40.uart_rx_oversample.4250640546 Jun 25 05:15:02 PM PDT 24 Jun 25 05:15:22 PM PDT 24 7278924410 ps
T1063 /workspace/coverage/default/21.uart_perf.1418250222 Jun 25 05:13:46 PM PDT 24 Jun 25 05:22:36 PM PDT 24 14552112064 ps
T1064 /workspace/coverage/default/17.uart_intr.1490088098 Jun 25 05:13:27 PM PDT 24 Jun 25 05:13:45 PM PDT 24 26461640594 ps
T1065 /workspace/coverage/default/27.uart_rx_parity_err.1402941763 Jun 25 05:14:12 PM PDT 24 Jun 25 05:14:33 PM PDT 24 21396557129 ps
T1066 /workspace/coverage/default/62.uart_stress_all_with_rand_reset.2763700688 Jun 25 05:15:54 PM PDT 24 Jun 25 05:23:36 PM PDT 24 286482463405 ps
T1067 /workspace/coverage/default/17.uart_tx_rx.2131795252 Jun 25 05:13:27 PM PDT 24 Jun 25 05:14:39 PM PDT 24 108109382448 ps
T1068 /workspace/coverage/default/31.uart_smoke.2289114264 Jun 25 05:14:20 PM PDT 24 Jun 25 05:14:23 PM PDT 24 676217370 ps
T1069 /workspace/coverage/default/264.uart_fifo_reset.675724651 Jun 25 05:17:22 PM PDT 24 Jun 25 05:24:38 PM PDT 24 286955388410 ps
T1070 /workspace/coverage/default/36.uart_rx_start_bit_filter.3350811657 Jun 25 05:14:53 PM PDT 24 Jun 25 05:14:58 PM PDT 24 2101463486 ps
T1071 /workspace/coverage/default/289.uart_fifo_reset.607365531 Jun 25 05:17:23 PM PDT 24 Jun 25 05:17:49 PM PDT 24 14990515882 ps
T1072 /workspace/coverage/default/49.uart_perf.244150658 Jun 25 05:15:49 PM PDT 24 Jun 25 05:21:04 PM PDT 24 9779316306 ps
T1073 /workspace/coverage/default/35.uart_fifo_full.3755826579 Jun 25 05:14:41 PM PDT 24 Jun 25 05:15:03 PM PDT 24 48865383008 ps
T1074 /workspace/coverage/default/3.uart_intr.2761343141 Jun 25 05:12:33 PM PDT 24 Jun 25 05:13:55 PM PDT 24 220886921072 ps
T1075 /workspace/coverage/default/30.uart_smoke.2069744351 Jun 25 05:14:25 PM PDT 24 Jun 25 05:14:28 PM PDT 24 502045003 ps
T1076 /workspace/coverage/default/6.uart_rx_start_bit_filter.2662486647 Jun 25 05:12:42 PM PDT 24 Jun 25 05:12:53 PM PDT 24 5298649836 ps
T1077 /workspace/coverage/default/278.uart_fifo_reset.381053010 Jun 25 05:17:16 PM PDT 24 Jun 25 05:18:02 PM PDT 24 24296084790 ps
T1078 /workspace/coverage/default/24.uart_rx_start_bit_filter.3309620250 Jun 25 05:13:55 PM PDT 24 Jun 25 05:13:57 PM PDT 24 688091757 ps
T1079 /workspace/coverage/default/78.uart_stress_all_with_rand_reset.1563650284 Jun 25 05:16:14 PM PDT 24 Jun 25 05:24:58 PM PDT 24 55372390272 ps
T1080 /workspace/coverage/default/8.uart_smoke.3838841016 Jun 25 05:12:58 PM PDT 24 Jun 25 05:13:04 PM PDT 24 695476081 ps
T1081 /workspace/coverage/default/6.uart_rx_parity_err.1436041500 Jun 25 05:12:45 PM PDT 24 Jun 25 05:13:18 PM PDT 24 86032097809 ps
T1082 /workspace/coverage/default/259.uart_fifo_reset.3243652328 Jun 25 05:17:16 PM PDT 24 Jun 25 05:17:34 PM PDT 24 72131217458 ps
T1083 /workspace/coverage/default/10.uart_fifo_overflow.1251461971 Jun 25 05:12:55 PM PDT 24 Jun 25 05:16:37 PM PDT 24 137281703505 ps
T1084 /workspace/coverage/default/18.uart_noise_filter.4097820832 Jun 25 05:13:28 PM PDT 24 Jun 25 05:13:43 PM PDT 24 7895880545 ps
T1085 /workspace/coverage/default/43.uart_alert_test.2466921085 Jun 25 05:15:18 PM PDT 24 Jun 25 05:15:20 PM PDT 24 19484453 ps
T1086 /workspace/coverage/default/7.uart_fifo_reset.584226138 Jun 25 05:12:55 PM PDT 24 Jun 25 05:13:52 PM PDT 24 31247424895 ps
T1087 /workspace/coverage/default/26.uart_rx_parity_err.795849687 Jun 25 05:14:01 PM PDT 24 Jun 25 05:14:13 PM PDT 24 28367606235 ps
T1088 /workspace/coverage/default/116.uart_fifo_reset.3677068658 Jun 25 05:16:18 PM PDT 24 Jun 25 05:16:31 PM PDT 24 6238622701 ps
T1089 /workspace/coverage/cover_reg_top/14.uart_tl_errors.1704708014 Jun 25 06:01:18 PM PDT 24 Jun 25 06:01:20 PM PDT 24 27580323 ps
T1090 /workspace/coverage/cover_reg_top/31.uart_intr_test.670373080 Jun 25 06:01:42 PM PDT 24 Jun 25 06:01:45 PM PDT 24 17688963 ps
T1091 /workspace/coverage/cover_reg_top/34.uart_intr_test.2004436853 Jun 25 06:01:46 PM PDT 24 Jun 25 06:01:47 PM PDT 24 65684050 ps
T70 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2739917756 Jun 25 06:01:30 PM PDT 24 Jun 25 06:01:33 PM PDT 24 31997171 ps
T1092 /workspace/coverage/cover_reg_top/47.uart_intr_test.110263744 Jun 25 06:01:38 PM PDT 24 Jun 25 06:01:40 PM PDT 24 15091141 ps
T81 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3439258055 Jun 25 06:01:03 PM PDT 24 Jun 25 06:01:06 PM PDT 24 352925366 ps
T1093 /workspace/coverage/cover_reg_top/27.uart_intr_test.240687329 Jun 25 06:01:41 PM PDT 24 Jun 25 06:01:44 PM PDT 24 50025271 ps
T82 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2946434417 Jun 25 06:00:54 PM PDT 24 Jun 25 06:00:56 PM PDT 24 269540941 ps
T71 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1014928923 Jun 25 06:01:03 PM PDT 24 Jun 25 06:01:05 PM PDT 24 26218791 ps
T72 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2141907996 Jun 25 06:01:03 PM PDT 24 Jun 25 06:01:05 PM PDT 24 12562828 ps
T83 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.112398387 Jun 25 06:01:04 PM PDT 24 Jun 25 06:01:07 PM PDT 24 49203908 ps
T1094 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.834243523 Jun 25 06:01:10 PM PDT 24 Jun 25 06:01:12 PM PDT 24 101129029 ps
T73 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.83123837 Jun 25 06:01:02 PM PDT 24 Jun 25 06:01:04 PM PDT 24 45066961 ps
T1095 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3374073065 Jun 25 06:00:47 PM PDT 24 Jun 25 06:00:48 PM PDT 24 35668187 ps
T1096 /workspace/coverage/cover_reg_top/7.uart_tl_errors.3718889186 Jun 25 06:01:02 PM PDT 24 Jun 25 06:01:06 PM PDT 24 63523513 ps
T1097 /workspace/coverage/cover_reg_top/19.uart_intr_test.3430396861 Jun 25 06:01:41 PM PDT 24 Jun 25 06:01:44 PM PDT 24 23933997 ps
T1098 /workspace/coverage/cover_reg_top/12.uart_tl_errors.3977523139 Jun 25 06:01:19 PM PDT 24 Jun 25 06:01:22 PM PDT 24 28278924 ps
T88 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1883826589 Jun 25 06:01:28 PM PDT 24 Jun 25 06:01:31 PM PDT 24 40002023 ps
T1099 /workspace/coverage/cover_reg_top/41.uart_intr_test.1501311630 Jun 25 06:01:41 PM PDT 24 Jun 25 06:01:44 PM PDT 24 42265866 ps
T1100 /workspace/coverage/cover_reg_top/5.uart_tl_errors.4163742008 Jun 25 06:01:02 PM PDT 24 Jun 25 06:01:05 PM PDT 24 198630475 ps
T74 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2468698448 Jun 25 06:00:57 PM PDT 24 Jun 25 06:00:59 PM PDT 24 44628167 ps
T58 /workspace/coverage/cover_reg_top/8.uart_csr_rw.2966038960 Jun 25 06:01:09 PM PDT 24 Jun 25 06:01:11 PM PDT 24 14695808 ps
T1101 /workspace/coverage/cover_reg_top/15.uart_tl_errors.398533797 Jun 25 06:01:19 PM PDT 24 Jun 25 06:01:23 PM PDT 24 99722456 ps
T1102 /workspace/coverage/cover_reg_top/42.uart_intr_test.2486485708 Jun 25 06:01:44 PM PDT 24 Jun 25 06:01:46 PM PDT 24 19789342 ps
T59 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.975163865 Jun 25 06:00:54 PM PDT 24 Jun 25 06:00:56 PM PDT 24 53355353 ps
T1103 /workspace/coverage/cover_reg_top/19.uart_tl_errors.3068394531 Jun 25 06:01:31 PM PDT 24 Jun 25 06:01:34 PM PDT 24 89196489 ps
T1104 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1180965397 Jun 25 06:01:17 PM PDT 24 Jun 25 06:01:19 PM PDT 24 20959625 ps
T1105 /workspace/coverage/cover_reg_top/45.uart_intr_test.2391031956 Jun 25 06:01:39 PM PDT 24 Jun 25 06:01:40 PM PDT 24 100341532 ps
T75 /workspace/coverage/cover_reg_top/16.uart_csr_rw.3096548736 Jun 25 06:01:27 PM PDT 24 Jun 25 06:01:29 PM PDT 24 29383993 ps
T76 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.614741763 Jun 25 06:01:30 PM PDT 24 Jun 25 06:01:33 PM PDT 24 40184874 ps
T77 /workspace/coverage/cover_reg_top/1.uart_csr_rw.1506629240 Jun 25 06:00:54 PM PDT 24 Jun 25 06:00:56 PM PDT 24 52157396 ps
T78 /workspace/coverage/cover_reg_top/14.uart_csr_rw.1715733830 Jun 25 06:01:19 PM PDT 24 Jun 25 06:01:21 PM PDT 24 50156126 ps
T1106 /workspace/coverage/cover_reg_top/24.uart_intr_test.3088641715 Jun 25 06:01:40 PM PDT 24 Jun 25 06:01:43 PM PDT 24 38795234 ps
T1107 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.436269313 Jun 25 06:01:02 PM PDT 24 Jun 25 06:01:04 PM PDT 24 30689525 ps
T85 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3964054682 Jun 25 06:01:10 PM PDT 24 Jun 25 06:01:13 PM PDT 24 825556715 ps
T1108 /workspace/coverage/cover_reg_top/7.uart_intr_test.2376574564 Jun 25 06:01:07 PM PDT 24 Jun 25 06:01:09 PM PDT 24 10964525 ps
T1109 /workspace/coverage/cover_reg_top/1.uart_intr_test.3345025072 Jun 25 06:00:53 PM PDT 24 Jun 25 06:00:55 PM PDT 24 14295469 ps
T1110 /workspace/coverage/cover_reg_top/13.uart_tl_errors.428670208 Jun 25 06:01:19 PM PDT 24 Jun 25 06:01:23 PM PDT 24 122615577 ps
T1111 /workspace/coverage/cover_reg_top/36.uart_intr_test.541392834 Jun 25 06:01:40 PM PDT 24 Jun 25 06:01:43 PM PDT 24 21217763 ps
T60 /workspace/coverage/cover_reg_top/18.uart_csr_rw.903951653 Jun 25 06:01:30 PM PDT 24 Jun 25 06:01:32 PM PDT 24 105610700 ps
T61 /workspace/coverage/cover_reg_top/19.uart_csr_rw.3736428109 Jun 25 06:01:39 PM PDT 24 Jun 25 06:01:41 PM PDT 24 67004358 ps
T1112 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3934296090 Jun 25 06:01:20 PM PDT 24 Jun 25 06:01:22 PM PDT 24 60688850 ps
T1113 /workspace/coverage/cover_reg_top/2.uart_intr_test.1448134874 Jun 25 06:00:57 PM PDT 24 Jun 25 06:00:59 PM PDT 24 28545717 ps
T111 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.290908824 Jun 25 06:01:21 PM PDT 24 Jun 25 06:01:24 PM PDT 24 134985422 ps
T1114 /workspace/coverage/cover_reg_top/9.uart_tl_errors.2330297991 Jun 25 06:01:10 PM PDT 24 Jun 25 06:01:14 PM PDT 24 37612991 ps
T1115 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3233504260 Jun 25 06:01:11 PM PDT 24 Jun 25 06:01:13 PM PDT 24 33310922 ps
T1116 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2422964212 Jun 25 06:00:53 PM PDT 24 Jun 25 06:00:55 PM PDT 24 67493804 ps
T1117 /workspace/coverage/cover_reg_top/17.uart_csr_rw.699448415 Jun 25 06:01:29 PM PDT 24 Jun 25 06:01:31 PM PDT 24 13973150 ps
T1118 /workspace/coverage/cover_reg_top/37.uart_intr_test.1975120022 Jun 25 06:01:42 PM PDT 24 Jun 25 06:01:45 PM PDT 24 69316748 ps
T1119 /workspace/coverage/cover_reg_top/11.uart_tl_errors.4037279425 Jun 25 06:01:08 PM PDT 24 Jun 25 06:01:11 PM PDT 24 130705236 ps
T1120 /workspace/coverage/cover_reg_top/0.uart_tl_errors.1640410754 Jun 25 06:00:46 PM PDT 24 Jun 25 06:00:49 PM PDT 24 284837197 ps
T1121 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1560407437 Jun 25 06:01:30 PM PDT 24 Jun 25 06:01:33 PM PDT 24 167719553 ps
T84 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3837490083 Jun 25 06:01:19 PM PDT 24 Jun 25 06:01:21 PM PDT 24 183944027 ps
T68 /workspace/coverage/cover_reg_top/7.uart_csr_rw.1998641143 Jun 25 06:01:09 PM PDT 24 Jun 25 06:01:10 PM PDT 24 33511600 ps
T1122 /workspace/coverage/cover_reg_top/2.uart_tl_errors.4024436116 Jun 25 06:00:54 PM PDT 24 Jun 25 06:00:57 PM PDT 24 72508254 ps
T1123 /workspace/coverage/cover_reg_top/5.uart_csr_rw.3788221850 Jun 25 06:01:04 PM PDT 24 Jun 25 06:01:06 PM PDT 24 13073507 ps
T1124 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2647425571 Jun 25 06:00:53 PM PDT 24 Jun 25 06:00:55 PM PDT 24 31936643 ps
T62 /workspace/coverage/cover_reg_top/6.uart_csr_rw.1043400174 Jun 25 06:01:01 PM PDT 24 Jun 25 06:01:03 PM PDT 24 11839098 ps
T1125 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3091940438 Jun 25 06:01:02 PM PDT 24 Jun 25 06:01:05 PM PDT 24 33866719 ps
T1126 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.166904486 Jun 25 06:01:19 PM PDT 24 Jun 25 06:01:22 PM PDT 24 18472259 ps
T86 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2505305949 Jun 25 06:01:09 PM PDT 24 Jun 25 06:01:11 PM PDT 24 48834034 ps
T1127 /workspace/coverage/cover_reg_top/3.uart_tl_errors.2445086468 Jun 25 06:01:02 PM PDT 24 Jun 25 06:01:05 PM PDT 24 290511990 ps
T1128 /workspace/coverage/cover_reg_top/39.uart_intr_test.343682748 Jun 25 06:01:40 PM PDT 24 Jun 25 06:01:43 PM PDT 24 32524138 ps
T1129 /workspace/coverage/cover_reg_top/9.uart_intr_test.2050406031 Jun 25 06:01:14 PM PDT 24 Jun 25 06:01:16 PM PDT 24 34637044 ps
T63 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.329758212 Jun 25 06:00:52 PM PDT 24 Jun 25 06:00:54 PM PDT 24 42731174 ps
T1130 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1379277815 Jun 25 06:01:29 PM PDT 24 Jun 25 06:01:32 PM PDT 24 37664248 ps
T1131 /workspace/coverage/cover_reg_top/21.uart_intr_test.199063432 Jun 25 06:01:40 PM PDT 24 Jun 25 06:01:43 PM PDT 24 13607037 ps
T1132 /workspace/coverage/cover_reg_top/44.uart_intr_test.1854292130 Jun 25 06:01:39 PM PDT 24 Jun 25 06:01:40 PM PDT 24 13904208 ps
T1133 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2071960541 Jun 25 06:01:32 PM PDT 24 Jun 25 06:01:34 PM PDT 24 68176050 ps
T1134 /workspace/coverage/cover_reg_top/12.uart_intr_test.1572312914 Jun 25 06:01:19 PM PDT 24 Jun 25 06:01:21 PM PDT 24 37279052 ps
T69 /workspace/coverage/cover_reg_top/2.uart_csr_rw.1674812917 Jun 25 06:00:53 PM PDT 24 Jun 25 06:00:55 PM PDT 24 38926164 ps
T1135 /workspace/coverage/cover_reg_top/16.uart_intr_test.2305050051 Jun 25 06:01:30 PM PDT 24 Jun 25 06:01:32 PM PDT 24 36423879 ps
T64 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2554801354 Jun 25 06:00:54 PM PDT 24 Jun 25 06:00:58 PM PDT 24 59441997 ps
T1136 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1206685429 Jun 25 06:01:17 PM PDT 24 Jun 25 06:01:19 PM PDT 24 181754933 ps
T1137 /workspace/coverage/cover_reg_top/25.uart_intr_test.963135782 Jun 25 06:01:40 PM PDT 24 Jun 25 06:01:43 PM PDT 24 116749976 ps
T89 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.841772778 Jun 25 06:01:03 PM PDT 24 Jun 25 06:01:06 PM PDT 24 250351948 ps
T1138 /workspace/coverage/cover_reg_top/1.uart_tl_errors.2030023527 Jun 25 06:00:55 PM PDT 24 Jun 25 06:00:58 PM PDT 24 37748144 ps
T1139 /workspace/coverage/cover_reg_top/46.uart_intr_test.1710627368 Jun 25 06:01:39 PM PDT 24 Jun 25 06:01:41 PM PDT 24 28779951 ps
T1140 /workspace/coverage/cover_reg_top/28.uart_intr_test.2862693160 Jun 25 06:01:41 PM PDT 24 Jun 25 06:01:45 PM PDT 24 60800614 ps
T1141 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3104099742 Jun 25 06:01:10 PM PDT 24 Jun 25 06:01:12 PM PDT 24 89550621 ps
T1142 /workspace/coverage/cover_reg_top/18.uart_tl_errors.964140762 Jun 25 06:01:29 PM PDT 24 Jun 25 06:01:33 PM PDT 24 142736625 ps
T1143 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2365843635 Jun 25 06:01:00 PM PDT 24 Jun 25 06:01:04 PM PDT 24 683758298 ps
T1144 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.4136484426 Jun 25 06:01:03 PM PDT 24 Jun 25 06:01:05 PM PDT 24 32118157 ps
T1145 /workspace/coverage/cover_reg_top/10.uart_intr_test.3421799346 Jun 25 06:01:11 PM PDT 24 Jun 25 06:01:13 PM PDT 24 39158488 ps
T1146 /workspace/coverage/cover_reg_top/3.uart_intr_test.2987357173 Jun 25 06:01:02 PM PDT 24 Jun 25 06:01:03 PM PDT 24 72597780 ps
T87 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1725236426 Jun 25 06:01:18 PM PDT 24 Jun 25 06:01:20 PM PDT 24 157738558 ps
T1147 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2980618358 Jun 25 06:01:18 PM PDT 24 Jun 25 06:01:21 PM PDT 24 190911682 ps
T1148 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3546666130 Jun 25 06:01:20 PM PDT 24 Jun 25 06:01:23 PM PDT 24 42570928 ps
T1149 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3042435489 Jun 25 06:01:29 PM PDT 24 Jun 25 06:01:32 PM PDT 24 193946889 ps
T1150 /workspace/coverage/cover_reg_top/0.uart_csr_rw.2138969478 Jun 25 06:00:47 PM PDT 24 Jun 25 06:00:49 PM PDT 24 22307711 ps
T1151 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.28205037 Jun 25 06:01:03 PM PDT 24 Jun 25 06:01:05 PM PDT 24 41537459 ps
T1152 /workspace/coverage/cover_reg_top/4.uart_csr_rw.2781850724 Jun 25 06:01:03 PM PDT 24 Jun 25 06:01:05 PM PDT 24 14489148 ps
T1153 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2153678020 Jun 25 06:00:53 PM PDT 24 Jun 25 06:00:56 PM PDT 24 58618740 ps
T1154 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.620944222 Jun 25 06:01:12 PM PDT 24 Jun 25 06:01:14 PM PDT 24 326889228 ps
T1155 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3280974863 Jun 25 06:01:10 PM PDT 24 Jun 25 06:01:12 PM PDT 24 36053361 ps
T1156 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2091316151 Jun 25 06:00:47 PM PDT 24 Jun 25 06:00:49 PM PDT 24 100046726 ps
T1157 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.4235125289 Jun 25 06:01:01 PM PDT 24 Jun 25 06:01:05 PM PDT 24 1872574298 ps
T1158 /workspace/coverage/cover_reg_top/10.uart_tl_errors.497288499 Jun 25 06:01:10 PM PDT 24 Jun 25 06:01:13 PM PDT 24 269842396 ps
T1159 /workspace/coverage/cover_reg_top/10.uart_csr_rw.3663942714 Jun 25 06:01:08 PM PDT 24 Jun 25 06:01:10 PM PDT 24 51007038 ps
T1160 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.731095378 Jun 25 06:01:02 PM PDT 24 Jun 25 06:01:05 PM PDT 24 267316953 ps
T1161 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2384625229 Jun 25 06:00:55 PM PDT 24 Jun 25 06:00:58 PM PDT 24 164035809 ps
T65 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1288070076 Jun 25 06:01:07 PM PDT 24 Jun 25 06:01:09 PM PDT 24 19147487 ps
T1162 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1693639265 Jun 25 06:01:29 PM PDT 24 Jun 25 06:01:32 PM PDT 24 210542965 ps
T1163 /workspace/coverage/cover_reg_top/22.uart_intr_test.1341989566 Jun 25 06:01:40 PM PDT 24 Jun 25 06:01:43 PM PDT 24 16584552 ps
T1164 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.786996175 Jun 25 06:01:19 PM PDT 24 Jun 25 06:01:22 PM PDT 24 69015758 ps
T1165 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.4124097712 Jun 25 06:01:31 PM PDT 24 Jun 25 06:01:34 PM PDT 24 821419502 ps
T1166 /workspace/coverage/cover_reg_top/6.uart_tl_errors.4092241393 Jun 25 06:01:04 PM PDT 24 Jun 25 06:01:08 PM PDT 24 261528987 ps
T1167 /workspace/coverage/cover_reg_top/29.uart_intr_test.2941330561 Jun 25 06:01:40 PM PDT 24 Jun 25 06:01:44 PM PDT 24 41808863 ps
T1168 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.469637322 Jun 25 06:01:31 PM PDT 24 Jun 25 06:01:34 PM PDT 24 85946340 ps
T1169 /workspace/coverage/cover_reg_top/13.uart_csr_rw.2432945255 Jun 25 06:01:17 PM PDT 24 Jun 25 06:01:18 PM PDT 24 34178853 ps
T1170 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3836558932 Jun 25 06:01:02 PM PDT 24 Jun 25 06:01:04 PM PDT 24 49677259 ps
T1171 /workspace/coverage/cover_reg_top/30.uart_intr_test.3821559669 Jun 25 06:01:39 PM PDT 24 Jun 25 06:01:41 PM PDT 24 15507235 ps
T1172 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3438828830 Jun 25 06:00:53 PM PDT 24 Jun 25 06:00:54 PM PDT 24 14474533 ps
T1173 /workspace/coverage/cover_reg_top/13.uart_intr_test.3526786105 Jun 25 06:01:18 PM PDT 24 Jun 25 06:01:21 PM PDT 24 14252536 ps
T1174 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.391512781 Jun 25 06:01:37 PM PDT 24 Jun 25 06:01:38 PM PDT 24 100283527 ps
T1175 /workspace/coverage/cover_reg_top/20.uart_intr_test.3545144837 Jun 25 06:01:40 PM PDT 24 Jun 25 06:01:42 PM PDT 24 61451818 ps
T1176 /workspace/coverage/cover_reg_top/15.uart_intr_test.1278838419 Jun 25 06:01:30 PM PDT 24 Jun 25 06:01:32 PM PDT 24 15233317 ps
T1177 /workspace/coverage/cover_reg_top/6.uart_intr_test.855873025 Jun 25 06:01:01 PM PDT 24 Jun 25 06:01:03 PM PDT 24 13332954 ps
T1178 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3087716893 Jun 25 06:01:17 PM PDT 24 Jun 25 06:01:19 PM PDT 24 271363939 ps
T1179 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2880521613 Jun 25 06:01:04 PM PDT 24 Jun 25 06:01:07 PM PDT 24 37005319 ps
T1180 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.183647636 Jun 25 06:00:55 PM PDT 24 Jun 25 06:00:57 PM PDT 24 191198698 ps
T1181 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.257052784 Jun 25 06:01:08 PM PDT 24 Jun 25 06:01:10 PM PDT 24 17630361 ps
T1182 /workspace/coverage/cover_reg_top/17.uart_intr_test.3988535359 Jun 25 06:01:31 PM PDT 24 Jun 25 06:01:33 PM PDT 24 50518171 ps
T1183 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.355720576 Jun 25 06:01:21 PM PDT 24 Jun 25 06:01:24 PM PDT 24 87723025 ps
T1184 /workspace/coverage/cover_reg_top/26.uart_intr_test.1965371749 Jun 25 06:01:40 PM PDT 24 Jun 25 06:01:44 PM PDT 24 27648035 ps
T1185 /workspace/coverage/cover_reg_top/4.uart_intr_test.987844602 Jun 25 06:01:04 PM PDT 24 Jun 25 06:01:07 PM PDT 24 47213299 ps
T1186 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1709746736 Jun 25 06:01:07 PM PDT 24 Jun 25 06:01:09 PM PDT 24 111885819 ps
T1187 /workspace/coverage/cover_reg_top/43.uart_intr_test.3721588805 Jun 25 06:01:41 PM PDT 24 Jun 25 06:01:44 PM PDT 24 72433392 ps
T1188 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.16659727 Jun 25 06:01:03 PM PDT 24 Jun 25 06:01:05 PM PDT 24 468455046 ps
T1189 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.558486436 Jun 25 06:01:02 PM PDT 24 Jun 25 06:01:05 PM PDT 24 20538485 ps
T1190 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.259251823 Jun 25 06:01:12 PM PDT 24 Jun 25 06:01:14 PM PDT 24 203230549 ps
T1191 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3457431548 Jun 25 06:00:51 PM PDT 24 Jun 25 06:00:53 PM PDT 24 113651319 ps
T1192 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3734810460 Jun 25 06:01:06 PM PDT 24 Jun 25 06:01:08 PM PDT 24 15486648 ps
T1193 /workspace/coverage/cover_reg_top/16.uart_tl_errors.1530973201 Jun 25 06:01:30 PM PDT 24 Jun 25 06:01:33 PM PDT 24 67139537 ps
T1194 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.712759028 Jun 25 06:01:29 PM PDT 24 Jun 25 06:01:32 PM PDT 24 48333793 ps
T66 /workspace/coverage/cover_reg_top/15.uart_csr_rw.1447568965 Jun 25 06:01:29 PM PDT 24 Jun 25 06:01:32 PM PDT 24 48385412 ps
T1195 /workspace/coverage/cover_reg_top/35.uart_intr_test.3619697455 Jun 25 06:01:42 PM PDT 24 Jun 25 06:01:45 PM PDT 24 47517266 ps
T1196 /workspace/coverage/cover_reg_top/12.uart_csr_rw.3137036703 Jun 25 06:01:18 PM PDT 24 Jun 25 06:01:20 PM PDT 24 28149688 ps
T1197 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1519088541 Jun 25 06:01:09 PM PDT 24 Jun 25 06:01:11 PM PDT 24 60259462 ps
T1198 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3774347634 Jun 25 06:01:40 PM PDT 24 Jun 25 06:01:43 PM PDT 24 91977213 ps
T1199 /workspace/coverage/cover_reg_top/0.uart_intr_test.3843292692 Jun 25 06:00:46 PM PDT 24 Jun 25 06:00:47 PM PDT 24 16076262 ps
T1200 /workspace/coverage/cover_reg_top/33.uart_intr_test.4038374740 Jun 25 06:01:40 PM PDT 24 Jun 25 06:01:43 PM PDT 24 19875501 ps
T1201 /workspace/coverage/cover_reg_top/32.uart_intr_test.2712078489 Jun 25 06:01:41 PM PDT 24 Jun 25 06:01:44 PM PDT 24 64727167 ps
T1202 /workspace/coverage/cover_reg_top/49.uart_intr_test.4100186724 Jun 25 06:01:39 PM PDT 24 Jun 25 06:01:41 PM PDT 24 24518383 ps
T1203 /workspace/coverage/cover_reg_top/23.uart_intr_test.2580642576 Jun 25 06:01:40 PM PDT 24 Jun 25 06:01:42 PM PDT 24 29950749 ps
T1204 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.487317489 Jun 25 06:00:54 PM PDT 24 Jun 25 06:00:58 PM PDT 24 222825321 ps
T1205 /workspace/coverage/cover_reg_top/8.uart_tl_errors.4026861201 Jun 25 06:01:15 PM PDT 24 Jun 25 06:01:17 PM PDT 24 251528015 ps
T1206 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2039289086 Jun 25 06:01:01 PM PDT 24 Jun 25 06:01:03 PM PDT 24 55754702 ps
T1207 /workspace/coverage/cover_reg_top/8.uart_intr_test.2014397645 Jun 25 06:01:10 PM PDT 24 Jun 25 06:01:12 PM PDT 24 49103186 ps
T1208 /workspace/coverage/cover_reg_top/17.uart_tl_errors.1935978982 Jun 25 06:01:28 PM PDT 24 Jun 25 06:01:32 PM PDT 24 38697665 ps
T1209 /workspace/coverage/cover_reg_top/3.uart_csr_rw.2873248795 Jun 25 06:01:04 PM PDT 24 Jun 25 06:01:07 PM PDT 24 37258974 ps
T1210 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.519583642 Jun 25 06:01:40 PM PDT 24 Jun 25 06:01:44 PM PDT 24 63750106 ps
T1211 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3809976667 Jun 25 06:01:40 PM PDT 24 Jun 25 06:01:43 PM PDT 24 20315909 ps
T1212 /workspace/coverage/cover_reg_top/18.uart_intr_test.3941129260 Jun 25 06:01:31 PM PDT 24 Jun 25 06:01:33 PM PDT 24 187448556 ps
T1213 /workspace/coverage/cover_reg_top/48.uart_intr_test.1879394316 Jun 25 06:01:40 PM PDT 24 Jun 25 06:01:43 PM PDT 24 14267411 ps
T1214 /workspace/coverage/cover_reg_top/38.uart_intr_test.2975425684 Jun 25 06:01:39 PM PDT 24 Jun 25 06:01:40 PM PDT 24 14243731 ps
T1215 /workspace/coverage/cover_reg_top/4.uart_tl_errors.2980501629 Jun 25 06:01:06 PM PDT 24 Jun 25 06:01:09 PM PDT 24 45676926 ps
T1216 /workspace/coverage/cover_reg_top/14.uart_intr_test.2740345411 Jun 25 06:01:20 PM PDT 24 Jun 25 06:01:23 PM PDT 24 33361542 ps
T1217 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3297880033 Jun 25 06:01:02 PM PDT 24 Jun 25 06:01:04 PM PDT 24 16565653 ps
T1218 /workspace/coverage/cover_reg_top/40.uart_intr_test.901190639 Jun 25 06:01:40 PM PDT 24 Jun 25 06:01:44 PM PDT 24 13154177 ps
T1219 /workspace/coverage/cover_reg_top/5.uart_intr_test.3746163064 Jun 25 06:01:00 PM PDT 24 Jun 25 06:01:02 PM PDT 24 49429212 ps
T67 /workspace/coverage/cover_reg_top/11.uart_csr_rw.1031450987 Jun 25 06:01:20 PM PDT 24 Jun 25 06:01:23 PM PDT 24 26588903 ps
T1220 /workspace/coverage/cover_reg_top/11.uart_intr_test.382642403 Jun 25 06:01:18 PM PDT 24 Jun 25 06:01:20 PM PDT 24 17035860 ps
T1221 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1349801949 Jun 25 06:01:14 PM PDT 24 Jun 25 06:01:16 PM PDT 24 13799383 ps
T1222 /workspace/coverage/cover_reg_top/9.uart_csr_rw.2935474106 Jun 25 06:01:15 PM PDT 24 Jun 25 06:01:16 PM PDT 24 19187591 ps

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.1278761903
Short name T8
Test name
Test status
Simulation time 48961530083 ps
CPU time 659.65 seconds
Started Jun 25 05:15:36 PM PDT 24
Finished Jun 25 05:26:38 PM PDT 24
Peak memory 216428 kb
Host smart-4b3dd202-e74d-4483-8463-0a8aef481b98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278761903 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.1278761903
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_stress_all.2149317404
Short name T9
Test name
Test status
Simulation time 291812653562 ps
CPU time 580.08 seconds
Started Jun 25 05:12:45 PM PDT 24
Finished Jun 25 05:22:28 PM PDT 24
Peak memory 199744 kb
Host smart-1bca3f3e-3037-4b73-83b7-cb08fdb5f804
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149317404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2149317404
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all.3744235087
Short name T117
Test name
Test status
Simulation time 223904163344 ps
CPU time 396.29 seconds
Started Jun 25 05:13:30 PM PDT 24
Finished Jun 25 05:20:09 PM PDT 24
Peak memory 199728 kb
Host smart-a227433d-38b1-48e1-929a-3c8b1d6a5656
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744235087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3744235087
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.982956146
Short name T36
Test name
Test status
Simulation time 79541786216 ps
CPU time 705.92 seconds
Started Jun 25 05:16:21 PM PDT 24
Finished Jun 25 05:28:08 PM PDT 24
Peak memory 216360 kb
Host smart-0446d4ef-535c-4563-9426-122bf93e9c89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982956146 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.982956146
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.770130562
Short name T35
Test name
Test status
Simulation time 406021018015 ps
CPU time 281.37 seconds
Started Jun 25 05:16:01 PM PDT 24
Finished Jun 25 05:20:43 PM PDT 24
Peak memory 211064 kb
Host smart-1bbac457-c00b-4a1b-b5fe-5d8e4486629b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770130562 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.770130562
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_stress_all.2094201951
Short name T17
Test name
Test status
Simulation time 98866172037 ps
CPU time 52.42 seconds
Started Jun 25 05:13:26 PM PDT 24
Finished Jun 25 05:14:20 PM PDT 24
Peak memory 199776 kb
Host smart-aae87ed8-c7e2-4e91-8485-45152ab8f87c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094201951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2094201951
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all.3369327878
Short name T159
Test name
Test status
Simulation time 226840563176 ps
CPU time 1088.1 seconds
Started Jun 25 05:12:42 PM PDT 24
Finished Jun 25 05:30:51 PM PDT 24
Peak memory 199876 kb
Host smart-f1f79d89-9ff6-41af-9a0b-31d241bdd0ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369327878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3369327878
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all.3859151909
Short name T80
Test name
Test status
Simulation time 166006730866 ps
CPU time 789.34 seconds
Started Jun 25 05:13:40 PM PDT 24
Finished Jun 25 05:26:51 PM PDT 24
Peak memory 200140 kb
Host smart-08826d92-f1b1-4a9f-a93a-e6deb8496ab9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859151909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.3859151909
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2871923470
Short name T6
Test name
Test status
Simulation time 35673088 ps
CPU time 0.77 seconds
Started Jun 25 05:12:31 PM PDT 24
Finished Jun 25 05:12:33 PM PDT 24
Peak memory 218228 kb
Host smart-1bd51e0e-9add-45ce-bfba-2661308130eb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871923470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2871923470
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/46.uart_stress_all.3266551536
Short name T138
Test name
Test status
Simulation time 358837811502 ps
CPU time 149.17 seconds
Started Jun 25 05:15:40 PM PDT 24
Finished Jun 25 05:18:11 PM PDT 24
Peak memory 199816 kb
Host smart-3952b8fe-fbdd-4588-a015-be294bcb74ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266551536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.3266551536
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.1047183038
Short name T246
Test name
Test status
Simulation time 275231865738 ps
CPU time 315.32 seconds
Started Jun 25 05:16:29 PM PDT 24
Finished Jun 25 05:21:46 PM PDT 24
Peak memory 199840 kb
Host smart-d451cada-62e0-4f59-96f9-bcd9eb313878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047183038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1047183038
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3438436445
Short name T128
Test name
Test status
Simulation time 42349738178 ps
CPU time 70.02 seconds
Started Jun 25 05:13:29 PM PDT 24
Finished Jun 25 05:14:42 PM PDT 24
Peak memory 199888 kb
Host smart-be8d94d6-6322-4a78-9ce3-d913b4d79657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438436445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3438436445
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.1613776324
Short name T92
Test name
Test status
Simulation time 48579733710 ps
CPU time 478.31 seconds
Started Jun 25 05:14:21 PM PDT 24
Finished Jun 25 05:22:21 PM PDT 24
Peak memory 216348 kb
Host smart-3b6dd041-5a03-4eeb-9c99-b257a16339ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613776324 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.1613776324
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_intr.3056517597
Short name T268
Test name
Test status
Simulation time 286590907539 ps
CPU time 103.99 seconds
Started Jun 25 05:15:20 PM PDT 24
Finished Jun 25 05:17:05 PM PDT 24
Peak memory 199856 kb
Host smart-7351244a-108a-4413-85f3-c63b971272a3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056517597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3056517597
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2509387720
Short name T256
Test name
Test status
Simulation time 99825706553 ps
CPU time 751.69 seconds
Started Jun 25 05:14:13 PM PDT 24
Finished Jun 25 05:26:46 PM PDT 24
Peak memory 199840 kb
Host smart-d2d468ee-95a9-4f26-8564-54039d64c3b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2509387720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2509387720
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.2208497424
Short name T34
Test name
Test status
Simulation time 139248769599 ps
CPU time 424.37 seconds
Started Jun 25 05:14:01 PM PDT 24
Finished Jun 25 05:21:07 PM PDT 24
Peak memory 216312 kb
Host smart-fee591ef-d6e5-460b-b8e5-1b6c69f0649c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208497424 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.2208497424
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.2862945082
Short name T32
Test name
Test status
Simulation time 33272922633 ps
CPU time 628.86 seconds
Started Jun 25 05:16:09 PM PDT 24
Finished Jun 25 05:26:39 PM PDT 24
Peak memory 200012 kb
Host smart-ff64a1e1-8afc-4295-bea4-c1d4fb1b3932
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862945082 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.2862945082
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.2768228514
Short name T28
Test name
Test status
Simulation time 148041164596 ps
CPU time 187.72 seconds
Started Jun 25 05:15:07 PM PDT 24
Finished Jun 25 05:18:15 PM PDT 24
Peak memory 199856 kb
Host smart-b7b8f644-87a9-4358-b796-18bc6276e569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768228514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2768228514
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2946434417
Short name T82
Test name
Test status
Simulation time 269540941 ps
CPU time 1.26 seconds
Started Jun 25 06:00:54 PM PDT 24
Finished Jun 25 06:00:56 PM PDT 24
Peak memory 199716 kb
Host smart-20fafa97-a26d-46b0-8aa9-8ff2cd4ac799
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946434417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2946434417
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/29.uart_tx_rx.324739804
Short name T248
Test name
Test status
Simulation time 114966279497 ps
CPU time 59.17 seconds
Started Jun 25 05:14:27 PM PDT 24
Finished Jun 25 05:15:27 PM PDT 24
Peak memory 199816 kb
Host smart-cf244f2e-83d9-4260-bbc7-4bb4b7d3cf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324739804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.324739804
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_stress_all.3249982238
Short name T163
Test name
Test status
Simulation time 604835182416 ps
CPU time 274.89 seconds
Started Jun 25 05:13:02 PM PDT 24
Finished Jun 25 05:17:39 PM PDT 24
Peak memory 199804 kb
Host smart-6d7b16ec-146d-4c90-b2c0-cd0fe7909030
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249982238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3249982238
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_alert_test.2663424079
Short name T368
Test name
Test status
Simulation time 37745174 ps
CPU time 0.56 seconds
Started Jun 25 05:12:36 PM PDT 24
Finished Jun 25 05:12:38 PM PDT 24
Peak memory 195240 kb
Host smart-33663500-ce8f-4506-b7e6-bf398b581f0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663424079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2663424079
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_stress_all.1536808883
Short name T262
Test name
Test status
Simulation time 210854622216 ps
CPU time 75.41 seconds
Started Jun 25 05:13:11 PM PDT 24
Finished Jun 25 05:14:28 PM PDT 24
Peak memory 199804 kb
Host smart-5c3d12dc-9361-4ad5-b925-c32046e47235
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536808883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1536808883
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_fifo_full.222962576
Short name T96
Test name
Test status
Simulation time 183954585121 ps
CPU time 21.92 seconds
Started Jun 25 05:15:42 PM PDT 24
Finished Jun 25 05:16:05 PM PDT 24
Peak memory 199848 kb
Host smart-095b3406-0ba6-4375-84fd-39faca5cf9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222962576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.222962576
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.3870693506
Short name T143
Test name
Test status
Simulation time 15439088527 ps
CPU time 7.68 seconds
Started Jun 25 05:16:21 PM PDT 24
Finished Jun 25 05:16:30 PM PDT 24
Peak memory 199908 kb
Host smart-d62abc22-33c9-43fd-9507-30d66a42c35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870693506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3870693506
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.3635274796
Short name T198
Test name
Test status
Simulation time 155466824525 ps
CPU time 430.66 seconds
Started Jun 25 05:16:20 PM PDT 24
Finished Jun 25 05:23:32 PM PDT 24
Peak memory 199836 kb
Host smart-ea5611f5-1716-4b05-8e75-44bd79764bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635274796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3635274796
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.1404926179
Short name T142
Test name
Test status
Simulation time 365231133518 ps
CPU time 1037.18 seconds
Started Jun 25 05:12:44 PM PDT 24
Finished Jun 25 05:30:03 PM PDT 24
Peak memory 226644 kb
Host smart-47303933-5b43-4b2a-bbdc-57e2841e8f22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404926179 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.1404926179
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2468698448
Short name T74
Test name
Test status
Simulation time 44628167 ps
CPU time 0.67 seconds
Started Jun 25 06:00:57 PM PDT 24
Finished Jun 25 06:00:59 PM PDT 24
Peak memory 194992 kb
Host smart-1140509c-7b78-4196-925f-09f0a95da6d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468698448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.2468698448
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.329758212
Short name T63
Test name
Test status
Simulation time 42731174 ps
CPU time 0.65 seconds
Started Jun 25 06:00:52 PM PDT 24
Finished Jun 25 06:00:54 PM PDT 24
Peak memory 195844 kb
Host smart-68d1317c-1571-4d2b-b6a6-1e9f66231ea6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329758212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.329758212
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3360959691
Short name T114
Test name
Test status
Simulation time 128542666697 ps
CPU time 195.53 seconds
Started Jun 25 05:12:57 PM PDT 24
Finished Jun 25 05:16:15 PM PDT 24
Peak memory 199856 kb
Host smart-7c59144d-6ebe-472c-9fc9-03a9eec03d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360959691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3360959691
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2756584017
Short name T153
Test name
Test status
Simulation time 277094092637 ps
CPU time 120.58 seconds
Started Jun 25 05:13:10 PM PDT 24
Finished Jun 25 05:15:12 PM PDT 24
Peak memory 199904 kb
Host smart-227e0aee-3f06-49c4-91b3-b57e11cc1505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756584017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2756584017
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.3612015396
Short name T149
Test name
Test status
Simulation time 124068227751 ps
CPU time 58.12 seconds
Started Jun 25 05:15:18 PM PDT 24
Finished Jun 25 05:16:17 PM PDT 24
Peak memory 199892 kb
Host smart-c54097db-b4b1-47fe-a93f-63a9016d46ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612015396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3612015396
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1725236426
Short name T87
Test name
Test status
Simulation time 157738558 ps
CPU time 1.22 seconds
Started Jun 25 06:01:18 PM PDT 24
Finished Jun 25 06:01:20 PM PDT 24
Peak memory 199672 kb
Host smart-7a020470-dd11-431a-9725-5721b4875957
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725236426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.1725236426
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.3139181592
Short name T53
Test name
Test status
Simulation time 230975559575 ps
CPU time 1265.22 seconds
Started Jun 25 05:15:46 PM PDT 24
Finished Jun 25 05:36:53 PM PDT 24
Peak memory 216284 kb
Host smart-df28005f-cd4b-4388-9f86-87ab11753971
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139181592 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.3139181592
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.1077878094
Short name T556
Test name
Test status
Simulation time 84270521673 ps
CPU time 884.55 seconds
Started Jun 25 05:13:21 PM PDT 24
Finished Jun 25 05:28:07 PM PDT 24
Peak memory 224576 kb
Host smart-09dfe685-687a-4f45-ae56-360dfbcb85d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077878094 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.1077878094
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_fifo_full.1270434786
Short name T104
Test name
Test status
Simulation time 89994877871 ps
CPU time 39.26 seconds
Started Jun 25 05:15:02 PM PDT 24
Finished Jun 25 05:15:43 PM PDT 24
Peak memory 199768 kb
Host smart-67f1d7ae-2115-464e-b54e-44de79800826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270434786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.1270434786
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.1836738384
Short name T155
Test name
Test status
Simulation time 230297566630 ps
CPU time 252.76 seconds
Started Jun 25 05:15:00 PM PDT 24
Finished Jun 25 05:19:14 PM PDT 24
Peak memory 199920 kb
Host smart-64132cc8-dbb7-4747-b2ab-45e5570d0a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836738384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1836738384
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.2358487724
Short name T132
Test name
Test status
Simulation time 110580531678 ps
CPU time 40.59 seconds
Started Jun 25 05:16:20 PM PDT 24
Finished Jun 25 05:17:02 PM PDT 24
Peak memory 199920 kb
Host smart-cd221764-4194-4b45-9530-ddb30147b811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358487724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.2358487724
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_perf.371906081
Short name T275
Test name
Test status
Simulation time 31845444243 ps
CPU time 392.79 seconds
Started Jun 25 05:13:11 PM PDT 24
Finished Jun 25 05:19:46 PM PDT 24
Peak memory 199896 kb
Host smart-7b9ed00d-f36f-4ad6-ab7f-f2823e0e9df4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=371906081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.371906081
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.2257958822
Short name T20
Test name
Test status
Simulation time 44078770190 ps
CPU time 265.88 seconds
Started Jun 25 05:13:55 PM PDT 24
Finished Jun 25 05:18:22 PM PDT 24
Peak memory 208276 kb
Host smart-d61dad1c-0faa-4805-a3fb-45f76cefb6d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257958822 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.2257958822
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.4219961409
Short name T56
Test name
Test status
Simulation time 126260756871 ps
CPU time 354.01 seconds
Started Jun 25 05:13:22 PM PDT 24
Finished Jun 25 05:19:18 PM PDT 24
Peak memory 216412 kb
Host smart-0a92e02d-e9b1-4550-af64-d321b0fdcaa7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219961409 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.4219961409
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.1865685247
Short name T79
Test name
Test status
Simulation time 25077066648 ps
CPU time 33.49 seconds
Started Jun 25 05:16:47 PM PDT 24
Finished Jun 25 05:17:22 PM PDT 24
Peak memory 199788 kb
Host smart-06f23a14-1827-412b-9d82-c0e1c3bce6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865685247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1865685247
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_fifo_full.3345747902
Short name T167
Test name
Test status
Simulation time 40133146035 ps
CPU time 18.03 seconds
Started Jun 25 05:13:47 PM PDT 24
Finished Jun 25 05:14:07 PM PDT 24
Peak memory 199800 kb
Host smart-c4413f7c-4840-4447-aa57-3041bbb2e44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345747902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3345747902
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.3156985001
Short name T215
Test name
Test status
Simulation time 111479044716 ps
CPU time 48.44 seconds
Started Jun 25 05:17:23 PM PDT 24
Finished Jun 25 05:18:12 PM PDT 24
Peak memory 199700 kb
Host smart-4cf40548-9a23-40c1-b6ad-6b45d6031464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156985001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3156985001
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.4074519806
Short name T342
Test name
Test status
Simulation time 175204518574 ps
CPU time 96.55 seconds
Started Jun 25 05:16:04 PM PDT 24
Finished Jun 25 05:17:41 PM PDT 24
Peak memory 199860 kb
Host smart-9ecbddea-8e01-44e1-b1d5-287caedbe9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074519806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.4074519806
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.3856926951
Short name T746
Test name
Test status
Simulation time 93573174429 ps
CPU time 26.46 seconds
Started Jun 25 05:16:19 PM PDT 24
Finished Jun 25 05:16:47 PM PDT 24
Peak memory 199912 kb
Host smart-23578d9d-4d89-4f7f-b0e1-1af37b15ccd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856926951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.3856926951
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all.1311082346
Short name T165
Test name
Test status
Simulation time 144956595183 ps
CPU time 100.63 seconds
Started Jun 25 05:13:24 PM PDT 24
Finished Jun 25 05:15:06 PM PDT 24
Peak memory 199724 kb
Host smart-83db5f30-2948-4028-ad3b-83941dff4c39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311082346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1311082346
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.1820940480
Short name T232
Test name
Test status
Simulation time 129466429898 ps
CPU time 254.94 seconds
Started Jun 25 05:16:49 PM PDT 24
Finished Jun 25 05:21:05 PM PDT 24
Peak memory 200032 kb
Host smart-669cc533-60a4-4e1b-b134-068f0bfbb209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820940480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1820940480
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.1266635100
Short name T237
Test name
Test status
Simulation time 184771987496 ps
CPU time 67.07 seconds
Started Jun 25 05:13:49 PM PDT 24
Finished Jun 25 05:14:58 PM PDT 24
Peak memory 199536 kb
Host smart-e43d912e-c1fe-48e8-bc66-395abb460168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266635100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.1266635100
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.471220027
Short name T348
Test name
Test status
Simulation time 10623162870 ps
CPU time 14.31 seconds
Started Jun 25 05:13:47 PM PDT 24
Finished Jun 25 05:14:03 PM PDT 24
Peak memory 198076 kb
Host smart-17ebe40f-4926-4636-9902-1df279043334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471220027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.471220027
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3222693127
Short name T244
Test name
Test status
Simulation time 162339749298 ps
CPU time 93.2 seconds
Started Jun 25 05:16:18 PM PDT 24
Finished Jun 25 05:17:53 PM PDT 24
Peak memory 199872 kb
Host smart-815f38f7-992d-4c15-94ff-aaa96bad6bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222693127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3222693127
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.3912353944
Short name T156
Test name
Test status
Simulation time 117463379425 ps
CPU time 52.06 seconds
Started Jun 25 05:16:37 PM PDT 24
Finished Jun 25 05:17:31 PM PDT 24
Peak memory 199816 kb
Host smart-53bcf473-8ac6-4ae0-8882-a7c2171ae412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912353944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3912353944
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.2672129034
Short name T179
Test name
Test status
Simulation time 134991240693 ps
CPU time 17.45 seconds
Started Jun 25 05:16:37 PM PDT 24
Finished Jun 25 05:16:56 PM PDT 24
Peak memory 199848 kb
Host smart-80330e0e-cd05-46f4-b815-006810911b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672129034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2672129034
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3155341695
Short name T170
Test name
Test status
Simulation time 223547559103 ps
CPU time 317.85 seconds
Started Jun 25 05:16:37 PM PDT 24
Finished Jun 25 05:21:56 PM PDT 24
Peak memory 199800 kb
Host smart-5e444708-60eb-4267-a0d7-53a4a1655361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155341695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3155341695
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_tx_rx.883331482
Short name T40
Test name
Test status
Simulation time 127014079670 ps
CPU time 276.58 seconds
Started Jun 25 05:13:46 PM PDT 24
Finished Jun 25 05:18:25 PM PDT 24
Peak memory 199836 kb
Host smart-6ee6b050-d68d-4054-86d0-b23b7fa293bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883331482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.883331482
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.1039759110
Short name T14
Test name
Test status
Simulation time 16344945293 ps
CPU time 7.93 seconds
Started Jun 25 05:13:55 PM PDT 24
Finished Jun 25 05:14:04 PM PDT 24
Peak memory 199636 kb
Host smart-ff593872-b44c-4410-9c25-8436ec3a6766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039759110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.1039759110
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1997875649
Short name T134
Test name
Test status
Simulation time 44880241792 ps
CPU time 70.77 seconds
Started Jun 25 05:17:16 PM PDT 24
Finished Jun 25 05:18:28 PM PDT 24
Peak memory 199848 kb
Host smart-9f5c9923-4f5e-4f52-bf9f-01e1ccdd6333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997875649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1997875649
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.3168622172
Short name T199
Test name
Test status
Simulation time 64636556578 ps
CPU time 24.88 seconds
Started Jun 25 05:14:02 PM PDT 24
Finished Jun 25 05:14:29 PM PDT 24
Peak memory 199920 kb
Host smart-d517d48b-48e5-472b-be93-563f90b95131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168622172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.3168622172
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.392594689
Short name T224
Test name
Test status
Simulation time 29482914810 ps
CPU time 50.3 seconds
Started Jun 25 05:16:10 PM PDT 24
Finished Jun 25 05:17:02 PM PDT 24
Peak memory 199808 kb
Host smart-8c6f269e-5e35-488c-a8ac-e7a84732c9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392594689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.392594689
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.3457025883
Short name T915
Test name
Test status
Simulation time 7284569828 ps
CPU time 14.12 seconds
Started Jun 25 05:12:56 PM PDT 24
Finished Jun 25 05:13:11 PM PDT 24
Peak memory 199832 kb
Host smart-72ef8edd-4cb0-4f04-9f8f-b9c463e1d664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457025883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3457025883
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.2775683799
Short name T241
Test name
Test status
Simulation time 79705493873 ps
CPU time 137.73 seconds
Started Jun 25 05:16:21 PM PDT 24
Finished Jun 25 05:18:40 PM PDT 24
Peak memory 199892 kb
Host smart-138d4238-b568-4713-bc03-7e7a30a0a42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775683799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.2775683799
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.673929583
Short name T914
Test name
Test status
Simulation time 19580581793 ps
CPU time 35.88 seconds
Started Jun 25 05:16:18 PM PDT 24
Finished Jun 25 05:16:55 PM PDT 24
Peak memory 199888 kb
Host smart-f7e1e7cb-1c35-4c05-8c8d-bfac238ed93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673929583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.673929583
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.4278302196
Short name T1034
Test name
Test status
Simulation time 133016911695 ps
CPU time 1111.49 seconds
Started Jun 25 05:13:12 PM PDT 24
Finished Jun 25 05:31:45 PM PDT 24
Peak memory 216480 kb
Host smart-0c524054-0ef2-40e0-8a9b-34a00cdeccf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278302196 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.4278302196
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.3944871028
Short name T857
Test name
Test status
Simulation time 47913875984 ps
CPU time 74.07 seconds
Started Jun 25 05:16:25 PM PDT 24
Finished Jun 25 05:17:40 PM PDT 24
Peak memory 199900 kb
Host smart-a1ddc4b6-2564-4c0b-98bc-a4679aef6c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944871028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3944871028
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.541957462
Short name T205
Test name
Test status
Simulation time 15694568704 ps
CPU time 7.82 seconds
Started Jun 25 05:16:28 PM PDT 24
Finished Jun 25 05:16:38 PM PDT 24
Peak memory 199776 kb
Host smart-5bcf9e75-22cc-4ba2-929e-b3bf420f36b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541957462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.541957462
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2772945347
Short name T235
Test name
Test status
Simulation time 61459579551 ps
CPU time 26.42 seconds
Started Jun 25 05:16:37 PM PDT 24
Finished Jun 25 05:17:05 PM PDT 24
Peak memory 199904 kb
Host smart-a265d087-6463-4300-8b80-5bac2a97c936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772945347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2772945347
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1645195940
Short name T709
Test name
Test status
Simulation time 45288967635 ps
CPU time 31.71 seconds
Started Jun 25 05:16:36 PM PDT 24
Finished Jun 25 05:17:09 PM PDT 24
Peak memory 199732 kb
Host smart-27dbb933-ae8f-4d82-8b83-81a9c3d8d1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645195940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1645195940
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2553001177
Short name T200
Test name
Test status
Simulation time 29988881029 ps
CPU time 25.06 seconds
Started Jun 25 05:16:37 PM PDT 24
Finished Jun 25 05:17:03 PM PDT 24
Peak memory 199888 kb
Host smart-cc47d9bb-143e-471f-82f3-d7ae2402f97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553001177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2553001177
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.570911924
Short name T231
Test name
Test status
Simulation time 93552767083 ps
CPU time 308.98 seconds
Started Jun 25 05:16:37 PM PDT 24
Finished Jun 25 05:21:47 PM PDT 24
Peak memory 199828 kb
Host smart-354f9fe9-3417-45af-bfc7-2b470319bea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570911924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.570911924
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2356836734
Short name T234
Test name
Test status
Simulation time 121662382809 ps
CPU time 115.83 seconds
Started Jun 25 05:16:46 PM PDT 24
Finished Jun 25 05:18:43 PM PDT 24
Peak memory 199856 kb
Host smart-a375de90-2b48-4c0d-8781-417f5e8adf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356836734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2356836734
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.859978257
Short name T125
Test name
Test status
Simulation time 68760130553 ps
CPU time 25.63 seconds
Started Jun 25 05:16:47 PM PDT 24
Finished Jun 25 05:17:13 PM PDT 24
Peak memory 199804 kb
Host smart-2ac88f77-4ad0-40e4-9592-a2d5ee64a17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859978257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.859978257
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.4221783966
Short name T211
Test name
Test status
Simulation time 54869263419 ps
CPU time 45.34 seconds
Started Jun 25 05:16:58 PM PDT 24
Finished Jun 25 05:17:45 PM PDT 24
Peak memory 199908 kb
Host smart-806447c6-9951-4d06-8afd-483d34a77aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221783966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.4221783966
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.2061257910
Short name T166
Test name
Test status
Simulation time 70457699122 ps
CPU time 23.33 seconds
Started Jun 25 05:17:05 PM PDT 24
Finished Jun 25 05:17:29 PM PDT 24
Peak memory 199848 kb
Host smart-65cc2610-c8ce-40a5-89aa-6d2b1e123c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061257910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2061257910
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2114119839
Short name T225
Test name
Test status
Simulation time 54918380007 ps
CPU time 130.26 seconds
Started Jun 25 05:17:03 PM PDT 24
Finished Jun 25 05:19:14 PM PDT 24
Peak memory 199864 kb
Host smart-e6130011-1b1d-4308-8a8e-6d4ff171238b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114119839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2114119839
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.1650700149
Short name T239
Test name
Test status
Simulation time 92645536005 ps
CPU time 198.05 seconds
Started Jun 25 05:17:05 PM PDT 24
Finished Jun 25 05:20:24 PM PDT 24
Peak memory 199876 kb
Host smart-191e6387-56f5-4528-97ad-2a3117f74277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650700149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1650700149
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1981032843
Short name T196
Test name
Test status
Simulation time 64251566444 ps
CPU time 20.22 seconds
Started Jun 25 05:17:04 PM PDT 24
Finished Jun 25 05:17:25 PM PDT 24
Peak memory 199804 kb
Host smart-caf769b4-3876-4d86-9e45-cf83d35ed01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981032843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1981032843
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3417329173
Short name T229
Test name
Test status
Simulation time 111942117930 ps
CPU time 276.24 seconds
Started Jun 25 05:17:23 PM PDT 24
Finished Jun 25 05:22:00 PM PDT 24
Peak memory 199908 kb
Host smart-0b413561-1bfb-4915-a272-edded82e3444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417329173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3417329173
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3803725507
Short name T219
Test name
Test status
Simulation time 36254890200 ps
CPU time 27.92 seconds
Started Jun 25 05:17:26 PM PDT 24
Finished Jun 25 05:17:55 PM PDT 24
Peak memory 199900 kb
Host smart-02fb7b19-0d6f-4ecb-9aff-54e28b8487e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803725507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3803725507
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2250703628
Short name T103
Test name
Test status
Simulation time 183969493768 ps
CPU time 27.68 seconds
Started Jun 25 05:14:45 PM PDT 24
Finished Jun 25 05:15:14 PM PDT 24
Peak memory 199836 kb
Host smart-26a380d8-172f-47af-94e9-009288666ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250703628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2250703628
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.2102084036
Short name T150
Test name
Test status
Simulation time 99579377716 ps
CPU time 51.56 seconds
Started Jun 25 05:16:00 PM PDT 24
Finished Jun 25 05:16:53 PM PDT 24
Peak memory 199656 kb
Host smart-39a17070-443a-4d16-b645-078ad07e1e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102084036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.2102084036
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.444298817
Short name T230
Test name
Test status
Simulation time 207506713699 ps
CPU time 42.05 seconds
Started Jun 25 05:16:10 PM PDT 24
Finished Jun 25 05:16:54 PM PDT 24
Peak memory 199764 kb
Host smart-75b9e1fa-2e7c-4dc1-8b6e-8284e77f5a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444298817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.444298817
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.975163865
Short name T59
Test name
Test status
Simulation time 53355353 ps
CPU time 0.75 seconds
Started Jun 25 06:00:54 PM PDT 24
Finished Jun 25 06:00:56 PM PDT 24
Peak memory 197076 kb
Host smart-5194c2fe-86b1-419a-9a75-51f156c12d2d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975163865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.975163865
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2153678020
Short name T1153
Test name
Test status
Simulation time 58618740 ps
CPU time 2.18 seconds
Started Jun 25 06:00:53 PM PDT 24
Finished Jun 25 06:00:56 PM PDT 24
Peak memory 198144 kb
Host smart-d6d8fe0d-123d-4017-86cd-b717ca5f95c3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153678020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2153678020
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3374073065
Short name T1095
Test name
Test status
Simulation time 35668187 ps
CPU time 0.61 seconds
Started Jun 25 06:00:47 PM PDT 24
Finished Jun 25 06:00:48 PM PDT 24
Peak memory 195784 kb
Host smart-06bbe6f0-fd08-4202-a4cc-6505d77935b8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374073065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.3374073065
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2647425571
Short name T1124
Test name
Test status
Simulation time 31936643 ps
CPU time 1.41 seconds
Started Jun 25 06:00:53 PM PDT 24
Finished Jun 25 06:00:55 PM PDT 24
Peak memory 200444 kb
Host smart-2a012774-117d-4ebc-9772-a4cc20448805
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647425571 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2647425571
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.2138969478
Short name T1150
Test name
Test status
Simulation time 22307711 ps
CPU time 0.61 seconds
Started Jun 25 06:00:47 PM PDT 24
Finished Jun 25 06:00:49 PM PDT 24
Peak memory 195780 kb
Host smart-4cad2464-70c5-47c8-a138-04c0c82b50a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138969478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.2138969478
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.3843292692
Short name T1199
Test name
Test status
Simulation time 16076262 ps
CPU time 0.59 seconds
Started Jun 25 06:00:46 PM PDT 24
Finished Jun 25 06:00:47 PM PDT 24
Peak memory 194844 kb
Host smart-02f103fa-bb3e-44a3-832e-a8483ec27c90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843292692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3843292692
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.1640410754
Short name T1120
Test name
Test status
Simulation time 284837197 ps
CPU time 2.28 seconds
Started Jun 25 06:00:46 PM PDT 24
Finished Jun 25 06:00:49 PM PDT 24
Peak memory 200480 kb
Host smart-1e3f648d-262a-44f0-be1d-4aea2a4e3a04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640410754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.1640410754
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2091316151
Short name T1156
Test name
Test status
Simulation time 100046726 ps
CPU time 1.32 seconds
Started Jun 25 06:00:47 PM PDT 24
Finished Jun 25 06:00:49 PM PDT 24
Peak memory 199668 kb
Host smart-5e24b2d7-4a00-44c2-b9f7-ce9d5f89e7fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091316151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2091316151
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2554801354
Short name T64
Test name
Test status
Simulation time 59441997 ps
CPU time 2.29 seconds
Started Jun 25 06:00:54 PM PDT 24
Finished Jun 25 06:00:58 PM PDT 24
Peak memory 198084 kb
Host smart-b78bd1f1-ec67-406e-bcf5-79a555585358
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554801354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2554801354
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3438828830
Short name T1172
Test name
Test status
Simulation time 14474533 ps
CPU time 0.59 seconds
Started Jun 25 06:00:53 PM PDT 24
Finished Jun 25 06:00:54 PM PDT 24
Peak memory 195832 kb
Host smart-2b97dc30-f896-4432-b365-ae5c5cf343f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438828830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3438828830
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3457431548
Short name T1191
Test name
Test status
Simulation time 113651319 ps
CPU time 0.82 seconds
Started Jun 25 06:00:51 PM PDT 24
Finished Jun 25 06:00:53 PM PDT 24
Peak memory 200240 kb
Host smart-0ed5ed38-9132-40f3-b8b8-151b1e1acafd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457431548 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.3457431548
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.1506629240
Short name T77
Test name
Test status
Simulation time 52157396 ps
CPU time 0.62 seconds
Started Jun 25 06:00:54 PM PDT 24
Finished Jun 25 06:00:56 PM PDT 24
Peak memory 195996 kb
Host smart-34855f26-f7b1-4039-8b7c-ae23f504bb66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506629240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.1506629240
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.3345025072
Short name T1109
Test name
Test status
Simulation time 14295469 ps
CPU time 0.56 seconds
Started Jun 25 06:00:53 PM PDT 24
Finished Jun 25 06:00:55 PM PDT 24
Peak memory 194816 kb
Host smart-f3110274-d01f-49df-a71d-9d6a9b467050
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345025072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3345025072
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2422964212
Short name T1116
Test name
Test status
Simulation time 67493804 ps
CPU time 0.65 seconds
Started Jun 25 06:00:53 PM PDT 24
Finished Jun 25 06:00:55 PM PDT 24
Peak memory 196952 kb
Host smart-bd27b291-17a1-4fab-8b24-ddf463cee760
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422964212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.2422964212
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.2030023527
Short name T1138
Test name
Test status
Simulation time 37748144 ps
CPU time 1.97 seconds
Started Jun 25 06:00:55 PM PDT 24
Finished Jun 25 06:00:58 PM PDT 24
Peak memory 200444 kb
Host smart-1d79ffeb-5a1a-48ab-a3c4-a2c3e1bc89fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030023527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2030023527
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1519088541
Short name T1197
Test name
Test status
Simulation time 60259462 ps
CPU time 0.85 seconds
Started Jun 25 06:01:09 PM PDT 24
Finished Jun 25 06:01:11 PM PDT 24
Peak memory 200236 kb
Host smart-674d5a83-b916-4442-ae89-cc6ea4a9b4ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519088541 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.1519088541
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3663942714
Short name T1159
Test name
Test status
Simulation time 51007038 ps
CPU time 0.56 seconds
Started Jun 25 06:01:08 PM PDT 24
Finished Jun 25 06:01:10 PM PDT 24
Peak memory 195848 kb
Host smart-cfcf9889-983e-436f-9de4-5699f77e3728
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663942714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3663942714
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.3421799346
Short name T1145
Test name
Test status
Simulation time 39158488 ps
CPU time 0.6 seconds
Started Jun 25 06:01:11 PM PDT 24
Finished Jun 25 06:01:13 PM PDT 24
Peak memory 194816 kb
Host smart-4f587473-98cf-4104-ad66-35f7b37e180a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421799346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3421799346
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3233504260
Short name T1115
Test name
Test status
Simulation time 33310922 ps
CPU time 0.78 seconds
Started Jun 25 06:01:11 PM PDT 24
Finished Jun 25 06:01:13 PM PDT 24
Peak memory 198004 kb
Host smart-cd58cc77-7e6c-47b0-a080-14896766e3bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233504260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.3233504260
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.497288499
Short name T1158
Test name
Test status
Simulation time 269842396 ps
CPU time 2.06 seconds
Started Jun 25 06:01:10 PM PDT 24
Finished Jun 25 06:01:13 PM PDT 24
Peak memory 200480 kb
Host smart-0084151d-9ee0-428c-ac3b-c5148e7d8c54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497288499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.497288499
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3964054682
Short name T85
Test name
Test status
Simulation time 825556715 ps
CPU time 1.32 seconds
Started Jun 25 06:01:10 PM PDT 24
Finished Jun 25 06:01:13 PM PDT 24
Peak memory 199832 kb
Host smart-e62d9ecb-a3d7-412a-befd-c99e855cadee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964054682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3964054682
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3546666130
Short name T1148
Test name
Test status
Simulation time 42570928 ps
CPU time 1.12 seconds
Started Jun 25 06:01:20 PM PDT 24
Finished Jun 25 06:01:23 PM PDT 24
Peak memory 200512 kb
Host smart-811d4fd8-49a5-43a7-a0cf-ce882eb4c021
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546666130 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.3546666130
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.1031450987
Short name T67
Test name
Test status
Simulation time 26588903 ps
CPU time 0.62 seconds
Started Jun 25 06:01:20 PM PDT 24
Finished Jun 25 06:01:23 PM PDT 24
Peak memory 195916 kb
Host smart-c00a280f-83ae-4e1c-9755-b76bb763a972
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031450987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1031450987
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.382642403
Short name T1220
Test name
Test status
Simulation time 17035860 ps
CPU time 0.56 seconds
Started Jun 25 06:01:18 PM PDT 24
Finished Jun 25 06:01:20 PM PDT 24
Peak memory 194800 kb
Host smart-a59f71e4-34f2-433f-9de8-52e58adc13c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382642403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.382642403
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3087716893
Short name T1178
Test name
Test status
Simulation time 271363939 ps
CPU time 0.62 seconds
Started Jun 25 06:01:17 PM PDT 24
Finished Jun 25 06:01:19 PM PDT 24
Peak memory 196012 kb
Host smart-07bbfaa9-7635-4b94-a403-8cbd4b68ba61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087716893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.3087716893
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.4037279425
Short name T1119
Test name
Test status
Simulation time 130705236 ps
CPU time 1.81 seconds
Started Jun 25 06:01:08 PM PDT 24
Finished Jun 25 06:01:11 PM PDT 24
Peak memory 200476 kb
Host smart-47ebb8c9-4610-42cb-8f5f-d922c1c376fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037279425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.4037279425
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2980618358
Short name T1147
Test name
Test status
Simulation time 190911682 ps
CPU time 1.3 seconds
Started Jun 25 06:01:18 PM PDT 24
Finished Jun 25 06:01:21 PM PDT 24
Peak memory 199744 kb
Host smart-8fc555ed-56c3-4c09-9386-45e9a7d5b2eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980618358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.2980618358
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1180965397
Short name T1104
Test name
Test status
Simulation time 20959625 ps
CPU time 0.7 seconds
Started Jun 25 06:01:17 PM PDT 24
Finished Jun 25 06:01:19 PM PDT 24
Peak memory 198372 kb
Host smart-f0dca4a3-f351-4d88-a0a2-5c12b8e18697
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180965397 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.1180965397
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.3137036703
Short name T1196
Test name
Test status
Simulation time 28149688 ps
CPU time 0.62 seconds
Started Jun 25 06:01:18 PM PDT 24
Finished Jun 25 06:01:20 PM PDT 24
Peak memory 195928 kb
Host smart-1af440be-6f8e-4da5-987a-44faf0519541
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137036703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3137036703
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.1572312914
Short name T1134
Test name
Test status
Simulation time 37279052 ps
CPU time 0.56 seconds
Started Jun 25 06:01:19 PM PDT 24
Finished Jun 25 06:01:21 PM PDT 24
Peak memory 194824 kb
Host smart-98bfc98e-7461-48f7-abdc-77a5f5916cd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572312914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1572312914
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3934296090
Short name T1112
Test name
Test status
Simulation time 60688850 ps
CPU time 0.61 seconds
Started Jun 25 06:01:20 PM PDT 24
Finished Jun 25 06:01:22 PM PDT 24
Peak memory 195932 kb
Host smart-39d1b3ee-5c00-4048-ad84-9ea11a6a436b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934296090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.3934296090
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.3977523139
Short name T1098
Test name
Test status
Simulation time 28278924 ps
CPU time 1.47 seconds
Started Jun 25 06:01:19 PM PDT 24
Finished Jun 25 06:01:22 PM PDT 24
Peak memory 200312 kb
Host smart-adbc1af9-8297-43b1-a086-56062c108977
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977523139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.3977523139
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1206685429
Short name T1136
Test name
Test status
Simulation time 181754933 ps
CPU time 0.94 seconds
Started Jun 25 06:01:17 PM PDT 24
Finished Jun 25 06:01:19 PM PDT 24
Peak memory 200192 kb
Host smart-2fb1c09f-30e8-40cd-8932-45f82b80353a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206685429 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1206685429
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.2432945255
Short name T1169
Test name
Test status
Simulation time 34178853 ps
CPU time 0.64 seconds
Started Jun 25 06:01:17 PM PDT 24
Finished Jun 25 06:01:18 PM PDT 24
Peak memory 195832 kb
Host smart-4946ca48-eb6f-4eae-a56c-3b4f18c80af0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432945255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2432945255
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.3526786105
Short name T1173
Test name
Test status
Simulation time 14252536 ps
CPU time 0.63 seconds
Started Jun 25 06:01:18 PM PDT 24
Finished Jun 25 06:01:21 PM PDT 24
Peak memory 194820 kb
Host smart-c96b90df-f71c-4675-8483-6de10c2db105
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526786105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3526786105
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.355720576
Short name T1183
Test name
Test status
Simulation time 87723025 ps
CPU time 0.72 seconds
Started Jun 25 06:01:21 PM PDT 24
Finished Jun 25 06:01:24 PM PDT 24
Peak memory 197380 kb
Host smart-bc990061-bbf6-4777-a6b6-57a1d79c1c9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355720576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr
_outstanding.355720576
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.428670208
Short name T1110
Test name
Test status
Simulation time 122615577 ps
CPU time 1.48 seconds
Started Jun 25 06:01:19 PM PDT 24
Finished Jun 25 06:01:23 PM PDT 24
Peak memory 200488 kb
Host smart-29b3fb6c-4572-432f-b898-186481475d1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428670208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.428670208
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.290908824
Short name T111
Test name
Test status
Simulation time 134985422 ps
CPU time 1.28 seconds
Started Jun 25 06:01:21 PM PDT 24
Finished Jun 25 06:01:24 PM PDT 24
Peak memory 199800 kb
Host smart-826d7557-e1c4-4af1-82e7-0c3fa82e9fa3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290908824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.290908824
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.786996175
Short name T1164
Test name
Test status
Simulation time 69015758 ps
CPU time 0.71 seconds
Started Jun 25 06:01:19 PM PDT 24
Finished Jun 25 06:01:22 PM PDT 24
Peak memory 198900 kb
Host smart-ad541a7d-94be-4be1-9a0b-fadf11db9d7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786996175 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.786996175
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1715733830
Short name T78
Test name
Test status
Simulation time 50156126 ps
CPU time 0.61 seconds
Started Jun 25 06:01:19 PM PDT 24
Finished Jun 25 06:01:21 PM PDT 24
Peak memory 195920 kb
Host smart-696526d3-1d9d-4fb9-aaad-81e4e6fd35fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715733830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1715733830
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.2740345411
Short name T1216
Test name
Test status
Simulation time 33361542 ps
CPU time 0.58 seconds
Started Jun 25 06:01:20 PM PDT 24
Finished Jun 25 06:01:23 PM PDT 24
Peak memory 194828 kb
Host smart-be9bd08c-a842-431c-bb86-d061bda1eb50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740345411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.2740345411
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.166904486
Short name T1126
Test name
Test status
Simulation time 18472259 ps
CPU time 0.68 seconds
Started Jun 25 06:01:19 PM PDT 24
Finished Jun 25 06:01:22 PM PDT 24
Peak memory 196372 kb
Host smart-262a6541-0e76-4dd5-a4be-f94f35e54f76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166904486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr
_outstanding.166904486
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1704708014
Short name T1089
Test name
Test status
Simulation time 27580323 ps
CPU time 1.31 seconds
Started Jun 25 06:01:18 PM PDT 24
Finished Jun 25 06:01:20 PM PDT 24
Peak memory 200496 kb
Host smart-2dd6a4a5-8ec1-4dc8-a985-2d91e5722d67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704708014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1704708014
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3837490083
Short name T84
Test name
Test status
Simulation time 183944027 ps
CPU time 0.94 seconds
Started Jun 25 06:01:19 PM PDT 24
Finished Jun 25 06:01:21 PM PDT 24
Peak memory 199240 kb
Host smart-cbd4c3ae-b034-4ffe-a051-bbc64b9fb21e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837490083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3837490083
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2071960541
Short name T1133
Test name
Test status
Simulation time 68176050 ps
CPU time 0.98 seconds
Started Jun 25 06:01:32 PM PDT 24
Finished Jun 25 06:01:34 PM PDT 24
Peak memory 200244 kb
Host smart-64039433-f2dc-49fe-9810-bf8985fe0708
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071960541 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.2071960541
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1447568965
Short name T66
Test name
Test status
Simulation time 48385412 ps
CPU time 0.59 seconds
Started Jun 25 06:01:29 PM PDT 24
Finished Jun 25 06:01:32 PM PDT 24
Peak memory 196032 kb
Host smart-7cfc5375-3660-4f54-a8fd-74b4e705e524
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447568965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1447568965
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.1278838419
Short name T1176
Test name
Test status
Simulation time 15233317 ps
CPU time 0.55 seconds
Started Jun 25 06:01:30 PM PDT 24
Finished Jun 25 06:01:32 PM PDT 24
Peak memory 194816 kb
Host smart-e6bd080b-e162-4b79-b719-dabfa3395fd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278838419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.1278838419
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.614741763
Short name T76
Test name
Test status
Simulation time 40184874 ps
CPU time 0.62 seconds
Started Jun 25 06:01:30 PM PDT 24
Finished Jun 25 06:01:33 PM PDT 24
Peak memory 196028 kb
Host smart-cf2a9382-995d-4b14-ae26-50eaec5ba2fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614741763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr
_outstanding.614741763
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.398533797
Short name T1101
Test name
Test status
Simulation time 99722456 ps
CPU time 1.51 seconds
Started Jun 25 06:01:19 PM PDT 24
Finished Jun 25 06:01:23 PM PDT 24
Peak memory 200416 kb
Host smart-5af39ef7-5360-4aed-ae1a-7f960366c89f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398533797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.398533797
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1883826589
Short name T88
Test name
Test status
Simulation time 40002023 ps
CPU time 0.93 seconds
Started Jun 25 06:01:28 PM PDT 24
Finished Jun 25 06:01:31 PM PDT 24
Peak memory 199208 kb
Host smart-eb5756ff-dcf6-4f66-bbc6-61b90027b7cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883826589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1883826589
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1379277815
Short name T1130
Test name
Test status
Simulation time 37664248 ps
CPU time 0.93 seconds
Started Jun 25 06:01:29 PM PDT 24
Finished Jun 25 06:01:32 PM PDT 24
Peak memory 200252 kb
Host smart-28916c70-c9e3-49f9-9587-a59e08aad7ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379277815 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.1379277815
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.3096548736
Short name T75
Test name
Test status
Simulation time 29383993 ps
CPU time 0.56 seconds
Started Jun 25 06:01:27 PM PDT 24
Finished Jun 25 06:01:29 PM PDT 24
Peak memory 195840 kb
Host smart-14b8299f-437a-4051-a04b-57c224d5eab0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096548736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3096548736
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2305050051
Short name T1135
Test name
Test status
Simulation time 36423879 ps
CPU time 0.57 seconds
Started Jun 25 06:01:30 PM PDT 24
Finished Jun 25 06:01:32 PM PDT 24
Peak memory 194836 kb
Host smart-3f30e153-ff45-4527-873f-a8bfda3efa4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305050051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2305050051
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3042435489
Short name T1149
Test name
Test status
Simulation time 193946889 ps
CPU time 0.77 seconds
Started Jun 25 06:01:29 PM PDT 24
Finished Jun 25 06:01:32 PM PDT 24
Peak memory 198488 kb
Host smart-6e6641f6-4aed-45b7-865f-db9209b45d0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042435489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.3042435489
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1530973201
Short name T1193
Test name
Test status
Simulation time 67139537 ps
CPU time 1.53 seconds
Started Jun 25 06:01:30 PM PDT 24
Finished Jun 25 06:01:33 PM PDT 24
Peak memory 200452 kb
Host smart-5049c82f-b218-491e-b089-ec571ee4538f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530973201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1530973201
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.712759028
Short name T1194
Test name
Test status
Simulation time 48333793 ps
CPU time 0.96 seconds
Started Jun 25 06:01:29 PM PDT 24
Finished Jun 25 06:01:32 PM PDT 24
Peak memory 199408 kb
Host smart-b09789ae-5fb8-4d99-90be-da31baa688e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712759028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.712759028
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.469637322
Short name T1168
Test name
Test status
Simulation time 85946340 ps
CPU time 1.24 seconds
Started Jun 25 06:01:31 PM PDT 24
Finished Jun 25 06:01:34 PM PDT 24
Peak memory 200668 kb
Host smart-de5f4f4c-0621-4ffa-990b-4723e4e7774f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469637322 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.469637322
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.699448415
Short name T1117
Test name
Test status
Simulation time 13973150 ps
CPU time 0.59 seconds
Started Jun 25 06:01:29 PM PDT 24
Finished Jun 25 06:01:31 PM PDT 24
Peak memory 195808 kb
Host smart-1edd5755-47cc-4304-98de-73084604e269
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699448415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.699448415
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.3988535359
Short name T1182
Test name
Test status
Simulation time 50518171 ps
CPU time 0.59 seconds
Started Jun 25 06:01:31 PM PDT 24
Finished Jun 25 06:01:33 PM PDT 24
Peak memory 194840 kb
Host smart-2c3fa7d2-15c0-44da-b491-74c4388f3fb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988535359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3988535359
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2739917756
Short name T70
Test name
Test status
Simulation time 31997171 ps
CPU time 0.75 seconds
Started Jun 25 06:01:30 PM PDT 24
Finished Jun 25 06:01:33 PM PDT 24
Peak memory 197364 kb
Host smart-65ff0f02-9a7d-48fa-aa7e-96d9bb97229a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739917756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2739917756
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.1935978982
Short name T1208
Test name
Test status
Simulation time 38697665 ps
CPU time 2.04 seconds
Started Jun 25 06:01:28 PM PDT 24
Finished Jun 25 06:01:32 PM PDT 24
Peak memory 200476 kb
Host smart-a029232b-7e17-4573-b546-f25b4960b497
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935978982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1935978982
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.4124097712
Short name T1165
Test name
Test status
Simulation time 821419502 ps
CPU time 0.94 seconds
Started Jun 25 06:01:31 PM PDT 24
Finished Jun 25 06:01:34 PM PDT 24
Peak memory 199020 kb
Host smart-351826da-a797-4bb7-8d6a-06411ee786cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124097712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.4124097712
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1693639265
Short name T1162
Test name
Test status
Simulation time 210542965 ps
CPU time 0.79 seconds
Started Jun 25 06:01:29 PM PDT 24
Finished Jun 25 06:01:32 PM PDT 24
Peak memory 200132 kb
Host smart-24a2752e-f1fb-4b72-aa95-f6370b4fe466
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693639265 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.1693639265
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.903951653
Short name T60
Test name
Test status
Simulation time 105610700 ps
CPU time 0.56 seconds
Started Jun 25 06:01:30 PM PDT 24
Finished Jun 25 06:01:32 PM PDT 24
Peak memory 195832 kb
Host smart-58a6a157-b1e2-4d5e-bbd9-efa5628ddf5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903951653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.903951653
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3941129260
Short name T1212
Test name
Test status
Simulation time 187448556 ps
CPU time 0.57 seconds
Started Jun 25 06:01:31 PM PDT 24
Finished Jun 25 06:01:33 PM PDT 24
Peak memory 194816 kb
Host smart-c45d32d9-0677-45de-876f-6aded623b005
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941129260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3941129260
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.391512781
Short name T1174
Test name
Test status
Simulation time 100283527 ps
CPU time 0.74 seconds
Started Jun 25 06:01:37 PM PDT 24
Finished Jun 25 06:01:38 PM PDT 24
Peak memory 197464 kb
Host smart-ea89c121-4116-405a-b1ff-cf08e99f5415
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391512781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr
_outstanding.391512781
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.964140762
Short name T1142
Test name
Test status
Simulation time 142736625 ps
CPU time 1.75 seconds
Started Jun 25 06:01:29 PM PDT 24
Finished Jun 25 06:01:33 PM PDT 24
Peak memory 200448 kb
Host smart-7f9d2a06-25db-47a9-b03e-592f5aca224c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964140762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.964140762
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1560407437
Short name T1121
Test name
Test status
Simulation time 167719553 ps
CPU time 1.32 seconds
Started Jun 25 06:01:30 PM PDT 24
Finished Jun 25 06:01:33 PM PDT 24
Peak memory 199788 kb
Host smart-002a6f14-ae2e-4fd2-a125-8a67ec924e37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560407437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1560407437
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.519583642
Short name T1210
Test name
Test status
Simulation time 63750106 ps
CPU time 0.68 seconds
Started Jun 25 06:01:40 PM PDT 24
Finished Jun 25 06:01:44 PM PDT 24
Peak memory 198740 kb
Host smart-ce476471-86f9-45d6-86a8-08ef9db0520c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519583642 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.519583642
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.3736428109
Short name T61
Test name
Test status
Simulation time 67004358 ps
CPU time 0.63 seconds
Started Jun 25 06:01:39 PM PDT 24
Finished Jun 25 06:01:41 PM PDT 24
Peak memory 196024 kb
Host smart-b494995a-75ff-4ef8-92c0-5d117fe1daa2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736428109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3736428109
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.3430396861
Short name T1097
Test name
Test status
Simulation time 23933997 ps
CPU time 0.58 seconds
Started Jun 25 06:01:41 PM PDT 24
Finished Jun 25 06:01:44 PM PDT 24
Peak memory 194852 kb
Host smart-007c58b2-e3cf-474d-8b2d-98f135fbef51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430396861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3430396861
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3809976667
Short name T1211
Test name
Test status
Simulation time 20315909 ps
CPU time 0.69 seconds
Started Jun 25 06:01:40 PM PDT 24
Finished Jun 25 06:01:43 PM PDT 24
Peak memory 196012 kb
Host smart-c436e9cb-e8ce-4f91-ab73-28744afbcd50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809976667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.3809976667
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.3068394531
Short name T1103
Test name
Test status
Simulation time 89196489 ps
CPU time 1.22 seconds
Started Jun 25 06:01:31 PM PDT 24
Finished Jun 25 06:01:34 PM PDT 24
Peak memory 200428 kb
Host smart-2331cbf8-93c4-4b62-9511-2e1231172579
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068394531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3068394531
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3774347634
Short name T1198
Test name
Test status
Simulation time 91977213 ps
CPU time 1.32 seconds
Started Jun 25 06:01:40 PM PDT 24
Finished Jun 25 06:01:43 PM PDT 24
Peak memory 199840 kb
Host smart-92df331c-1d04-4e3a-9e26-6509706d7f46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774347634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3774347634
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.436269313
Short name T1107
Test name
Test status
Simulation time 30689525 ps
CPU time 0.81 seconds
Started Jun 25 06:01:02 PM PDT 24
Finished Jun 25 06:01:04 PM PDT 24
Peak memory 196816 kb
Host smart-c6eb3fd0-e7d4-4cfd-bcfe-acd65d3f9b41
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436269313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.436269313
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.487317489
Short name T1204
Test name
Test status
Simulation time 222825321 ps
CPU time 2.22 seconds
Started Jun 25 06:00:54 PM PDT 24
Finished Jun 25 06:00:58 PM PDT 24
Peak memory 198308 kb
Host smart-4b5608df-ad93-4d2f-b5ea-4e18feb13f76
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487317489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.487317489
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.183647636
Short name T1180
Test name
Test status
Simulation time 191198698 ps
CPU time 0.58 seconds
Started Jun 25 06:00:55 PM PDT 24
Finished Jun 25 06:00:57 PM PDT 24
Peak memory 195836 kb
Host smart-f88cc9a9-9934-4c78-ba24-5c4f7e3a023e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183647636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.183647636
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3836558932
Short name T1170
Test name
Test status
Simulation time 49677259 ps
CPU time 0.81 seconds
Started Jun 25 06:01:02 PM PDT 24
Finished Jun 25 06:01:04 PM PDT 24
Peak memory 199152 kb
Host smart-947ae7dc-f904-4a22-a07c-c3dcc0546dc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836558932 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3836558932
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.1674812917
Short name T69
Test name
Test status
Simulation time 38926164 ps
CPU time 0.57 seconds
Started Jun 25 06:00:53 PM PDT 24
Finished Jun 25 06:00:55 PM PDT 24
Peak memory 195844 kb
Host smart-c9cbee8f-8a25-4408-a811-16f356a855b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674812917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1674812917
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.1448134874
Short name T1113
Test name
Test status
Simulation time 28545717 ps
CPU time 0.59 seconds
Started Jun 25 06:00:57 PM PDT 24
Finished Jun 25 06:00:59 PM PDT 24
Peak memory 194636 kb
Host smart-4843e6d3-78bc-467a-9568-7e6390529655
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448134874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1448134874
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.83123837
Short name T73
Test name
Test status
Simulation time 45066961 ps
CPU time 0.69 seconds
Started Jun 25 06:01:02 PM PDT 24
Finished Jun 25 06:01:04 PM PDT 24
Peak memory 194928 kb
Host smart-0572d001-7fa9-4fb1-bb03-589b30afbd1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83123837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_o
utstanding.83123837
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.4024436116
Short name T1122
Test name
Test status
Simulation time 72508254 ps
CPU time 1.55 seconds
Started Jun 25 06:00:54 PM PDT 24
Finished Jun 25 06:00:57 PM PDT 24
Peak memory 200492 kb
Host smart-1b3bd834-c8be-4e1e-88cd-7d3011ed666f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024436116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.4024436116
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2384625229
Short name T1161
Test name
Test status
Simulation time 164035809 ps
CPU time 1.29 seconds
Started Jun 25 06:00:55 PM PDT 24
Finished Jun 25 06:00:58 PM PDT 24
Peak memory 199536 kb
Host smart-d6dfcdc6-4435-4b24-accf-22423cd256cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384625229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2384625229
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.3545144837
Short name T1175
Test name
Test status
Simulation time 61451818 ps
CPU time 0.57 seconds
Started Jun 25 06:01:40 PM PDT 24
Finished Jun 25 06:01:42 PM PDT 24
Peak memory 194836 kb
Host smart-471143d8-cbf5-42d2-bf2e-862415d7b84f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545144837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3545144837
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.199063432
Short name T1131
Test name
Test status
Simulation time 13607037 ps
CPU time 0.58 seconds
Started Jun 25 06:01:40 PM PDT 24
Finished Jun 25 06:01:43 PM PDT 24
Peak memory 194784 kb
Host smart-915679a4-7524-462a-9d94-c1ebd535e232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199063432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.199063432
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1341989566
Short name T1163
Test name
Test status
Simulation time 16584552 ps
CPU time 0.61 seconds
Started Jun 25 06:01:40 PM PDT 24
Finished Jun 25 06:01:43 PM PDT 24
Peak memory 194820 kb
Host smart-878479d6-6418-4812-b534-f055628c18cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341989566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1341989566
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2580642576
Short name T1203
Test name
Test status
Simulation time 29950749 ps
CPU time 0.6 seconds
Started Jun 25 06:01:40 PM PDT 24
Finished Jun 25 06:01:42 PM PDT 24
Peak memory 194772 kb
Host smart-f8bdbf44-fea7-439b-bd9f-d3f3a7c3da25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580642576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2580642576
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.3088641715
Short name T1106
Test name
Test status
Simulation time 38795234 ps
CPU time 0.55 seconds
Started Jun 25 06:01:40 PM PDT 24
Finished Jun 25 06:01:43 PM PDT 24
Peak memory 194780 kb
Host smart-7603051b-c145-4710-be84-6ce42aefc223
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088641715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3088641715
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.963135782
Short name T1137
Test name
Test status
Simulation time 116749976 ps
CPU time 0.59 seconds
Started Jun 25 06:01:40 PM PDT 24
Finished Jun 25 06:01:43 PM PDT 24
Peak memory 194824 kb
Host smart-4d372d9e-40da-4e2b-bdd8-abba7f3edb22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963135782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.963135782
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.1965371749
Short name T1184
Test name
Test status
Simulation time 27648035 ps
CPU time 0.56 seconds
Started Jun 25 06:01:40 PM PDT 24
Finished Jun 25 06:01:44 PM PDT 24
Peak memory 194812 kb
Host smart-18555411-4640-4825-a356-df3cc303b61f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965371749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1965371749
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.240687329
Short name T1093
Test name
Test status
Simulation time 50025271 ps
CPU time 0.56 seconds
Started Jun 25 06:01:41 PM PDT 24
Finished Jun 25 06:01:44 PM PDT 24
Peak memory 194736 kb
Host smart-0b4270fe-a363-4f09-9baf-397be38e1c45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240687329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.240687329
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2862693160
Short name T1140
Test name
Test status
Simulation time 60800614 ps
CPU time 0.6 seconds
Started Jun 25 06:01:41 PM PDT 24
Finished Jun 25 06:01:45 PM PDT 24
Peak memory 194816 kb
Host smart-46b30eb3-e643-4b9c-98d0-7262395cea80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862693160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2862693160
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.2941330561
Short name T1167
Test name
Test status
Simulation time 41808863 ps
CPU time 0.56 seconds
Started Jun 25 06:01:40 PM PDT 24
Finished Jun 25 06:01:44 PM PDT 24
Peak memory 194812 kb
Host smart-31dc7376-7bfa-433b-97e6-fc2ba21d2949
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941330561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2941330561
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1288070076
Short name T65
Test name
Test status
Simulation time 19147487 ps
CPU time 0.65 seconds
Started Jun 25 06:01:07 PM PDT 24
Finished Jun 25 06:01:09 PM PDT 24
Peak memory 195200 kb
Host smart-44e740dd-18a2-4c6e-9c7f-9925536bfa68
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288070076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1288070076
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2365843635
Short name T1143
Test name
Test status
Simulation time 683758298 ps
CPU time 2.44 seconds
Started Jun 25 06:01:00 PM PDT 24
Finished Jun 25 06:01:04 PM PDT 24
Peak memory 198140 kb
Host smart-a1698a75-64d7-4062-855a-ad5d91af9dab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365843635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.2365843635
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3297880033
Short name T1217
Test name
Test status
Simulation time 16565653 ps
CPU time 0.59 seconds
Started Jun 25 06:01:02 PM PDT 24
Finished Jun 25 06:01:04 PM PDT 24
Peak memory 195868 kb
Host smart-b3486161-5ebe-4227-8495-8deeabf0d311
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297880033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3297880033
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.558486436
Short name T1189
Test name
Test status
Simulation time 20538485 ps
CPU time 1.03 seconds
Started Jun 25 06:01:02 PM PDT 24
Finished Jun 25 06:01:05 PM PDT 24
Peak memory 200268 kb
Host smart-66f65bb2-9b91-486e-8416-9a7d3b2100f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558486436 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.558486436
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.2873248795
Short name T1209
Test name
Test status
Simulation time 37258974 ps
CPU time 0.6 seconds
Started Jun 25 06:01:04 PM PDT 24
Finished Jun 25 06:01:07 PM PDT 24
Peak memory 196212 kb
Host smart-2000472c-0c38-4396-9255-1bbc1e578332
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873248795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2873248795
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.2987357173
Short name T1146
Test name
Test status
Simulation time 72597780 ps
CPU time 0.57 seconds
Started Jun 25 06:01:02 PM PDT 24
Finished Jun 25 06:01:03 PM PDT 24
Peak memory 194816 kb
Host smart-09770767-5962-4f36-bfb8-f0743e2c3f19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987357173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2987357173
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2141907996
Short name T72
Test name
Test status
Simulation time 12562828 ps
CPU time 0.67 seconds
Started Jun 25 06:01:03 PM PDT 24
Finished Jun 25 06:01:05 PM PDT 24
Peak memory 196772 kb
Host smart-e57f67cf-2bda-4bc6-983b-c585b4f713fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141907996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.2141907996
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2445086468
Short name T1127
Test name
Test status
Simulation time 290511990 ps
CPU time 1.6 seconds
Started Jun 25 06:01:02 PM PDT 24
Finished Jun 25 06:01:05 PM PDT 24
Peak memory 200456 kb
Host smart-a983f4b7-2f3e-4fcc-b60c-18ce6f1a6b72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445086468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2445086468
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.112398387
Short name T83
Test name
Test status
Simulation time 49203908 ps
CPU time 0.94 seconds
Started Jun 25 06:01:04 PM PDT 24
Finished Jun 25 06:01:07 PM PDT 24
Peak memory 199332 kb
Host smart-88861a4d-b14c-4f38-adb1-651939fdb49b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112398387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.112398387
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.3821559669
Short name T1171
Test name
Test status
Simulation time 15507235 ps
CPU time 0.6 seconds
Started Jun 25 06:01:39 PM PDT 24
Finished Jun 25 06:01:41 PM PDT 24
Peak memory 194852 kb
Host smart-762066eb-d5ec-4d36-9bd6-202a83e5d483
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821559669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3821559669
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.670373080
Short name T1090
Test name
Test status
Simulation time 17688963 ps
CPU time 0.6 seconds
Started Jun 25 06:01:42 PM PDT 24
Finished Jun 25 06:01:45 PM PDT 24
Peak memory 194780 kb
Host smart-142755bc-da44-4ef2-ae06-3010ab9de5d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670373080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.670373080
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.2712078489
Short name T1201
Test name
Test status
Simulation time 64727167 ps
CPU time 0.55 seconds
Started Jun 25 06:01:41 PM PDT 24
Finished Jun 25 06:01:44 PM PDT 24
Peak memory 194772 kb
Host smart-fdc94002-6142-4941-8f25-b0ec0cc7c983
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712078489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2712078489
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.4038374740
Short name T1200
Test name
Test status
Simulation time 19875501 ps
CPU time 0.62 seconds
Started Jun 25 06:01:40 PM PDT 24
Finished Jun 25 06:01:43 PM PDT 24
Peak memory 194820 kb
Host smart-d58dd705-32ad-44d5-8a4b-63fac8140107
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038374740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.4038374740
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.2004436853
Short name T1091
Test name
Test status
Simulation time 65684050 ps
CPU time 0.59 seconds
Started Jun 25 06:01:46 PM PDT 24
Finished Jun 25 06:01:47 PM PDT 24
Peak memory 194848 kb
Host smart-b30e7a44-ced4-43bf-9893-580a777d6a5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004436853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2004436853
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.3619697455
Short name T1195
Test name
Test status
Simulation time 47517266 ps
CPU time 0.58 seconds
Started Jun 25 06:01:42 PM PDT 24
Finished Jun 25 06:01:45 PM PDT 24
Peak memory 194816 kb
Host smart-dd6026c5-b6b5-4962-8762-cd451340fb2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619697455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3619697455
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.541392834
Short name T1111
Test name
Test status
Simulation time 21217763 ps
CPU time 0.58 seconds
Started Jun 25 06:01:40 PM PDT 24
Finished Jun 25 06:01:43 PM PDT 24
Peak memory 194752 kb
Host smart-4315958f-c5b6-4471-a910-194adedbbfc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541392834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.541392834
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1975120022
Short name T1118
Test name
Test status
Simulation time 69316748 ps
CPU time 0.57 seconds
Started Jun 25 06:01:42 PM PDT 24
Finished Jun 25 06:01:45 PM PDT 24
Peak memory 194748 kb
Host smart-9f91a70d-c525-46ae-97e7-7f690a363c26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975120022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1975120022
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.2975425684
Short name T1214
Test name
Test status
Simulation time 14243731 ps
CPU time 0.59 seconds
Started Jun 25 06:01:39 PM PDT 24
Finished Jun 25 06:01:40 PM PDT 24
Peak memory 194852 kb
Host smart-f74614a4-9c09-4868-80af-784cd20d8e1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975425684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2975425684
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.343682748
Short name T1128
Test name
Test status
Simulation time 32524138 ps
CPU time 0.57 seconds
Started Jun 25 06:01:40 PM PDT 24
Finished Jun 25 06:01:43 PM PDT 24
Peak memory 194840 kb
Host smart-93e58e6c-f19e-4956-8e3c-6310058f2be2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343682748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.343682748
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.4136484426
Short name T1144
Test name
Test status
Simulation time 32118157 ps
CPU time 0.83 seconds
Started Jun 25 06:01:03 PM PDT 24
Finished Jun 25 06:01:05 PM PDT 24
Peak memory 196716 kb
Host smart-b832e51e-95e6-46d8-8a47-96fcac52980a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136484426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.4136484426
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.4235125289
Short name T1157
Test name
Test status
Simulation time 1872574298 ps
CPU time 2.49 seconds
Started Jun 25 06:01:01 PM PDT 24
Finished Jun 25 06:01:05 PM PDT 24
Peak memory 198116 kb
Host smart-d5dbae70-5a0f-46d5-9de1-c6b29594265a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235125289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.4235125289
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3734810460
Short name T1192
Test name
Test status
Simulation time 15486648 ps
CPU time 0.56 seconds
Started Jun 25 06:01:06 PM PDT 24
Finished Jun 25 06:01:08 PM PDT 24
Peak memory 195804 kb
Host smart-9d90f301-8b18-4ef7-88ff-5475e00ff659
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734810460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3734810460
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2039289086
Short name T1206
Test name
Test status
Simulation time 55754702 ps
CPU time 0.73 seconds
Started Jun 25 06:01:01 PM PDT 24
Finished Jun 25 06:01:03 PM PDT 24
Peak memory 198984 kb
Host smart-503c2f70-3f21-4b67-85e8-8fc59b1d8003
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039289086 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2039289086
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2781850724
Short name T1152
Test name
Test status
Simulation time 14489148 ps
CPU time 0.59 seconds
Started Jun 25 06:01:03 PM PDT 24
Finished Jun 25 06:01:05 PM PDT 24
Peak memory 195852 kb
Host smart-b5f01f0a-95c0-4500-b7fb-fde1b51b8d1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781850724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2781850724
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.987844602
Short name T1185
Test name
Test status
Simulation time 47213299 ps
CPU time 0.57 seconds
Started Jun 25 06:01:04 PM PDT 24
Finished Jun 25 06:01:07 PM PDT 24
Peak memory 194768 kb
Host smart-7442fa96-2fbe-4269-bd03-e03db1eedf32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987844602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.987844602
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1014928923
Short name T71
Test name
Test status
Simulation time 26218791 ps
CPU time 0.7 seconds
Started Jun 25 06:01:03 PM PDT 24
Finished Jun 25 06:01:05 PM PDT 24
Peak memory 195316 kb
Host smart-fc1fea48-7166-456a-b84f-f35cf9261d63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014928923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.1014928923
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.2980501629
Short name T1215
Test name
Test status
Simulation time 45676926 ps
CPU time 2.22 seconds
Started Jun 25 06:01:06 PM PDT 24
Finished Jun 25 06:01:09 PM PDT 24
Peak memory 200440 kb
Host smart-2c4a4af0-230c-45b6-8860-cdc70f3e0708
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980501629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2980501629
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3439258055
Short name T81
Test name
Test status
Simulation time 352925366 ps
CPU time 1.33 seconds
Started Jun 25 06:01:03 PM PDT 24
Finished Jun 25 06:01:06 PM PDT 24
Peak memory 199712 kb
Host smart-05c63ba1-7a1b-41d4-b931-4ed78975388f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439258055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3439258055
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.901190639
Short name T1218
Test name
Test status
Simulation time 13154177 ps
CPU time 0.61 seconds
Started Jun 25 06:01:40 PM PDT 24
Finished Jun 25 06:01:44 PM PDT 24
Peak memory 194844 kb
Host smart-f46c388b-536c-4c37-a111-503ec8af7c85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901190639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.901190639
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.1501311630
Short name T1099
Test name
Test status
Simulation time 42265866 ps
CPU time 0.56 seconds
Started Jun 25 06:01:41 PM PDT 24
Finished Jun 25 06:01:44 PM PDT 24
Peak memory 194708 kb
Host smart-fcb4f1e3-6404-423c-857a-f88c27842524
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501311630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1501311630
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.2486485708
Short name T1102
Test name
Test status
Simulation time 19789342 ps
CPU time 0.63 seconds
Started Jun 25 06:01:44 PM PDT 24
Finished Jun 25 06:01:46 PM PDT 24
Peak memory 194804 kb
Host smart-6dbf3c9a-85fb-44e1-8223-4d6d8391d70f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486485708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2486485708
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.3721588805
Short name T1187
Test name
Test status
Simulation time 72433392 ps
CPU time 0.57 seconds
Started Jun 25 06:01:41 PM PDT 24
Finished Jun 25 06:01:44 PM PDT 24
Peak memory 194772 kb
Host smart-c987eaa5-48a0-477c-95cd-31327d8114bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721588805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3721588805
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.1854292130
Short name T1132
Test name
Test status
Simulation time 13904208 ps
CPU time 0.55 seconds
Started Jun 25 06:01:39 PM PDT 24
Finished Jun 25 06:01:40 PM PDT 24
Peak memory 194844 kb
Host smart-5bd3c0fe-3b0e-4faa-af08-7a61ed19fff8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854292130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.1854292130
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2391031956
Short name T1105
Test name
Test status
Simulation time 100341532 ps
CPU time 0.59 seconds
Started Jun 25 06:01:39 PM PDT 24
Finished Jun 25 06:01:40 PM PDT 24
Peak memory 194828 kb
Host smart-8d5c20dd-7534-4f78-954b-72172406a277
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391031956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2391031956
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.1710627368
Short name T1139
Test name
Test status
Simulation time 28779951 ps
CPU time 0.58 seconds
Started Jun 25 06:01:39 PM PDT 24
Finished Jun 25 06:01:41 PM PDT 24
Peak memory 194824 kb
Host smart-4112c4cf-0ac4-45a3-a66f-c80357f58046
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710627368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1710627368
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.110263744
Short name T1092
Test name
Test status
Simulation time 15091141 ps
CPU time 0.57 seconds
Started Jun 25 06:01:38 PM PDT 24
Finished Jun 25 06:01:40 PM PDT 24
Peak memory 194756 kb
Host smart-d1fcbca1-68ed-49a7-9454-4d9002e69353
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110263744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.110263744
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.1879394316
Short name T1213
Test name
Test status
Simulation time 14267411 ps
CPU time 0.58 seconds
Started Jun 25 06:01:40 PM PDT 24
Finished Jun 25 06:01:43 PM PDT 24
Peak memory 194820 kb
Host smart-3214f1ea-53cb-472d-8e3b-eeb9369504d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879394316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.1879394316
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.4100186724
Short name T1202
Test name
Test status
Simulation time 24518383 ps
CPU time 0.56 seconds
Started Jun 25 06:01:39 PM PDT 24
Finished Jun 25 06:01:41 PM PDT 24
Peak memory 194828 kb
Host smart-95b4da00-ef49-4cd8-850c-db32b87fcaf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100186724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.4100186724
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2880521613
Short name T1179
Test name
Test status
Simulation time 37005319 ps
CPU time 0.87 seconds
Started Jun 25 06:01:04 PM PDT 24
Finished Jun 25 06:01:07 PM PDT 24
Peak memory 200196 kb
Host smart-d7e44682-9244-4289-9a66-24cfe1d77b2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880521613 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.2880521613
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3788221850
Short name T1123
Test name
Test status
Simulation time 13073507 ps
CPU time 0.58 seconds
Started Jun 25 06:01:04 PM PDT 24
Finished Jun 25 06:01:06 PM PDT 24
Peak memory 195828 kb
Host smart-5916e364-b7b9-4705-9492-f74911019297
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788221850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3788221850
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3746163064
Short name T1219
Test name
Test status
Simulation time 49429212 ps
CPU time 0.62 seconds
Started Jun 25 06:01:00 PM PDT 24
Finished Jun 25 06:01:02 PM PDT 24
Peak memory 194772 kb
Host smart-4d5dcbcb-780a-459b-ab94-d144730e15b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746163064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3746163064
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3091940438
Short name T1125
Test name
Test status
Simulation time 33866719 ps
CPU time 0.7 seconds
Started Jun 25 06:01:02 PM PDT 24
Finished Jun 25 06:01:05 PM PDT 24
Peak memory 195980 kb
Host smart-68e13592-bd8d-4bb0-b5b9-84e6cf085a13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091940438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.3091940438
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.4163742008
Short name T1100
Test name
Test status
Simulation time 198630475 ps
CPU time 1.16 seconds
Started Jun 25 06:01:02 PM PDT 24
Finished Jun 25 06:01:05 PM PDT 24
Peak memory 200396 kb
Host smart-89b72865-9419-483f-a2fc-c6f666d63535
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163742008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.4163742008
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.841772778
Short name T89
Test name
Test status
Simulation time 250351948 ps
CPU time 1.37 seconds
Started Jun 25 06:01:03 PM PDT 24
Finished Jun 25 06:01:06 PM PDT 24
Peak memory 199776 kb
Host smart-d0052ba1-83ba-45e9-9871-4af3009c37e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841772778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.841772778
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1709746736
Short name T1186
Test name
Test status
Simulation time 111885819 ps
CPU time 0.81 seconds
Started Jun 25 06:01:07 PM PDT 24
Finished Jun 25 06:01:09 PM PDT 24
Peak memory 199596 kb
Host smart-2cd647b1-5971-48c8-96b0-84aa24df9797
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709746736 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1709746736
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.1043400174
Short name T62
Test name
Test status
Simulation time 11839098 ps
CPU time 0.57 seconds
Started Jun 25 06:01:01 PM PDT 24
Finished Jun 25 06:01:03 PM PDT 24
Peak memory 195832 kb
Host smart-3807d1e5-c238-4520-8f53-ce41fffbe1e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043400174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1043400174
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.855873025
Short name T1177
Test name
Test status
Simulation time 13332954 ps
CPU time 0.58 seconds
Started Jun 25 06:01:01 PM PDT 24
Finished Jun 25 06:01:03 PM PDT 24
Peak memory 194692 kb
Host smart-c665d335-65cc-429d-8a7e-07e21030bb2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855873025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.855873025
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.16659727
Short name T1188
Test name
Test status
Simulation time 468455046 ps
CPU time 0.79 seconds
Started Jun 25 06:01:03 PM PDT 24
Finished Jun 25 06:01:05 PM PDT 24
Peak memory 196280 kb
Host smart-e81369c4-9702-4f74-b297-45c3226d2ce8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16659727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_o
utstanding.16659727
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.4092241393
Short name T1166
Test name
Test status
Simulation time 261528987 ps
CPU time 2.72 seconds
Started Jun 25 06:01:04 PM PDT 24
Finished Jun 25 06:01:08 PM PDT 24
Peak memory 200492 kb
Host smart-5acb155e-3557-44d7-9c2e-b1e9ae29f4f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092241393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.4092241393
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.28205037
Short name T1151
Test name
Test status
Simulation time 41537459 ps
CPU time 0.9 seconds
Started Jun 25 06:01:03 PM PDT 24
Finished Jun 25 06:01:05 PM PDT 24
Peak memory 199092 kb
Host smart-9d469cca-bff7-4f1c-ae0f-ed20263d3ead
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28205037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.28205037
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3104099742
Short name T1141
Test name
Test status
Simulation time 89550621 ps
CPU time 0.76 seconds
Started Jun 25 06:01:10 PM PDT 24
Finished Jun 25 06:01:12 PM PDT 24
Peak memory 199568 kb
Host smart-b2339e5d-f2f3-4f8f-b4c5-be8688e8cab9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104099742 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.3104099742
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1998641143
Short name T68
Test name
Test status
Simulation time 33511600 ps
CPU time 0.59 seconds
Started Jun 25 06:01:09 PM PDT 24
Finished Jun 25 06:01:10 PM PDT 24
Peak memory 195832 kb
Host smart-d75d8ff1-fdd0-4d2c-adbd-e45c5290bf27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998641143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1998641143
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.2376574564
Short name T1108
Test name
Test status
Simulation time 10964525 ps
CPU time 0.56 seconds
Started Jun 25 06:01:07 PM PDT 24
Finished Jun 25 06:01:09 PM PDT 24
Peak memory 194780 kb
Host smart-bd9357e9-9b32-4246-9b01-c42b5e508210
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376574564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2376574564
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3280974863
Short name T1155
Test name
Test status
Simulation time 36053361 ps
CPU time 0.66 seconds
Started Jun 25 06:01:10 PM PDT 24
Finished Jun 25 06:01:12 PM PDT 24
Peak memory 197032 kb
Host smart-35d76efc-ea3b-4626-ae58-a0a9b84b9c2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280974863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.3280974863
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.3718889186
Short name T1096
Test name
Test status
Simulation time 63523513 ps
CPU time 1.6 seconds
Started Jun 25 06:01:02 PM PDT 24
Finished Jun 25 06:01:06 PM PDT 24
Peak memory 200472 kb
Host smart-65764670-4c3d-480a-b02b-4a8c92b39a89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718889186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.3718889186
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.731095378
Short name T1160
Test name
Test status
Simulation time 267316953 ps
CPU time 1.24 seconds
Started Jun 25 06:01:02 PM PDT 24
Finished Jun 25 06:01:05 PM PDT 24
Peak memory 199636 kb
Host smart-9705dddb-1d32-4112-80c1-2b5fb4e6f31d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731095378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.731095378
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.257052784
Short name T1181
Test name
Test status
Simulation time 17630361 ps
CPU time 0.84 seconds
Started Jun 25 06:01:08 PM PDT 24
Finished Jun 25 06:01:10 PM PDT 24
Peak memory 200280 kb
Host smart-d228ccec-cc8f-42e5-b7ca-84f34c84737c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257052784 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.257052784
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.2966038960
Short name T58
Test name
Test status
Simulation time 14695808 ps
CPU time 0.57 seconds
Started Jun 25 06:01:09 PM PDT 24
Finished Jun 25 06:01:11 PM PDT 24
Peak memory 195776 kb
Host smart-3e9e273b-f745-4364-8225-dab1a748f808
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966038960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.2966038960
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.2014397645
Short name T1207
Test name
Test status
Simulation time 49103186 ps
CPU time 0.58 seconds
Started Jun 25 06:01:10 PM PDT 24
Finished Jun 25 06:01:12 PM PDT 24
Peak memory 194816 kb
Host smart-264b9592-22e5-4208-be9d-9d2b87d7087e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014397645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2014397645
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.259251823
Short name T1190
Test name
Test status
Simulation time 203230549 ps
CPU time 0.64 seconds
Started Jun 25 06:01:12 PM PDT 24
Finished Jun 25 06:01:14 PM PDT 24
Peak memory 194980 kb
Host smart-b62df4bd-1281-4503-824e-1d38d55a8e8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259251823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_
outstanding.259251823
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.4026861201
Short name T1205
Test name
Test status
Simulation time 251528015 ps
CPU time 1.32 seconds
Started Jun 25 06:01:15 PM PDT 24
Finished Jun 25 06:01:17 PM PDT 24
Peak memory 199536 kb
Host smart-176697ec-bd18-48c8-a8bc-dc8e1d610a87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026861201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.4026861201
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2505305949
Short name T86
Test name
Test status
Simulation time 48834034 ps
CPU time 0.91 seconds
Started Jun 25 06:01:09 PM PDT 24
Finished Jun 25 06:01:11 PM PDT 24
Peak memory 199360 kb
Host smart-00aaf546-157f-4c35-ae71-742dc94b0d61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505305949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2505305949
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.834243523
Short name T1094
Test name
Test status
Simulation time 101129029 ps
CPU time 0.65 seconds
Started Jun 25 06:01:10 PM PDT 24
Finished Jun 25 06:01:12 PM PDT 24
Peak memory 197968 kb
Host smart-a5ab56df-dd6c-44f6-b5b9-c58764ee4128
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834243523 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.834243523
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.2935474106
Short name T1222
Test name
Test status
Simulation time 19187591 ps
CPU time 0.59 seconds
Started Jun 25 06:01:15 PM PDT 24
Finished Jun 25 06:01:16 PM PDT 24
Peak memory 195080 kb
Host smart-a012d3d2-eb9c-4fdc-ac5f-1c9535e80a34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935474106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2935474106
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.2050406031
Short name T1129
Test name
Test status
Simulation time 34637044 ps
CPU time 0.58 seconds
Started Jun 25 06:01:14 PM PDT 24
Finished Jun 25 06:01:16 PM PDT 24
Peak memory 194816 kb
Host smart-0362588e-9d76-47e5-949f-39fba8342a15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050406031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2050406031
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1349801949
Short name T1221
Test name
Test status
Simulation time 13799383 ps
CPU time 0.64 seconds
Started Jun 25 06:01:14 PM PDT 24
Finished Jun 25 06:01:16 PM PDT 24
Peak memory 195052 kb
Host smart-cf29f24a-5866-4b20-9605-31850b1def0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349801949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.1349801949
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.2330297991
Short name T1114
Test name
Test status
Simulation time 37612991 ps
CPU time 1.87 seconds
Started Jun 25 06:01:10 PM PDT 24
Finished Jun 25 06:01:14 PM PDT 24
Peak memory 200476 kb
Host smart-6f46e5c5-d77a-43da-8008-8bcd53d21baf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330297991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2330297991
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.620944222
Short name T1154
Test name
Test status
Simulation time 326889228 ps
CPU time 1 seconds
Started Jun 25 06:01:12 PM PDT 24
Finished Jun 25 06:01:14 PM PDT 24
Peak memory 199652 kb
Host smart-3ee53867-8418-40ab-a0ac-4bcf675f1036
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620944222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.620944222
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_fifo_full.2402544104
Short name T821
Test name
Test status
Simulation time 29124198617 ps
CPU time 45.88 seconds
Started Jun 25 05:12:23 PM PDT 24
Finished Jun 25 05:13:12 PM PDT 24
Peak memory 200084 kb
Host smart-0ae20108-a318-447a-bdb9-b8578db933a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402544104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2402544104
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.370617004
Short name T896
Test name
Test status
Simulation time 108216885951 ps
CPU time 31.33 seconds
Started Jun 25 05:12:23 PM PDT 24
Finished Jun 25 05:12:57 PM PDT 24
Peak memory 199492 kb
Host smart-67d46a61-db9f-4fa9-97a1-9719c420bf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370617004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.370617004
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.1116085772
Short name T890
Test name
Test status
Simulation time 125539537447 ps
CPU time 47.1 seconds
Started Jun 25 05:12:20 PM PDT 24
Finished Jun 25 05:13:08 PM PDT 24
Peak memory 199832 kb
Host smart-d06d8066-fa18-4a23-a716-a45eb0459be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116085772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.1116085772
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.3948906520
Short name T553
Test name
Test status
Simulation time 6308630713 ps
CPU time 5.31 seconds
Started Jun 25 05:12:22 PM PDT 24
Finished Jun 25 05:12:30 PM PDT 24
Peak memory 199760 kb
Host smart-d72a4532-b003-489d-8f99-e72e0168fee9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948906520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3948906520
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.4027715881
Short name T322
Test name
Test status
Simulation time 109390124828 ps
CPU time 311.47 seconds
Started Jun 25 05:12:23 PM PDT 24
Finished Jun 25 05:17:37 PM PDT 24
Peak memory 199916 kb
Host smart-d77d8371-ac5a-462e-a953-961a56ae3adb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4027715881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.4027715881
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.327894475
Short name T886
Test name
Test status
Simulation time 7833962878 ps
CPU time 8.14 seconds
Started Jun 25 05:12:23 PM PDT 24
Finished Jun 25 05:12:34 PM PDT 24
Peak memory 199048 kb
Host smart-e8497046-e00d-4c4d-8dda-18cfca4bf357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327894475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.327894475
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_perf.3458252018
Short name T43
Test name
Test status
Simulation time 12233306265 ps
CPU time 180.24 seconds
Started Jun 25 05:12:25 PM PDT 24
Finished Jun 25 05:15:27 PM PDT 24
Peak memory 199824 kb
Host smart-f3906efc-04af-4288-8689-d80b1dbe6137
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3458252018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3458252018
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.2641592586
Short name T49
Test name
Test status
Simulation time 3202031587 ps
CPU time 6.07 seconds
Started Jun 25 05:12:21 PM PDT 24
Finished Jun 25 05:12:29 PM PDT 24
Peak memory 197956 kb
Host smart-74b5fb9e-8c07-463a-856f-85c5d82ad07c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2641592586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2641592586
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.1993888172
Short name T801
Test name
Test status
Simulation time 100561829753 ps
CPU time 39.9 seconds
Started Jun 25 05:12:26 PM PDT 24
Finished Jun 25 05:13:08 PM PDT 24
Peak memory 199856 kb
Host smart-9091f07e-cc87-4618-8371-b78729ee2532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993888172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.1993888172
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.145042058
Short name T827
Test name
Test status
Simulation time 42642181538 ps
CPU time 10.67 seconds
Started Jun 25 05:12:22 PM PDT 24
Finished Jun 25 05:12:36 PM PDT 24
Peak memory 195896 kb
Host smart-e4a7c34f-b3a0-4741-b604-cbd7316ea421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145042058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.145042058
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.468242733
Short name T450
Test name
Test status
Simulation time 276092685 ps
CPU time 1.19 seconds
Started Jun 25 05:12:26 PM PDT 24
Finished Jun 25 05:12:28 PM PDT 24
Peak memory 198196 kb
Host smart-579007f8-82d8-4500-bea0-51eeba9fac20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468242733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.468242733
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.2937937459
Short name T1054
Test name
Test status
Simulation time 85277707795 ps
CPU time 80.58 seconds
Started Jun 25 05:12:24 PM PDT 24
Finished Jun 25 05:13:47 PM PDT 24
Peak memory 199812 kb
Host smart-004c2dcf-203f-4d9e-8222-e7fc7aae8519
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937937459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.2937937459
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.694043477
Short name T583
Test name
Test status
Simulation time 6473638441 ps
CPU time 25 seconds
Started Jun 25 05:12:23 PM PDT 24
Finished Jun 25 05:12:50 PM PDT 24
Peak memory 199876 kb
Host smart-5055f998-fd4d-4ff0-93c7-70d9a62c92fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694043477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.694043477
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.3464999081
Short name T895
Test name
Test status
Simulation time 19988836917 ps
CPU time 9.03 seconds
Started Jun 25 05:12:23 PM PDT 24
Finished Jun 25 05:12:35 PM PDT 24
Peak memory 199176 kb
Host smart-b605ca4e-3f30-4db2-8c43-5e48cd8ce72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464999081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3464999081
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.1382146510
Short name T659
Test name
Test status
Simulation time 15617530 ps
CPU time 0.58 seconds
Started Jun 25 05:12:34 PM PDT 24
Finished Jun 25 05:12:36 PM PDT 24
Peak memory 195152 kb
Host smart-83f5c8cc-8748-4660-9124-3e9ff08e635c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382146510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.1382146510
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.2523642201
Short name T320
Test name
Test status
Simulation time 68560129639 ps
CPU time 40.79 seconds
Started Jun 25 05:12:34 PM PDT 24
Finished Jun 25 05:13:16 PM PDT 24
Peak memory 199848 kb
Host smart-0ac23ab8-6921-459f-91a0-6827a2b0669d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523642201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.2523642201
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.115444188
Short name T948
Test name
Test status
Simulation time 166223649135 ps
CPU time 213.82 seconds
Started Jun 25 05:12:35 PM PDT 24
Finished Jun 25 05:16:10 PM PDT 24
Peak memory 199848 kb
Host smart-aef396dc-ba2f-434a-9f41-ad9b8eec2708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115444188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.115444188
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.3492133754
Short name T183
Test name
Test status
Simulation time 15796445526 ps
CPU time 26.2 seconds
Started Jun 25 05:12:34 PM PDT 24
Finished Jun 25 05:13:02 PM PDT 24
Peak memory 199404 kb
Host smart-dfab2b94-b8d8-4ce4-9dfb-7a24a5201b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492133754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3492133754
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.2545988895
Short name T356
Test name
Test status
Simulation time 9964856201 ps
CPU time 13.38 seconds
Started Jun 25 05:12:33 PM PDT 24
Finished Jun 25 05:12:48 PM PDT 24
Peak memory 196292 kb
Host smart-4a92d463-8651-4199-97a9-964d98a4d5e4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545988895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2545988895
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.1413867909
Short name T786
Test name
Test status
Simulation time 133939297406 ps
CPU time 529.49 seconds
Started Jun 25 05:12:37 PM PDT 24
Finished Jun 25 05:21:27 PM PDT 24
Peak memory 199880 kb
Host smart-223a99f5-1e79-4ac1-81cc-1d9dfdf23950
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1413867909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1413867909
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.3827454635
Short name T484
Test name
Test status
Simulation time 8283878176 ps
CPU time 4.59 seconds
Started Jun 25 05:12:33 PM PDT 24
Finished Jun 25 05:12:39 PM PDT 24
Peak memory 199188 kb
Host smart-c84550d7-0f79-4342-8675-94061a287463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827454635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3827454635
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_perf.1585401068
Short name T516
Test name
Test status
Simulation time 20655225535 ps
CPU time 311.63 seconds
Started Jun 25 05:12:35 PM PDT 24
Finished Jun 25 05:17:48 PM PDT 24
Peak memory 199752 kb
Host smart-4c27fb11-ca06-44bc-917e-88d3d2d635a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1585401068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1585401068
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.1933923911
Short name T528
Test name
Test status
Simulation time 2249540348 ps
CPU time 3.44 seconds
Started Jun 25 05:12:36 PM PDT 24
Finished Jun 25 05:12:41 PM PDT 24
Peak memory 199080 kb
Host smart-6a285f1a-bf52-4036-9eaf-7352b00b7b1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1933923911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.1933923911
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.962358575
Short name T326
Test name
Test status
Simulation time 206707083655 ps
CPU time 85.83 seconds
Started Jun 25 05:12:34 PM PDT 24
Finished Jun 25 05:14:02 PM PDT 24
Peak memory 198940 kb
Host smart-f725c859-c1b8-421c-81d6-ef270b179fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962358575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.962358575
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.1470139388
Short name T312
Test name
Test status
Simulation time 6359691328 ps
CPU time 7.76 seconds
Started Jun 25 05:12:36 PM PDT 24
Finished Jun 25 05:12:45 PM PDT 24
Peak memory 196328 kb
Host smart-b7e92bd5-8e82-4dcb-8566-fe64e099738a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470139388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1470139388
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.3419363656
Short name T26
Test name
Test status
Simulation time 58112512 ps
CPU time 0.79 seconds
Started Jun 25 05:12:36 PM PDT 24
Finished Jun 25 05:12:38 PM PDT 24
Peak memory 218348 kb
Host smart-84c5ade9-3bcb-49ce-9df9-baa075910775
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419363656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3419363656
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.2161787006
Short name T995
Test name
Test status
Simulation time 5448678733 ps
CPU time 16.36 seconds
Started Jun 25 05:12:33 PM PDT 24
Finished Jun 25 05:12:51 PM PDT 24
Peak memory 199644 kb
Host smart-c99f3877-8769-4280-9852-8728c535354c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161787006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2161787006
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.1587556051
Short name T106
Test name
Test status
Simulation time 74526113128 ps
CPU time 217.11 seconds
Started Jun 25 05:12:32 PM PDT 24
Finished Jun 25 05:16:10 PM PDT 24
Peak memory 216088 kb
Host smart-38ade96b-69e0-4c69-ae14-741094bc3047
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587556051 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.1587556051
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.1447791832
Short name T759
Test name
Test status
Simulation time 10584236194 ps
CPU time 8.04 seconds
Started Jun 25 05:12:35 PM PDT 24
Finished Jun 25 05:12:44 PM PDT 24
Peak memory 199736 kb
Host smart-012874c7-2df6-42da-b149-1078254e9846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447791832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.1447791832
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.2955097334
Short name T477
Test name
Test status
Simulation time 60663748310 ps
CPU time 25.52 seconds
Started Jun 25 05:12:32 PM PDT 24
Finished Jun 25 05:13:00 PM PDT 24
Peak memory 199888 kb
Host smart-5455ea57-6137-4d64-b143-139d2c793428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955097334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.2955097334
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.3331666811
Short name T385
Test name
Test status
Simulation time 12492079 ps
CPU time 0.57 seconds
Started Jun 25 05:13:02 PM PDT 24
Finished Jun 25 05:13:05 PM PDT 24
Peak memory 195516 kb
Host smart-d798b068-d6c9-4ae9-a821-6d85b69c46aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331666811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3331666811
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.1251461971
Short name T1083
Test name
Test status
Simulation time 137281703505 ps
CPU time 220.21 seconds
Started Jun 25 05:12:55 PM PDT 24
Finished Jun 25 05:16:37 PM PDT 24
Peak memory 199856 kb
Host smart-5fe600d6-a549-48b7-b59e-74bdc655099c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251461971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.1251461971
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_intr.1270137496
Short name T817
Test name
Test status
Simulation time 308490288360 ps
CPU time 113.36 seconds
Started Jun 25 05:12:58 PM PDT 24
Finished Jun 25 05:14:53 PM PDT 24
Peak memory 199328 kb
Host smart-8cbebd35-ed94-4856-a0ec-cdc55f1be759
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270137496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1270137496
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.1010366285
Short name T1048
Test name
Test status
Simulation time 160111644722 ps
CPU time 121.73 seconds
Started Jun 25 05:13:03 PM PDT 24
Finished Jun 25 05:15:07 PM PDT 24
Peak memory 200028 kb
Host smart-6fa59dd1-6727-4152-89eb-ca51270b9c6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1010366285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.1010366285
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.235654640
Short name T550
Test name
Test status
Simulation time 8607158483 ps
CPU time 13.9 seconds
Started Jun 25 05:13:01 PM PDT 24
Finished Jun 25 05:13:18 PM PDT 24
Peak memory 199756 kb
Host smart-fea64ba1-89ed-4ad1-ae62-75e1317226d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235654640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.235654640
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_perf.2471366742
Short name T529
Test name
Test status
Simulation time 10391953051 ps
CPU time 290.94 seconds
Started Jun 25 05:13:06 PM PDT 24
Finished Jun 25 05:17:58 PM PDT 24
Peak memory 199840 kb
Host smart-a3d06f5a-d65b-4ab9-b902-b068d93f98c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2471366742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2471366742
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.3403851009
Short name T418
Test name
Test status
Simulation time 5147329385 ps
CPU time 24.78 seconds
Started Jun 25 05:13:01 PM PDT 24
Finished Jun 25 05:13:28 PM PDT 24
Peak memory 197668 kb
Host smart-44d6e50a-3b6c-4122-9b0d-288447f167bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3403851009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.3403851009
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.1411752417
Short name T121
Test name
Test status
Simulation time 47971204764 ps
CPU time 26.25 seconds
Started Jun 25 05:13:05 PM PDT 24
Finished Jun 25 05:13:32 PM PDT 24
Peak memory 199920 kb
Host smart-71637267-21d2-432e-a211-ffe37d45af50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411752417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1411752417
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.788806007
Short name T1042
Test name
Test status
Simulation time 4670850705 ps
CPU time 7.67 seconds
Started Jun 25 05:13:03 PM PDT 24
Finished Jun 25 05:13:12 PM PDT 24
Peak memory 196272 kb
Host smart-a70c5505-c2f5-4879-8828-0c350d3105d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788806007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.788806007
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.1079929294
Short name T630
Test name
Test status
Simulation time 693159427 ps
CPU time 3.29 seconds
Started Jun 25 05:12:58 PM PDT 24
Finished Jun 25 05:13:03 PM PDT 24
Peak memory 198268 kb
Host smart-9e22b52b-0490-4457-9a27-605831885dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079929294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.1079929294
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.1057852296
Short name T310
Test name
Test status
Simulation time 93060770129 ps
CPU time 327.96 seconds
Started Jun 25 05:12:59 PM PDT 24
Finished Jun 25 05:18:30 PM PDT 24
Peak memory 215620 kb
Host smart-ea33b62c-6fe5-4018-81bf-681194036d9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057852296 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.1057852296
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.3771140889
Short name T609
Test name
Test status
Simulation time 1043740197 ps
CPU time 1.18 seconds
Started Jun 25 05:13:10 PM PDT 24
Finished Jun 25 05:13:12 PM PDT 24
Peak memory 198052 kb
Host smart-ef948158-3426-4ead-b3ab-f12b01967397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771140889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3771140889
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.2987602722
Short name T863
Test name
Test status
Simulation time 7930536655 ps
CPU time 13.69 seconds
Started Jun 25 05:12:55 PM PDT 24
Finished Jun 25 05:13:09 PM PDT 24
Peak memory 197972 kb
Host smart-429eeb4a-38c7-4785-8ff7-5b54dbd680ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987602722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2987602722
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.596823942
Short name T434
Test name
Test status
Simulation time 72593348463 ps
CPU time 68.19 seconds
Started Jun 25 05:16:19 PM PDT 24
Finished Jun 25 05:17:29 PM PDT 24
Peak memory 199840 kb
Host smart-ae962b21-d629-4a0e-9f7a-d6534dd7769a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596823942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.596823942
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.138538543
Short name T29
Test name
Test status
Simulation time 127382218948 ps
CPU time 38.51 seconds
Started Jun 25 05:16:19 PM PDT 24
Finished Jun 25 05:16:59 PM PDT 24
Peak memory 199908 kb
Host smart-df9dafa1-05d4-4576-b967-d1bf4e67e616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138538543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.138538543
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1921345447
Short name T616
Test name
Test status
Simulation time 99368390625 ps
CPU time 300.5 seconds
Started Jun 25 05:16:20 PM PDT 24
Finished Jun 25 05:21:22 PM PDT 24
Peak memory 199908 kb
Host smart-74eb3b2a-8006-4529-bb2e-70429ad9590a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921345447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1921345447
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.154659569
Short name T188
Test name
Test status
Simulation time 100658626676 ps
CPU time 33.29 seconds
Started Jun 25 05:16:20 PM PDT 24
Finished Jun 25 05:16:55 PM PDT 24
Peak memory 199840 kb
Host smart-a1d04510-a266-45fe-83fa-043a6322ddcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154659569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.154659569
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.3317268927
Short name T912
Test name
Test status
Simulation time 19855077707 ps
CPU time 16.99 seconds
Started Jun 25 05:16:20 PM PDT 24
Finished Jun 25 05:16:39 PM PDT 24
Peak memory 199836 kb
Host smart-33ca581e-313d-4011-a164-c8c9cfe07e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317268927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.3317268927
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.2860115797
Short name T300
Test name
Test status
Simulation time 9506044941 ps
CPU time 12.1 seconds
Started Jun 25 05:16:19 PM PDT 24
Finished Jun 25 05:16:33 PM PDT 24
Peak memory 198336 kb
Host smart-800e5ddf-99a6-4d81-b1e5-70e8723ecb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860115797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2860115797
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.2670177746
Short name T911
Test name
Test status
Simulation time 67332573524 ps
CPU time 27.3 seconds
Started Jun 25 05:16:19 PM PDT 24
Finished Jun 25 05:16:48 PM PDT 24
Peak memory 199808 kb
Host smart-3cea0f32-ab51-48f1-88f2-ccf696115054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670177746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.2670177746
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.183323068
Short name T640
Test name
Test status
Simulation time 15161701 ps
CPU time 0.6 seconds
Started Jun 25 05:13:01 PM PDT 24
Finished Jun 25 05:13:04 PM PDT 24
Peak memory 195212 kb
Host smart-db040637-8d48-449a-9ff6-1dddb79bfda3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183323068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.183323068
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.305277209
Short name T164
Test name
Test status
Simulation time 60062484211 ps
CPU time 21.81 seconds
Started Jun 25 05:13:03 PM PDT 24
Finished Jun 25 05:13:27 PM PDT 24
Peak memory 199824 kb
Host smart-43e7b469-8bc5-4e3e-93ac-71db90b32df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305277209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.305277209
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.2790257327
Short name T389
Test name
Test status
Simulation time 27054261592 ps
CPU time 51.25 seconds
Started Jun 25 05:13:01 PM PDT 24
Finished Jun 25 05:13:55 PM PDT 24
Peak memory 199696 kb
Host smart-42a123fc-b547-4355-a8fb-452b42011b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790257327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.2790257327
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.161330224
Short name T213
Test name
Test status
Simulation time 168082815744 ps
CPU time 54.56 seconds
Started Jun 25 05:13:02 PM PDT 24
Finished Jun 25 05:13:59 PM PDT 24
Peak memory 199880 kb
Host smart-8e5b3c38-f5b4-450b-a0ab-f78960c39975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161330224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.161330224
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.3289932039
Short name T13
Test name
Test status
Simulation time 289611176268 ps
CPU time 376.78 seconds
Started Jun 25 05:13:01 PM PDT 24
Finished Jun 25 05:19:20 PM PDT 24
Peak memory 199040 kb
Host smart-07c30a85-90ed-403e-aa81-3f98794626f4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289932039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.3289932039
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.4077941997
Short name T974
Test name
Test status
Simulation time 124272276800 ps
CPU time 245.66 seconds
Started Jun 25 05:13:03 PM PDT 24
Finished Jun 25 05:17:10 PM PDT 24
Peak memory 199740 kb
Host smart-901d484f-f82c-46ed-af4e-cdc769e405e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4077941997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.4077941997
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.102113026
Short name T519
Test name
Test status
Simulation time 8559282158 ps
CPU time 12.15 seconds
Started Jun 25 05:13:03 PM PDT 24
Finished Jun 25 05:13:17 PM PDT 24
Peak memory 199780 kb
Host smart-a7023e49-640f-44b3-b178-04dff7f686f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102113026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.102113026
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_perf.4192845891
Short name T850
Test name
Test status
Simulation time 30609877378 ps
CPU time 419.55 seconds
Started Jun 25 05:13:06 PM PDT 24
Finished Jun 25 05:20:07 PM PDT 24
Peak memory 199900 kb
Host smart-d40eb469-ff26-4fe4-81d1-aecc8819c158
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4192845891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.4192845891
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.3363456418
Short name T594
Test name
Test status
Simulation time 4410632336 ps
CPU time 37.55 seconds
Started Jun 25 05:13:03 PM PDT 24
Finished Jun 25 05:13:43 PM PDT 24
Peak memory 198932 kb
Host smart-2eba611e-3e73-44b0-a490-fda86451ed1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3363456418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3363456418
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.3446760383
Short name T1039
Test name
Test status
Simulation time 200757038500 ps
CPU time 80.5 seconds
Started Jun 25 05:13:00 PM PDT 24
Finished Jun 25 05:14:24 PM PDT 24
Peak memory 199896 kb
Host smart-26905a21-4b32-4d09-adcb-dbea987293d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446760383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3446760383
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.3608402892
Short name T278
Test name
Test status
Simulation time 1990732294 ps
CPU time 1.37 seconds
Started Jun 25 05:13:01 PM PDT 24
Finished Jun 25 05:13:05 PM PDT 24
Peak memory 195316 kb
Host smart-0bbc7859-beb5-4416-a9d4-7809f71d38c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608402892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.3608402892
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.3686051230
Short name T632
Test name
Test status
Simulation time 688326159 ps
CPU time 1.49 seconds
Started Jun 25 05:13:02 PM PDT 24
Finished Jun 25 05:13:06 PM PDT 24
Peak memory 199772 kb
Host smart-7da8d116-46bd-489a-87e8-6b6b75aa8f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686051230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3686051230
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.1955566735
Short name T465
Test name
Test status
Simulation time 1027230863 ps
CPU time 4.16 seconds
Started Jun 25 05:13:02 PM PDT 24
Finished Jun 25 05:13:08 PM PDT 24
Peak memory 199612 kb
Host smart-b2136a90-baf0-4b7c-a0ca-0dc7ce05e867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955566735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.1955566735
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.1597376576
Short name T802
Test name
Test status
Simulation time 15361527828 ps
CPU time 15.33 seconds
Started Jun 25 05:13:06 PM PDT 24
Finished Jun 25 05:13:22 PM PDT 24
Peak memory 199892 kb
Host smart-63aaaf19-c44e-4db9-a139-eaea779c3ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597376576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.1597376576
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1109266384
Short name T1058
Test name
Test status
Simulation time 181510036110 ps
CPU time 180.93 seconds
Started Jun 25 05:16:21 PM PDT 24
Finished Jun 25 05:19:23 PM PDT 24
Peak memory 199864 kb
Host smart-b6d9d663-e892-4e7f-82e7-67d4964c8922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109266384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1109266384
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3824209298
Short name T115
Test name
Test status
Simulation time 12922980167 ps
CPU time 28.32 seconds
Started Jun 25 05:16:18 PM PDT 24
Finished Jun 25 05:16:47 PM PDT 24
Peak memory 199904 kb
Host smart-bc457ce3-d9b6-4ca7-ba86-f3c60625217b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824209298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3824209298
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.665616509
Short name T779
Test name
Test status
Simulation time 42949945112 ps
CPU time 22.37 seconds
Started Jun 25 05:16:18 PM PDT 24
Finished Jun 25 05:16:42 PM PDT 24
Peak memory 199776 kb
Host smart-20115032-0dae-47a9-b825-8b992fb22558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665616509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.665616509
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.3498313804
Short name T218
Test name
Test status
Simulation time 5325260450 ps
CPU time 11.17 seconds
Started Jun 25 05:16:20 PM PDT 24
Finished Jun 25 05:16:33 PM PDT 24
Peak memory 199896 kb
Host smart-09ed89b7-ff41-44cf-8d59-ceba639c5adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498313804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.3498313804
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.3677068658
Short name T1088
Test name
Test status
Simulation time 6238622701 ps
CPU time 11.62 seconds
Started Jun 25 05:16:18 PM PDT 24
Finished Jun 25 05:16:31 PM PDT 24
Peak memory 199592 kb
Host smart-40a452fe-0f20-411d-9bd7-7e5b3f592587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677068658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3677068658
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.1122639219
Short name T5
Test name
Test status
Simulation time 23703242864 ps
CPU time 37.11 seconds
Started Jun 25 05:16:19 PM PDT 24
Finished Jun 25 05:16:58 PM PDT 24
Peak memory 199932 kb
Host smart-c96abdda-6333-491d-ba00-a806815f4391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122639219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1122639219
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2620995670
Short name T178
Test name
Test status
Simulation time 135210738735 ps
CPU time 64.47 seconds
Started Jun 25 05:16:21 PM PDT 24
Finished Jun 25 05:17:27 PM PDT 24
Peak memory 199848 kb
Host smart-c6d928d3-335d-4172-8c00-f714741dd392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620995670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2620995670
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.4083301273
Short name T987
Test name
Test status
Simulation time 172968745 ps
CPU time 0.55 seconds
Started Jun 25 05:13:12 PM PDT 24
Finished Jun 25 05:13:14 PM PDT 24
Peak memory 195520 kb
Host smart-68aa8d59-f83e-4868-a5a0-833dc5c8aff9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083301273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.4083301273
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.857512426
Short name T1043
Test name
Test status
Simulation time 54129557576 ps
CPU time 14.55 seconds
Started Jun 25 05:13:10 PM PDT 24
Finished Jun 25 05:13:26 PM PDT 24
Peak memory 199804 kb
Host smart-0fe77aeb-d2e1-49ef-96c2-6d2a5b3352a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857512426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.857512426
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2271550930
Short name T124
Test name
Test status
Simulation time 100469269534 ps
CPU time 36.81 seconds
Started Jun 25 05:13:10 PM PDT 24
Finished Jun 25 05:13:49 PM PDT 24
Peak memory 199648 kb
Host smart-6cdd7e75-2792-4b1c-a7a2-0a02896f2608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271550930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2271550930
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2787968589
Short name T488
Test name
Test status
Simulation time 128383221517 ps
CPU time 119.3 seconds
Started Jun 25 05:13:10 PM PDT 24
Finished Jun 25 05:15:11 PM PDT 24
Peak memory 199536 kb
Host smart-789c0212-d212-4c96-bb77-d93a95499620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787968589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2787968589
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.2794601000
Short name T629
Test name
Test status
Simulation time 41645875529 ps
CPU time 16.42 seconds
Started Jun 25 05:13:05 PM PDT 24
Finished Jun 25 05:13:22 PM PDT 24
Peak memory 197704 kb
Host smart-acb784c6-ab46-4b76-8859-e37617fbbd22
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794601000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2794601000
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1143891174
Short name T782
Test name
Test status
Simulation time 119642275026 ps
CPU time 621.91 seconds
Started Jun 25 05:13:02 PM PDT 24
Finished Jun 25 05:23:26 PM PDT 24
Peak memory 199824 kb
Host smart-2e226e8a-b6d9-4f05-9bc0-ca5983be83c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1143891174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1143891174
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.116101506
Short name T605
Test name
Test status
Simulation time 1645774883 ps
CPU time 3.37 seconds
Started Jun 25 05:13:03 PM PDT 24
Finished Jun 25 05:13:09 PM PDT 24
Peak memory 198368 kb
Host smart-27110986-4f4a-4357-8ba8-76014cd16619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116101506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.116101506
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_perf.3092134732
Short name T856
Test name
Test status
Simulation time 12487469261 ps
CPU time 472.61 seconds
Started Jun 25 05:13:10 PM PDT 24
Finished Jun 25 05:21:04 PM PDT 24
Peak memory 199816 kb
Host smart-908ba871-2398-4aa5-938b-ef3dd1a4d88e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3092134732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3092134732
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.3754655108
Short name T1057
Test name
Test status
Simulation time 3701213729 ps
CPU time 25.52 seconds
Started Jun 25 05:13:10 PM PDT 24
Finished Jun 25 05:13:37 PM PDT 24
Peak memory 197912 kb
Host smart-35d46b9f-fe01-4ec1-a212-8ca4d8c1b8d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3754655108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.3754655108
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.1845897288
Short name T937
Test name
Test status
Simulation time 17458060472 ps
CPU time 28.69 seconds
Started Jun 25 05:13:04 PM PDT 24
Finished Jun 25 05:13:34 PM PDT 24
Peak memory 199844 kb
Host smart-f356dd1c-e6b4-4935-846c-76fe68fa3eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845897288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1845897288
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.2168477003
Short name T1013
Test name
Test status
Simulation time 3137162307 ps
CPU time 1.92 seconds
Started Jun 25 05:13:04 PM PDT 24
Finished Jun 25 05:13:08 PM PDT 24
Peak memory 196140 kb
Host smart-a25373d4-cad1-4c99-97d9-a972eefa8416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168477003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2168477003
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.2805546439
Short name T894
Test name
Test status
Simulation time 91846167 ps
CPU time 0.79 seconds
Started Jun 25 05:13:10 PM PDT 24
Finished Jun 25 05:13:12 PM PDT 24
Peak memory 196708 kb
Host smart-85d4eaa3-686d-4fac-b2f3-5efb588cdb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805546439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2805546439
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3921859749
Short name T865
Test name
Test status
Simulation time 6783682988 ps
CPU time 26.3 seconds
Started Jun 25 05:13:04 PM PDT 24
Finished Jun 25 05:13:32 PM PDT 24
Peak memory 200000 kb
Host smart-2dedc576-d5b3-406a-a2d5-45eb2ecf9c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921859749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3921859749
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.3934156166
Short name T812
Test name
Test status
Simulation time 148642087634 ps
CPU time 62.83 seconds
Started Jun 25 05:13:01 PM PDT 24
Finished Jun 25 05:14:06 PM PDT 24
Peak memory 199872 kb
Host smart-6753d9aa-b705-4739-a138-27a37b56e219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934156166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.3934156166
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.1396171784
Short name T683
Test name
Test status
Simulation time 20290922365 ps
CPU time 31.84 seconds
Started Jun 25 05:16:20 PM PDT 24
Finished Jun 25 05:16:53 PM PDT 24
Peak memory 199476 kb
Host smart-7d3187bd-413f-45e6-9adc-4843418cbc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396171784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.1396171784
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.3277089559
Short name T568
Test name
Test status
Simulation time 150231836298 ps
CPU time 100.57 seconds
Started Jun 25 05:16:26 PM PDT 24
Finished Jun 25 05:18:08 PM PDT 24
Peak memory 199924 kb
Host smart-d71e774e-1288-429e-ad36-e86b63707fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277089559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3277089559
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.2132135193
Short name T343
Test name
Test status
Simulation time 19609052842 ps
CPU time 17.22 seconds
Started Jun 25 05:16:27 PM PDT 24
Finished Jun 25 05:16:46 PM PDT 24
Peak memory 199904 kb
Host smart-6c5cff0d-8d8e-49a7-b26c-72da4346f7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132135193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.2132135193
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.1813727868
Short name T1032
Test name
Test status
Simulation time 46511526984 ps
CPU time 37.84 seconds
Started Jun 25 05:16:26 PM PDT 24
Finished Jun 25 05:17:06 PM PDT 24
Peak memory 199720 kb
Host smart-38c3077e-8093-4e55-9f61-aeff56d2205a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813727868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1813727868
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1531876513
Short name T538
Test name
Test status
Simulation time 54996418554 ps
CPU time 24.19 seconds
Started Jun 25 05:16:26 PM PDT 24
Finished Jun 25 05:16:51 PM PDT 24
Peak memory 199744 kb
Host smart-2170fa87-a6c1-4619-81d8-fc10f4acac9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531876513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1531876513
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.2705760751
Short name T212
Test name
Test status
Simulation time 50194838268 ps
CPU time 84.54 seconds
Started Jun 25 05:16:26 PM PDT 24
Finished Jun 25 05:17:51 PM PDT 24
Peak memory 199784 kb
Host smart-5621a1df-9585-4eb0-9573-654d1612f5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705760751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2705760751
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.115463460
Short name T181
Test name
Test status
Simulation time 8103828511 ps
CPU time 12.14 seconds
Started Jun 25 05:16:28 PM PDT 24
Finished Jun 25 05:16:42 PM PDT 24
Peak memory 199892 kb
Host smart-5749341d-5a72-4d6d-bb05-235a42e94892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115463460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.115463460
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.2950093782
Short name T430
Test name
Test status
Simulation time 18045916516 ps
CPU time 27.01 seconds
Started Jun 25 05:16:27 PM PDT 24
Finished Jun 25 05:16:56 PM PDT 24
Peak memory 199820 kb
Host smart-a60983f5-1b8e-4729-9a9b-f86368faadab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950093782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2950093782
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.677265133
Short name T513
Test name
Test status
Simulation time 16276926449 ps
CPU time 27.28 seconds
Started Jun 25 05:16:27 PM PDT 24
Finished Jun 25 05:16:56 PM PDT 24
Peak memory 199724 kb
Host smart-e1eb4d56-33e2-4186-8ee2-8b9ea723f21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677265133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.677265133
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.278065685
Short name T381
Test name
Test status
Simulation time 11657441 ps
CPU time 0.53 seconds
Started Jun 25 05:13:10 PM PDT 24
Finished Jun 25 05:13:11 PM PDT 24
Peak memory 194868 kb
Host smart-17f399f2-e23b-45e1-9a22-795c61ab76be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278065685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.278065685
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.2765058263
Short name T628
Test name
Test status
Simulation time 22234445521 ps
CPU time 36.52 seconds
Started Jun 25 05:13:13 PM PDT 24
Finished Jun 25 05:13:51 PM PDT 24
Peak memory 199844 kb
Host smart-72d29e85-083c-416c-b2dd-709405d1381c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765058263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.2765058263
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.342216785
Short name T718
Test name
Test status
Simulation time 134737777546 ps
CPU time 48.71 seconds
Started Jun 25 05:13:12 PM PDT 24
Finished Jun 25 05:14:02 PM PDT 24
Peak memory 199840 kb
Host smart-e3a6328a-8908-4515-9ce3-6707a4b6901e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342216785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.342216785
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.1918030170
Short name T1052
Test name
Test status
Simulation time 63585950338 ps
CPU time 17.62 seconds
Started Jun 25 05:13:13 PM PDT 24
Finished Jun 25 05:13:31 PM PDT 24
Peak memory 199896 kb
Host smart-a1cd7ebb-0c91-4249-9c51-c632e1b804e3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918030170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1918030170
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.2807901282
Short name T714
Test name
Test status
Simulation time 160685338297 ps
CPU time 685.58 seconds
Started Jun 25 05:13:09 PM PDT 24
Finished Jun 25 05:24:36 PM PDT 24
Peak memory 199880 kb
Host smart-45a2ce3b-7b2a-4c9c-951e-79f23898519a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2807901282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2807901282
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.334450934
Short name T764
Test name
Test status
Simulation time 5738244229 ps
CPU time 5.52 seconds
Started Jun 25 05:13:12 PM PDT 24
Finished Jun 25 05:13:19 PM PDT 24
Peak memory 198980 kb
Host smart-05865a1b-fd74-407a-a93d-2367f60a6e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334450934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.334450934
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.3830912111
Short name T449
Test name
Test status
Simulation time 12396751243 ps
CPU time 18.91 seconds
Started Jun 25 05:13:13 PM PDT 24
Finished Jun 25 05:13:33 PM PDT 24
Peak memory 199960 kb
Host smart-a811dcd7-dcaf-4ec3-9763-57cb3c68910f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830912111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3830912111
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.1725330268
Short name T932
Test name
Test status
Simulation time 3676049461 ps
CPU time 7.14 seconds
Started Jun 25 05:13:10 PM PDT 24
Finished Jun 25 05:13:20 PM PDT 24
Peak memory 199084 kb
Host smart-c54598ac-eebe-41ec-9387-52d09673ca55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1725330268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.1725330268
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.1297264494
Short name T126
Test name
Test status
Simulation time 61434237620 ps
CPU time 28.04 seconds
Started Jun 25 05:13:12 PM PDT 24
Finished Jun 25 05:13:41 PM PDT 24
Peak memory 199740 kb
Host smart-0d9e43a4-4ec4-4d4d-b084-635e78d9c280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297264494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.1297264494
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.4014280340
Short name T1015
Test name
Test status
Simulation time 43792933970 ps
CPU time 17.98 seconds
Started Jun 25 05:13:17 PM PDT 24
Finished Jun 25 05:13:36 PM PDT 24
Peak memory 195860 kb
Host smart-7c2bbaf2-9167-4acc-bb7b-07cc0a3a13fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014280340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.4014280340
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.3348162148
Short name T432
Test name
Test status
Simulation time 312782987 ps
CPU time 1.58 seconds
Started Jun 25 05:13:11 PM PDT 24
Finished Jun 25 05:13:15 PM PDT 24
Peak memory 198232 kb
Host smart-3a11cacc-f818-46a2-96f6-b7814a3ed14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348162148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3348162148
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.3055302142
Short name T840
Test name
Test status
Simulation time 329982697843 ps
CPU time 242.12 seconds
Started Jun 25 05:13:13 PM PDT 24
Finished Jun 25 05:17:16 PM PDT 24
Peak memory 199692 kb
Host smart-6e0e6566-2898-4772-b44f-efad7d152b84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055302142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.3055302142
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.3921803089
Short name T298
Test name
Test status
Simulation time 2083343722 ps
CPU time 2.19 seconds
Started Jun 25 05:13:16 PM PDT 24
Finished Jun 25 05:13:19 PM PDT 24
Peak memory 198704 kb
Host smart-7b95d285-dc30-4b26-8174-d665263ca05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921803089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3921803089
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.1558212815
Short name T646
Test name
Test status
Simulation time 37310488471 ps
CPU time 53.51 seconds
Started Jun 25 05:13:10 PM PDT 24
Finished Jun 25 05:14:06 PM PDT 24
Peak memory 199784 kb
Host smart-ec150529-aca8-48bf-befb-981ffdf5d0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558212815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.1558212815
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2545658172
Short name T172
Test name
Test status
Simulation time 84667126051 ps
CPU time 47.96 seconds
Started Jun 25 05:16:27 PM PDT 24
Finished Jun 25 05:17:17 PM PDT 24
Peak memory 199864 kb
Host smart-431a90e8-9ff1-486e-850c-abb9908a29bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545658172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2545658172
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.2304735707
Short name T500
Test name
Test status
Simulation time 79602718821 ps
CPU time 73.55 seconds
Started Jun 25 05:16:27 PM PDT 24
Finished Jun 25 05:17:43 PM PDT 24
Peak memory 199844 kb
Host smart-9a9760f8-5c60-41d7-b102-34d32a7c8f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304735707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2304735707
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.3081826429
Short name T589
Test name
Test status
Simulation time 22193197905 ps
CPU time 17.07 seconds
Started Jun 25 05:16:30 PM PDT 24
Finished Jun 25 05:16:48 PM PDT 24
Peak memory 199440 kb
Host smart-97dfaccb-387f-4fa9-b334-76006d4e27c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081826429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3081826429
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.2574926074
Short name T731
Test name
Test status
Simulation time 114287052763 ps
CPU time 15.6 seconds
Started Jun 25 05:16:28 PM PDT 24
Finished Jun 25 05:16:46 PM PDT 24
Peak memory 199780 kb
Host smart-a0905c5f-4104-4452-8003-9c73b16908ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574926074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.2574926074
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.1324094715
Short name T601
Test name
Test status
Simulation time 133576496362 ps
CPU time 558.82 seconds
Started Jun 25 05:16:30 PM PDT 24
Finished Jun 25 05:25:50 PM PDT 24
Peak memory 199884 kb
Host smart-62a2a330-b622-49cb-83d1-08fe0159f750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324094715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1324094715
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.2359612168
Short name T189
Test name
Test status
Simulation time 117083729733 ps
CPU time 98.98 seconds
Started Jun 25 05:16:30 PM PDT 24
Finished Jun 25 05:18:10 PM PDT 24
Peak memory 199836 kb
Host smart-6144c51d-ab99-45a2-b033-eabb3bf4d5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359612168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.2359612168
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.1262279684
Short name T347
Test name
Test status
Simulation time 47751364693 ps
CPU time 59.95 seconds
Started Jun 25 05:16:27 PM PDT 24
Finished Jun 25 05:17:29 PM PDT 24
Peak memory 199840 kb
Host smart-cf598359-1882-42ea-9770-71d09f6632c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262279684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1262279684
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.3119646281
Short name T146
Test name
Test status
Simulation time 57077074552 ps
CPU time 23.13 seconds
Started Jun 25 05:16:30 PM PDT 24
Finished Jun 25 05:16:55 PM PDT 24
Peak memory 199612 kb
Host smart-38b817d0-a6b4-4bc2-8718-894370aa47a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119646281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.3119646281
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.2480008653
Short name T772
Test name
Test status
Simulation time 19025475 ps
CPU time 0.54 seconds
Started Jun 25 05:13:19 PM PDT 24
Finished Jun 25 05:13:21 PM PDT 24
Peak memory 194124 kb
Host smart-850a00f3-8931-461e-8af1-48d9af04e531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480008653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.2480008653
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.1169868282
Short name T1003
Test name
Test status
Simulation time 145091584356 ps
CPU time 54.7 seconds
Started Jun 25 05:13:10 PM PDT 24
Finished Jun 25 05:14:07 PM PDT 24
Peak memory 199920 kb
Host smart-f11e9bfc-3b5b-4588-9bb1-5075ee01804f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169868282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1169868282
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.3689467721
Short name T649
Test name
Test status
Simulation time 29474910650 ps
CPU time 12.43 seconds
Started Jun 25 05:13:13 PM PDT 24
Finished Jun 25 05:13:27 PM PDT 24
Peak memory 199744 kb
Host smart-0514e5b5-905d-4873-a358-ce169e4a808d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689467721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3689467721
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.196818955
Short name T299
Test name
Test status
Simulation time 46661246635 ps
CPU time 58.61 seconds
Started Jun 25 05:13:10 PM PDT 24
Finished Jun 25 05:14:11 PM PDT 24
Peak memory 199832 kb
Host smart-809a9e23-48fd-42d0-b78f-3dce837376e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196818955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.196818955
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.2122011145
Short name T614
Test name
Test status
Simulation time 21394215109 ps
CPU time 9.59 seconds
Started Jun 25 05:13:10 PM PDT 24
Finished Jun 25 05:13:22 PM PDT 24
Peak memory 199392 kb
Host smart-4d214875-5974-49e8-ac1d-d9fe0a2c960f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122011145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2122011145
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.1573507330
Short name T975
Test name
Test status
Simulation time 102542230849 ps
CPU time 300.16 seconds
Started Jun 25 05:13:17 PM PDT 24
Finished Jun 25 05:18:18 PM PDT 24
Peak memory 199836 kb
Host smart-b2090270-6331-4439-b4bd-0df2a97f5228
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1573507330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1573507330
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3090915160
Short name T2
Test name
Test status
Simulation time 13832766993 ps
CPU time 25.04 seconds
Started Jun 25 05:13:10 PM PDT 24
Finished Jun 25 05:13:37 PM PDT 24
Peak memory 199836 kb
Host smart-d8321c9c-d62f-4b00-81c8-0305aee19ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090915160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3090915160
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_perf.2606207230
Short name T767
Test name
Test status
Simulation time 12123418639 ps
CPU time 63.24 seconds
Started Jun 25 05:13:12 PM PDT 24
Finished Jun 25 05:14:16 PM PDT 24
Peak memory 200088 kb
Host smart-63ec166d-3452-48e8-ab04-7ac1a11b9c06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2606207230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.2606207230
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.2938308110
Short name T371
Test name
Test status
Simulation time 2725998129 ps
CPU time 4.39 seconds
Started Jun 25 05:13:10 PM PDT 24
Finished Jun 25 05:13:16 PM PDT 24
Peak memory 197856 kb
Host smart-5786332f-319c-4276-a2f2-fbd829fc06ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2938308110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2938308110
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.4082051158
Short name T689
Test name
Test status
Simulation time 41809297045 ps
CPU time 17.91 seconds
Started Jun 25 05:13:10 PM PDT 24
Finished Jun 25 05:13:29 PM PDT 24
Peak memory 199800 kb
Host smart-da07b47c-f323-4200-82a2-915533ddc4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082051158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.4082051158
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.3793828316
Short name T661
Test name
Test status
Simulation time 2852843422 ps
CPU time 5.24 seconds
Started Jun 25 05:13:11 PM PDT 24
Finished Jun 25 05:13:18 PM PDT 24
Peak memory 195780 kb
Host smart-155b8972-1368-4d78-aa2c-7bb2af4fc5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793828316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3793828316
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.395750266
Short name T533
Test name
Test status
Simulation time 672219717 ps
CPU time 2.18 seconds
Started Jun 25 05:13:12 PM PDT 24
Finished Jun 25 05:13:16 PM PDT 24
Peak memory 198472 kb
Host smart-65e3743f-3860-439f-9a10-b0b18109e277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395750266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.395750266
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.3070147662
Short name T456
Test name
Test status
Simulation time 47662102192 ps
CPU time 38.88 seconds
Started Jun 25 05:13:21 PM PDT 24
Finished Jun 25 05:14:01 PM PDT 24
Peak memory 199884 kb
Host smart-286dd0b3-bc4a-42ce-bc83-1eb46adf6f9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070147662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3070147662
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.3061645755
Short name T1
Test name
Test status
Simulation time 6582100055 ps
CPU time 16.91 seconds
Started Jun 25 05:13:17 PM PDT 24
Finished Jun 25 05:13:35 PM PDT 24
Peak memory 199920 kb
Host smart-d0efa358-3424-4c62-a19c-7abee4120c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061645755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.3061645755
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.1962342310
Short name T296
Test name
Test status
Simulation time 40054095039 ps
CPU time 67.48 seconds
Started Jun 25 05:13:17 PM PDT 24
Finished Jun 25 05:14:25 PM PDT 24
Peak memory 199920 kb
Host smart-8846c6a2-40a3-49b5-a804-13689a5f203c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962342310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1962342310
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1459359058
Short name T475
Test name
Test status
Simulation time 34692924979 ps
CPU time 25.37 seconds
Started Jun 25 05:16:25 PM PDT 24
Finished Jun 25 05:16:52 PM PDT 24
Peak memory 199900 kb
Host smart-c68b71c7-912f-4066-b0fe-0aff3f99a9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459359058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1459359058
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.3548508432
Short name T269
Test name
Test status
Simulation time 63635682871 ps
CPU time 510.78 seconds
Started Jun 25 05:16:26 PM PDT 24
Finished Jun 25 05:24:58 PM PDT 24
Peak memory 199880 kb
Host smart-2a7fa121-b1a2-4b19-bb4d-584ee16d68e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548508432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.3548508432
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.3605655058
Short name T184
Test name
Test status
Simulation time 190151773581 ps
CPU time 136.7 seconds
Started Jun 25 05:16:26 PM PDT 24
Finished Jun 25 05:18:44 PM PDT 24
Peak memory 199892 kb
Host smart-6941c005-ae43-49ae-a3a3-86d3d63e0c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605655058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3605655058
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3881017899
Short name T151
Test name
Test status
Simulation time 9877058364 ps
CPU time 26.41 seconds
Started Jun 25 05:16:29 PM PDT 24
Finished Jun 25 05:16:57 PM PDT 24
Peak memory 199836 kb
Host smart-8561d492-a81a-43d5-8d21-c76d0da20b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881017899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3881017899
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.1837152260
Short name T252
Test name
Test status
Simulation time 63840785481 ps
CPU time 90.99 seconds
Started Jun 25 05:16:30 PM PDT 24
Finished Jun 25 05:18:02 PM PDT 24
Peak memory 199840 kb
Host smart-ddf63901-05f9-4f9c-8aa3-7ef739e6c718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837152260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.1837152260
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2029977997
Short name T792
Test name
Test status
Simulation time 22590512726 ps
CPU time 59.05 seconds
Started Jun 25 05:16:26 PM PDT 24
Finished Jun 25 05:17:27 PM PDT 24
Peak memory 199916 kb
Host smart-685739a6-d939-44a8-a8fd-6f40b3203997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029977997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2029977997
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.1673828727
Short name T338
Test name
Test status
Simulation time 65776584915 ps
CPU time 49.62 seconds
Started Jun 25 05:16:30 PM PDT 24
Finished Jun 25 05:17:21 PM PDT 24
Peak memory 199848 kb
Host smart-e6c7998e-74a8-4737-b1fc-acd236ea1419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673828727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1673828727
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3860685414
Short name T263
Test name
Test status
Simulation time 99480022898 ps
CPU time 191.03 seconds
Started Jun 25 05:16:26 PM PDT 24
Finished Jun 25 05:19:39 PM PDT 24
Peak memory 199800 kb
Host smart-60217dd1-2c9f-48e1-90c9-94c8e4ef2057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860685414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3860685414
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.1752960517
Short name T177
Test name
Test status
Simulation time 22258965498 ps
CPU time 36.14 seconds
Started Jun 25 05:16:26 PM PDT 24
Finished Jun 25 05:17:04 PM PDT 24
Peak memory 199932 kb
Host smart-e9232165-bd78-41fe-be77-605ecc927b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752960517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1752960517
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.1367819598
Short name T599
Test name
Test status
Simulation time 72138841 ps
CPU time 0.52 seconds
Started Jun 25 05:13:19 PM PDT 24
Finished Jun 25 05:13:20 PM PDT 24
Peak memory 194144 kb
Host smart-4401d617-1569-41c4-af80-410908a4c298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367819598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1367819598
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2547009600
Short name T467
Test name
Test status
Simulation time 35779771668 ps
CPU time 60.68 seconds
Started Jun 25 05:13:20 PM PDT 24
Finished Jun 25 05:14:22 PM PDT 24
Peak memory 199912 kb
Host smart-c593bba2-3486-463a-a42e-eb96051ac0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547009600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2547009600
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.3898366008
Short name T157
Test name
Test status
Simulation time 74028259399 ps
CPU time 149.92 seconds
Started Jun 25 05:13:18 PM PDT 24
Finished Jun 25 05:15:49 PM PDT 24
Peak memory 199900 kb
Host smart-e130ec82-7fea-4640-88e9-c0e470a5992c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898366008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3898366008
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.235675803
Short name T871
Test name
Test status
Simulation time 27650172837 ps
CPU time 13.41 seconds
Started Jun 25 05:13:20 PM PDT 24
Finished Jun 25 05:13:35 PM PDT 24
Peak memory 199784 kb
Host smart-e0ed0993-ec24-4479-8f6e-9347701278b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235675803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.235675803
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.1027775270
Short name T925
Test name
Test status
Simulation time 43979082825 ps
CPU time 86.09 seconds
Started Jun 25 05:13:20 PM PDT 24
Finished Jun 25 05:14:47 PM PDT 24
Peak memory 199884 kb
Host smart-c114426e-fa50-4fc4-aeec-5619231836a6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027775270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1027775270
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.1372174085
Short name T944
Test name
Test status
Simulation time 127981772950 ps
CPU time 256.47 seconds
Started Jun 25 05:13:20 PM PDT 24
Finished Jun 25 05:17:37 PM PDT 24
Peak memory 199868 kb
Host smart-60f3f9f2-3205-4f0c-84a1-bb9a86b04bde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1372174085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1372174085
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.754111894
Short name T428
Test name
Test status
Simulation time 7358020619 ps
CPU time 16.41 seconds
Started Jun 25 05:13:24 PM PDT 24
Finished Jun 25 05:13:42 PM PDT 24
Peak memory 199624 kb
Host smart-784e9e87-4535-4208-ad6e-3c720c4dc388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754111894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.754111894
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_perf.2639879689
Short name T627
Test name
Test status
Simulation time 13714913769 ps
CPU time 157.89 seconds
Started Jun 25 05:13:19 PM PDT 24
Finished Jun 25 05:15:58 PM PDT 24
Peak memory 199812 kb
Host smart-43a1c41b-cee2-4d2a-b40e-b6f14ca118f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2639879689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2639879689
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.4199942667
Short name T879
Test name
Test status
Simulation time 6797753098 ps
CPU time 25.8 seconds
Started Jun 25 05:13:21 PM PDT 24
Finished Jun 25 05:13:48 PM PDT 24
Peak memory 198684 kb
Host smart-095fae89-94e8-405b-a924-f98c74720756
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4199942667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.4199942667
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.29063315
Short name T699
Test name
Test status
Simulation time 34422859472 ps
CPU time 16.96 seconds
Started Jun 25 05:13:24 PM PDT 24
Finished Jun 25 05:13:42 PM PDT 24
Peak memory 199864 kb
Host smart-57490c8f-0f71-4f5c-9cd3-ef03a4b1e641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29063315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.29063315
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.1231929024
Short name T266
Test name
Test status
Simulation time 38560412499 ps
CPU time 14.99 seconds
Started Jun 25 05:13:19 PM PDT 24
Finished Jun 25 05:13:35 PM PDT 24
Peak memory 195852 kb
Host smart-3ce12a4a-b662-4d8e-963f-7803521d4061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231929024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.1231929024
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.3190243052
Short name T927
Test name
Test status
Simulation time 852643697 ps
CPU time 2.83 seconds
Started Jun 25 05:13:20 PM PDT 24
Finished Jun 25 05:13:24 PM PDT 24
Peak memory 199416 kb
Host smart-62234a98-6f05-4c22-bf59-e2fd836289c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190243052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3190243052
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.1288296486
Short name T308
Test name
Test status
Simulation time 1338612259 ps
CPU time 2.72 seconds
Started Jun 25 05:13:22 PM PDT 24
Finished Jun 25 05:13:26 PM PDT 24
Peak memory 198720 kb
Host smart-33d51b10-d0f6-47ce-a3b7-30548950fb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288296486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1288296486
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.4176468515
Short name T798
Test name
Test status
Simulation time 4288303974 ps
CPU time 6.7 seconds
Started Jun 25 05:13:20 PM PDT 24
Finished Jun 25 05:13:27 PM PDT 24
Peak memory 197760 kb
Host smart-bb900b04-8822-497a-8b59-fa704d1559c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176468515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.4176468515
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.596882873
Short name T829
Test name
Test status
Simulation time 110282019392 ps
CPU time 45.86 seconds
Started Jun 25 05:16:28 PM PDT 24
Finished Jun 25 05:17:16 PM PDT 24
Peak memory 199896 kb
Host smart-2d4efc2d-5a27-4a57-85a7-d244b5702938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596882873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.596882873
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1064539739
Short name T811
Test name
Test status
Simulation time 70867322948 ps
CPU time 29.7 seconds
Started Jun 25 05:16:38 PM PDT 24
Finished Jun 25 05:17:09 PM PDT 24
Peak memory 199776 kb
Host smart-745e0a76-4ee1-4ec0-88ec-cede72315253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064539739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1064539739
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.3653442076
Short name T969
Test name
Test status
Simulation time 50358554531 ps
CPU time 39.75 seconds
Started Jun 25 05:16:36 PM PDT 24
Finished Jun 25 05:17:16 PM PDT 24
Peak memory 199872 kb
Host smart-c747d777-9fa9-41b8-b666-dcf25eb72976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653442076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3653442076
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.4084365203
Short name T558
Test name
Test status
Simulation time 54913304801 ps
CPU time 86.84 seconds
Started Jun 25 05:16:36 PM PDT 24
Finished Jun 25 05:18:05 PM PDT 24
Peak memory 199664 kb
Host smart-fd750925-317c-46af-ab0a-afa27148bf0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084365203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.4084365203
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.2940434396
Short name T415
Test name
Test status
Simulation time 104100961734 ps
CPU time 14.95 seconds
Started Jun 25 05:16:36 PM PDT 24
Finished Jun 25 05:16:51 PM PDT 24
Peak memory 199824 kb
Host smart-24ef9a34-2ed6-42fd-bee9-49ccfe84177b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940434396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.2940434396
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.4011928555
Short name T405
Test name
Test status
Simulation time 158023511065 ps
CPU time 98.57 seconds
Started Jun 25 05:16:41 PM PDT 24
Finished Jun 25 05:18:20 PM PDT 24
Peak memory 199912 kb
Host smart-f88c2b7b-0cc2-4a5b-8169-f17e7f73bc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011928555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.4011928555
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2620376034
Short name T486
Test name
Test status
Simulation time 21020413124 ps
CPU time 30.69 seconds
Started Jun 25 05:16:35 PM PDT 24
Finished Jun 25 05:17:07 PM PDT 24
Peak memory 199724 kb
Host smart-99f22cd2-1600-47aa-91a5-38fe71070be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620376034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2620376034
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.1260521115
Short name T733
Test name
Test status
Simulation time 76157266653 ps
CPU time 32.38 seconds
Started Jun 25 05:16:38 PM PDT 24
Finished Jun 25 05:17:11 PM PDT 24
Peak memory 199904 kb
Host smart-a22b8bd8-0990-424c-9360-5b26237dce02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260521115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1260521115
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.2650588992
Short name T24
Test name
Test status
Simulation time 17952610 ps
CPU time 0.62 seconds
Started Jun 25 05:13:28 PM PDT 24
Finished Jun 25 05:13:31 PM PDT 24
Peak memory 195144 kb
Host smart-5b8ded43-cb57-416d-8439-84dc34c4a17a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650588992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2650588992
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.984016000
Short name T835
Test name
Test status
Simulation time 24152761367 ps
CPU time 39.08 seconds
Started Jun 25 05:13:22 PM PDT 24
Finished Jun 25 05:14:03 PM PDT 24
Peak memory 199916 kb
Host smart-30c76631-25c6-47cd-b09c-29c066e5d955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984016000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.984016000
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.3175468339
Short name T581
Test name
Test status
Simulation time 130848451808 ps
CPU time 13.52 seconds
Started Jun 25 05:13:24 PM PDT 24
Finished Jun 25 05:13:39 PM PDT 24
Peak memory 199752 kb
Host smart-70de9740-6a61-4050-99c3-483af24a7121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175468339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3175468339
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.1693047024
Short name T559
Test name
Test status
Simulation time 92206669364 ps
CPU time 41.02 seconds
Started Jun 25 05:13:20 PM PDT 24
Finished Jun 25 05:14:02 PM PDT 24
Peak memory 199852 kb
Host smart-e89c5e7d-cb85-4622-9ae0-3b6b9c791b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693047024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1693047024
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.1370572311
Short name T928
Test name
Test status
Simulation time 43376528899 ps
CPU time 47.97 seconds
Started Jun 25 05:13:24 PM PDT 24
Finished Jun 25 05:14:13 PM PDT 24
Peak memory 199776 kb
Host smart-93ece7bd-a000-4e09-b5ea-3ce41391dd1c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370572311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1370572311
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.107829331
Short name T406
Test name
Test status
Simulation time 150493121538 ps
CPU time 864.91 seconds
Started Jun 25 05:13:28 PM PDT 24
Finished Jun 25 05:27:55 PM PDT 24
Peak memory 199784 kb
Host smart-5f88a615-0dcb-4100-bb8e-c1b02eb6bd8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=107829331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.107829331
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.2511146417
Short name T407
Test name
Test status
Simulation time 9137348905 ps
CPU time 6.58 seconds
Started Jun 25 05:13:27 PM PDT 24
Finished Jun 25 05:13:36 PM PDT 24
Peak memory 199028 kb
Host smart-1562c214-7bf9-4262-a6b4-4b8c40b1fde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511146417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2511146417
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_perf.1976171829
Short name T889
Test name
Test status
Simulation time 6483395164 ps
CPU time 205.29 seconds
Started Jun 25 05:13:28 PM PDT 24
Finished Jun 25 05:16:56 PM PDT 24
Peak memory 199876 kb
Host smart-799376af-8921-4f49-a356-769df7ab1f8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1976171829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.1976171829
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.508467896
Short name T496
Test name
Test status
Simulation time 2580011336 ps
CPU time 16.71 seconds
Started Jun 25 05:13:24 PM PDT 24
Finished Jun 25 05:13:42 PM PDT 24
Peak memory 197744 kb
Host smart-185b4e6e-f29e-4a8a-a458-7960aa15b838
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=508467896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.508467896
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.3000132664
Short name T425
Test name
Test status
Simulation time 38183638900 ps
CPU time 29.66 seconds
Started Jun 25 05:13:29 PM PDT 24
Finished Jun 25 05:14:01 PM PDT 24
Peak memory 199716 kb
Host smart-732f1e9f-95c5-4228-ad51-1348f4633a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000132664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3000132664
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.3668920702
Short name T880
Test name
Test status
Simulation time 2820771594 ps
CPU time 4.85 seconds
Started Jun 25 05:13:19 PM PDT 24
Finished Jun 25 05:13:25 PM PDT 24
Peak memory 196416 kb
Host smart-19a63d74-6e05-4a4c-9d2f-6efb88dffbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668920702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.3668920702
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1824288960
Short name T913
Test name
Test status
Simulation time 685250669 ps
CPU time 2.74 seconds
Started Jun 25 05:13:18 PM PDT 24
Finished Jun 25 05:13:21 PM PDT 24
Peak memory 198768 kb
Host smart-49c372ac-277b-4ebb-b732-82aca9fca1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824288960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1824288960
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.2080515724
Short name T361
Test name
Test status
Simulation time 397742381 ps
CPU time 1.61 seconds
Started Jun 25 05:13:27 PM PDT 24
Finished Jun 25 05:13:31 PM PDT 24
Peak memory 197108 kb
Host smart-bd91675a-7acc-426c-9219-c2674061423e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080515724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2080515724
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.3628472790
Short name T678
Test name
Test status
Simulation time 75959292286 ps
CPU time 273.08 seconds
Started Jun 25 05:13:20 PM PDT 24
Finished Jun 25 05:17:54 PM PDT 24
Peak memory 199820 kb
Host smart-94a2a68a-16c8-40fd-ad89-1c8dc03cc7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628472790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3628472790
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.528723280
Short name T868
Test name
Test status
Simulation time 66126853466 ps
CPU time 27.8 seconds
Started Jun 25 05:16:35 PM PDT 24
Finished Jun 25 05:17:03 PM PDT 24
Peak memory 199924 kb
Host smart-9ec022cd-b3a7-4811-9672-9cd5209b2d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528723280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.528723280
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.976117653
Short name T690
Test name
Test status
Simulation time 38648002798 ps
CPU time 13.92 seconds
Started Jun 25 05:16:38 PM PDT 24
Finished Jun 25 05:16:53 PM PDT 24
Peak memory 199916 kb
Host smart-9c0429f9-0697-4132-ace6-785e076f87e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976117653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.976117653
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.4228942357
Short name T532
Test name
Test status
Simulation time 18077551644 ps
CPU time 10.86 seconds
Started Jun 25 05:16:37 PM PDT 24
Finished Jun 25 05:16:49 PM PDT 24
Peak memory 199920 kb
Host smart-aac0e759-7db8-4f7b-a1bd-03ecb16c3a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228942357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.4228942357
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1238020300
Short name T747
Test name
Test status
Simulation time 19310384576 ps
CPU time 14.58 seconds
Started Jun 25 05:16:37 PM PDT 24
Finished Jun 25 05:16:53 PM PDT 24
Peak memory 199804 kb
Host smart-335db410-7db3-4822-84f2-fdbfcbb2f660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238020300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1238020300
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1392549563
Short name T220
Test name
Test status
Simulation time 40021386296 ps
CPU time 18.62 seconds
Started Jun 25 05:16:36 PM PDT 24
Finished Jun 25 05:16:55 PM PDT 24
Peak memory 199388 kb
Host smart-dc1f6e0e-6943-4f05-b194-c7080f038b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392549563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1392549563
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2525624323
Short name T173
Test name
Test status
Simulation time 17041578164 ps
CPU time 23.14 seconds
Started Jun 25 05:16:37 PM PDT 24
Finished Jun 25 05:17:01 PM PDT 24
Peak memory 199820 kb
Host smart-7cf7afaf-74fa-42ad-ade2-30e3fc659b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525624323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2525624323
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.2539954944
Short name T774
Test name
Test status
Simulation time 20776530 ps
CPU time 0.57 seconds
Started Jun 25 05:13:30 PM PDT 24
Finished Jun 25 05:13:34 PM PDT 24
Peak memory 195196 kb
Host smart-be17cb09-e089-4ba7-887e-b33718001111
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539954944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2539954944
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.1720128278
Short name T791
Test name
Test status
Simulation time 150210171884 ps
CPU time 70.2 seconds
Started Jun 25 05:13:26 PM PDT 24
Finished Jun 25 05:14:39 PM PDT 24
Peak memory 199896 kb
Host smart-8975ce45-691f-4a36-988d-7ee40e53e120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720128278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1720128278
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.3973722471
Short name T133
Test name
Test status
Simulation time 17668723642 ps
CPU time 9.24 seconds
Started Jun 25 05:13:28 PM PDT 24
Finished Jun 25 05:13:40 PM PDT 24
Peak memory 199836 kb
Host smart-0390fd48-ec1f-4ce0-99c8-59d0676e1403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973722471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3973722471
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.436859302
Short name T236
Test name
Test status
Simulation time 128267745491 ps
CPU time 197.33 seconds
Started Jun 25 05:13:28 PM PDT 24
Finished Jun 25 05:16:48 PM PDT 24
Peak memory 199828 kb
Host smart-335213e4-6d38-4a36-ae8f-906fdf344769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436859302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.436859302
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.1490088098
Short name T1064
Test name
Test status
Simulation time 26461640594 ps
CPU time 15.42 seconds
Started Jun 25 05:13:27 PM PDT 24
Finished Jun 25 05:13:45 PM PDT 24
Peak memory 199808 kb
Host smart-cbdb4ec9-6667-4e1e-838b-1d56b232136f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490088098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.1490088098
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.1264638315
Short name T261
Test name
Test status
Simulation time 123905735937 ps
CPU time 380.32 seconds
Started Jun 25 05:13:27 PM PDT 24
Finished Jun 25 05:19:50 PM PDT 24
Peak memory 199884 kb
Host smart-9a8db3b0-f0e6-4873-846a-930d956d39ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1264638315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.1264638315
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.3547777354
Short name T546
Test name
Test status
Simulation time 3936059638 ps
CPU time 5.07 seconds
Started Jun 25 05:13:30 PM PDT 24
Finished Jun 25 05:13:38 PM PDT 24
Peak memory 198632 kb
Host smart-ac344798-9204-445d-b8b1-efde458a142a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547777354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.3547777354
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_perf.764436075
Short name T1061
Test name
Test status
Simulation time 14866272768 ps
CPU time 397.94 seconds
Started Jun 25 05:13:30 PM PDT 24
Finished Jun 25 05:20:11 PM PDT 24
Peak memory 199780 kb
Host smart-8638d5fd-a269-46e8-9c4e-646f3e3b9a94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=764436075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.764436075
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.1692782998
Short name T435
Test name
Test status
Simulation time 1938532723 ps
CPU time 2.19 seconds
Started Jun 25 05:13:30 PM PDT 24
Finished Jun 25 05:13:35 PM PDT 24
Peak memory 197988 kb
Host smart-e53bb659-0f71-4b68-a79f-49b77a0382e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1692782998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.1692782998
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.4014804591
Short name T520
Test name
Test status
Simulation time 223231360310 ps
CPU time 77.87 seconds
Started Jun 25 05:13:27 PM PDT 24
Finished Jun 25 05:14:47 PM PDT 24
Peak memory 199840 kb
Host smart-179944b9-437f-4782-b028-2ffc8122293f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014804591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.4014804591
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.2899599728
Short name T991
Test name
Test status
Simulation time 48265132946 ps
CPU time 37.07 seconds
Started Jun 25 05:13:29 PM PDT 24
Finished Jun 25 05:14:09 PM PDT 24
Peak memory 195692 kb
Host smart-6eb90d7b-6693-4e64-ae4c-db4a35a494fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899599728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.2899599728
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.133110630
Short name T48
Test name
Test status
Simulation time 6069565494 ps
CPU time 22.19 seconds
Started Jun 25 05:13:29 PM PDT 24
Finished Jun 25 05:13:54 PM PDT 24
Peak memory 199848 kb
Host smart-84435248-09cd-435e-8224-b72ad6f52777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133110630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.133110630
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.1005444167
Short name T949
Test name
Test status
Simulation time 241101803711 ps
CPU time 965.46 seconds
Started Jun 25 05:13:28 PM PDT 24
Finished Jun 25 05:29:37 PM PDT 24
Peak memory 216496 kb
Host smart-936f1df5-cf80-48b3-8614-41b7ceeeb7b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005444167 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.1005444167
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.3978762744
Short name T445
Test name
Test status
Simulation time 1151672829 ps
CPU time 3.99 seconds
Started Jun 25 05:13:29 PM PDT 24
Finished Jun 25 05:13:36 PM PDT 24
Peak memory 198932 kb
Host smart-ca4f5a48-db3e-4fa8-9241-48b01703c8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978762744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.3978762744
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.2131795252
Short name T1067
Test name
Test status
Simulation time 108109382448 ps
CPU time 69.55 seconds
Started Jun 25 05:13:27 PM PDT 24
Finished Jun 25 05:14:39 PM PDT 24
Peak memory 199844 kb
Host smart-8d119f5e-2318-469c-9ac5-aa8d36f04bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131795252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2131795252
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.3968576414
Short name T837
Test name
Test status
Simulation time 36539083374 ps
CPU time 59.49 seconds
Started Jun 25 05:16:37 PM PDT 24
Finished Jun 25 05:17:37 PM PDT 24
Peak memory 199856 kb
Host smart-83de9eae-7643-45ef-89df-d1e9bd99bc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968576414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.3968576414
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.2681702865
Short name T277
Test name
Test status
Simulation time 19530675722 ps
CPU time 31.86 seconds
Started Jun 25 05:16:41 PM PDT 24
Finished Jun 25 05:17:13 PM PDT 24
Peak memory 199916 kb
Host smart-49ee5607-3e57-4108-b4fe-680d2ae47de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681702865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2681702865
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.4048140130
Short name T171
Test name
Test status
Simulation time 18442033593 ps
CPU time 33.69 seconds
Started Jun 25 05:16:38 PM PDT 24
Finished Jun 25 05:17:12 PM PDT 24
Peak memory 199836 kb
Host smart-0099e279-8893-44f6-918c-c26aa871baa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048140130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.4048140130
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.1993245739
Short name T187
Test name
Test status
Simulation time 31166888159 ps
CPU time 48.34 seconds
Started Jun 25 05:16:36 PM PDT 24
Finished Jun 25 05:17:26 PM PDT 24
Peak memory 199840 kb
Host smart-c1119de3-838b-44a4-b52f-520c914ee742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993245739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1993245739
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.923546849
Short name T898
Test name
Test status
Simulation time 57492171365 ps
CPU time 22.33 seconds
Started Jun 25 05:16:38 PM PDT 24
Finished Jun 25 05:17:01 PM PDT 24
Peak memory 199856 kb
Host smart-2336d268-9d74-458b-8482-6cc0a3060daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923546849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.923546849
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.2748717013
Short name T311
Test name
Test status
Simulation time 130243743696 ps
CPU time 28.41 seconds
Started Jun 25 05:16:37 PM PDT 24
Finished Jun 25 05:17:06 PM PDT 24
Peak memory 199948 kb
Host smart-0fbd6f2b-e518-48e8-a330-0d71e87b09e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748717013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.2748717013
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.3396618554
Short name T908
Test name
Test status
Simulation time 134629462779 ps
CPU time 212.75 seconds
Started Jun 25 05:16:43 PM PDT 24
Finished Jun 25 05:20:17 PM PDT 24
Peak memory 199908 kb
Host smart-983edd51-f24c-4ebf-aa71-341061c08ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396618554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3396618554
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.1048082698
Short name T598
Test name
Test status
Simulation time 8843071279 ps
CPU time 18.35 seconds
Started Jun 25 05:16:43 PM PDT 24
Finished Jun 25 05:17:02 PM PDT 24
Peak memory 199856 kb
Host smart-6b86c5f8-6c61-4a7e-b7e7-cfb8a7603ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048082698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1048082698
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.1896445152
Short name T926
Test name
Test status
Simulation time 17669192 ps
CPU time 0.57 seconds
Started Jun 25 05:13:40 PM PDT 24
Finished Jun 25 05:13:43 PM PDT 24
Peak memory 195220 kb
Host smart-2ff61925-c224-4d41-8af5-48467f9d93c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896445152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1896445152
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2775808487
Short name T751
Test name
Test status
Simulation time 115355398526 ps
CPU time 84.35 seconds
Started Jun 25 05:13:29 PM PDT 24
Finished Jun 25 05:14:56 PM PDT 24
Peak memory 199836 kb
Host smart-0cbf6a9a-3ebd-4fd5-a03c-0399cabb7e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775808487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2775808487
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.2316721667
Short name T217
Test name
Test status
Simulation time 29915831801 ps
CPU time 56 seconds
Started Jun 25 05:13:27 PM PDT 24
Finished Jun 25 05:14:25 PM PDT 24
Peak memory 199868 kb
Host smart-96176167-6861-4897-8a52-693c1938b3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316721667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2316721667
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.666803596
Short name T597
Test name
Test status
Simulation time 15278672769 ps
CPU time 28.77 seconds
Started Jun 25 05:13:29 PM PDT 24
Finished Jun 25 05:14:00 PM PDT 24
Peak memory 199500 kb
Host smart-7e7402a1-b149-487c-8d3e-4976a6551373
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666803596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.666803596
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.734766465
Short name T410
Test name
Test status
Simulation time 87503394777 ps
CPU time 630.12 seconds
Started Jun 25 05:13:27 PM PDT 24
Finished Jun 25 05:24:00 PM PDT 24
Peak memory 199848 kb
Host smart-138b0d5f-379b-44d4-a907-476c3ff43dfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=734766465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.734766465
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2213675783
Short name T352
Test name
Test status
Simulation time 433850396 ps
CPU time 1.5 seconds
Started Jun 25 05:13:28 PM PDT 24
Finished Jun 25 05:13:33 PM PDT 24
Peak memory 196968 kb
Host smart-86d60f1c-5d59-4611-981d-5ee6c6477c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213675783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2213675783
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.4097820832
Short name T1084
Test name
Test status
Simulation time 7895880545 ps
CPU time 12.78 seconds
Started Jun 25 05:13:28 PM PDT 24
Finished Jun 25 05:13:43 PM PDT 24
Peak memory 198144 kb
Host smart-64c331eb-2c43-41a7-bd8b-ee88618318cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097820832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.4097820832
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.1081227479
Short name T626
Test name
Test status
Simulation time 13397291051 ps
CPU time 670.8 seconds
Started Jun 25 05:13:29 PM PDT 24
Finished Jun 25 05:24:43 PM PDT 24
Peak memory 199812 kb
Host smart-ce33c2f1-c3f0-40ac-ba31-574aeb117679
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1081227479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1081227479
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.453537749
Short name T1019
Test name
Test status
Simulation time 4826071774 ps
CPU time 33.65 seconds
Started Jun 25 05:13:28 PM PDT 24
Finished Jun 25 05:14:05 PM PDT 24
Peak memory 198072 kb
Host smart-9677fbad-8e30-4b4d-9031-a211ab9b3572
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=453537749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.453537749
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2171233909
Short name T168
Test name
Test status
Simulation time 107777185906 ps
CPU time 147.87 seconds
Started Jun 25 05:13:27 PM PDT 24
Finished Jun 25 05:15:57 PM PDT 24
Peak memory 199784 kb
Host smart-4bd62a0e-ef48-485c-8edd-e4d778ad869a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171233909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2171233909
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.3706427149
Short name T1005
Test name
Test status
Simulation time 2001309182 ps
CPU time 1.49 seconds
Started Jun 25 05:13:28 PM PDT 24
Finished Jun 25 05:13:33 PM PDT 24
Peak memory 195324 kb
Host smart-3dd49380-90c2-423f-8f7a-f74eed2c3ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706427149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3706427149
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2889315892
Short name T461
Test name
Test status
Simulation time 648821965 ps
CPU time 3.19 seconds
Started Jun 25 05:13:30 PM PDT 24
Finished Jun 25 05:13:36 PM PDT 24
Peak memory 198816 kb
Host smart-2ce59073-681a-40fc-a20f-bdbf56c08449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889315892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2889315892
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.4275108786
Short name T685
Test name
Test status
Simulation time 272941293017 ps
CPU time 432.01 seconds
Started Jun 25 05:13:38 PM PDT 24
Finished Jun 25 05:20:52 PM PDT 24
Peak memory 199824 kb
Host smart-44775acc-7a11-42e5-b408-0f693abd5647
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275108786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.4275108786
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.130985018
Short name T994
Test name
Test status
Simulation time 3297597399 ps
CPU time 1.53 seconds
Started Jun 25 05:13:29 PM PDT 24
Finished Jun 25 05:13:33 PM PDT 24
Peak memory 198880 kb
Host smart-3b4b18c5-2a43-4f20-916d-e7ab58e1ee19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130985018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.130985018
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.4149880215
Short name T662
Test name
Test status
Simulation time 274291235705 ps
CPU time 99.36 seconds
Started Jun 25 05:13:29 PM PDT 24
Finished Jun 25 05:15:11 PM PDT 24
Peak memory 199868 kb
Host smart-0da8e272-45d7-4986-9571-da11798f89bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149880215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.4149880215
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.584143149
Short name T207
Test name
Test status
Simulation time 30907600665 ps
CPU time 24.19 seconds
Started Jun 25 05:16:46 PM PDT 24
Finished Jun 25 05:17:12 PM PDT 24
Peak memory 199808 kb
Host smart-3784fdb9-bf94-4cef-8a95-8c1b02a9f3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584143149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.584143149
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.946320477
Short name T1007
Test name
Test status
Simulation time 97179357360 ps
CPU time 38.31 seconds
Started Jun 25 05:16:47 PM PDT 24
Finished Jun 25 05:17:27 PM PDT 24
Peak memory 199544 kb
Host smart-d4b510f3-a9dc-4fe5-a135-af2a044a267e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946320477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.946320477
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.1889632172
Short name T1029
Test name
Test status
Simulation time 213535739924 ps
CPU time 77.6 seconds
Started Jun 25 05:16:47 PM PDT 24
Finished Jun 25 05:18:05 PM PDT 24
Peak memory 200152 kb
Host smart-e5c0c4a5-7970-4e0a-9ae1-9b49067f86dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889632172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1889632172
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.679365165
Short name T1016
Test name
Test status
Simulation time 131932332801 ps
CPU time 97.43 seconds
Started Jun 25 05:16:47 PM PDT 24
Finished Jun 25 05:18:26 PM PDT 24
Peak memory 199908 kb
Host smart-2ab94c70-1d2c-42d5-ac7c-d7f776d3a44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679365165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.679365165
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.2976599473
Short name T785
Test name
Test status
Simulation time 10826479159 ps
CPU time 6.28 seconds
Started Jun 25 05:16:47 PM PDT 24
Finished Jun 25 05:16:55 PM PDT 24
Peak memory 199840 kb
Host smart-534454ec-391a-43b3-864e-a9d96f6883df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976599473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2976599473
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.3533447919
Short name T483
Test name
Test status
Simulation time 74041512313 ps
CPU time 160.11 seconds
Started Jun 25 05:16:48 PM PDT 24
Finished Jun 25 05:19:29 PM PDT 24
Peak memory 199776 kb
Host smart-bfe30885-f427-45fc-bcd7-27665b5338a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533447919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3533447919
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.2776864177
Short name T639
Test name
Test status
Simulation time 20926703525 ps
CPU time 10.91 seconds
Started Jun 25 05:16:47 PM PDT 24
Finished Jun 25 05:16:59 PM PDT 24
Peak memory 199864 kb
Host smart-073dc04a-9d82-4e44-a2ce-83165bff170f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776864177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2776864177
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.4257488679
Short name T611
Test name
Test status
Simulation time 156564853852 ps
CPU time 65.15 seconds
Started Jun 25 05:16:47 PM PDT 24
Finished Jun 25 05:17:53 PM PDT 24
Peak memory 199808 kb
Host smart-9b2f23c4-07ee-4f2c-921b-cf5e94de6e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257488679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.4257488679
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.261418814
Short name T137
Test name
Test status
Simulation time 21498150972 ps
CPU time 18.69 seconds
Started Jun 25 05:16:49 PM PDT 24
Finished Jun 25 05:17:09 PM PDT 24
Peak memory 199904 kb
Host smart-e111b96d-d375-4dd2-a9c7-e5ae4922fe2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261418814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.261418814
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.1160336777
Short name T493
Test name
Test status
Simulation time 37317029436 ps
CPU time 20.17 seconds
Started Jun 25 05:16:48 PM PDT 24
Finished Jun 25 05:17:09 PM PDT 24
Peak memory 199920 kb
Host smart-94d78d53-9176-4728-acc0-6849b82ee5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160336777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1160336777
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.107580818
Short name T466
Test name
Test status
Simulation time 20970566 ps
CPU time 0.54 seconds
Started Jun 25 05:13:38 PM PDT 24
Finished Jun 25 05:13:41 PM PDT 24
Peak memory 195520 kb
Host smart-1ecb981d-e54f-4220-94ac-950329c18763
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107580818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.107580818
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.3362112164
Short name T42
Test name
Test status
Simulation time 89550597049 ps
CPU time 38.85 seconds
Started Jun 25 05:13:37 PM PDT 24
Finished Jun 25 05:14:18 PM PDT 24
Peak memory 199832 kb
Host smart-7c5f6a90-29b8-4c94-abea-76a9e352bad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362112164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.3362112164
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.2297726221
Short name T663
Test name
Test status
Simulation time 59126964482 ps
CPU time 67.17 seconds
Started Jun 25 05:13:41 PM PDT 24
Finished Jun 25 05:14:50 PM PDT 24
Peak memory 199776 kb
Host smart-6f936dbc-61c5-4a5f-9cb1-0a13dad707cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297726221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.2297726221
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2765466180
Short name T1055
Test name
Test status
Simulation time 78928636914 ps
CPU time 114.11 seconds
Started Jun 25 05:13:38 PM PDT 24
Finished Jun 25 05:15:34 PM PDT 24
Peak memory 199832 kb
Host smart-1197d359-f733-4c41-bfd6-ab204ac16a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765466180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2765466180
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.3374007093
Short name T923
Test name
Test status
Simulation time 127370614515 ps
CPU time 286.99 seconds
Started Jun 25 05:13:39 PM PDT 24
Finished Jun 25 05:18:28 PM PDT 24
Peak memory 199756 kb
Host smart-0df01a7c-4627-4e05-bee0-06e5035bd6b7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374007093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3374007093
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.4282659170
Short name T1031
Test name
Test status
Simulation time 87524294531 ps
CPU time 894.52 seconds
Started Jun 25 05:13:38 PM PDT 24
Finished Jun 25 05:28:35 PM PDT 24
Peak memory 199804 kb
Host smart-99be4240-d431-40f2-bc55-f8874352473f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4282659170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.4282659170
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.803654251
Short name T555
Test name
Test status
Simulation time 2866220646 ps
CPU time 6.05 seconds
Started Jun 25 05:13:38 PM PDT 24
Finished Jun 25 05:13:46 PM PDT 24
Peak memory 198960 kb
Host smart-5b1929f8-2ee4-4333-9a72-2c98822c4d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803654251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.803654251
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_perf.3439773304
Short name T1006
Test name
Test status
Simulation time 28972213009 ps
CPU time 343.82 seconds
Started Jun 25 05:13:40 PM PDT 24
Finished Jun 25 05:19:26 PM PDT 24
Peak memory 199840 kb
Host smart-7a2566e3-f7ed-4024-a0a5-a8cfdfaef71a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3439773304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3439773304
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1633242163
Short name T998
Test name
Test status
Simulation time 5477502566 ps
CPU time 25.67 seconds
Started Jun 25 05:13:39 PM PDT 24
Finished Jun 25 05:14:07 PM PDT 24
Peak memory 197992 kb
Host smart-7c8f986c-ce88-48eb-87e0-5974b58b364f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1633242163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1633242163
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.3089253475
Short name T561
Test name
Test status
Simulation time 65048110230 ps
CPU time 23.25 seconds
Started Jun 25 05:13:37 PM PDT 24
Finished Jun 25 05:14:02 PM PDT 24
Peak memory 199776 kb
Host smart-afc2f328-9cba-415f-9e37-d0ae20d36fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089253475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3089253475
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.3797797075
Short name T722
Test name
Test status
Simulation time 30671161263 ps
CPU time 11.78 seconds
Started Jun 25 05:13:36 PM PDT 24
Finished Jun 25 05:13:50 PM PDT 24
Peak memory 195972 kb
Host smart-372680a3-0795-43d2-9755-50fbae77a293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797797075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3797797075
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2118295789
Short name T281
Test name
Test status
Simulation time 688144579 ps
CPU time 1.45 seconds
Started Jun 25 05:13:37 PM PDT 24
Finished Jun 25 05:13:41 PM PDT 24
Peak memory 199856 kb
Host smart-cbc37c73-6424-428d-afa0-13c67dfae14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118295789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2118295789
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.1499134211
Short name T223
Test name
Test status
Simulation time 423600780493 ps
CPU time 97.18 seconds
Started Jun 25 05:13:42 PM PDT 24
Finished Jun 25 05:15:20 PM PDT 24
Peak memory 199808 kb
Host smart-cf5c678a-bbfc-468b-a579-929b5199f414
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499134211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1499134211
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.2146577184
Short name T1053
Test name
Test status
Simulation time 1592026565 ps
CPU time 1.76 seconds
Started Jun 25 05:13:38 PM PDT 24
Finished Jun 25 05:13:42 PM PDT 24
Peak memory 198316 kb
Host smart-5ae70a92-6522-469b-b9ba-6e29849fcd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146577184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2146577184
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.135899430
Short name T818
Test name
Test status
Simulation time 62720581973 ps
CPU time 108.7 seconds
Started Jun 25 05:13:40 PM PDT 24
Finished Jun 25 05:15:30 PM PDT 24
Peak memory 199896 kb
Host smart-3b1e60c2-c45c-41f2-b8f2-7cd84568d30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135899430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.135899430
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.1161809504
Short name T726
Test name
Test status
Simulation time 100236973498 ps
CPU time 208.58 seconds
Started Jun 25 05:16:49 PM PDT 24
Finished Jun 25 05:20:19 PM PDT 24
Peak memory 199804 kb
Host smart-b6807f83-4080-497f-a3e1-8814967ce759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161809504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.1161809504
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.1436555516
Short name T828
Test name
Test status
Simulation time 21581645795 ps
CPU time 41.47 seconds
Started Jun 25 05:16:48 PM PDT 24
Finished Jun 25 05:17:31 PM PDT 24
Peak memory 199804 kb
Host smart-a0dcdfbf-6557-4789-a164-9b75dc9d4e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436555516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1436555516
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.1017763829
Short name T919
Test name
Test status
Simulation time 46889875939 ps
CPU time 65.28 seconds
Started Jun 25 05:16:48 PM PDT 24
Finished Jun 25 05:17:55 PM PDT 24
Peak memory 199932 kb
Host smart-dbe0e271-77ce-4776-a458-29805fec9e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017763829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1017763829
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.804126554
Short name T620
Test name
Test status
Simulation time 77315681628 ps
CPU time 54.22 seconds
Started Jun 25 05:16:47 PM PDT 24
Finished Jun 25 05:17:43 PM PDT 24
Peak memory 199904 kb
Host smart-47c001ce-effa-4a0c-980d-c43841a8fa0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804126554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.804126554
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.741413741
Short name T195
Test name
Test status
Simulation time 16493030014 ps
CPU time 27.72 seconds
Started Jun 25 05:16:48 PM PDT 24
Finished Jun 25 05:17:17 PM PDT 24
Peak memory 199628 kb
Host smart-955ef9cc-901b-4773-a7b6-51c172a5886e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741413741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.741413741
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2926051120
Short name T340
Test name
Test status
Simulation time 102252822315 ps
CPU time 167.44 seconds
Started Jun 25 05:16:47 PM PDT 24
Finished Jun 25 05:19:36 PM PDT 24
Peak memory 199884 kb
Host smart-7048d978-a868-45c4-813e-7b0c211589a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926051120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2926051120
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.1424722815
Short name T129
Test name
Test status
Simulation time 19937812855 ps
CPU time 39.28 seconds
Started Jun 25 05:16:49 PM PDT 24
Finished Jun 25 05:17:29 PM PDT 24
Peak memory 199908 kb
Host smart-cc9f5a6d-651d-4542-a2a0-52cebe46e46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424722815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1424722815
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.1472127731
Short name T273
Test name
Test status
Simulation time 83164772893 ps
CPU time 44.61 seconds
Started Jun 25 05:16:48 PM PDT 24
Finished Jun 25 05:17:34 PM PDT 24
Peak memory 199840 kb
Host smart-d6a933dd-8565-4ab7-9273-6745131a8d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472127731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1472127731
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.1705420831
Short name T388
Test name
Test status
Simulation time 59662960 ps
CPU time 0.57 seconds
Started Jun 25 05:12:36 PM PDT 24
Finished Jun 25 05:12:38 PM PDT 24
Peak memory 195228 kb
Host smart-9990e5d0-407d-4723-be8b-26f2e186a1bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705420831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1705420831
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.2042883372
Short name T413
Test name
Test status
Simulation time 109586411158 ps
CPU time 23.87 seconds
Started Jun 25 05:12:34 PM PDT 24
Finished Jun 25 05:12:59 PM PDT 24
Peak memory 199516 kb
Host smart-da7dd534-d014-49d1-aa84-5b61a08d6aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042883372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2042883372
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.1156040244
Short name T4
Test name
Test status
Simulation time 25073582181 ps
CPU time 13.8 seconds
Started Jun 25 05:12:36 PM PDT 24
Finished Jun 25 05:12:51 PM PDT 24
Peak memory 199832 kb
Host smart-b1daba95-2834-4cac-b5b8-9b3c33ca229b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156040244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1156040244
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.4080057253
Short name T238
Test name
Test status
Simulation time 37935188238 ps
CPU time 16.87 seconds
Started Jun 25 05:12:32 PM PDT 24
Finished Jun 25 05:12:51 PM PDT 24
Peak memory 199844 kb
Host smart-6acd73b8-25ac-49da-b0ea-8235deb6b567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080057253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.4080057253
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.645759522
Short name T362
Test name
Test status
Simulation time 58870860939 ps
CPU time 81.44 seconds
Started Jun 25 05:12:33 PM PDT 24
Finished Jun 25 05:13:56 PM PDT 24
Peak memory 197156 kb
Host smart-d5bc6302-adb9-48b8-b337-d632646fc693
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645759522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.645759522
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.3866984306
Short name T619
Test name
Test status
Simulation time 128300587222 ps
CPU time 336.55 seconds
Started Jun 25 05:12:37 PM PDT 24
Finished Jun 25 05:18:15 PM PDT 24
Peak memory 199884 kb
Host smart-da6ac7db-16ad-40c7-94c2-3c44920dea2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3866984306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.3866984306
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.1671641424
Short name T587
Test name
Test status
Simulation time 10029941268 ps
CPU time 6.29 seconds
Started Jun 25 05:12:42 PM PDT 24
Finished Jun 25 05:12:50 PM PDT 24
Peak memory 199584 kb
Host smart-fd490878-3605-4d4c-9a8c-6796e819cbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671641424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1671641424
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_perf.1894033827
Short name T874
Test name
Test status
Simulation time 9576884866 ps
CPU time 134.19 seconds
Started Jun 25 05:12:35 PM PDT 24
Finished Jun 25 05:14:50 PM PDT 24
Peak memory 199788 kb
Host smart-e4713803-b1bd-4947-b124-9d076b0b3856
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1894033827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.1894033827
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.3859356950
Short name T403
Test name
Test status
Simulation time 6533327868 ps
CPU time 64.8 seconds
Started Jun 25 05:12:34 PM PDT 24
Finished Jun 25 05:13:40 PM PDT 24
Peak memory 198064 kb
Host smart-90ebb3cb-2ffd-4220-baae-1d03c4389dad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3859356950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.3859356950
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1213828023
Short name T657
Test name
Test status
Simulation time 148576904466 ps
CPU time 178.05 seconds
Started Jun 25 05:12:33 PM PDT 24
Finished Jun 25 05:15:32 PM PDT 24
Peak memory 199832 kb
Host smart-ed5d181d-9aad-44e8-bfc4-49499c7f3317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213828023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1213828023
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.1303178681
Short name T682
Test name
Test status
Simulation time 40136127358 ps
CPU time 28.2 seconds
Started Jun 25 05:12:45 PM PDT 24
Finished Jun 25 05:13:16 PM PDT 24
Peak memory 195488 kb
Host smart-cbfdb8ca-2685-48b5-8415-3d6607807e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303178681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.1303178681
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.3505557970
Short name T27
Test name
Test status
Simulation time 57718475 ps
CPU time 0.84 seconds
Started Jun 25 05:12:42 PM PDT 24
Finished Jun 25 05:12:45 PM PDT 24
Peak memory 218228 kb
Host smart-514c880d-b50e-4854-afb7-66d117a144f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505557970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.3505557970
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.4056328102
Short name T668
Test name
Test status
Simulation time 273460055 ps
CPU time 1.33 seconds
Started Jun 25 05:12:32 PM PDT 24
Finished Jun 25 05:12:35 PM PDT 24
Peak memory 198364 kb
Host smart-b4340097-ebb5-4614-bcce-cde57262ee05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056328102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.4056328102
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.1742979771
Short name T1036
Test name
Test status
Simulation time 84174126454 ps
CPU time 1009.13 seconds
Started Jun 25 05:12:34 PM PDT 24
Finished Jun 25 05:29:25 PM PDT 24
Peak memory 216320 kb
Host smart-4bed668a-a885-4dd9-b4a5-8ed6b4c36459
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742979771 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.1742979771
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.2724733387
Short name T941
Test name
Test status
Simulation time 2344618353 ps
CPU time 2.07 seconds
Started Jun 25 05:12:34 PM PDT 24
Finished Jun 25 05:12:38 PM PDT 24
Peak memory 198064 kb
Host smart-29d17f17-43a0-45e0-a9cf-4fcb2c2df197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724733387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.2724733387
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3558983750
Short name T1041
Test name
Test status
Simulation time 12879735471 ps
CPU time 10.9 seconds
Started Jun 25 05:12:43 PM PDT 24
Finished Jun 25 05:12:56 PM PDT 24
Peak memory 198124 kb
Host smart-66395143-8403-4ec1-8f78-22b6b010a1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558983750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3558983750
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.1683130078
Short name T354
Test name
Test status
Simulation time 23862101 ps
CPU time 0.59 seconds
Started Jun 25 05:13:38 PM PDT 24
Finished Jun 25 05:13:41 PM PDT 24
Peak memory 195228 kb
Host smart-f4138a18-8bf1-43f2-b842-3cb9f0f5a79e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683130078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1683130078
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.2862231532
Short name T433
Test name
Test status
Simulation time 20387909631 ps
CPU time 23.62 seconds
Started Jun 25 05:13:38 PM PDT 24
Finished Jun 25 05:14:03 PM PDT 24
Peak memory 199816 kb
Host smart-a3643290-a062-4a7a-83b5-047bec0fbe63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862231532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.2862231532
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.2956736394
Short name T162
Test name
Test status
Simulation time 30358809741 ps
CPU time 14.86 seconds
Started Jun 25 05:13:42 PM PDT 24
Finished Jun 25 05:13:58 PM PDT 24
Peak memory 199676 kb
Host smart-d36bc5cd-7fdb-4d4c-8589-0e472d4a7bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956736394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2956736394
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.126207157
Short name T888
Test name
Test status
Simulation time 19423801283 ps
CPU time 10.01 seconds
Started Jun 25 05:13:39 PM PDT 24
Finished Jun 25 05:13:51 PM PDT 24
Peak memory 199632 kb
Host smart-13ab2cc6-c0e0-41f9-b184-a46961f92c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126207157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.126207157
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.1150706301
Short name T1045
Test name
Test status
Simulation time 35529785271 ps
CPU time 58.53 seconds
Started Jun 25 05:13:40 PM PDT 24
Finished Jun 25 05:14:40 PM PDT 24
Peak memory 199760 kb
Host smart-f169e262-ef3b-4b08-96cf-0b23c4d7a642
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150706301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.1150706301
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.3674338311
Short name T472
Test name
Test status
Simulation time 72230231931 ps
CPU time 434.93 seconds
Started Jun 25 05:13:40 PM PDT 24
Finished Jun 25 05:20:57 PM PDT 24
Peak memory 199848 kb
Host smart-e45ec59b-d788-4b7f-b649-1cafabb339f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3674338311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3674338311
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2854381205
Short name T543
Test name
Test status
Simulation time 5404235432 ps
CPU time 9.17 seconds
Started Jun 25 05:13:37 PM PDT 24
Finished Jun 25 05:13:48 PM PDT 24
Peak memory 198452 kb
Host smart-9c5bce18-aac0-4f0d-a675-7bfef5e571cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854381205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2854381205
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_perf.2644307291
Short name T643
Test name
Test status
Simulation time 16203553296 ps
CPU time 202.35 seconds
Started Jun 25 05:13:37 PM PDT 24
Finished Jun 25 05:17:02 PM PDT 24
Peak memory 199884 kb
Host smart-333e2312-9716-4ea9-baae-c462d48e8243
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2644307291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.2644307291
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.2995537562
Short name T881
Test name
Test status
Simulation time 5311370792 ps
CPU time 8.72 seconds
Started Jun 25 05:13:41 PM PDT 24
Finished Jun 25 05:13:51 PM PDT 24
Peak memory 198000 kb
Host smart-f17da295-f1cb-421f-a1fb-678be253d331
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2995537562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2995537562
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.1119882107
Short name T567
Test name
Test status
Simulation time 27417736778 ps
CPU time 22 seconds
Started Jun 25 05:13:40 PM PDT 24
Finished Jun 25 05:14:04 PM PDT 24
Peak memory 199212 kb
Host smart-45fe2fc7-09f3-4db9-b53f-3a61c77283fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119882107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1119882107
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.4024076726
Short name T515
Test name
Test status
Simulation time 34581625968 ps
CPU time 52.74 seconds
Started Jun 25 05:13:39 PM PDT 24
Finished Jun 25 05:14:34 PM PDT 24
Peak memory 195880 kb
Host smart-654c6b76-151e-415f-98f9-1bffb0d49445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024076726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.4024076726
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.2457534527
Short name T993
Test name
Test status
Simulation time 276008980 ps
CPU time 1.18 seconds
Started Jun 25 05:13:39 PM PDT 24
Finished Jun 25 05:13:42 PM PDT 24
Peak memory 198168 kb
Host smart-7f36b170-4636-409e-bd29-4d03e899ddca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457534527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2457534527
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.2968521336
Short name T721
Test name
Test status
Simulation time 199757731624 ps
CPU time 469.88 seconds
Started Jun 25 05:13:37 PM PDT 24
Finished Jun 25 05:21:30 PM PDT 24
Peak memory 216164 kb
Host smart-3ff73e56-f5ee-4559-b1f7-117ae38fd6cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968521336 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.2968521336
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.902529298
Short name T625
Test name
Test status
Simulation time 6915778299 ps
CPU time 40.01 seconds
Started Jun 25 05:13:39 PM PDT 24
Finished Jun 25 05:14:21 PM PDT 24
Peak memory 199796 kb
Host smart-ae01f231-6ad5-4fbe-b819-2fe9c4207538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902529298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.902529298
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.3227458596
Short name T10
Test name
Test status
Simulation time 74412661639 ps
CPU time 33.62 seconds
Started Jun 25 05:13:40 PM PDT 24
Finished Jun 25 05:14:15 PM PDT 24
Peak memory 199780 kb
Host smart-abc77d3c-e449-460d-aaba-e80ff526bbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227458596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3227458596
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.1838838933
Short name T742
Test name
Test status
Simulation time 55531695964 ps
CPU time 87.13 seconds
Started Jun 25 05:16:50 PM PDT 24
Finished Jun 25 05:18:18 PM PDT 24
Peak memory 199904 kb
Host smart-d3196603-0750-4d13-9f57-fb0cd31b6680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838838933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1838838933
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1157334436
Short name T279
Test name
Test status
Simulation time 34912563060 ps
CPU time 18.6 seconds
Started Jun 25 05:16:47 PM PDT 24
Finished Jun 25 05:17:07 PM PDT 24
Peak memory 199876 kb
Host smart-342bb08d-806e-44c0-93be-297bfec663d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157334436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1157334436
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.3783007410
Short name T190
Test name
Test status
Simulation time 128743442298 ps
CPU time 71.28 seconds
Started Jun 25 05:16:50 PM PDT 24
Finished Jun 25 05:18:03 PM PDT 24
Peak memory 199924 kb
Host smart-bad37f40-c19b-499f-a2c6-8302c6220c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783007410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3783007410
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.2921832719
Short name T517
Test name
Test status
Simulation time 49045835567 ps
CPU time 27.78 seconds
Started Jun 25 05:16:48 PM PDT 24
Finished Jun 25 05:17:18 PM PDT 24
Peak memory 199852 kb
Host smart-9a21b201-ebab-409a-a13e-17830adc23d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921832719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2921832719
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.627061860
Short name T961
Test name
Test status
Simulation time 132296209679 ps
CPU time 173.7 seconds
Started Jun 25 05:16:50 PM PDT 24
Finished Jun 25 05:19:45 PM PDT 24
Peak memory 199704 kb
Host smart-2a40baa4-514f-4387-95cb-b041fb02eecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627061860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.627061860
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.3639812910
Short name T370
Test name
Test status
Simulation time 47718226573 ps
CPU time 70.44 seconds
Started Jun 25 05:17:06 PM PDT 24
Finished Jun 25 05:18:17 PM PDT 24
Peak memory 199896 kb
Host smart-5ec09199-ccf7-4bc9-a3c9-4235cf52e691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639812910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.3639812910
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1228672364
Short name T527
Test name
Test status
Simulation time 31546206764 ps
CPU time 48.21 seconds
Started Jun 25 05:16:55 PM PDT 24
Finished Jun 25 05:17:44 PM PDT 24
Peak memory 199840 kb
Host smart-51786e09-ea3e-4838-8952-ba474867e33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228672364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1228672364
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.3657959854
Short name T570
Test name
Test status
Simulation time 31421291719 ps
CPU time 12.1 seconds
Started Jun 25 05:16:58 PM PDT 24
Finished Jun 25 05:17:11 PM PDT 24
Peak memory 198660 kb
Host smart-e8bb2d19-4425-4a7e-89bb-2747e828d608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657959854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3657959854
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.835859176
Short name T687
Test name
Test status
Simulation time 22297757 ps
CPU time 0.56 seconds
Started Jun 25 05:13:46 PM PDT 24
Finished Jun 25 05:13:48 PM PDT 24
Peak memory 195236 kb
Host smart-714ddbd9-96f8-40f7-a12f-4a5cd795f44a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835859176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.835859176
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.437901031
Short name T152
Test name
Test status
Simulation time 43605950563 ps
CPU time 67.49 seconds
Started Jun 25 05:13:45 PM PDT 24
Finished Jun 25 05:14:54 PM PDT 24
Peak memory 199428 kb
Host smart-b67078fb-63ea-4ac8-a30c-3114708153cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437901031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.437901031
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.3358744969
Short name T292
Test name
Test status
Simulation time 93145646274 ps
CPU time 206.55 seconds
Started Jun 25 05:13:46 PM PDT 24
Finished Jun 25 05:17:14 PM PDT 24
Peak memory 199880 kb
Host smart-a5c5696f-844b-4384-984c-0071cd03cb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358744969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.3358744969
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.1367490281
Short name T729
Test name
Test status
Simulation time 17096755502 ps
CPU time 26.4 seconds
Started Jun 25 05:13:47 PM PDT 24
Finished Jun 25 05:14:15 PM PDT 24
Peak memory 197720 kb
Host smart-f7bcdcef-bdf7-40fd-82b7-b8514ae07685
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367490281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1367490281
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.4089169836
Short name T426
Test name
Test status
Simulation time 91098376634 ps
CPU time 400.25 seconds
Started Jun 25 05:13:46 PM PDT 24
Finished Jun 25 05:20:28 PM PDT 24
Peak memory 199820 kb
Host smart-97561a3b-8646-4c77-8256-7a439771376d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4089169836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.4089169836
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.1121777434
Short name T337
Test name
Test status
Simulation time 12881194405 ps
CPU time 6.87 seconds
Started Jun 25 05:13:47 PM PDT 24
Finished Jun 25 05:13:56 PM PDT 24
Peak memory 199784 kb
Host smart-76270ef2-c7a0-482c-af5c-2989b2736abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121777434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1121777434
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_perf.1418250222
Short name T1063
Test name
Test status
Simulation time 14552112064 ps
CPU time 528.63 seconds
Started Jun 25 05:13:46 PM PDT 24
Finished Jun 25 05:22:36 PM PDT 24
Peak memory 199784 kb
Host smart-178239fa-2247-42f0-8180-164bd27f053f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1418250222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1418250222
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3483408078
Short name T427
Test name
Test status
Simulation time 3705759952 ps
CPU time 14.92 seconds
Started Jun 25 05:13:48 PM PDT 24
Finished Jun 25 05:14:04 PM PDT 24
Peak memory 198108 kb
Host smart-27fd8834-0e54-41f7-be52-91c499cad9e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3483408078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3483408078
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.140856902
Short name T869
Test name
Test status
Simulation time 153434499776 ps
CPU time 166 seconds
Started Jun 25 05:13:47 PM PDT 24
Finished Jun 25 05:16:35 PM PDT 24
Peak memory 199892 kb
Host smart-430d7e07-20c7-4d45-9c35-3eb856253d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140856902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.140856902
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.1887034903
Short name T673
Test name
Test status
Simulation time 4124188704 ps
CPU time 3.77 seconds
Started Jun 25 05:13:49 PM PDT 24
Finished Jun 25 05:13:54 PM PDT 24
Peak memory 196688 kb
Host smart-56a74627-bf70-474d-b437-2a0a919c63bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887034903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1887034903
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.777558824
Short name T400
Test name
Test status
Simulation time 539099873 ps
CPU time 1.57 seconds
Started Jun 25 05:13:50 PM PDT 24
Finished Jun 25 05:13:53 PM PDT 24
Peak memory 198332 kb
Host smart-56351d86-8c87-4012-9b25-c9aa96c91002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777558824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.777558824
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2126791117
Short name T768
Test name
Test status
Simulation time 850856428 ps
CPU time 2.77 seconds
Started Jun 25 05:13:45 PM PDT 24
Finished Jun 25 05:13:49 PM PDT 24
Peak memory 198724 kb
Host smart-aab20a47-dea0-40f4-998b-bc0ff17cd98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126791117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2126791117
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2882184759
Short name T112
Test name
Test status
Simulation time 37886780797 ps
CPU time 29.24 seconds
Started Jun 25 05:13:47 PM PDT 24
Finished Jun 25 05:14:18 PM PDT 24
Peak memory 199756 kb
Host smart-1e7998ed-71a5-42e1-b229-7eec95c18a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882184759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2882184759
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.3839114275
Short name T204
Test name
Test status
Simulation time 108184851618 ps
CPU time 89.74 seconds
Started Jun 25 05:17:06 PM PDT 24
Finished Jun 25 05:18:37 PM PDT 24
Peak memory 199836 kb
Host smart-bcb49222-6ac6-4e26-9778-4a15d54fe5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839114275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3839114275
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.346088014
Short name T458
Test name
Test status
Simulation time 80372231808 ps
CPU time 14.01 seconds
Started Jun 25 05:16:58 PM PDT 24
Finished Jun 25 05:17:13 PM PDT 24
Peak memory 199620 kb
Host smart-2ff7ee5e-4e92-4f7f-8f44-57ab6e00c6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346088014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.346088014
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.955047698
Short name T749
Test name
Test status
Simulation time 39806168478 ps
CPU time 15.51 seconds
Started Jun 25 05:16:59 PM PDT 24
Finished Jun 25 05:17:15 PM PDT 24
Peak memory 198852 kb
Host smart-1bc9a8aa-c088-43db-9c8e-92505ae553fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955047698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.955047698
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2532469956
Short name T805
Test name
Test status
Simulation time 43769334613 ps
CPU time 33.15 seconds
Started Jun 25 05:16:58 PM PDT 24
Finished Jun 25 05:17:32 PM PDT 24
Peak memory 200016 kb
Host smart-a41c4b9f-e9b4-42f8-aa20-201c536822ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532469956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2532469956
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.212086334
Short name T194
Test name
Test status
Simulation time 110496829911 ps
CPU time 93.1 seconds
Started Jun 25 05:16:56 PM PDT 24
Finished Jun 25 05:18:30 PM PDT 24
Peak memory 199864 kb
Host smart-6fb9207c-49e2-4858-a29d-45e8d082e940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212086334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.212086334
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.670083568
Short name T384
Test name
Test status
Simulation time 160334716629 ps
CPU time 20.9 seconds
Started Jun 25 05:16:57 PM PDT 24
Finished Jun 25 05:17:19 PM PDT 24
Peak memory 199880 kb
Host smart-00329463-2458-439d-b479-bf384740dc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670083568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.670083568
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.4259226704
Short name T186
Test name
Test status
Simulation time 97881749759 ps
CPU time 40.64 seconds
Started Jun 25 05:16:59 PM PDT 24
Finished Jun 25 05:17:40 PM PDT 24
Peak memory 199844 kb
Host smart-bd6c8958-2440-42d2-a9e9-d4393ba9c6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259226704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.4259226704
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.2086695053
Short name T704
Test name
Test status
Simulation time 166920914671 ps
CPU time 38.04 seconds
Started Jun 25 05:17:06 PM PDT 24
Finished Jun 25 05:17:45 PM PDT 24
Peak memory 199824 kb
Host smart-64f6d2c2-41fe-4f9f-bea2-302e76525105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086695053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.2086695053
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.3212520787
Short name T744
Test name
Test status
Simulation time 20012353075 ps
CPU time 15.28 seconds
Started Jun 25 05:16:58 PM PDT 24
Finished Jun 25 05:17:14 PM PDT 24
Peak memory 199940 kb
Host smart-86f13fb9-80dc-4870-bd67-11b3fc991c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212520787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.3212520787
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.4145083080
Short name T436
Test name
Test status
Simulation time 219967447734 ps
CPU time 64.21 seconds
Started Jun 25 05:16:57 PM PDT 24
Finished Jun 25 05:18:03 PM PDT 24
Peak memory 199844 kb
Host smart-3ad4b8d6-801f-487e-9bbe-6cb1aeb4892b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145083080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.4145083080
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.3466667127
Short name T924
Test name
Test status
Simulation time 11678901 ps
CPU time 0.57 seconds
Started Jun 25 05:13:47 PM PDT 24
Finished Jun 25 05:13:49 PM PDT 24
Peak memory 195236 kb
Host smart-690352a4-c425-40ed-9eb4-ed9b20ad8a17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466667127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.3466667127
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2884388823
Short name T892
Test name
Test status
Simulation time 36531668950 ps
CPU time 57.72 seconds
Started Jun 25 05:13:46 PM PDT 24
Finished Jun 25 05:14:46 PM PDT 24
Peak memory 199900 kb
Host smart-41aa7b47-8f84-4d7f-b764-28bf7a9a2455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884388823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2884388823
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.3197500166
Short name T1002
Test name
Test status
Simulation time 229819323259 ps
CPU time 34.14 seconds
Started Jun 25 05:13:46 PM PDT 24
Finished Jun 25 05:14:21 PM PDT 24
Peak memory 199852 kb
Host smart-6a458b06-4c9a-4e1f-b6ae-6fdd112e9b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197500166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3197500166
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.1854631120
Short name T176
Test name
Test status
Simulation time 120965748729 ps
CPU time 151.26 seconds
Started Jun 25 05:13:47 PM PDT 24
Finished Jun 25 05:16:20 PM PDT 24
Peak memory 199844 kb
Host smart-ce72fc25-b6a1-43e3-9b88-3c838111d8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854631120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1854631120
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.775118919
Short name T686
Test name
Test status
Simulation time 41112505351 ps
CPU time 55.93 seconds
Started Jun 25 05:13:50 PM PDT 24
Finished Jun 25 05:14:48 PM PDT 24
Peak memory 199744 kb
Host smart-db41a231-c6b9-41fd-a3b3-5b87582aab6d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775118919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.775118919
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.2057378443
Short name T799
Test name
Test status
Simulation time 104779939024 ps
CPU time 742.3 seconds
Started Jun 25 05:13:48 PM PDT 24
Finished Jun 25 05:26:12 PM PDT 24
Peak memory 199752 kb
Host smart-a0844de2-a789-4e75-b5a5-8ffc0d6fd954
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2057378443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.2057378443
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.1362056929
Short name T830
Test name
Test status
Simulation time 3384189073 ps
CPU time 6.56 seconds
Started Jun 25 05:13:48 PM PDT 24
Finished Jun 25 05:13:56 PM PDT 24
Peak memory 198736 kb
Host smart-4dc7e5e2-77dd-4e2f-a720-d3359a8d63dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362056929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1362056929
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_perf.2878412716
Short name T390
Test name
Test status
Simulation time 7514500689 ps
CPU time 416.71 seconds
Started Jun 25 05:13:49 PM PDT 24
Finished Jun 25 05:20:47 PM PDT 24
Peak memory 199752 kb
Host smart-c0c60a60-7ffb-4656-9e36-1abdcdf308fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2878412716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2878412716
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.138515129
Short name T51
Test name
Test status
Simulation time 4116237599 ps
CPU time 32.86 seconds
Started Jun 25 05:13:48 PM PDT 24
Finished Jun 25 05:14:22 PM PDT 24
Peak memory 198044 kb
Host smart-dade36ec-7b69-4f31-95e2-827d2f4e5f0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=138515129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.138515129
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1080307969
Short name T1023
Test name
Test status
Simulation time 42056443478 ps
CPU time 31.68 seconds
Started Jun 25 05:13:45 PM PDT 24
Finished Jun 25 05:14:19 PM PDT 24
Peak memory 199080 kb
Host smart-dbae0962-ebdc-4b80-9adc-6a508459f3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080307969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1080307969
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.783148283
Short name T980
Test name
Test status
Simulation time 48326579420 ps
CPU time 13.38 seconds
Started Jun 25 05:13:47 PM PDT 24
Finished Jun 25 05:14:02 PM PDT 24
Peak memory 196160 kb
Host smart-c2bab077-c026-4717-8882-750d348e55a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783148283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.783148283
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.3771353353
Short name T669
Test name
Test status
Simulation time 435593772 ps
CPU time 1.39 seconds
Started Jun 25 05:13:47 PM PDT 24
Finished Jun 25 05:13:50 PM PDT 24
Peak memory 198428 kb
Host smart-ab803156-e14f-4a28-b35b-f25dc557d632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771353353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3771353353
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.3700006794
Short name T154
Test name
Test status
Simulation time 132674424516 ps
CPU time 206.24 seconds
Started Jun 25 05:13:50 PM PDT 24
Finished Jun 25 05:17:18 PM PDT 24
Peak memory 199812 kb
Host smart-c5292e26-c893-4b5d-b780-56debe9068ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700006794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3700006794
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.1478008023
Short name T968
Test name
Test status
Simulation time 49126524563 ps
CPU time 152.24 seconds
Started Jun 25 05:13:47 PM PDT 24
Finished Jun 25 05:16:21 PM PDT 24
Peak memory 208152 kb
Host smart-d27ef8e4-3a33-4e17-830e-5e4abdbe7dcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478008023 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.1478008023
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.2061131974
Short name T294
Test name
Test status
Simulation time 7484906439 ps
CPU time 12.85 seconds
Started Jun 25 05:13:51 PM PDT 24
Finished Jun 25 05:14:05 PM PDT 24
Peak memory 199816 kb
Host smart-942b3d02-54ba-4729-8152-bf4bdaa2097b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061131974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2061131974
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.3498269210
Short name T900
Test name
Test status
Simulation time 77582179332 ps
CPU time 56.34 seconds
Started Jun 25 05:16:59 PM PDT 24
Finished Jun 25 05:17:56 PM PDT 24
Peak memory 199932 kb
Host smart-86ae7955-5b6b-41e1-bc25-2967166f6fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498269210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3498269210
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.2971304394
Short name T447
Test name
Test status
Simulation time 32586100353 ps
CPU time 34.82 seconds
Started Jun 25 05:16:56 PM PDT 24
Finished Jun 25 05:17:32 PM PDT 24
Peak memory 199880 kb
Host smart-847298fe-294d-4529-9525-af160694fc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971304394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2971304394
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.2497110696
Short name T1010
Test name
Test status
Simulation time 91856730039 ps
CPU time 148.66 seconds
Started Jun 25 05:16:57 PM PDT 24
Finished Jun 25 05:19:27 PM PDT 24
Peak memory 199844 kb
Host smart-35a8d696-50b9-43a6-be5f-13d110cdea1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497110696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2497110696
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.3214962269
Short name T182
Test name
Test status
Simulation time 115460405414 ps
CPU time 42.41 seconds
Started Jun 25 05:16:57 PM PDT 24
Finished Jun 25 05:17:41 PM PDT 24
Peak memory 199812 kb
Host smart-4bb67c28-9e28-40ac-9be1-f0b9fd05ea75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214962269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3214962269
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.2816771825
Short name T723
Test name
Test status
Simulation time 28672856623 ps
CPU time 49.72 seconds
Started Jun 25 05:16:58 PM PDT 24
Finished Jun 25 05:17:49 PM PDT 24
Peak memory 199776 kb
Host smart-6f4cdd24-8023-4118-92d9-7695d2350364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816771825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.2816771825
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.481774263
Short name T325
Test name
Test status
Simulation time 25497826012 ps
CPU time 32.06 seconds
Started Jun 25 05:16:58 PM PDT 24
Finished Jun 25 05:17:31 PM PDT 24
Peak memory 199880 kb
Host smart-4a08a699-021a-4174-8019-c3956dafac22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481774263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.481774263
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.4154031696
Short name T280
Test name
Test status
Simulation time 56100078868 ps
CPU time 37.13 seconds
Started Jun 25 05:16:58 PM PDT 24
Finished Jun 25 05:17:36 PM PDT 24
Peak memory 199776 kb
Host smart-903009a2-7d60-4c47-a314-b3c8d876d0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154031696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.4154031696
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.2304809331
Short name T867
Test name
Test status
Simulation time 35495822081 ps
CPU time 50.38 seconds
Started Jun 25 05:16:55 PM PDT 24
Finished Jun 25 05:17:47 PM PDT 24
Peak memory 199844 kb
Host smart-644ec998-2acc-437b-9102-2a2aeaec2317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304809331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2304809331
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.3850320203
Short name T259
Test name
Test status
Simulation time 49210279751 ps
CPU time 16.19 seconds
Started Jun 25 05:16:57 PM PDT 24
Finished Jun 25 05:17:14 PM PDT 24
Peak memory 199860 kb
Host smart-c3c8fa14-bb55-4421-8d0c-ea81c6c0180e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850320203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3850320203
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.980443443
Short name T820
Test name
Test status
Simulation time 20823138 ps
CPU time 0.55 seconds
Started Jun 25 05:13:53 PM PDT 24
Finished Jun 25 05:13:55 PM PDT 24
Peak memory 195200 kb
Host smart-935146f3-8d3d-4296-be19-ff99e7abdec1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980443443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.980443443
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.1280268319
Short name T131
Test name
Test status
Simulation time 41101052684 ps
CPU time 45.68 seconds
Started Jun 25 05:13:47 PM PDT 24
Finished Jun 25 05:14:34 PM PDT 24
Peak memory 199836 kb
Host smart-38d5a605-d929-4661-811b-c0178ef6e7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280268319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1280268319
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.4292260855
Short name T676
Test name
Test status
Simulation time 173088337934 ps
CPU time 58.63 seconds
Started Jun 25 05:13:46 PM PDT 24
Finished Jun 25 05:14:47 PM PDT 24
Peak memory 199928 kb
Host smart-dfdf8be2-5e8c-47b3-a0dd-56e9f766cdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292260855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.4292260855
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_intr.2394033813
Short name T916
Test name
Test status
Simulation time 7827874102 ps
CPU time 12.24 seconds
Started Jun 25 05:13:46 PM PDT 24
Finished Jun 25 05:14:00 PM PDT 24
Peak memory 196152 kb
Host smart-84d3598c-c756-47db-b580-e696f332ea81
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394033813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2394033813
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.2492038152
Short name T369
Test name
Test status
Simulation time 51640776824 ps
CPU time 249.91 seconds
Started Jun 25 05:13:55 PM PDT 24
Finished Jun 25 05:18:06 PM PDT 24
Peak memory 199916 kb
Host smart-0e673c5a-228e-41d1-ab13-1d2ea4d4983e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2492038152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.2492038152
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.4066011401
Short name T489
Test name
Test status
Simulation time 6971524173 ps
CPU time 1.93 seconds
Started Jun 25 05:13:46 PM PDT 24
Finished Jun 25 05:13:50 PM PDT 24
Peak memory 199492 kb
Host smart-2cdfe3bc-6b20-4623-b4f0-327de5ccadbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066011401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.4066011401
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_perf.2302077599
Short name T756
Test name
Test status
Simulation time 8407336867 ps
CPU time 248.35 seconds
Started Jun 25 05:13:55 PM PDT 24
Finished Jun 25 05:18:05 PM PDT 24
Peak memory 199756 kb
Host smart-0ce29e0d-834a-4a69-8395-3d8011511699
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2302077599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.2302077599
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.3672946535
Short name T562
Test name
Test status
Simulation time 3548300664 ps
CPU time 24.56 seconds
Started Jun 25 05:13:47 PM PDT 24
Finished Jun 25 05:14:13 PM PDT 24
Peak memory 198020 kb
Host smart-f277b4bc-8441-4b44-aa5a-fd80896d5caf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3672946535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.3672946535
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.4094620536
Short name T591
Test name
Test status
Simulation time 4355150494 ps
CPU time 2.14 seconds
Started Jun 25 05:13:46 PM PDT 24
Finished Jun 25 05:13:49 PM PDT 24
Peak memory 195960 kb
Host smart-a6f5028f-3bf2-4791-ab07-a57b3cb168e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094620536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.4094620536
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.4268179818
Short name T873
Test name
Test status
Simulation time 524343851 ps
CPU time 1.62 seconds
Started Jun 25 05:13:48 PM PDT 24
Finished Jun 25 05:13:51 PM PDT 24
Peak memory 198132 kb
Host smart-8ba006a5-02f5-4f64-9f28-37661c23f5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268179818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.4268179818
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.1689280720
Short name T688
Test name
Test status
Simulation time 1291039426 ps
CPU time 5.77 seconds
Started Jun 25 05:13:45 PM PDT 24
Finished Jun 25 05:13:52 PM PDT 24
Peak memory 199764 kb
Host smart-a99dfe47-3872-42f3-88e7-b124d7093819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689280720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1689280720
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.2508322499
Short name T468
Test name
Test status
Simulation time 5356859124 ps
CPU time 18.26 seconds
Started Jun 25 05:13:46 PM PDT 24
Finished Jun 25 05:14:06 PM PDT 24
Peak memory 199844 kb
Host smart-84980f82-d6eb-493b-98df-4bf53a544b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508322499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.2508322499
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.3367644932
Short name T474
Test name
Test status
Simulation time 118965236755 ps
CPU time 27.85 seconds
Started Jun 25 05:16:57 PM PDT 24
Finished Jun 25 05:17:26 PM PDT 24
Peak memory 199832 kb
Host smart-554f72a1-16c7-4bd3-8c3a-b1daf289bf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367644932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.3367644932
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.280385884
Short name T1018
Test name
Test status
Simulation time 111510502897 ps
CPU time 78.55 seconds
Started Jun 25 05:16:59 PM PDT 24
Finished Jun 25 05:18:19 PM PDT 24
Peak memory 199712 kb
Host smart-f7ee3c12-21f6-41d7-92c9-82bc7827763b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280385884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.280385884
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.3842958436
Short name T284
Test name
Test status
Simulation time 103780523213 ps
CPU time 172.39 seconds
Started Jun 25 05:17:06 PM PDT 24
Finished Jun 25 05:19:59 PM PDT 24
Peak memory 199896 kb
Host smart-8a62456c-56e1-4eae-90f4-5f68e45bf875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842958436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.3842958436
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.718127778
Short name T44
Test name
Test status
Simulation time 67422916943 ps
CPU time 111.93 seconds
Started Jun 25 05:16:57 PM PDT 24
Finished Jun 25 05:18:51 PM PDT 24
Peak memory 199732 kb
Host smart-52c65071-d859-4619-bd97-33fcfc8f53e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718127778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.718127778
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2939987924
Short name T289
Test name
Test status
Simulation time 20662148490 ps
CPU time 35.92 seconds
Started Jun 25 05:17:00 PM PDT 24
Finished Jun 25 05:17:36 PM PDT 24
Peak memory 199848 kb
Host smart-a3428bca-552a-4866-945a-0251aaa5ab8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939987924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2939987924
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.1873286104
Short name T700
Test name
Test status
Simulation time 8409464871 ps
CPU time 12.47 seconds
Started Jun 25 05:16:56 PM PDT 24
Finished Jun 25 05:17:09 PM PDT 24
Peak memory 199824 kb
Host smart-74063e7f-1dde-46dc-9fe3-fd51de8aa7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873286104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1873286104
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.459536818
Short name T797
Test name
Test status
Simulation time 16796797334 ps
CPU time 27.68 seconds
Started Jun 25 05:16:58 PM PDT 24
Finished Jun 25 05:17:27 PM PDT 24
Peak memory 199868 kb
Host smart-2c7a1233-e757-437d-a9ef-26fd4dd96882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459536818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.459536818
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.1329346417
Short name T750
Test name
Test status
Simulation time 64456698715 ps
CPU time 111.75 seconds
Started Jun 25 05:16:58 PM PDT 24
Finished Jun 25 05:18:51 PM PDT 24
Peak memory 199812 kb
Host smart-d12395a7-e416-4914-a97e-a13400ab5f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329346417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1329346417
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.332666770
Short name T359
Test name
Test status
Simulation time 101775241969 ps
CPU time 16.01 seconds
Started Jun 25 05:16:59 PM PDT 24
Finished Jun 25 05:17:16 PM PDT 24
Peak memory 198804 kb
Host smart-1748879f-7fbf-490a-a1cf-bb931ce46a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332666770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.332666770
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.1065154460
Short name T221
Test name
Test status
Simulation time 16841660094 ps
CPU time 26.48 seconds
Started Jun 25 05:17:06 PM PDT 24
Finished Jun 25 05:17:33 PM PDT 24
Peak memory 199828 kb
Host smart-7d4b7900-c0d2-4950-a153-45ed225dfe69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065154460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1065154460
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.3663734103
Short name T512
Test name
Test status
Simulation time 18440445 ps
CPU time 0.57 seconds
Started Jun 25 05:13:56 PM PDT 24
Finished Jun 25 05:13:57 PM PDT 24
Peak memory 195496 kb
Host smart-d0bfe0d9-7afa-4725-8a78-731385bd8189
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663734103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3663734103
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.3599250816
Short name T394
Test name
Test status
Simulation time 14807209950 ps
CPU time 22.32 seconds
Started Jun 25 05:13:54 PM PDT 24
Finished Jun 25 05:14:18 PM PDT 24
Peak memory 199884 kb
Host smart-5af50577-7592-4244-89e2-746e2bd66a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599250816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3599250816
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.3471964723
Short name T963
Test name
Test status
Simulation time 78121629901 ps
CPU time 29.74 seconds
Started Jun 25 05:13:55 PM PDT 24
Finished Jun 25 05:14:27 PM PDT 24
Peak memory 199896 kb
Host smart-7016405b-f4b7-43e4-a154-3f1d886afab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471964723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3471964723
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.2088490681
Short name T492
Test name
Test status
Simulation time 180085829772 ps
CPU time 72.96 seconds
Started Jun 25 05:13:54 PM PDT 24
Finished Jun 25 05:15:07 PM PDT 24
Peak memory 199840 kb
Host smart-6c708147-904a-47f4-81c2-504c3719f603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088490681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2088490681
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.2011832030
Short name T1025
Test name
Test status
Simulation time 52057167320 ps
CPU time 38.11 seconds
Started Jun 25 05:13:57 PM PDT 24
Finished Jun 25 05:14:36 PM PDT 24
Peak memory 199828 kb
Host smart-47ef087b-92e8-4933-8589-bb68da6cbbb1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011832030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2011832030
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.3509069612
Short name T451
Test name
Test status
Simulation time 44177364942 ps
CPU time 192.29 seconds
Started Jun 25 05:13:57 PM PDT 24
Finished Jun 25 05:17:11 PM PDT 24
Peak memory 199756 kb
Host smart-b0f762a5-c8b9-48fe-b5b2-27279ae6f609
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3509069612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.3509069612
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3873590016
Short name T741
Test name
Test status
Simulation time 2346194464 ps
CPU time 4.33 seconds
Started Jun 25 05:13:57 PM PDT 24
Finished Jun 25 05:14:02 PM PDT 24
Peak memory 196024 kb
Host smart-0a29a78e-78f4-4541-9de6-33c5ae6f65c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873590016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3873590016
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_perf.3624006848
Short name T247
Test name
Test status
Simulation time 30941861287 ps
CPU time 1564.62 seconds
Started Jun 25 05:13:57 PM PDT 24
Finished Jun 25 05:40:03 PM PDT 24
Peak memory 199836 kb
Host smart-a5562d85-7063-4a79-add0-e779a48738f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3624006848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3624006848
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.710563271
Short name T478
Test name
Test status
Simulation time 4758390311 ps
CPU time 9.71 seconds
Started Jun 25 05:13:53 PM PDT 24
Finished Jun 25 05:14:04 PM PDT 24
Peak memory 198784 kb
Host smart-4ad7db94-9ddf-44f7-95c7-c1bdc851a3de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=710563271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.710563271
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1085963375
Short name T309
Test name
Test status
Simulation time 32084520229 ps
CPU time 32.93 seconds
Started Jun 25 05:13:56 PM PDT 24
Finished Jun 25 05:14:30 PM PDT 24
Peak memory 199868 kb
Host smart-0e965cab-cd6c-4951-95c0-ae41aaa8a96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085963375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1085963375
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.3309620250
Short name T1078
Test name
Test status
Simulation time 688091757 ps
CPU time 0.86 seconds
Started Jun 25 05:13:55 PM PDT 24
Finished Jun 25 05:13:57 PM PDT 24
Peak memory 195356 kb
Host smart-599f3dfe-ff27-441f-98d1-fa92fe3ef501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309620250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3309620250
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.2406338301
Short name T615
Test name
Test status
Simulation time 889599022 ps
CPU time 4.33 seconds
Started Jun 25 05:13:57 PM PDT 24
Finished Jun 25 05:14:03 PM PDT 24
Peak memory 199820 kb
Host smart-6291d799-ae3b-4c40-bac6-5d940bac0d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406338301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2406338301
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3193613132
Short name T826
Test name
Test status
Simulation time 3525776382 ps
CPU time 1.95 seconds
Started Jun 25 05:13:57 PM PDT 24
Finished Jun 25 05:14:00 PM PDT 24
Peak memory 198536 kb
Host smart-2e1ce7d6-0770-4c7c-8849-d73efed4d269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193613132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3193613132
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.1813019642
Short name T788
Test name
Test status
Simulation time 69208964254 ps
CPU time 53.38 seconds
Started Jun 25 05:13:56 PM PDT 24
Finished Jun 25 05:14:51 PM PDT 24
Peak memory 199868 kb
Host smart-83542d27-53da-4f2a-a51c-c2ce6ffcad7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813019642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.1813019642
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.36847016
Short name T240
Test name
Test status
Simulation time 258417909513 ps
CPU time 56.99 seconds
Started Jun 25 05:16:57 PM PDT 24
Finished Jun 25 05:17:55 PM PDT 24
Peak memory 199844 kb
Host smart-ee4dc7aa-0b64-4d3d-9640-4d2d6c4d6536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36847016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.36847016
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3551949668
Short name T535
Test name
Test status
Simulation time 39817815882 ps
CPU time 13.84 seconds
Started Jun 25 05:17:05 PM PDT 24
Finished Jun 25 05:17:20 PM PDT 24
Peak memory 199892 kb
Host smart-c2063ba9-344e-4d5f-b0d7-654103e292a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551949668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3551949668
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1273651946
Short name T97
Test name
Test status
Simulation time 18082412529 ps
CPU time 14.47 seconds
Started Jun 25 05:17:03 PM PDT 24
Finished Jun 25 05:17:18 PM PDT 24
Peak memory 199868 kb
Host smart-ef66c96e-117f-4ebc-8629-3a8a5a182fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273651946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1273651946
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.2891745050
Short name T175
Test name
Test status
Simulation time 130684974358 ps
CPU time 191.63 seconds
Started Jun 25 05:17:06 PM PDT 24
Finished Jun 25 05:20:18 PM PDT 24
Peak memory 199772 kb
Host smart-2d224dda-e61b-4e2c-8a11-2a7be9bf9f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891745050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2891745050
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1729104599
Short name T956
Test name
Test status
Simulation time 47274018566 ps
CPU time 21.09 seconds
Started Jun 25 05:17:06 PM PDT 24
Finished Jun 25 05:17:28 PM PDT 24
Peak memory 199740 kb
Host smart-0ec28e86-511c-418c-a5e2-650ffd94443e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729104599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1729104599
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2284011081
Short name T140
Test name
Test status
Simulation time 157919700654 ps
CPU time 57.46 seconds
Started Jun 25 05:17:05 PM PDT 24
Finished Jun 25 05:18:03 PM PDT 24
Peak memory 199892 kb
Host smart-7df0704d-b42a-4123-8f93-b0f56fddbae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284011081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2284011081
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.299173028
Short name T724
Test name
Test status
Simulation time 9847044224 ps
CPU time 13.73 seconds
Started Jun 25 05:17:05 PM PDT 24
Finished Jun 25 05:17:20 PM PDT 24
Peak memory 199828 kb
Host smart-ae6744a8-2421-4559-8b01-3548adc8a8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299173028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.299173028
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.1664566641
Short name T859
Test name
Test status
Simulation time 41988080911 ps
CPU time 18.28 seconds
Started Jun 25 05:17:07 PM PDT 24
Finished Jun 25 05:17:26 PM PDT 24
Peak memory 200092 kb
Host smart-a47be208-0d92-4c3e-99ab-ff469fc2aea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664566641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.1664566641
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.3561351480
Short name T905
Test name
Test status
Simulation time 35143515046 ps
CPU time 34.06 seconds
Started Jun 25 05:17:06 PM PDT 24
Finished Jun 25 05:17:42 PM PDT 24
Peak memory 199832 kb
Host smart-f7457b8c-55c0-4e5e-92df-670d3d725e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561351480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3561351480
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.1241969468
Short name T522
Test name
Test status
Simulation time 24898991 ps
CPU time 0.57 seconds
Started Jun 25 05:14:01 PM PDT 24
Finished Jun 25 05:14:03 PM PDT 24
Peak memory 195452 kb
Host smart-dcad816f-0a75-472b-9977-b045482262f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241969468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1241969468
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.4161212247
Short name T725
Test name
Test status
Simulation time 39603264322 ps
CPU time 75.83 seconds
Started Jun 25 05:13:55 PM PDT 24
Finished Jun 25 05:15:12 PM PDT 24
Peak memory 199932 kb
Host smart-ee4f6c82-7680-4835-b342-78c7ce0a2700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161212247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.4161212247
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.3079434983
Short name T328
Test name
Test status
Simulation time 56758518741 ps
CPU time 26.83 seconds
Started Jun 25 05:13:54 PM PDT 24
Finished Jun 25 05:14:22 PM PDT 24
Peak memory 199824 kb
Host smart-07030856-82e8-4056-a844-0962cf587664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079434983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3079434983
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.2942019028
Short name T819
Test name
Test status
Simulation time 41978200647 ps
CPU time 65.19 seconds
Started Jun 25 05:13:57 PM PDT 24
Finished Jun 25 05:15:03 PM PDT 24
Peak memory 199828 kb
Host smart-552e4213-b0b2-48b3-8316-1de532715b66
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942019028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2942019028
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.2445556639
Short name T836
Test name
Test status
Simulation time 88866623682 ps
CPU time 507.54 seconds
Started Jun 25 05:14:02 PM PDT 24
Finished Jun 25 05:22:31 PM PDT 24
Peak memory 199908 kb
Host smart-20278a42-1d8a-4f34-a3e9-4f19f19860ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2445556639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2445556639
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.2358295592
Short name T396
Test name
Test status
Simulation time 8393712182 ps
CPU time 5.03 seconds
Started Jun 25 05:14:00 PM PDT 24
Finished Jun 25 05:14:06 PM PDT 24
Peak memory 198992 kb
Host smart-077a1559-e3fb-4eca-936c-55e22f96c7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358295592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2358295592
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.1677718766
Short name T622
Test name
Test status
Simulation time 113261070422 ps
CPU time 79.99 seconds
Started Jun 25 05:13:54 PM PDT 24
Finished Jun 25 05:15:15 PM PDT 24
Peak memory 199896 kb
Host smart-ceb191f7-6183-4448-821f-1ccef9a58fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677718766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.1677718766
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.2241017363
Short name T375
Test name
Test status
Simulation time 15167524679 ps
CPU time 408.11 seconds
Started Jun 25 05:14:06 PM PDT 24
Finished Jun 25 05:20:55 PM PDT 24
Peak memory 199756 kb
Host smart-876cea26-b516-4f6e-a0de-56efbda3d0d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2241017363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2241017363
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.1363628099
Short name T367
Test name
Test status
Simulation time 3758844548 ps
CPU time 15.19 seconds
Started Jun 25 05:13:57 PM PDT 24
Finished Jun 25 05:14:13 PM PDT 24
Peak memory 197708 kb
Host smart-7bc74f92-9da4-48a7-ad0a-e88401f2f58a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1363628099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1363628099
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.3972984600
Short name T100
Test name
Test status
Simulation time 16752174977 ps
CPU time 26.74 seconds
Started Jun 25 05:13:55 PM PDT 24
Finished Jun 25 05:14:23 PM PDT 24
Peak memory 199392 kb
Host smart-67d4cfe1-5f82-4d97-8d4e-e1b602fe94d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972984600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3972984600
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.2324456503
Short name T397
Test name
Test status
Simulation time 40627441941 ps
CPU time 67.79 seconds
Started Jun 25 05:13:56 PM PDT 24
Finished Jun 25 05:15:05 PM PDT 24
Peak memory 195940 kb
Host smart-2af708e7-6ea3-49c0-9e31-eeb579802581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324456503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.2324456503
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.3323968650
Short name T374
Test name
Test status
Simulation time 6077261855 ps
CPU time 18.14 seconds
Started Jun 25 05:13:55 PM PDT 24
Finished Jun 25 05:14:15 PM PDT 24
Peak memory 199884 kb
Host smart-00ae822b-2f63-421e-8bba-b381c609607f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323968650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.3323968650
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.3903881403
Short name T979
Test name
Test status
Simulation time 94172715344 ps
CPU time 770.42 seconds
Started Jun 25 05:14:04 PM PDT 24
Finished Jun 25 05:26:56 PM PDT 24
Peak memory 199888 kb
Host smart-b0d4f561-2e58-40b1-b48d-c3a2389455c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903881403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3903881403
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.3589102295
Short name T602
Test name
Test status
Simulation time 804077752 ps
CPU time 1.5 seconds
Started Jun 25 05:14:03 PM PDT 24
Finished Jun 25 05:14:06 PM PDT 24
Peak memory 198200 kb
Host smart-e486cf22-2589-41f5-b6b6-0e312ec41e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589102295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3589102295
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.543421968
Short name T482
Test name
Test status
Simulation time 28793369270 ps
CPU time 9.31 seconds
Started Jun 25 05:13:57 PM PDT 24
Finished Jun 25 05:14:07 PM PDT 24
Peak memory 199872 kb
Host smart-916ed74d-26f8-4933-b9af-de951e25584b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543421968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.543421968
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.2002058908
Short name T814
Test name
Test status
Simulation time 72470080146 ps
CPU time 31.69 seconds
Started Jun 25 05:17:06 PM PDT 24
Finished Jun 25 05:17:38 PM PDT 24
Peak memory 199780 kb
Host smart-5203daf7-2c90-4e0d-b75b-84e179c6a8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002058908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2002058908
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2196894690
Short name T487
Test name
Test status
Simulation time 130894987450 ps
CPU time 46.08 seconds
Started Jun 25 05:17:04 PM PDT 24
Finished Jun 25 05:17:51 PM PDT 24
Peak memory 199852 kb
Host smart-9aed3606-e604-4130-be7f-456a02926ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196894690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2196894690
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.3017197658
Short name T983
Test name
Test status
Simulation time 64209695243 ps
CPU time 12.92 seconds
Started Jun 25 05:17:06 PM PDT 24
Finished Jun 25 05:17:20 PM PDT 24
Peak memory 199868 kb
Host smart-96057e92-8f09-4db8-bd26-0d54bfd2f66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017197658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3017197658
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.212364110
Short name T745
Test name
Test status
Simulation time 89013277899 ps
CPU time 39.13 seconds
Started Jun 25 05:17:06 PM PDT 24
Finished Jun 25 05:17:46 PM PDT 24
Peak memory 199920 kb
Host smart-1dba85c0-8c44-421c-afbe-397d5d514695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212364110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.212364110
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.1542075594
Short name T250
Test name
Test status
Simulation time 112272756743 ps
CPU time 49.84 seconds
Started Jun 25 05:17:08 PM PDT 24
Finished Jun 25 05:17:58 PM PDT 24
Peak memory 200076 kb
Host smart-76843eb0-6aa2-4cbb-b565-f6a6f8c1706b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542075594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1542075594
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.4188271842
Short name T210
Test name
Test status
Simulation time 175907040591 ps
CPU time 25.87 seconds
Started Jun 25 05:17:06 PM PDT 24
Finished Jun 25 05:17:33 PM PDT 24
Peak memory 199868 kb
Host smart-fc88db15-dad1-4f8a-8a47-8970c7af66d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188271842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.4188271842
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.3243652328
Short name T1082
Test name
Test status
Simulation time 72131217458 ps
CPU time 16.6 seconds
Started Jun 25 05:17:16 PM PDT 24
Finished Jun 25 05:17:34 PM PDT 24
Peak memory 199788 kb
Host smart-8b2b448d-2643-4bdc-a1cd-f0aacdfa4d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243652328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.3243652328
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.1993177225
Short name T823
Test name
Test status
Simulation time 11851791 ps
CPU time 0.58 seconds
Started Jun 25 05:14:01 PM PDT 24
Finished Jun 25 05:14:02 PM PDT 24
Peak memory 195432 kb
Host smart-9f124833-018d-4a97-baa7-85f5d3769025
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993177225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1993177225
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.3037466086
Short name T470
Test name
Test status
Simulation time 75993972439 ps
CPU time 60.75 seconds
Started Jun 25 05:14:04 PM PDT 24
Finished Jun 25 05:15:07 PM PDT 24
Peak memory 199852 kb
Host smart-a291224b-f4e6-4fc3-8a59-7eb9c7ce3464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037466086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3037466086
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.4056520551
Short name T660
Test name
Test status
Simulation time 94245082921 ps
CPU time 141.73 seconds
Started Jun 25 05:14:04 PM PDT 24
Finished Jun 25 05:16:27 PM PDT 24
Peak memory 199912 kb
Host smart-9ede3f11-aebb-45b5-bc32-c4b83807bc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056520551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.4056520551
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3733410138
Short name T209
Test name
Test status
Simulation time 74381404068 ps
CPU time 31.57 seconds
Started Jun 25 05:14:02 PM PDT 24
Finished Jun 25 05:14:35 PM PDT 24
Peak memory 199916 kb
Host smart-06da91bc-fd65-41a2-ad35-72021e15261d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733410138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3733410138
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.3578903936
Short name T460
Test name
Test status
Simulation time 96055108619 ps
CPU time 128.69 seconds
Started Jun 25 05:14:03 PM PDT 24
Finished Jun 25 05:16:13 PM PDT 24
Peak memory 196568 kb
Host smart-f5bff6fc-da05-4718-a98c-2334349221f8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578903936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3578903936
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.872410832
Short name T287
Test name
Test status
Simulation time 121800091665 ps
CPU time 326.87 seconds
Started Jun 25 05:14:04 PM PDT 24
Finished Jun 25 05:19:32 PM PDT 24
Peak memory 199820 kb
Host smart-76363547-6a67-49b5-b581-9058feaa3404
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=872410832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.872410832
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.1287729660
Short name T735
Test name
Test status
Simulation time 2335366369 ps
CPU time 4.36 seconds
Started Jun 25 05:14:04 PM PDT 24
Finished Jun 25 05:14:09 PM PDT 24
Peak memory 199556 kb
Host smart-2a9e4562-eecb-4659-bbdd-9cb557d1c473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287729660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1287729660
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_perf.3824796172
Short name T253
Test name
Test status
Simulation time 10289358488 ps
CPU time 638.32 seconds
Started Jun 25 05:14:02 PM PDT 24
Finished Jun 25 05:24:42 PM PDT 24
Peak memory 199908 kb
Host smart-3404000d-8dac-44f6-ae5b-cdada0064cf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3824796172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3824796172
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.2880287863
Short name T715
Test name
Test status
Simulation time 3574126223 ps
CPU time 16.7 seconds
Started Jun 25 05:14:04 PM PDT 24
Finished Jun 25 05:14:22 PM PDT 24
Peak memory 199052 kb
Host smart-30589a8c-7ed8-4cf3-86f2-4e983e756f9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2880287863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.2880287863
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.795849687
Short name T1087
Test name
Test status
Simulation time 28367606235 ps
CPU time 11.45 seconds
Started Jun 25 05:14:01 PM PDT 24
Finished Jun 25 05:14:13 PM PDT 24
Peak memory 199828 kb
Host smart-5e0c3fe4-3087-40c7-a328-278237a50c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795849687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.795849687
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.135557638
Short name T930
Test name
Test status
Simulation time 2052282184 ps
CPU time 1.53 seconds
Started Jun 25 05:14:02 PM PDT 24
Finished Jun 25 05:14:04 PM PDT 24
Peak memory 195424 kb
Host smart-49596be9-30cf-4f96-894a-fa15b95e051e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135557638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.135557638
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.2143488412
Short name T101
Test name
Test status
Simulation time 5992799614 ps
CPU time 11.46 seconds
Started Jun 25 05:14:03 PM PDT 24
Finished Jun 25 05:14:16 PM PDT 24
Peak memory 199664 kb
Host smart-5eb7a9a7-15e1-43db-b6e7-4a685dd2768c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143488412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2143488412
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2004930275
Short name T728
Test name
Test status
Simulation time 636873227 ps
CPU time 1.33 seconds
Started Jun 25 05:14:03 PM PDT 24
Finished Jun 25 05:14:05 PM PDT 24
Peak memory 198096 kb
Host smart-ca2d92f0-c0a2-43ae-bdd8-b3f77757ff8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004930275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2004930275
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.3803347024
Short name T666
Test name
Test status
Simulation time 5656994351 ps
CPU time 10.02 seconds
Started Jun 25 05:14:05 PM PDT 24
Finished Jun 25 05:14:16 PM PDT 24
Peak memory 197564 kb
Host smart-155c3e2b-fe31-490a-9f95-6b4180307ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803347024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.3803347024
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2668153818
Short name T226
Test name
Test status
Simulation time 48442608898 ps
CPU time 17.94 seconds
Started Jun 25 05:17:18 PM PDT 24
Finished Jun 25 05:17:37 PM PDT 24
Peak memory 199852 kb
Host smart-dc71c401-bd31-45a8-8a51-55a26cd3eb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668153818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2668153818
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.2741194824
Short name T572
Test name
Test status
Simulation time 12593105529 ps
CPU time 34.87 seconds
Started Jun 25 05:17:16 PM PDT 24
Finished Jun 25 05:17:52 PM PDT 24
Peak memory 199780 kb
Host smart-882b03a0-0481-4a99-8673-74614cf26650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741194824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2741194824
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.1488177061
Short name T737
Test name
Test status
Simulation time 52080910183 ps
CPU time 22.97 seconds
Started Jun 25 05:17:18 PM PDT 24
Finished Jun 25 05:17:42 PM PDT 24
Peak memory 199836 kb
Host smart-024fe87c-a268-4e53-b5f0-a2aed52a1e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488177061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1488177061
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.675724651
Short name T1069
Test name
Test status
Simulation time 286955388410 ps
CPU time 435.43 seconds
Started Jun 25 05:17:22 PM PDT 24
Finished Jun 25 05:24:38 PM PDT 24
Peak memory 199888 kb
Host smart-f2da55a6-ba0f-4951-b620-061cd0eb2b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675724651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.675724651
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.2246299582
Short name T341
Test name
Test status
Simulation time 13404170370 ps
CPU time 29.43 seconds
Started Jun 25 05:17:17 PM PDT 24
Finished Jun 25 05:17:48 PM PDT 24
Peak memory 199848 kb
Host smart-a5b62a00-a53f-4efb-96ef-3f7d881f37af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246299582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.2246299582
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.1155144505
Short name T740
Test name
Test status
Simulation time 100917042292 ps
CPU time 217.98 seconds
Started Jun 25 05:17:17 PM PDT 24
Finished Jun 25 05:20:56 PM PDT 24
Peak memory 199904 kb
Host smart-315b9295-dade-448d-a392-670572593a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155144505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.1155144505
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.1066913894
Short name T127
Test name
Test status
Simulation time 54724579527 ps
CPU time 44.02 seconds
Started Jun 25 05:17:18 PM PDT 24
Finished Jun 25 05:18:03 PM PDT 24
Peak memory 199876 kb
Host smart-cf5fdb0b-0fdb-4c75-bd3a-50a4876f140c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066913894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1066913894
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.3835097733
Short name T399
Test name
Test status
Simulation time 65167095003 ps
CPU time 22.66 seconds
Started Jun 25 05:17:15 PM PDT 24
Finished Jun 25 05:17:38 PM PDT 24
Peak memory 199896 kb
Host smart-28875373-998d-4384-894c-99e5d48bc6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835097733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.3835097733
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2834821628
Short name T1026
Test name
Test status
Simulation time 210055702589 ps
CPU time 60.71 seconds
Started Jun 25 05:17:16 PM PDT 24
Finished Jun 25 05:18:18 PM PDT 24
Peak memory 199840 kb
Host smart-aac65403-4435-4860-b274-e91ace1b579a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834821628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2834821628
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.194051806
Short name T674
Test name
Test status
Simulation time 13445461 ps
CPU time 0.58 seconds
Started Jun 25 05:14:13 PM PDT 24
Finished Jun 25 05:14:15 PM PDT 24
Peak memory 194896 kb
Host smart-5c9847b5-0a78-43b7-bd13-126e504d33c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194051806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.194051806
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.3268137171
Short name T929
Test name
Test status
Simulation time 258789821161 ps
CPU time 594.64 seconds
Started Jun 25 05:14:04 PM PDT 24
Finished Jun 25 05:24:00 PM PDT 24
Peak memory 199812 kb
Host smart-954414e4-23b5-4fbc-a4f7-796430a161c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268137171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3268137171
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.867001617
Short name T841
Test name
Test status
Simulation time 15840978505 ps
CPU time 21.41 seconds
Started Jun 25 05:14:02 PM PDT 24
Finished Jun 25 05:14:24 PM PDT 24
Peak memory 199832 kb
Host smart-9abc0f83-14f5-42ec-95ce-7df3e9cce521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867001617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.867001617
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_intr.1074657514
Short name T909
Test name
Test status
Simulation time 104521893279 ps
CPU time 84.92 seconds
Started Jun 25 05:14:11 PM PDT 24
Finished Jun 25 05:15:38 PM PDT 24
Peak memory 199824 kb
Host smart-a5123013-6977-49e8-b3e8-e8fba19aec7d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074657514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1074657514
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.4106307345
Short name T907
Test name
Test status
Simulation time 145669461961 ps
CPU time 426.4 seconds
Started Jun 25 05:14:12 PM PDT 24
Finished Jun 25 05:21:20 PM PDT 24
Peak memory 199888 kb
Host smart-e883bcad-e29b-4b55-a544-5648c69feb58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4106307345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.4106307345
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.3814673471
Short name T536
Test name
Test status
Simulation time 9333151040 ps
CPU time 8.66 seconds
Started Jun 25 05:14:11 PM PDT 24
Finished Jun 25 05:14:20 PM PDT 24
Peak memory 199556 kb
Host smart-2ce5c203-37a6-46cb-9381-519f977bd8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814673471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3814673471
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_perf.2647722623
Short name T540
Test name
Test status
Simulation time 11537522619 ps
CPU time 303.83 seconds
Started Jun 25 05:14:13 PM PDT 24
Finished Jun 25 05:19:19 PM PDT 24
Peak memory 200212 kb
Host smart-2071703b-f62c-4aba-9753-6848c4bff846
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2647722623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2647722623
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.2986112404
Short name T363
Test name
Test status
Simulation time 2192972365 ps
CPU time 4.88 seconds
Started Jun 25 05:14:11 PM PDT 24
Finished Jun 25 05:14:17 PM PDT 24
Peak memory 198104 kb
Host smart-061dd44d-9352-4486-bd05-e695c73f126e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2986112404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.2986112404
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.1402941763
Short name T1065
Test name
Test status
Simulation time 21396557129 ps
CPU time 18.34 seconds
Started Jun 25 05:14:12 PM PDT 24
Finished Jun 25 05:14:33 PM PDT 24
Peak memory 199796 kb
Host smart-b3650a7b-a653-48ef-8e36-330b062a6265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402941763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1402941763
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.3223019568
Short name T551
Test name
Test status
Simulation time 39336974111 ps
CPU time 12.86 seconds
Started Jun 25 05:14:13 PM PDT 24
Finished Jun 25 05:14:28 PM PDT 24
Peak memory 195676 kb
Host smart-9386b241-6d12-47ef-8909-914b68aab084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223019568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3223019568
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.552266679
Short name T576
Test name
Test status
Simulation time 617460695 ps
CPU time 1.72 seconds
Started Jun 25 05:14:03 PM PDT 24
Finished Jun 25 05:14:06 PM PDT 24
Peak memory 199380 kb
Host smart-7397310c-7575-4654-83e2-db24533378ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552266679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.552266679
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.263583700
Short name T607
Test name
Test status
Simulation time 6210047577 ps
CPU time 24.92 seconds
Started Jun 25 05:14:13 PM PDT 24
Finished Jun 25 05:14:40 PM PDT 24
Peak memory 199784 kb
Host smart-dac79a51-ff29-40e5-a49e-068d43ce4559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263583700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.263583700
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.4175106331
Short name T852
Test name
Test status
Simulation time 18758278209 ps
CPU time 21.13 seconds
Started Jun 25 05:14:03 PM PDT 24
Finished Jun 25 05:14:25 PM PDT 24
Peak memory 199912 kb
Host smart-4f02a91b-e4ac-4f36-bdd3-8807a4accd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175106331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.4175106331
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.3106261119
Short name T330
Test name
Test status
Simulation time 54077927070 ps
CPU time 83.84 seconds
Started Jun 25 05:17:16 PM PDT 24
Finished Jun 25 05:18:41 PM PDT 24
Peak memory 199840 kb
Host smart-fbfb5ba5-1c0b-423b-801d-17ad1f2e6132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106261119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3106261119
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.497286880
Short name T922
Test name
Test status
Simulation time 8141322346 ps
CPU time 14.95 seconds
Started Jun 25 05:17:18 PM PDT 24
Finished Jun 25 05:17:34 PM PDT 24
Peak memory 199808 kb
Host smart-4bf47fc8-abe2-4fd4-bbab-aa11949880df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497286880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.497286880
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.1926360588
Short name T934
Test name
Test status
Simulation time 8637732190 ps
CPU time 15.89 seconds
Started Jun 25 05:17:16 PM PDT 24
Finished Jun 25 05:17:33 PM PDT 24
Peak memory 199832 kb
Host smart-8029accd-08a0-4548-af73-dd6f4daf9296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926360588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1926360588
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.2780015859
Short name T345
Test name
Test status
Simulation time 74444014704 ps
CPU time 17.54 seconds
Started Jun 25 05:17:18 PM PDT 24
Finished Jun 25 05:17:37 PM PDT 24
Peak memory 199684 kb
Host smart-d93197fe-22a5-473a-8299-9914285e6db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780015859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2780015859
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.57813052
Short name T339
Test name
Test status
Simulation time 26687803546 ps
CPU time 12.56 seconds
Started Jun 25 05:17:15 PM PDT 24
Finished Jun 25 05:17:29 PM PDT 24
Peak memory 199904 kb
Host smart-6085913a-c81d-4ebd-adcf-ed19fabba611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57813052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.57813052
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.411454469
Short name T444
Test name
Test status
Simulation time 227846662822 ps
CPU time 79.85 seconds
Started Jun 25 05:17:21 PM PDT 24
Finished Jun 25 05:18:41 PM PDT 24
Peak memory 199724 kb
Host smart-9f5cdc8c-c744-48cd-bfa8-8be9f4c146c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411454469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.411454469
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.4036430505
Short name T884
Test name
Test status
Simulation time 28720051096 ps
CPU time 45.03 seconds
Started Jun 25 05:17:16 PM PDT 24
Finished Jun 25 05:18:02 PM PDT 24
Peak memory 199888 kb
Host smart-f86e4fb2-5863-45c3-a081-bc1c320055d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036430505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.4036430505
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.818953029
Short name T526
Test name
Test status
Simulation time 18665330321 ps
CPU time 27.8 seconds
Started Jun 25 05:17:21 PM PDT 24
Finished Jun 25 05:17:49 PM PDT 24
Peak memory 199868 kb
Host smart-486f3d9d-4c95-458d-be22-01c7967ec97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818953029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.818953029
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.381053010
Short name T1077
Test name
Test status
Simulation time 24296084790 ps
CPU time 45.08 seconds
Started Jun 25 05:17:16 PM PDT 24
Finished Jun 25 05:18:02 PM PDT 24
Peak memory 199888 kb
Host smart-26fa2c2c-859c-4e82-8cef-f7f444af1150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381053010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.381053010
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.198729979
Short name T693
Test name
Test status
Simulation time 106474487262 ps
CPU time 62.49 seconds
Started Jun 25 05:17:19 PM PDT 24
Finished Jun 25 05:18:22 PM PDT 24
Peak memory 199916 kb
Host smart-7693fcda-07e1-4143-bb3e-29df68608b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198729979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.198729979
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.1542411898
Short name T973
Test name
Test status
Simulation time 18159092 ps
CPU time 0.54 seconds
Started Jun 25 05:14:12 PM PDT 24
Finished Jun 25 05:14:14 PM PDT 24
Peak memory 195212 kb
Host smart-1de80819-5690-4b5a-8dc1-41f7dee8d2b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542411898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1542411898
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.1008073952
Short name T727
Test name
Test status
Simulation time 46131065837 ps
CPU time 20.6 seconds
Started Jun 25 05:14:14 PM PDT 24
Finished Jun 25 05:14:36 PM PDT 24
Peak memory 199856 kb
Host smart-1beb9f34-f4b3-4dd0-a246-63e83c11e003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008073952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.1008073952
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.670245782
Short name T113
Test name
Test status
Simulation time 56715916130 ps
CPU time 25.38 seconds
Started Jun 25 05:14:12 PM PDT 24
Finished Jun 25 05:14:39 PM PDT 24
Peak memory 199896 kb
Host smart-6814ad73-8b15-4e37-9ae9-789f38d1058c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670245782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.670245782
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.4127513116
Short name T681
Test name
Test status
Simulation time 106521327048 ps
CPU time 80.53 seconds
Started Jun 25 05:14:11 PM PDT 24
Finished Jun 25 05:15:33 PM PDT 24
Peak memory 199592 kb
Host smart-3d3da9b6-2400-4f82-9d5e-bba5a89f7b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127513116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.4127513116
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.3133859068
Short name T692
Test name
Test status
Simulation time 26966340079 ps
CPU time 14.4 seconds
Started Jun 25 05:14:11 PM PDT 24
Finished Jun 25 05:14:26 PM PDT 24
Peak memory 199856 kb
Host smart-06135bab-53ab-4dd7-b269-3f8a1d4cb86a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133859068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3133859068
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_loopback.3451317948
Short name T595
Test name
Test status
Simulation time 4253879418 ps
CPU time 1.75 seconds
Started Jun 25 05:14:12 PM PDT 24
Finished Jun 25 05:14:16 PM PDT 24
Peak memory 198736 kb
Host smart-f2c58120-3259-4d2e-bf3d-0c9fc867ac80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451317948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.3451317948
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_perf.223463020
Short name T854
Test name
Test status
Simulation time 4515230337 ps
CPU time 58.26 seconds
Started Jun 25 05:14:13 PM PDT 24
Finished Jun 25 05:15:13 PM PDT 24
Peak memory 199892 kb
Host smart-47858ff7-323c-4124-9440-c1a1d973e566
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=223463020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.223463020
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.2213408044
Short name T872
Test name
Test status
Simulation time 7070771730 ps
CPU time 32.68 seconds
Started Jun 25 05:14:13 PM PDT 24
Finished Jun 25 05:14:47 PM PDT 24
Peak memory 199120 kb
Host smart-c8b900cc-1733-4775-9e44-f1f731e7cc29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2213408044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2213408044
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.2173408329
Short name T804
Test name
Test status
Simulation time 24924245897 ps
CPU time 38.14 seconds
Started Jun 25 05:14:11 PM PDT 24
Finished Jun 25 05:14:50 PM PDT 24
Peak memory 199756 kb
Host smart-dad04e7e-e94a-48b8-9765-91339d3e005e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173408329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2173408329
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.3746963192
Short name T21
Test name
Test status
Simulation time 4289464405 ps
CPU time 3.7 seconds
Started Jun 25 05:14:13 PM PDT 24
Finished Jun 25 05:14:18 PM PDT 24
Peak memory 196028 kb
Host smart-4bdc08ad-7d1a-42e7-8a97-e2d1d129a2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746963192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3746963192
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.20142364
Short name T276
Test name
Test status
Simulation time 142353712 ps
CPU time 0.8 seconds
Started Jun 25 05:14:11 PM PDT 24
Finished Jun 25 05:14:13 PM PDT 24
Peak memory 197164 kb
Host smart-b7f2c139-7ceb-452b-86bc-65062e83bb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20142364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.20142364
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.2107821014
Short name T904
Test name
Test status
Simulation time 41274631586 ps
CPU time 40.63 seconds
Started Jun 25 05:14:14 PM PDT 24
Finished Jun 25 05:14:56 PM PDT 24
Peak memory 199800 kb
Host smart-8f0ef161-15f7-4f34-847c-66e09706967a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107821014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.2107821014
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.2751858992
Short name T373
Test name
Test status
Simulation time 637079095 ps
CPU time 2.09 seconds
Started Jun 25 05:14:13 PM PDT 24
Finished Jun 25 05:14:17 PM PDT 24
Peak memory 198596 kb
Host smart-9bdceede-1baa-4319-a81f-624a1f2055f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751858992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2751858992
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.622534468
Short name T656
Test name
Test status
Simulation time 39215776503 ps
CPU time 56.37 seconds
Started Jun 25 05:14:12 PM PDT 24
Finished Jun 25 05:15:10 PM PDT 24
Peak memory 199852 kb
Host smart-47a05172-32cc-4f94-9e52-478b94c6bf51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622534468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.622534468
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.4129865622
Short name T846
Test name
Test status
Simulation time 92029657367 ps
CPU time 38.84 seconds
Started Jun 25 05:17:18 PM PDT 24
Finished Jun 25 05:17:58 PM PDT 24
Peak memory 199832 kb
Host smart-9250daee-bfb7-48d1-b5b9-19a9c8f9d963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129865622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.4129865622
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.4083386373
Short name T119
Test name
Test status
Simulation time 37457899153 ps
CPU time 16.03 seconds
Started Jun 25 05:17:17 PM PDT 24
Finished Jun 25 05:17:34 PM PDT 24
Peak memory 199900 kb
Host smart-ddd63f14-666e-45fb-8da6-a4d0c316300d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083386373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.4083386373
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.2892842147
Short name T719
Test name
Test status
Simulation time 34586529490 ps
CPU time 62.47 seconds
Started Jun 25 05:17:16 PM PDT 24
Finished Jun 25 05:18:20 PM PDT 24
Peak memory 199920 kb
Host smart-262d1eb5-2138-43c9-ba7b-52df9873c5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892842147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2892842147
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.3116434728
Short name T580
Test name
Test status
Simulation time 35988462348 ps
CPU time 68.57 seconds
Started Jun 25 05:17:24 PM PDT 24
Finished Jun 25 05:18:33 PM PDT 24
Peak memory 199872 kb
Host smart-a54716a2-b540-41b5-a9f2-19c5cccbf940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116434728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3116434728
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.3330311417
Short name T883
Test name
Test status
Simulation time 31426013910 ps
CPU time 12.32 seconds
Started Jun 25 05:17:22 PM PDT 24
Finished Jun 25 05:17:36 PM PDT 24
Peak memory 199532 kb
Host smart-0ce24b08-8b28-4287-b338-03554c680886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330311417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3330311417
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.3111602059
Short name T307
Test name
Test status
Simulation time 29572876863 ps
CPU time 43.09 seconds
Started Jun 25 05:17:22 PM PDT 24
Finished Jun 25 05:18:06 PM PDT 24
Peak memory 199772 kb
Host smart-0ba07db6-3635-4f23-a274-56623febd1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111602059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3111602059
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.3918291758
Short name T1050
Test name
Test status
Simulation time 47910770019 ps
CPU time 78.33 seconds
Started Jun 25 05:17:25 PM PDT 24
Finished Jun 25 05:18:44 PM PDT 24
Peak memory 199904 kb
Host smart-9a4f8fe2-657a-4f6d-adcd-1985d92d09d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918291758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.3918291758
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.607365531
Short name T1071
Test name
Test status
Simulation time 14990515882 ps
CPU time 24.74 seconds
Started Jun 25 05:17:23 PM PDT 24
Finished Jun 25 05:17:49 PM PDT 24
Peak memory 199832 kb
Host smart-e333a383-d1e4-4ce1-ad1e-891598b4a952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607365531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.607365531
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2179891410
Short name T903
Test name
Test status
Simulation time 38957526 ps
CPU time 0.53 seconds
Started Jun 25 05:14:24 PM PDT 24
Finished Jun 25 05:14:26 PM PDT 24
Peak memory 194104 kb
Host smart-b1ea945b-92c2-4e42-b109-ff004e0c5b27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179891410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2179891410
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3487200954
Short name T758
Test name
Test status
Simulation time 34896951954 ps
CPU time 21.82 seconds
Started Jun 25 05:14:21 PM PDT 24
Finished Jun 25 05:14:44 PM PDT 24
Peak memory 199916 kb
Host smart-892daf2e-bde0-4df1-896c-398198ca1c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487200954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3487200954
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.2565186701
Short name T120
Test name
Test status
Simulation time 86231966061 ps
CPU time 133.8 seconds
Started Jun 25 05:14:25 PM PDT 24
Finished Jun 25 05:16:40 PM PDT 24
Peak memory 199820 kb
Host smart-51a8f451-d80b-46f9-9460-0c80da5af648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565186701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2565186701
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3738513627
Short name T778
Test name
Test status
Simulation time 36669004071 ps
CPU time 36.21 seconds
Started Jun 25 05:14:19 PM PDT 24
Finished Jun 25 05:14:56 PM PDT 24
Peak memory 199828 kb
Host smart-f83d22e9-b98b-43af-9b89-7d17f6410867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738513627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3738513627
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.3824298699
Short name T575
Test name
Test status
Simulation time 54075902376 ps
CPU time 110.27 seconds
Started Jun 25 05:14:22 PM PDT 24
Finished Jun 25 05:16:14 PM PDT 24
Peak memory 199764 kb
Host smart-08f84b52-3c51-4507-8d16-3ad602dbdff2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824298699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3824298699
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2331858291
Short name T503
Test name
Test status
Simulation time 154763792633 ps
CPU time 378.82 seconds
Started Jun 25 05:14:22 PM PDT 24
Finished Jun 25 05:20:42 PM PDT 24
Peak memory 199812 kb
Host smart-87809fdc-db32-4117-bbf6-1baa5c6df798
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2331858291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2331858291
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.2868813824
Short name T350
Test name
Test status
Simulation time 6223734683 ps
CPU time 3.6 seconds
Started Jun 25 05:14:21 PM PDT 24
Finished Jun 25 05:14:26 PM PDT 24
Peak memory 198832 kb
Host smart-bb7c2d62-122e-4702-9277-e37433517ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868813824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2868813824
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_perf.945028509
Short name T379
Test name
Test status
Simulation time 5599074170 ps
CPU time 69.37 seconds
Started Jun 25 05:14:25 PM PDT 24
Finished Jun 25 05:15:35 PM PDT 24
Peak memory 199828 kb
Host smart-30cf9926-77f1-4354-a520-5712f05fec9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=945028509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.945028509
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2441540643
Short name T807
Test name
Test status
Simulation time 2528680328 ps
CPU time 15.25 seconds
Started Jun 25 05:14:21 PM PDT 24
Finished Jun 25 05:14:37 PM PDT 24
Peak memory 197900 kb
Host smart-ec90b0ea-53c7-4ec4-a656-00d46e048df1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2441540643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2441540643
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1214112961
Short name T411
Test name
Test status
Simulation time 137809018935 ps
CPU time 66.58 seconds
Started Jun 25 05:14:26 PM PDT 24
Finished Jun 25 05:15:34 PM PDT 24
Peak memory 199792 kb
Host smart-c1a1d84a-bc30-4907-bf6f-5c6aff8d4799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214112961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1214112961
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.252816762
Short name T490
Test name
Test status
Simulation time 4676864294 ps
CPU time 2.71 seconds
Started Jun 25 05:14:26 PM PDT 24
Finished Jun 25 05:14:30 PM PDT 24
Peak memory 196700 kb
Host smart-5f8cda08-2a2c-4f55-b63c-fc154a5c7442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252816762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.252816762
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.1043941900
Short name T634
Test name
Test status
Simulation time 295453606 ps
CPU time 1.56 seconds
Started Jun 25 05:14:12 PM PDT 24
Finished Jun 25 05:14:16 PM PDT 24
Peak memory 199696 kb
Host smart-29f809fc-b2b9-4764-a9a1-8f190a7cbf52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043941900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1043941900
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.723073069
Short name T548
Test name
Test status
Simulation time 182522447867 ps
CPU time 673.83 seconds
Started Jun 25 05:14:23 PM PDT 24
Finished Jun 25 05:25:38 PM PDT 24
Peak memory 199748 kb
Host smart-670eceb2-a217-42bc-8fd6-be4e67ea097a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723073069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.723073069
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.2777612334
Short name T702
Test name
Test status
Simulation time 6947767435 ps
CPU time 20.27 seconds
Started Jun 25 05:14:21 PM PDT 24
Finished Jun 25 05:14:43 PM PDT 24
Peak memory 199216 kb
Host smart-92008b97-3d2a-46b3-af0a-a71310117dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777612334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2777612334
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1753866732
Short name T665
Test name
Test status
Simulation time 10486749640 ps
CPU time 14.01 seconds
Started Jun 25 05:17:23 PM PDT 24
Finished Jun 25 05:17:38 PM PDT 24
Peak memory 199856 kb
Host smart-89b60bef-fdbb-430f-bb85-4765b06f0c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753866732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1753866732
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.864562575
Short name T606
Test name
Test status
Simulation time 27277086318 ps
CPU time 36.18 seconds
Started Jun 25 05:17:24 PM PDT 24
Finished Jun 25 05:18:01 PM PDT 24
Peak memory 199888 kb
Host smart-8af9deb5-fd22-4d90-88a5-785069b20c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864562575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.864562575
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.4103617200
Short name T201
Test name
Test status
Simulation time 15024547214 ps
CPU time 11.74 seconds
Started Jun 25 05:17:23 PM PDT 24
Finished Jun 25 05:17:35 PM PDT 24
Peak memory 199852 kb
Host smart-6181e763-e0ee-48b9-8cc4-6e584d5a1fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103617200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.4103617200
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.2157597679
Short name T443
Test name
Test status
Simulation time 30041211894 ps
CPU time 10.5 seconds
Started Jun 25 05:17:25 PM PDT 24
Finished Jun 25 05:17:36 PM PDT 24
Peak memory 199732 kb
Host smart-b2b76be6-17e0-445e-8877-067e42b76474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157597679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2157597679
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.1828365777
Short name T193
Test name
Test status
Simulation time 132836726934 ps
CPU time 208.98 seconds
Started Jun 25 05:17:23 PM PDT 24
Finished Jun 25 05:20:53 PM PDT 24
Peak memory 199764 kb
Host smart-91bc2bc0-e994-4482-a55b-5afd77a7a755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828365777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1828365777
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.1880025847
Short name T624
Test name
Test status
Simulation time 180709530204 ps
CPU time 33.54 seconds
Started Jun 25 05:17:23 PM PDT 24
Finished Jun 25 05:17:58 PM PDT 24
Peak memory 199844 kb
Host smart-ed493d4e-b2b7-4941-8a04-3a13c9595965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880025847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1880025847
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.423557506
Short name T30
Test name
Test status
Simulation time 17920250510 ps
CPU time 33.54 seconds
Started Jun 25 05:17:25 PM PDT 24
Finished Jun 25 05:18:00 PM PDT 24
Peak memory 199908 kb
Host smart-96fcaa2e-7b6b-4422-8ae5-e3e543765b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423557506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.423557506
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1442970343
Short name T228
Test name
Test status
Simulation time 35163588838 ps
CPU time 17.92 seconds
Started Jun 25 05:17:23 PM PDT 24
Finished Jun 25 05:17:42 PM PDT 24
Peak memory 199824 kb
Host smart-7e1228dc-4697-49fe-96b1-a156419111e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442970343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1442970343
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.225210168
Short name T136
Test name
Test status
Simulation time 93666409548 ps
CPU time 278.22 seconds
Started Jun 25 05:17:25 PM PDT 24
Finished Jun 25 05:22:04 PM PDT 24
Peak memory 199844 kb
Host smart-e614b8a6-1ca7-47dc-99e6-8dac25030622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225210168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.225210168
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.4028558335
Short name T504
Test name
Test status
Simulation time 32880069 ps
CPU time 0.59 seconds
Started Jun 25 05:12:45 PM PDT 24
Finished Jun 25 05:12:48 PM PDT 24
Peak memory 195148 kb
Host smart-a286b09d-9a1f-4f36-9813-1c91ca113a4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028558335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.4028558335
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.3943528581
Short name T1014
Test name
Test status
Simulation time 10636968458 ps
CPU time 14.73 seconds
Started Jun 25 05:12:32 PM PDT 24
Finished Jun 25 05:12:48 PM PDT 24
Peak memory 199120 kb
Host smart-d9330583-74d3-43b5-9687-3dc65460bdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943528581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.3943528581
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.3836594637
Short name T893
Test name
Test status
Simulation time 105583643897 ps
CPU time 161.07 seconds
Started Jun 25 05:12:32 PM PDT 24
Finished Jun 25 05:15:15 PM PDT 24
Peak memory 199904 kb
Host smart-1b691d0f-54c9-4f3e-8eba-a5f24bbbf8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836594637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3836594637
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.2911395743
Short name T705
Test name
Test status
Simulation time 185892540436 ps
CPU time 104.8 seconds
Started Jun 25 05:12:35 PM PDT 24
Finished Jun 25 05:14:22 PM PDT 24
Peak memory 199852 kb
Host smart-a8216c51-c830-471d-b256-5d944ae4b35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911395743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2911395743
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.2761343141
Short name T1074
Test name
Test status
Simulation time 220886921072 ps
CPU time 80.41 seconds
Started Jun 25 05:12:33 PM PDT 24
Finished Jun 25 05:13:55 PM PDT 24
Peak memory 198120 kb
Host smart-7075299b-88da-4626-a4de-be2d897a6e62
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761343141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2761343141
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.3566185129
Short name T402
Test name
Test status
Simulation time 95034469868 ps
CPU time 602.64 seconds
Started Jun 25 05:12:35 PM PDT 24
Finished Jun 25 05:22:39 PM PDT 24
Peak memory 199736 kb
Host smart-3f1a849f-23e1-4cd7-a7f6-c1f61980c595
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3566185129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3566185129
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.1291189069
Short name T763
Test name
Test status
Simulation time 9796891305 ps
CPU time 16.92 seconds
Started Jun 25 05:12:36 PM PDT 24
Finished Jun 25 05:12:54 PM PDT 24
Peak memory 198968 kb
Host smart-b31c0c3b-11cd-40a4-8f48-e94fe3c847db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291189069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1291189069
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_perf.1928542844
Short name T623
Test name
Test status
Simulation time 13606176811 ps
CPU time 175.49 seconds
Started Jun 25 05:12:43 PM PDT 24
Finished Jun 25 05:15:41 PM PDT 24
Peak memory 199608 kb
Host smart-10deff57-34d1-457c-b4fe-5e70931d62fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1928542844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1928542844
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3005761210
Short name T834
Test name
Test status
Simulation time 2746041998 ps
CPU time 21.91 seconds
Started Jun 25 05:12:35 PM PDT 24
Finished Jun 25 05:12:58 PM PDT 24
Peak memory 199804 kb
Host smart-fd47e697-72bf-496a-b6bc-4fa18049d4da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3005761210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3005761210
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.3007444370
Short name T392
Test name
Test status
Simulation time 130902008928 ps
CPU time 43.72 seconds
Started Jun 25 05:12:33 PM PDT 24
Finished Jun 25 05:13:18 PM PDT 24
Peak memory 199832 kb
Host smart-2841d96b-46dc-42de-b8ea-67a4f05d2d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007444370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3007444370
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.1103391202
Short name T789
Test name
Test status
Simulation time 2874193000 ps
CPU time 2.54 seconds
Started Jun 25 05:12:37 PM PDT 24
Finished Jun 25 05:12:41 PM PDT 24
Peak memory 195680 kb
Host smart-edc38b7d-9d0a-4c80-a55b-481fad7d18fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103391202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1103391202
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1632654365
Short name T91
Test name
Test status
Simulation time 72594840 ps
CPU time 0.87 seconds
Started Jun 25 05:12:35 PM PDT 24
Finished Jun 25 05:12:37 PM PDT 24
Peak memory 218164 kb
Host smart-d4ac3ff9-1d5e-434e-8ec3-a003b47680e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632654365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1632654365
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.217980277
Short name T38
Test name
Test status
Simulation time 6189625491 ps
CPU time 13.41 seconds
Started Jun 25 05:12:32 PM PDT 24
Finished Jun 25 05:12:47 PM PDT 24
Peak memory 199720 kb
Host smart-045b60ad-4996-4784-bdea-90520138c8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217980277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.217980277
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.2773434884
Short name T761
Test name
Test status
Simulation time 87843719315 ps
CPU time 27.71 seconds
Started Jun 25 05:12:46 PM PDT 24
Finished Jun 25 05:13:15 PM PDT 24
Peak memory 199580 kb
Host smart-05d1e43f-55de-4d00-a64a-8431818a899e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773434884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2773434884
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.620391485
Short name T717
Test name
Test status
Simulation time 213239624370 ps
CPU time 1005.05 seconds
Started Jun 25 05:12:45 PM PDT 24
Finished Jun 25 05:29:33 PM PDT 24
Peak memory 225748 kb
Host smart-9cacc74e-2f9c-4699-8971-b4ab6ddd262c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620391485 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.620391485
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.154596339
Short name T438
Test name
Test status
Simulation time 402416880 ps
CPU time 1.8 seconds
Started Jun 25 05:12:32 PM PDT 24
Finished Jun 25 05:12:36 PM PDT 24
Peak memory 198168 kb
Host smart-a6103a38-3710-49d2-bb95-ce348c7c2b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154596339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.154596339
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.3466600313
Short name T448
Test name
Test status
Simulation time 28064300730 ps
CPU time 14.48 seconds
Started Jun 25 05:12:34 PM PDT 24
Finished Jun 25 05:12:50 PM PDT 24
Peak memory 199376 kb
Host smart-2860310b-6389-4cd6-96a2-d0accc9faa2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466600313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3466600313
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.2828778476
Short name T366
Test name
Test status
Simulation time 23598582 ps
CPU time 0.58 seconds
Started Jun 25 05:14:26 PM PDT 24
Finished Jun 25 05:14:27 PM PDT 24
Peak memory 195416 kb
Host smart-4160f109-8ea1-404c-a31b-ec33fe8a02e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828778476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.2828778476
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.1914796313
Short name T473
Test name
Test status
Simulation time 43076969386 ps
CPU time 41.03 seconds
Started Jun 25 05:14:21 PM PDT 24
Finished Jun 25 05:15:03 PM PDT 24
Peak memory 199904 kb
Host smart-ebdc6f7a-198e-4c53-8933-23fb139ca792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914796313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.1914796313
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.4033339463
Short name T855
Test name
Test status
Simulation time 167248847966 ps
CPU time 69.65 seconds
Started Jun 25 05:14:25 PM PDT 24
Finished Jun 25 05:15:36 PM PDT 24
Peak memory 199900 kb
Host smart-7c26adce-761d-4374-85d7-21a7948ca96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033339463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.4033339463
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.4134879431
Short name T233
Test name
Test status
Simulation time 195094422195 ps
CPU time 161.22 seconds
Started Jun 25 05:14:22 PM PDT 24
Finished Jun 25 05:17:04 PM PDT 24
Peak memory 199860 kb
Host smart-043764cf-dbc9-4f16-a419-13bc128375fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134879431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.4134879431
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.3536602497
Short name T376
Test name
Test status
Simulation time 31426082416 ps
CPU time 13.63 seconds
Started Jun 25 05:14:23 PM PDT 24
Finished Jun 25 05:14:38 PM PDT 24
Peak memory 199892 kb
Host smart-292c72c3-9407-4db0-9e32-181acf062d54
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536602497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3536602497
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.833734851
Short name T862
Test name
Test status
Simulation time 35722848838 ps
CPU time 273.11 seconds
Started Jun 25 05:14:26 PM PDT 24
Finished Jun 25 05:19:00 PM PDT 24
Peak memory 199900 kb
Host smart-65703888-2725-4681-95a5-1088b2f457a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=833734851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.833734851
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1138462319
Short name T353
Test name
Test status
Simulation time 1064455558 ps
CPU time 2.37 seconds
Started Jun 25 05:14:22 PM PDT 24
Finished Jun 25 05:14:26 PM PDT 24
Peak memory 197428 kb
Host smart-a7141ed9-2018-49f7-b881-a48cd6b8e50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138462319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1138462319
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.2339073118
Short name T245
Test name
Test status
Simulation time 52669205653 ps
CPU time 184.98 seconds
Started Jun 25 05:14:23 PM PDT 24
Finished Jun 25 05:17:29 PM PDT 24
Peak memory 199828 kb
Host smart-05606cb6-59ca-4621-b2c2-46741cde6932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339073118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2339073118
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.48778019
Short name T39
Test name
Test status
Simulation time 9253515377 ps
CPU time 475.09 seconds
Started Jun 25 05:14:22 PM PDT 24
Finished Jun 25 05:22:19 PM PDT 24
Peak memory 199904 kb
Host smart-906599c9-61a5-43a6-a74c-f0017bcb5ee7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=48778019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.48778019
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.368325368
Short name T769
Test name
Test status
Simulation time 7890581318 ps
CPU time 17.82 seconds
Started Jun 25 05:14:21 PM PDT 24
Finished Jun 25 05:14:40 PM PDT 24
Peak memory 197760 kb
Host smart-44b573c6-90a1-4ea0-8a40-09ab17ec7a15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=368325368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.368325368
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1154776266
Short name T796
Test name
Test status
Simulation time 14728145701 ps
CPU time 11.8 seconds
Started Jun 25 05:14:26 PM PDT 24
Finished Jun 25 05:14:39 PM PDT 24
Peak memory 198592 kb
Host smart-08c84c5e-2cb8-4f5c-a451-02255a149a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154776266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1154776266
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.3109896015
Short name T469
Test name
Test status
Simulation time 3674150216 ps
CPU time 6.52 seconds
Started Jun 25 05:14:23 PM PDT 24
Finished Jun 25 05:14:31 PM PDT 24
Peak memory 196332 kb
Host smart-570056b2-5bc5-496f-87c7-c4a791eead13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109896015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.3109896015
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.2069744351
Short name T1075
Test name
Test status
Simulation time 502045003 ps
CPU time 1.24 seconds
Started Jun 25 05:14:25 PM PDT 24
Finished Jun 25 05:14:28 PM PDT 24
Peak memory 198444 kb
Host smart-be32ef86-335f-40d1-960e-530a52fce593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069744351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.2069744351
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.436480536
Short name T37
Test name
Test status
Simulation time 94821586875 ps
CPU time 276.24 seconds
Started Jun 25 05:14:27 PM PDT 24
Finished Jun 25 05:19:04 PM PDT 24
Peak memory 216400 kb
Host smart-32db3f6a-1d9c-4a0a-9488-4199854fadc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436480536 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.436480536
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.3746710017
Short name T431
Test name
Test status
Simulation time 904856666 ps
CPU time 4 seconds
Started Jun 25 05:14:22 PM PDT 24
Finished Jun 25 05:14:27 PM PDT 24
Peak memory 198296 kb
Host smart-982de1ec-babf-4bf8-abe0-2e3af17e5b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746710017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3746710017
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.1086979471
Short name T586
Test name
Test status
Simulation time 92753462371 ps
CPU time 34.67 seconds
Started Jun 25 05:14:26 PM PDT 24
Finished Jun 25 05:15:02 PM PDT 24
Peak memory 199872 kb
Host smart-c509e239-22f9-4281-8a45-5f766c1f8d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086979471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.1086979471
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.3004480036
Short name T680
Test name
Test status
Simulation time 14104887 ps
CPU time 0.56 seconds
Started Jun 25 05:14:31 PM PDT 24
Finished Jun 25 05:14:32 PM PDT 24
Peak memory 195152 kb
Host smart-02ded177-83e7-4c47-aab9-8e5edc1bf4f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004480036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3004480036
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.359131611
Short name T958
Test name
Test status
Simulation time 38865438473 ps
CPU time 40.41 seconds
Started Jun 25 05:14:22 PM PDT 24
Finished Jun 25 05:15:03 PM PDT 24
Peak memory 199856 kb
Host smart-665bb0de-923f-4b9e-b793-46b8a0e5c69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359131611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.359131611
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1424183796
Short name T988
Test name
Test status
Simulation time 193992604240 ps
CPU time 89.88 seconds
Started Jun 25 05:14:27 PM PDT 24
Finished Jun 25 05:15:58 PM PDT 24
Peak memory 199900 kb
Host smart-99eb9107-637d-4fb8-9003-b4c7f1c1bfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424183796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1424183796
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.696447349
Short name T227
Test name
Test status
Simulation time 53115449974 ps
CPU time 41.2 seconds
Started Jun 25 05:14:23 PM PDT 24
Finished Jun 25 05:15:05 PM PDT 24
Peak memory 199804 kb
Host smart-c3784929-d084-43cf-914b-154468a79c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696447349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.696447349
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.2771866550
Short name T336
Test name
Test status
Simulation time 242212371077 ps
CPU time 169.49 seconds
Started Jun 25 05:14:25 PM PDT 24
Finished Jun 25 05:17:15 PM PDT 24
Peak memory 197524 kb
Host smart-f8bcb96b-30d6-4cc9-a0d0-442709423480
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771866550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2771866550
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.4074161873
Short name T471
Test name
Test status
Simulation time 81134982150 ps
CPU time 542.39 seconds
Started Jun 25 05:14:32 PM PDT 24
Finished Jun 25 05:23:36 PM PDT 24
Peak memory 199812 kb
Host smart-6ad66f49-2625-47e2-b7b8-93a515531ce0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4074161873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.4074161873
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.2353594097
Short name T349
Test name
Test status
Simulation time 3519677275 ps
CPU time 3.17 seconds
Started Jun 25 05:14:24 PM PDT 24
Finished Jun 25 05:14:28 PM PDT 24
Peak memory 198660 kb
Host smart-700e27fa-3678-4651-9177-4b0cbfc2e7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353594097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2353594097
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_perf.582891292
Short name T564
Test name
Test status
Simulation time 19621379508 ps
CPU time 249.79 seconds
Started Jun 25 05:14:33 PM PDT 24
Finished Jun 25 05:18:44 PM PDT 24
Peak memory 199844 kb
Host smart-35232293-b1fe-4975-b625-78fc48664073
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=582891292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.582891292
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.350846084
Short name T360
Test name
Test status
Simulation time 5190604391 ps
CPU time 23.53 seconds
Started Jun 25 05:14:28 PM PDT 24
Finished Jun 25 05:14:52 PM PDT 24
Peak memory 199116 kb
Host smart-e4f330a9-00df-418e-bfb9-c1a806bb7581
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=350846084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.350846084
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.3494021374
Short name T499
Test name
Test status
Simulation time 124313639243 ps
CPU time 56.89 seconds
Started Jun 25 05:14:21 PM PDT 24
Finished Jun 25 05:15:19 PM PDT 24
Peak memory 199860 kb
Host smart-a3b4c110-f4c4-4133-869a-23fd57e3b3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494021374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3494021374
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.2689660659
Short name T315
Test name
Test status
Simulation time 29263517019 ps
CPU time 41.37 seconds
Started Jun 25 05:14:23 PM PDT 24
Finished Jun 25 05:15:05 PM PDT 24
Peak memory 196136 kb
Host smart-2a2c8da5-2a96-4d8f-bef7-04b3010b4309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689660659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.2689660659
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.2289114264
Short name T1068
Test name
Test status
Simulation time 676217370 ps
CPU time 2.46 seconds
Started Jun 25 05:14:20 PM PDT 24
Finished Jun 25 05:14:23 PM PDT 24
Peak memory 198112 kb
Host smart-093fc35a-d31f-4847-8374-4510286cfb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289114264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2289114264
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.2882698956
Short name T917
Test name
Test status
Simulation time 209924838916 ps
CPU time 1074.47 seconds
Started Jun 25 05:14:33 PM PDT 24
Finished Jun 25 05:32:29 PM PDT 24
Peak memory 224524 kb
Host smart-d9240077-875a-40cd-ac91-3c386d7a5a2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882698956 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.2882698956
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.43411996
Short name T766
Test name
Test status
Simulation time 1299613536 ps
CPU time 5.01 seconds
Started Jun 25 05:14:23 PM PDT 24
Finished Jun 25 05:14:29 PM PDT 24
Peak memory 198372 kb
Host smart-beb54311-2067-4343-9529-8dbd69af8fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43411996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.43411996
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.4266672306
Short name T260
Test name
Test status
Simulation time 41925814912 ps
CPU time 4.89 seconds
Started Jun 25 05:14:24 PM PDT 24
Finished Jun 25 05:14:30 PM PDT 24
Peak memory 199896 kb
Host smart-7f7db95e-2052-49a9-82cb-70b6b34a610c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266672306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.4266672306
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.2362885346
Short name T839
Test name
Test status
Simulation time 17978382 ps
CPU time 0.54 seconds
Started Jun 25 05:14:32 PM PDT 24
Finished Jun 25 05:14:33 PM PDT 24
Peak memory 195148 kb
Host smart-6baeab17-489f-4763-a0a9-3daed1e12ebc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362885346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2362885346
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.3834331834
Short name T145
Test name
Test status
Simulation time 31395941570 ps
CPU time 44.04 seconds
Started Jun 25 05:14:33 PM PDT 24
Finished Jun 25 05:15:18 PM PDT 24
Peak memory 199856 kb
Host smart-9ad54df9-a8b4-4655-9b17-daf57d71a7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834331834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3834331834
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.3678877018
Short name T305
Test name
Test status
Simulation time 13582950221 ps
CPU time 5.76 seconds
Started Jun 25 05:14:31 PM PDT 24
Finished Jun 25 05:14:38 PM PDT 24
Peak memory 199328 kb
Host smart-64f5722d-2673-401f-a68f-514abe0ec0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678877018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.3678877018
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1175270221
Short name T806
Test name
Test status
Simulation time 181893286625 ps
CPU time 14.47 seconds
Started Jun 25 05:14:33 PM PDT 24
Finished Jun 25 05:14:49 PM PDT 24
Peak memory 199892 kb
Host smart-a1956a8a-36ce-4121-8d7b-402b6138e025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175270221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1175270221
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.3459650663
Short name T655
Test name
Test status
Simulation time 42894231139 ps
CPU time 21.71 seconds
Started Jun 25 05:14:33 PM PDT 24
Finished Jun 25 05:14:56 PM PDT 24
Peak memory 199812 kb
Host smart-f22df09d-1c20-4489-91de-44bc582f09f1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459650663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3459650663
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.2198793871
Short name T671
Test name
Test status
Simulation time 129296908803 ps
CPU time 1171.28 seconds
Started Jun 25 05:14:32 PM PDT 24
Finished Jun 25 05:34:05 PM PDT 24
Peak memory 199884 kb
Host smart-444f4bd5-4924-46f6-80c5-bae4c0dafca3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2198793871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2198793871
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.1717858566
Short name T441
Test name
Test status
Simulation time 3767694901 ps
CPU time 5.82 seconds
Started Jun 25 05:14:32 PM PDT 24
Finished Jun 25 05:14:39 PM PDT 24
Peak memory 199664 kb
Host smart-c0a972fc-fad4-46af-882e-b951ac4e0b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717858566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.1717858566
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.4098559583
Short name T332
Test name
Test status
Simulation time 33186749956 ps
CPU time 28.35 seconds
Started Jun 25 05:14:31 PM PDT 24
Finished Jun 25 05:15:00 PM PDT 24
Peak memory 199892 kb
Host smart-2c26dce0-1206-4c63-8a59-a0e72bf94907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098559583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.4098559583
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.3641091998
Short name T437
Test name
Test status
Simulation time 32029529734 ps
CPU time 422.73 seconds
Started Jun 25 05:14:32 PM PDT 24
Finished Jun 25 05:21:37 PM PDT 24
Peak memory 199860 kb
Host smart-aa70d1d4-52a9-405c-b2b7-c6f4be4e854f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3641091998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.3641091998
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.2923455898
Short name T906
Test name
Test status
Simulation time 6571035166 ps
CPU time 6.56 seconds
Started Jun 25 05:14:31 PM PDT 24
Finished Jun 25 05:14:39 PM PDT 24
Peak memory 197980 kb
Host smart-93c09009-d93e-4bcb-ac18-628a094f587b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2923455898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2923455898
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.2399720506
Short name T161
Test name
Test status
Simulation time 37683750846 ps
CPU time 27.53 seconds
Started Jun 25 05:14:33 PM PDT 24
Finished Jun 25 05:15:02 PM PDT 24
Peak memory 199820 kb
Host smart-49f8fef8-f7d8-4e3c-904e-dba842f99e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399720506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.2399720506
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.251622967
Short name T918
Test name
Test status
Simulation time 5568163558 ps
CPU time 1.27 seconds
Started Jun 25 05:14:32 PM PDT 24
Finished Jun 25 05:14:34 PM PDT 24
Peak memory 196072 kb
Host smart-4c780830-f04f-408a-ac1e-c1464abe214e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251622967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.251622967
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.3875396442
Short name T463
Test name
Test status
Simulation time 540651538 ps
CPU time 2.34 seconds
Started Jun 25 05:14:34 PM PDT 24
Finished Jun 25 05:14:37 PM PDT 24
Peak memory 198344 kb
Host smart-43a959fd-4f08-4f91-aeec-3ed43d042806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875396442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3875396442
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.137297849
Short name T55
Test name
Test status
Simulation time 80450520977 ps
CPU time 195.55 seconds
Started Jun 25 05:14:32 PM PDT 24
Finished Jun 25 05:17:48 PM PDT 24
Peak memory 216276 kb
Host smart-c114cc9f-6e1c-41d2-bbcf-cf6ead62bde7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137297849 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.137297849
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3392463242
Short name T815
Test name
Test status
Simulation time 524646029 ps
CPU time 1.88 seconds
Started Jun 25 05:14:32 PM PDT 24
Finished Jun 25 05:14:35 PM PDT 24
Peak memory 198596 kb
Host smart-f77bdf04-46fe-4efd-bbd7-cd62f18825bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392463242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3392463242
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.2748844647
Short name T506
Test name
Test status
Simulation time 127438918298 ps
CPU time 45.59 seconds
Started Jun 25 05:14:34 PM PDT 24
Finished Jun 25 05:15:21 PM PDT 24
Peak memory 199844 kb
Host smart-69d02ed7-0a60-4bcd-9d4f-b5174f2459cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748844647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2748844647
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.32205845
Short name T25
Test name
Test status
Simulation time 19704606 ps
CPU time 0.58 seconds
Started Jun 25 05:14:42 PM PDT 24
Finished Jun 25 05:14:44 PM PDT 24
Peak memory 195208 kb
Host smart-6eba89a4-2ec2-4d64-8124-a9713076e763
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32205845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.32205845
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.2072346436
Short name T734
Test name
Test status
Simulation time 126531322361 ps
CPU time 54.11 seconds
Started Jun 25 05:14:34 PM PDT 24
Finished Jun 25 05:15:29 PM PDT 24
Peak memory 199844 kb
Host smart-d5e40280-61b2-4d9e-8a9d-f92718fcaa1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072346436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2072346436
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.3236598333
Short name T848
Test name
Test status
Simulation time 96544393022 ps
CPU time 197.05 seconds
Started Jun 25 05:14:32 PM PDT 24
Finished Jun 25 05:17:50 PM PDT 24
Peak memory 199800 kb
Host smart-c6ea5c4a-1228-4466-9012-33ee2a13e45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236598333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3236598333
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.3090857753
Short name T652
Test name
Test status
Simulation time 43721315939 ps
CPU time 73.97 seconds
Started Jun 25 05:14:40 PM PDT 24
Finished Jun 25 05:15:54 PM PDT 24
Peak memory 199920 kb
Host smart-d3d2e5f9-222d-479f-a891-8dbecc95f12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090857753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3090857753
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.3014841472
Short name T293
Test name
Test status
Simulation time 19699771516 ps
CPU time 31.07 seconds
Started Jun 25 05:14:32 PM PDT 24
Finished Jun 25 05:15:05 PM PDT 24
Peak memory 199740 kb
Host smart-2b74388c-db39-424c-81f3-641763018cea
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014841472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3014841472
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2992411100
Short name T498
Test name
Test status
Simulation time 47586795153 ps
CPU time 191.01 seconds
Started Jun 25 05:14:43 PM PDT 24
Finished Jun 25 05:17:56 PM PDT 24
Peak memory 199892 kb
Host smart-1bef66df-c483-4d69-99ab-f8f8a764089a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2992411100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2992411100
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.3373006513
Short name T706
Test name
Test status
Simulation time 398110746 ps
CPU time 0.75 seconds
Started Jun 25 05:14:42 PM PDT 24
Finished Jun 25 05:14:44 PM PDT 24
Peak memory 195712 kb
Host smart-b1c14302-30ac-4dc6-88e5-fe9bbe58dd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373006513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3373006513
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_perf.3534073750
Short name T255
Test name
Test status
Simulation time 32826300731 ps
CPU time 438.64 seconds
Started Jun 25 05:14:42 PM PDT 24
Finished Jun 25 05:22:02 PM PDT 24
Peak memory 199884 kb
Host smart-d6b56079-c0ff-40b1-a192-c136fe9ed620
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3534073750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3534073750
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3387102880
Short name T582
Test name
Test status
Simulation time 7107468915 ps
CPU time 61.91 seconds
Started Jun 25 05:14:32 PM PDT 24
Finished Jun 25 05:15:35 PM PDT 24
Peak memory 199888 kb
Host smart-5157f401-951b-45d6-98b1-14baae790a69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3387102880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3387102880
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.1080263571
Short name T446
Test name
Test status
Simulation time 14940608778 ps
CPU time 18.36 seconds
Started Jun 25 05:14:45 PM PDT 24
Finished Jun 25 05:15:05 PM PDT 24
Peak memory 199912 kb
Host smart-6b48bcf5-60a3-483e-b71e-468be2b83401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080263571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.1080263571
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.2999931753
Short name T946
Test name
Test status
Simulation time 3478213993 ps
CPU time 5.21 seconds
Started Jun 25 05:14:42 PM PDT 24
Finished Jun 25 05:14:48 PM PDT 24
Peak memory 196012 kb
Host smart-54c9ef90-b1f1-4c1a-850e-ad1f7a8ba0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999931753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2999931753
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.583162639
Short name T264
Test name
Test status
Simulation time 671257532 ps
CPU time 2.59 seconds
Started Jun 25 05:14:33 PM PDT 24
Finished Jun 25 05:14:36 PM PDT 24
Peak memory 199796 kb
Host smart-1ff0f57d-28f6-4ae7-821d-cb1995478cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583162639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.583162639
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.953247680
Short name T439
Test name
Test status
Simulation time 67212292676 ps
CPU time 1392.44 seconds
Started Jun 25 05:14:42 PM PDT 24
Finished Jun 25 05:37:56 PM PDT 24
Peak memory 199872 kb
Host smart-151ea258-34ee-4466-932f-de462e64a6dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953247680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.953247680
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.2191704746
Short name T254
Test name
Test status
Simulation time 220969400984 ps
CPU time 766.44 seconds
Started Jun 25 05:14:43 PM PDT 24
Finished Jun 25 05:27:31 PM PDT 24
Peak memory 216364 kb
Host smart-0a36c03e-87ba-48ee-96d0-eb4374c4332e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191704746 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.2191704746
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.3428881044
Short name T416
Test name
Test status
Simulation time 8973710883 ps
CPU time 14.25 seconds
Started Jun 25 05:14:43 PM PDT 24
Finished Jun 25 05:14:59 PM PDT 24
Peak memory 199272 kb
Host smart-88522665-ffaf-4fb4-a7b2-dc3b6ab61bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428881044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.3428881044
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.1322172371
Short name T642
Test name
Test status
Simulation time 77469869102 ps
CPU time 38.2 seconds
Started Jun 25 05:14:40 PM PDT 24
Finished Jun 25 05:15:19 PM PDT 24
Peak memory 199928 kb
Host smart-6b9a0de7-226f-4e37-9d3e-c52b2e72dd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322172371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1322172371
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.3191993966
Short name T645
Test name
Test status
Simulation time 19319968 ps
CPU time 0.59 seconds
Started Jun 25 05:14:42 PM PDT 24
Finished Jun 25 05:14:45 PM PDT 24
Peak memory 195508 kb
Host smart-1c21eb81-3499-4bd3-af36-e0cb2e249c7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191993966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3191993966
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.524515382
Short name T608
Test name
Test status
Simulation time 33353587980 ps
CPU time 55.94 seconds
Started Jun 25 05:14:41 PM PDT 24
Finished Jun 25 05:15:38 PM PDT 24
Peak memory 199916 kb
Host smart-fd93ad92-ac07-45f0-a705-2ce9d5efa0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524515382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.524515382
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.2046372266
Short name T851
Test name
Test status
Simulation time 50865336699 ps
CPU time 28.6 seconds
Started Jun 25 05:14:43 PM PDT 24
Finished Jun 25 05:15:14 PM PDT 24
Peak memory 199912 kb
Host smart-d59234e8-9ce9-45fb-bc0b-70d1e03891da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046372266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2046372266
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.879442603
Short name T387
Test name
Test status
Simulation time 66685983373 ps
CPU time 17.48 seconds
Started Jun 25 05:14:43 PM PDT 24
Finished Jun 25 05:15:02 PM PDT 24
Peak memory 199808 kb
Host smart-c1c7cc8c-7af7-4ac4-8f14-8d141877f4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879442603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.879442603
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3208204169
Short name T545
Test name
Test status
Simulation time 16751835457 ps
CPU time 7.12 seconds
Started Jun 25 05:14:42 PM PDT 24
Finished Jun 25 05:14:51 PM PDT 24
Peak memory 198784 kb
Host smart-cc6944a9-291a-4779-b2fe-05e93b089fdc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208204169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3208204169
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.762480191
Short name T592
Test name
Test status
Simulation time 83639826649 ps
CPU time 484.95 seconds
Started Jun 25 05:14:45 PM PDT 24
Finished Jun 25 05:22:51 PM PDT 24
Peak memory 199832 kb
Host smart-f697aed4-4d42-4460-b152-65ed6c7dfeb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=762480191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.762480191
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.1921509897
Short name T861
Test name
Test status
Simulation time 14112080185 ps
CPU time 7.33 seconds
Started Jun 25 05:14:44 PM PDT 24
Finished Jun 25 05:14:53 PM PDT 24
Peak memory 198712 kb
Host smart-c3a4f3a7-c6d3-42f6-bda1-919fd7d376db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921509897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.1921509897
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.1624079848
Short name T524
Test name
Test status
Simulation time 49170324842 ps
CPU time 44.65 seconds
Started Jun 25 05:14:44 PM PDT 24
Finished Jun 25 05:15:31 PM PDT 24
Peak memory 199808 kb
Host smart-9d3ba5fe-015e-452e-9a46-ca6937961143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624079848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.1624079848
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.563698702
Short name T530
Test name
Test status
Simulation time 10925805264 ps
CPU time 184.85 seconds
Started Jun 25 05:14:40 PM PDT 24
Finished Jun 25 05:17:46 PM PDT 24
Peak memory 199760 kb
Host smart-2c47b4fc-4253-4173-a17f-ad3be9dae4e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=563698702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.563698702
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.306794661
Short name T364
Test name
Test status
Simulation time 7491682436 ps
CPU time 59.39 seconds
Started Jun 25 05:14:42 PM PDT 24
Finished Jun 25 05:15:44 PM PDT 24
Peak memory 199880 kb
Host smart-d6ff6c3e-d928-47fb-b1ad-14e9b668d1e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=306794661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.306794661
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1083682959
Short name T518
Test name
Test status
Simulation time 41094970811 ps
CPU time 31.42 seconds
Started Jun 25 05:14:45 PM PDT 24
Finished Jun 25 05:15:18 PM PDT 24
Peak memory 199716 kb
Host smart-e167434d-989f-4701-8e96-5835b143d9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083682959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1083682959
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.846394536
Short name T285
Test name
Test status
Simulation time 4248816209 ps
CPU time 2.43 seconds
Started Jun 25 05:14:43 PM PDT 24
Finished Jun 25 05:14:47 PM PDT 24
Peak memory 195852 kb
Host smart-cfd0052d-1de0-43e5-b69a-6993ccdde362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846394536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.846394536
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.117820795
Short name T314
Test name
Test status
Simulation time 285038770 ps
CPU time 1.54 seconds
Started Jun 25 05:14:42 PM PDT 24
Finished Jun 25 05:14:46 PM PDT 24
Peak memory 198088 kb
Host smart-db23b622-5e34-47a5-a563-4754ad61963c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117820795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.117820795
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1958601370
Short name T414
Test name
Test status
Simulation time 2346800766 ps
CPU time 2.18 seconds
Started Jun 25 05:14:44 PM PDT 24
Finished Jun 25 05:14:48 PM PDT 24
Peak memory 198388 kb
Host smart-9b4c7c55-889c-44a6-a60d-c491f7b79317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958601370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1958601370
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.3980687025
Short name T962
Test name
Test status
Simulation time 124771841371 ps
CPU time 199.85 seconds
Started Jun 25 05:14:42 PM PDT 24
Finished Jun 25 05:18:04 PM PDT 24
Peak memory 199752 kb
Host smart-a937ef0b-7095-4871-a11d-bf845f41d0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980687025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3980687025
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.2057648159
Short name T1038
Test name
Test status
Simulation time 32700917 ps
CPU time 0.54 seconds
Started Jun 25 05:14:43 PM PDT 24
Finished Jun 25 05:14:45 PM PDT 24
Peak memory 194592 kb
Host smart-034989cf-653c-4905-873f-8a0c4fa15700
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057648159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2057648159
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.3755826579
Short name T1073
Test name
Test status
Simulation time 48865383008 ps
CPU time 20.52 seconds
Started Jun 25 05:14:41 PM PDT 24
Finished Jun 25 05:15:03 PM PDT 24
Peak memory 199840 kb
Host smart-c42ea18f-9ef7-41b2-b715-72be6b17a117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755826579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3755826579
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.397601965
Short name T1022
Test name
Test status
Simulation time 334475815470 ps
CPU time 70.48 seconds
Started Jun 25 05:14:42 PM PDT 24
Finished Jun 25 05:15:54 PM PDT 24
Peak memory 199852 kb
Host smart-d7627c69-6ea2-431f-9967-1221d2ae0a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397601965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.397601965
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_intr.2869752699
Short name T16
Test name
Test status
Simulation time 50045937830 ps
CPU time 7.74 seconds
Started Jun 25 05:14:45 PM PDT 24
Finished Jun 25 05:14:54 PM PDT 24
Peak memory 199900 kb
Host smart-24877e6a-d10a-47f4-b088-11d9b1573786
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869752699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2869752699
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.639930979
Short name T858
Test name
Test status
Simulation time 291289038732 ps
CPU time 171.92 seconds
Started Jun 25 05:14:41 PM PDT 24
Finished Jun 25 05:17:35 PM PDT 24
Peak memory 199880 kb
Host smart-14d5731c-59c2-46ff-92ea-e16af7c840ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=639930979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.639930979
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3434678367
Short name T638
Test name
Test status
Simulation time 1928824795 ps
CPU time 4.06 seconds
Started Jun 25 05:14:44 PM PDT 24
Finished Jun 25 05:14:50 PM PDT 24
Peak memory 198448 kb
Host smart-21adf352-137a-470c-aeb1-a2e14ad283e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434678367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3434678367
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_perf.2220966429
Short name T743
Test name
Test status
Simulation time 5600495302 ps
CPU time 160.7 seconds
Started Jun 25 05:14:42 PM PDT 24
Finished Jun 25 05:17:24 PM PDT 24
Peak memory 199816 kb
Host smart-b880c552-3b20-40c1-aa7c-f02e1acec884
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2220966429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2220966429
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.719836971
Short name T936
Test name
Test status
Simulation time 6945172626 ps
CPU time 8.05 seconds
Started Jun 25 05:14:41 PM PDT 24
Finished Jun 25 05:14:51 PM PDT 24
Peak memory 199136 kb
Host smart-7c9c8cbd-2255-47a9-9360-d20a57616639
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=719836971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.719836971
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.2104205345
Short name T952
Test name
Test status
Simulation time 134461038762 ps
CPU time 215.57 seconds
Started Jun 25 05:14:43 PM PDT 24
Finished Jun 25 05:18:20 PM PDT 24
Peak memory 199804 kb
Host smart-79a8f351-495d-4743-aef3-4e2706921731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104205345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2104205345
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.418045909
Short name T603
Test name
Test status
Simulation time 2177118412 ps
CPU time 4.05 seconds
Started Jun 25 05:14:42 PM PDT 24
Finished Jun 25 05:14:48 PM PDT 24
Peak memory 195488 kb
Host smart-32582433-925c-4208-8707-15a3e5149a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418045909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.418045909
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.1301855477
Short name T1040
Test name
Test status
Simulation time 250302933 ps
CPU time 1.57 seconds
Started Jun 25 05:14:43 PM PDT 24
Finished Jun 25 05:14:47 PM PDT 24
Peak memory 198636 kb
Host smart-fafc1b9b-7922-4412-82ed-07a6f338fb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301855477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1301855477
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2650028518
Short name T203
Test name
Test status
Simulation time 51235102054 ps
CPU time 1343.91 seconds
Started Jun 25 05:14:42 PM PDT 24
Finished Jun 25 05:37:08 PM PDT 24
Peak memory 215456 kb
Host smart-c0b68bc9-922c-43c0-a541-26e0038b9bf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650028518 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2650028518
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.3543387542
Short name T321
Test name
Test status
Simulation time 4027811385 ps
CPU time 3.21 seconds
Started Jun 25 05:14:41 PM PDT 24
Finished Jun 25 05:14:46 PM PDT 24
Peak memory 199184 kb
Host smart-6d7a682d-78bc-4b4b-a8c9-645ed9ae259c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543387542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3543387542
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.2338042129
Short name T757
Test name
Test status
Simulation time 76524274780 ps
CPU time 57.31 seconds
Started Jun 25 05:14:41 PM PDT 24
Finished Jun 25 05:15:39 PM PDT 24
Peak memory 199728 kb
Host smart-02089c30-b79e-49a0-8a56-9d2f110869cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338042129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2338042129
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.436625396
Short name T650
Test name
Test status
Simulation time 43896620 ps
CPU time 0.57 seconds
Started Jun 25 05:14:51 PM PDT 24
Finished Jun 25 05:14:53 PM PDT 24
Peak memory 195504 kb
Host smart-91e79cc4-cfe0-4b24-a742-1042634c9807
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436625396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.436625396
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.169153318
Short name T957
Test name
Test status
Simulation time 40708899330 ps
CPU time 26.17 seconds
Started Jun 25 05:14:52 PM PDT 24
Finished Jun 25 05:15:19 PM PDT 24
Peak memory 199900 kb
Host smart-4de64ed9-36f2-42af-b9f5-310209dca8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169153318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.169153318
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.1644954361
Short name T560
Test name
Test status
Simulation time 12518109811 ps
CPU time 13.51 seconds
Started Jun 25 05:14:54 PM PDT 24
Finished Jun 25 05:15:08 PM PDT 24
Peak memory 199792 kb
Host smart-cca0f77a-d467-49cd-80f9-01b3e8820e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644954361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.1644954361
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.717930788
Short name T270
Test name
Test status
Simulation time 109853637222 ps
CPU time 43.67 seconds
Started Jun 25 05:14:50 PM PDT 24
Finished Jun 25 05:15:35 PM PDT 24
Peak memory 199768 kb
Host smart-ee310a57-4d33-413b-aa8a-afcaf95a8917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717930788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.717930788
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.804845553
Short name T563
Test name
Test status
Simulation time 55046312983 ps
CPU time 93.84 seconds
Started Jun 25 05:14:52 PM PDT 24
Finished Jun 25 05:16:27 PM PDT 24
Peak memory 199772 kb
Host smart-12aec267-143d-4854-834a-275b4eb1152a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804845553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.804845553
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.354302263
Short name T633
Test name
Test status
Simulation time 115014862333 ps
CPU time 350.3 seconds
Started Jun 25 05:14:52 PM PDT 24
Finished Jun 25 05:20:44 PM PDT 24
Peak memory 199844 kb
Host smart-e87ebefa-5ed4-4e89-9e80-4698ab779378
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=354302263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.354302263
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.925737764
Short name T755
Test name
Test status
Simulation time 7070027326 ps
CPU time 6.37 seconds
Started Jun 25 05:14:52 PM PDT 24
Finished Jun 25 05:15:00 PM PDT 24
Peak memory 199280 kb
Host smart-33c617f3-b483-4a10-a6f7-9670e6947dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925737764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.925737764
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_perf.692356998
Short name T997
Test name
Test status
Simulation time 7060255342 ps
CPU time 365.42 seconds
Started Jun 25 05:14:52 PM PDT 24
Finished Jun 25 05:20:58 PM PDT 24
Peak memory 199880 kb
Host smart-590cdd7b-4ef7-4b2a-8666-4078b2b6da2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=692356998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.692356998
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.2108221998
Short name T494
Test name
Test status
Simulation time 2336068470 ps
CPU time 10.86 seconds
Started Jun 25 05:14:52 PM PDT 24
Finished Jun 25 05:15:04 PM PDT 24
Peak memory 197812 kb
Host smart-cb688fdb-8391-4bf1-950f-fe30e8713a2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2108221998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.2108221998
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.3133839004
Short name T459
Test name
Test status
Simulation time 19405915243 ps
CPU time 29.04 seconds
Started Jun 25 05:14:54 PM PDT 24
Finished Jun 25 05:15:24 PM PDT 24
Peak memory 199916 kb
Host smart-6750b79d-53a9-424c-a2b4-47a51c9ea189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133839004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3133839004
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.3350811657
Short name T1070
Test name
Test status
Simulation time 2101463486 ps
CPU time 3.74 seconds
Started Jun 25 05:14:53 PM PDT 24
Finished Jun 25 05:14:58 PM PDT 24
Peak memory 195308 kb
Host smart-b0c523e4-dcf7-455b-8a46-3be055f36c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350811657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3350811657
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1894909720
Short name T635
Test name
Test status
Simulation time 482992543 ps
CPU time 2 seconds
Started Jun 25 05:14:52 PM PDT 24
Finished Jun 25 05:14:55 PM PDT 24
Peak memory 198276 kb
Host smart-ed624f97-36da-419c-b7b0-95682de84e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894909720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1894909720
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.2635467026
Short name T1024
Test name
Test status
Simulation time 849457544981 ps
CPU time 818.65 seconds
Started Jun 25 05:14:53 PM PDT 24
Finished Jun 25 05:28:33 PM PDT 24
Peak memory 199876 kb
Host smart-504e28c9-3bc5-47ed-896d-b9a534a878c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635467026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2635467026
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.834234249
Short name T422
Test name
Test status
Simulation time 13268613827 ps
CPU time 23.66 seconds
Started Jun 25 05:14:53 PM PDT 24
Finished Jun 25 05:15:18 PM PDT 24
Peak memory 199848 kb
Host smart-4e0ee4df-2db6-4f10-ab48-424ab7ee9fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834234249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.834234249
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.2968093543
Short name T481
Test name
Test status
Simulation time 31944076319 ps
CPU time 12.6 seconds
Started Jun 25 05:14:54 PM PDT 24
Finished Jun 25 05:15:08 PM PDT 24
Peak memory 199768 kb
Host smart-b63d117d-33e1-4998-858b-2398cb033254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968093543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.2968093543
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.837007701
Short name T23
Test name
Test status
Simulation time 19319623 ps
CPU time 0.56 seconds
Started Jun 25 05:14:54 PM PDT 24
Finished Jun 25 05:14:56 PM PDT 24
Peak memory 195148 kb
Host smart-236a4354-8333-454b-856e-8bf71dd12dbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837007701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.837007701
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.2179827919
Short name T972
Test name
Test status
Simulation time 54044310012 ps
CPU time 9.77 seconds
Started Jun 25 05:14:50 PM PDT 24
Finished Jun 25 05:15:01 PM PDT 24
Peak memory 199832 kb
Host smart-969d7f70-da86-4d6a-b120-5855eb23b9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179827919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2179827919
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.1378275684
Short name T954
Test name
Test status
Simulation time 29836616200 ps
CPU time 45.93 seconds
Started Jun 25 05:14:52 PM PDT 24
Finished Jun 25 05:15:39 PM PDT 24
Peak memory 199780 kb
Host smart-525ebcae-a09f-4e8d-b7f2-dbc01014899e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378275684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1378275684
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.1078377650
Short name T573
Test name
Test status
Simulation time 128022725986 ps
CPU time 210.16 seconds
Started Jun 25 05:14:53 PM PDT 24
Finished Jun 25 05:18:24 PM PDT 24
Peak memory 199916 kb
Host smart-2774c948-ff54-4102-9ac1-8602ebef51cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078377650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1078377650
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.1570414489
Short name T442
Test name
Test status
Simulation time 76036722402 ps
CPU time 64.38 seconds
Started Jun 25 05:14:54 PM PDT 24
Finished Jun 25 05:15:59 PM PDT 24
Peak memory 199840 kb
Host smart-ac81528f-fb73-4685-a44b-4200ccc2d2cc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570414489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1570414489
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2763432531
Short name T910
Test name
Test status
Simulation time 147837664114 ps
CPU time 554.75 seconds
Started Jun 25 05:14:51 PM PDT 24
Finished Jun 25 05:24:07 PM PDT 24
Peak memory 199892 kb
Host smart-7dea65f3-ac88-4906-b9a4-0537cd61c76b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2763432531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2763432531
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2783126535
Short name T748
Test name
Test status
Simulation time 7678995275 ps
CPU time 5.68 seconds
Started Jun 25 05:14:52 PM PDT 24
Finished Jun 25 05:14:59 PM PDT 24
Peak memory 199896 kb
Host smart-27781f16-b0a7-40a1-868a-a4a96d4ecefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783126535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2783126535
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_perf.3849234792
Short name T393
Test name
Test status
Simulation time 14746719557 ps
CPU time 818.99 seconds
Started Jun 25 05:14:54 PM PDT 24
Finished Jun 25 05:28:34 PM PDT 24
Peak memory 199844 kb
Host smart-7f4b1995-91f4-4f69-b557-44a3178f16bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3849234792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.3849234792
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.545964498
Short name T479
Test name
Test status
Simulation time 5534871186 ps
CPU time 22.08 seconds
Started Jun 25 05:14:49 PM PDT 24
Finished Jun 25 05:15:12 PM PDT 24
Peak memory 198068 kb
Host smart-528b7645-6418-4583-81fb-1870635fad4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=545964498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.545964498
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.646818255
Short name T135
Test name
Test status
Simulation time 141832349593 ps
CPU time 21.37 seconds
Started Jun 25 05:14:53 PM PDT 24
Finished Jun 25 05:15:16 PM PDT 24
Peak memory 199788 kb
Host smart-79b940c3-ae92-4a92-9765-65ef3dd9f7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646818255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.646818255
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.685045902
Short name T288
Test name
Test status
Simulation time 43911992327 ps
CPU time 9.96 seconds
Started Jun 25 05:14:54 PM PDT 24
Finished Jun 25 05:15:05 PM PDT 24
Peak memory 195788 kb
Host smart-bbf9b8f6-26c2-4952-a6c2-8e97edba7f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685045902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.685045902
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.1623581876
Short name T380
Test name
Test status
Simulation time 460253905 ps
CPU time 2.16 seconds
Started Jun 25 05:14:53 PM PDT 24
Finished Jun 25 05:14:57 PM PDT 24
Peak memory 198268 kb
Host smart-1cf40fa2-1094-40f1-9494-91e1a44f4197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623581876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.1623581876
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.138337124
Short name T675
Test name
Test status
Simulation time 69044767469 ps
CPU time 141.29 seconds
Started Jun 25 05:14:51 PM PDT 24
Finished Jun 25 05:17:13 PM PDT 24
Peak memory 199820 kb
Host smart-565b3f96-9018-442d-8086-60e0082ebc0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138337124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.138337124
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.1081370988
Short name T1047
Test name
Test status
Simulation time 125229439556 ps
CPU time 2177.99 seconds
Started Jun 25 05:14:50 PM PDT 24
Finished Jun 25 05:51:10 PM PDT 24
Peak memory 227724 kb
Host smart-93824281-036e-4e35-b77d-cb277dc0599c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081370988 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1081370988
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.3267996309
Short name T654
Test name
Test status
Simulation time 2085753468 ps
CPU time 2.19 seconds
Started Jun 25 05:14:52 PM PDT 24
Finished Jun 25 05:14:55 PM PDT 24
Peak memory 199724 kb
Host smart-5c79b5da-2041-44be-a462-6839f2c4640a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267996309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3267996309
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.173329621
Short name T391
Test name
Test status
Simulation time 19100913174 ps
CPU time 37.04 seconds
Started Jun 25 05:14:52 PM PDT 24
Finished Jun 25 05:15:30 PM PDT 24
Peak memory 199864 kb
Host smart-125987f9-7ed2-48db-a423-cb6e49931228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173329621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.173329621
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.2826770850
Short name T942
Test name
Test status
Simulation time 12262879 ps
CPU time 0.58 seconds
Started Jun 25 05:15:02 PM PDT 24
Finished Jun 25 05:15:04 PM PDT 24
Peak memory 195220 kb
Host smart-ddee9a68-561d-4042-b1f8-dd92e7c77541
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826770850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2826770850
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.2852621396
Short name T1046
Test name
Test status
Simulation time 187198899188 ps
CPU time 65.77 seconds
Started Jun 25 05:14:51 PM PDT 24
Finished Jun 25 05:15:58 PM PDT 24
Peak memory 199556 kb
Host smart-05d1e2af-3a2a-4413-ac92-bdefe067ff1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852621396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2852621396
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.3066299036
Short name T249
Test name
Test status
Simulation time 92159425603 ps
CPU time 35.39 seconds
Started Jun 25 05:15:00 PM PDT 24
Finished Jun 25 05:15:37 PM PDT 24
Peak memory 199832 kb
Host smart-145e3c07-34de-4f6f-8a07-fb469716fa8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066299036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.3066299036
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.2930109159
Short name T636
Test name
Test status
Simulation time 50634478323 ps
CPU time 28.48 seconds
Started Jun 25 05:15:02 PM PDT 24
Finished Jun 25 05:15:31 PM PDT 24
Peak memory 199836 kb
Host smart-fb62e8e1-fd3e-41db-9c07-a1a5b53f110c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930109159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.2930109159
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.654741007
Short name T976
Test name
Test status
Simulation time 217982729311 ps
CPU time 109.32 seconds
Started Jun 25 05:15:00 PM PDT 24
Finished Jun 25 05:16:51 PM PDT 24
Peak memory 199576 kb
Host smart-63acfa93-097f-48f1-afe0-6449c90d6f73
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654741007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.654741007
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.3357056614
Short name T712
Test name
Test status
Simulation time 116168547463 ps
CPU time 547.26 seconds
Started Jun 25 05:15:01 PM PDT 24
Finished Jun 25 05:24:10 PM PDT 24
Peak memory 199880 kb
Host smart-76e04037-1b08-4a05-a4a5-92847152719c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3357056614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.3357056614
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.816506500
Short name T691
Test name
Test status
Simulation time 984308107 ps
CPU time 2.06 seconds
Started Jun 25 05:15:00 PM PDT 24
Finished Jun 25 05:15:03 PM PDT 24
Peak memory 197760 kb
Host smart-f465aec2-0d29-4d82-b22f-8d76092780a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816506500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.816506500
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.1641159233
Short name T939
Test name
Test status
Simulation time 8589535840 ps
CPU time 11.27 seconds
Started Jun 25 05:15:01 PM PDT 24
Finished Jun 25 05:15:13 PM PDT 24
Peak memory 196976 kb
Host smart-9991f978-372f-4d49-bb56-6339a1dfc87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641159233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.1641159233
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.2707658277
Short name T847
Test name
Test status
Simulation time 18308246976 ps
CPU time 219.31 seconds
Started Jun 25 05:15:01 PM PDT 24
Finished Jun 25 05:18:42 PM PDT 24
Peak memory 200088 kb
Host smart-4959b8f4-d14b-424d-a25a-3f45e78fb878
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2707658277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.2707658277
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.2753752270
Short name T537
Test name
Test status
Simulation time 4869510783 ps
CPU time 13.77 seconds
Started Jun 25 05:14:59 PM PDT 24
Finished Jun 25 05:15:14 PM PDT 24
Peak memory 199236 kb
Host smart-5cd9047d-8a35-4f58-943c-7cb1fe6f8382
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2753752270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2753752270
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.1830159247
Short name T864
Test name
Test status
Simulation time 64653974169 ps
CPU time 87 seconds
Started Jun 25 05:15:00 PM PDT 24
Finished Jun 25 05:16:29 PM PDT 24
Peak memory 199892 kb
Host smart-8225e9b9-154f-474a-b033-40b99ac13d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830159247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.1830159247
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.676163725
Short name T610
Test name
Test status
Simulation time 1698932935 ps
CPU time 3.27 seconds
Started Jun 25 05:15:05 PM PDT 24
Finished Jun 25 05:15:09 PM PDT 24
Peak memory 195248 kb
Host smart-c0415ae9-767c-4756-ba5b-61399c3db2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676163725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.676163725
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.2580573849
Short name T283
Test name
Test status
Simulation time 275090753 ps
CPU time 1.12 seconds
Started Jun 25 05:14:51 PM PDT 24
Finished Jun 25 05:14:53 PM PDT 24
Peak memory 198120 kb
Host smart-8bfb390b-3cd0-4b54-8ae5-4b8689012f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580573849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2580573849
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.1537804878
Short name T102
Test name
Test status
Simulation time 314649106389 ps
CPU time 702.87 seconds
Started Jun 25 05:15:02 PM PDT 24
Finished Jun 25 05:26:46 PM PDT 24
Peak memory 199872 kb
Host smart-db1aa3d8-a59c-48ce-86e3-6ea400077c38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537804878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.1537804878
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.3589195929
Short name T999
Test name
Test status
Simulation time 1921969733 ps
CPU time 2.52 seconds
Started Jun 25 05:15:07 PM PDT 24
Finished Jun 25 05:15:11 PM PDT 24
Peak memory 199748 kb
Host smart-b88624db-ce67-4097-8822-f23362032682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589195929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.3589195929
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.1606647693
Short name T1011
Test name
Test status
Simulation time 19467125971 ps
CPU time 33.86 seconds
Started Jun 25 05:14:51 PM PDT 24
Finished Jun 25 05:15:26 PM PDT 24
Peak memory 199844 kb
Host smart-7c37c1b3-da7c-4b7a-97bd-7a2b157b806e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606647693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.1606647693
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.2727846375
Short name T1035
Test name
Test status
Simulation time 36642662 ps
CPU time 0.56 seconds
Started Jun 25 05:14:59 PM PDT 24
Finished Jun 25 05:15:00 PM PDT 24
Peak memory 195144 kb
Host smart-76d09376-dfad-4b10-93f7-822faf4a3c28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727846375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2727846375
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.2572368183
Short name T566
Test name
Test status
Simulation time 197653363654 ps
CPU time 79.1 seconds
Started Jun 25 05:15:03 PM PDT 24
Finished Jun 25 05:16:23 PM PDT 24
Peak memory 199904 kb
Host smart-1b1da944-64c0-4523-9cb7-a54ec419788a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572368183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2572368183
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.1262487424
Short name T191
Test name
Test status
Simulation time 201825394551 ps
CPU time 84.05 seconds
Started Jun 25 05:15:05 PM PDT 24
Finished Jun 25 05:16:30 PM PDT 24
Peak memory 199860 kb
Host smart-54f18ff2-2e4b-4520-a356-85db1d0844a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262487424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1262487424
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.234294530
Short name T476
Test name
Test status
Simulation time 103228653594 ps
CPU time 160.6 seconds
Started Jun 25 05:15:02 PM PDT 24
Finished Jun 25 05:17:44 PM PDT 24
Peak memory 199844 kb
Host smart-53ed425e-7183-42b0-91a6-90775fe58f81
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234294530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.234294530
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.903670640
Short name T423
Test name
Test status
Simulation time 95909576784 ps
CPU time 747.79 seconds
Started Jun 25 05:15:00 PM PDT 24
Finished Jun 25 05:27:29 PM PDT 24
Peak memory 199816 kb
Host smart-6322b1be-9ffa-4f82-ad05-ab12142794ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=903670640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.903670640
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.2925015046
Short name T497
Test name
Test status
Simulation time 13125867276 ps
CPU time 9.17 seconds
Started Jun 25 05:15:01 PM PDT 24
Finished Jun 25 05:15:12 PM PDT 24
Peak memory 199816 kb
Host smart-a642cd85-acee-4a5d-8127-0191bcec2403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925015046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2925015046
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_perf.908989098
Short name T408
Test name
Test status
Simulation time 10956667478 ps
CPU time 621.33 seconds
Started Jun 25 05:15:01 PM PDT 24
Finished Jun 25 05:25:24 PM PDT 24
Peak memory 199748 kb
Host smart-f02c282f-3ab0-4f92-bd95-a80e6454eeea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=908989098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.908989098
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.2069100863
Short name T585
Test name
Test status
Simulation time 2420364457 ps
CPU time 16.43 seconds
Started Jun 25 05:15:01 PM PDT 24
Finished Jun 25 05:15:19 PM PDT 24
Peak memory 199056 kb
Host smart-59c3a34b-1749-46aa-a4e5-f1a13a2c8e02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2069100863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2069100863
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.2720522933
Short name T793
Test name
Test status
Simulation time 18174713152 ps
CPU time 23.84 seconds
Started Jun 25 05:15:01 PM PDT 24
Finished Jun 25 05:15:26 PM PDT 24
Peak memory 199516 kb
Host smart-8e53963b-5e42-468d-8e01-f7d990f85376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720522933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2720522933
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.826424094
Short name T318
Test name
Test status
Simulation time 2776676326 ps
CPU time 4.8 seconds
Started Jun 25 05:15:01 PM PDT 24
Finished Jun 25 05:15:07 PM PDT 24
Peak memory 195612 kb
Host smart-e0947ef2-a46a-428a-ba75-cc321810d6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826424094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.826424094
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.3279237907
Short name T324
Test name
Test status
Simulation time 648658649 ps
CPU time 2.7 seconds
Started Jun 25 05:15:02 PM PDT 24
Finished Jun 25 05:15:05 PM PDT 24
Peak memory 198688 kb
Host smart-d62d6399-4a41-447d-8c53-0b9e86a1bbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279237907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3279237907
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.3083669977
Short name T523
Test name
Test status
Simulation time 166424352025 ps
CPU time 795.7 seconds
Started Jun 25 05:15:03 PM PDT 24
Finished Jun 25 05:28:20 PM PDT 24
Peak memory 199876 kb
Host smart-e5cc7aea-8773-4a68-8582-df94fbfaad2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083669977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3083669977
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.3963201234
Short name T1060
Test name
Test status
Simulation time 21250346903 ps
CPU time 92.67 seconds
Started Jun 25 05:15:03 PM PDT 24
Finished Jun 25 05:16:37 PM PDT 24
Peak memory 208176 kb
Host smart-ef967982-ea55-450f-b716-b8c2154f9f78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963201234 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.3963201234
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.3920076569
Short name T377
Test name
Test status
Simulation time 1371602506 ps
CPU time 3.99 seconds
Started Jun 25 05:15:04 PM PDT 24
Finished Jun 25 05:15:08 PM PDT 24
Peak memory 199784 kb
Host smart-59726036-83dd-4758-b288-e239921415cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920076569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3920076569
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1077969968
Short name T521
Test name
Test status
Simulation time 145617686988 ps
CPU time 63.61 seconds
Started Jun 25 05:15:01 PM PDT 24
Finished Jun 25 05:16:06 PM PDT 24
Peak memory 199784 kb
Host smart-16f3f54b-fde3-4793-a155-75ba0ac32d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077969968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1077969968
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.2594587141
Short name T996
Test name
Test status
Simulation time 20402766 ps
CPU time 0.6 seconds
Started Jun 25 05:12:45 PM PDT 24
Finished Jun 25 05:12:48 PM PDT 24
Peak memory 195220 kb
Host smart-5aa557d1-9370-4630-bea8-9a881f070352
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594587141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.2594587141
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.3380445857
Short name T304
Test name
Test status
Simulation time 173495348855 ps
CPU time 100.78 seconds
Started Jun 25 05:12:41 PM PDT 24
Finished Jun 25 05:14:23 PM PDT 24
Peak memory 199844 kb
Host smart-e05191fd-ef5a-406a-b405-e2ffd5680962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380445857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.3380445857
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3682551896
Short name T501
Test name
Test status
Simulation time 143259453677 ps
CPU time 132.95 seconds
Started Jun 25 05:12:38 PM PDT 24
Finished Jun 25 05:14:52 PM PDT 24
Peak memory 199864 kb
Host smart-ca50941e-1484-49c9-82d9-24a36e6ee6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682551896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3682551896
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.372278684
Short name T901
Test name
Test status
Simulation time 25845290135 ps
CPU time 39.5 seconds
Started Jun 25 05:12:37 PM PDT 24
Finished Jun 25 05:13:18 PM PDT 24
Peak memory 199920 kb
Host smart-e7d86ae8-6b9b-4495-82d5-e284855417d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372278684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.372278684
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.3017627521
Short name T600
Test name
Test status
Simulation time 318462728118 ps
CPU time 181.79 seconds
Started Jun 25 05:12:36 PM PDT 24
Finished Jun 25 05:15:39 PM PDT 24
Peak memory 197268 kb
Host smart-a6c05d35-6af7-4e12-a58d-ad24ac7739fb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017627521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3017627521
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.2565380775
Short name T267
Test name
Test status
Simulation time 101770266823 ps
CPU time 444.89 seconds
Started Jun 25 05:12:43 PM PDT 24
Finished Jun 25 05:20:10 PM PDT 24
Peak memory 199812 kb
Host smart-cac2f192-9865-47a8-92d6-4c4725ff7220
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2565380775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.2565380775
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.933888042
Short name T754
Test name
Test status
Simulation time 7886016611 ps
CPU time 7.86 seconds
Started Jun 25 05:12:45 PM PDT 24
Finished Jun 25 05:12:56 PM PDT 24
Peak memory 199552 kb
Host smart-edab1ce5-18e5-4227-9dac-bef3e274c80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933888042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.933888042
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_perf.234484302
Short name T902
Test name
Test status
Simulation time 15772433907 ps
CPU time 775.59 seconds
Started Jun 25 05:12:34 PM PDT 24
Finished Jun 25 05:25:32 PM PDT 24
Peak memory 199848 kb
Host smart-c7437121-5255-43cf-a667-40ab131661bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=234484302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.234484302
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.1033746861
Short name T641
Test name
Test status
Simulation time 6565729638 ps
CPU time 15.5 seconds
Started Jun 25 05:12:35 PM PDT 24
Finished Jun 25 05:12:52 PM PDT 24
Peak memory 198012 kb
Host smart-e1adbb61-07c3-4800-bc48-85f9710213b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1033746861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1033746861
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.641969485
Short name T577
Test name
Test status
Simulation time 28501258888 ps
CPU time 52.2 seconds
Started Jun 25 05:12:36 PM PDT 24
Finished Jun 25 05:13:30 PM PDT 24
Peak memory 199908 kb
Host smart-ac84c250-f93f-4c3c-bd7a-ec57decc4550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641969485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.641969485
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.190879039
Short name T716
Test name
Test status
Simulation time 1892040583 ps
CPU time 2.19 seconds
Started Jun 25 05:12:45 PM PDT 24
Finished Jun 25 05:12:50 PM PDT 24
Peak memory 195196 kb
Host smart-5b76d9f1-92db-4e3d-9914-b9dedc7c0328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190879039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.190879039
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.1049132234
Short name T90
Test name
Test status
Simulation time 106789956 ps
CPU time 0.86 seconds
Started Jun 25 05:12:44 PM PDT 24
Finished Jun 25 05:12:47 PM PDT 24
Peak memory 218216 kb
Host smart-76cce178-1719-4d32-901a-8bb60ad48b44
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049132234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.1049132234
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.327964948
Short name T395
Test name
Test status
Simulation time 97006395 ps
CPU time 0.76 seconds
Started Jun 25 05:12:42 PM PDT 24
Finished Jun 25 05:12:44 PM PDT 24
Peak memory 196704 kb
Host smart-8e63584b-d7d4-40f4-9790-8d7571a1fb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327964948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.327964948
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2706926226
Short name T118
Test name
Test status
Simulation time 144203136390 ps
CPU time 55.17 seconds
Started Jun 25 05:12:44 PM PDT 24
Finished Jun 25 05:13:41 PM PDT 24
Peak memory 199884 kb
Host smart-af7b42c6-77c7-40cd-b040-1a2296c53424
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706926226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2706926226
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.3251315058
Short name T303
Test name
Test status
Simulation time 5114783079 ps
CPU time 2.7 seconds
Started Jun 25 05:12:31 PM PDT 24
Finished Jun 25 05:12:35 PM PDT 24
Peak memory 199020 kb
Host smart-c89a0f34-c803-443e-9765-b442ee37b583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251315058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3251315058
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3877481727
Short name T981
Test name
Test status
Simulation time 91698878323 ps
CPU time 48.08 seconds
Started Jun 25 05:12:35 PM PDT 24
Finished Jun 25 05:13:25 PM PDT 24
Peak memory 199796 kb
Host smart-107dfe6c-7aaa-4e10-83e5-85bc8eb5c328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877481727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3877481727
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2731349973
Short name T50
Test name
Test status
Simulation time 13665334 ps
CPU time 0.6 seconds
Started Jun 25 05:15:10 PM PDT 24
Finished Jun 25 05:15:12 PM PDT 24
Peak memory 195148 kb
Host smart-e900a525-fbe5-4202-8fb8-53dd603b678e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731349973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2731349973
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.2210618870
Short name T258
Test name
Test status
Simulation time 86027361821 ps
CPU time 140.83 seconds
Started Jun 25 05:15:01 PM PDT 24
Finished Jun 25 05:17:23 PM PDT 24
Peak memory 199884 kb
Host smart-37f39033-436d-460a-8c0d-05728c6c7ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210618870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2210618870
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.1103942437
Short name T876
Test name
Test status
Simulation time 87313069023 ps
CPU time 43.19 seconds
Started Jun 25 05:15:05 PM PDT 24
Finished Jun 25 05:15:49 PM PDT 24
Peak memory 199900 kb
Host smart-912c914b-9e2d-45d5-bc55-3978802cb7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103942437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1103942437
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_intr.597934595
Short name T404
Test name
Test status
Simulation time 16481901696 ps
CPU time 9.11 seconds
Started Jun 25 05:15:07 PM PDT 24
Finished Jun 25 05:15:17 PM PDT 24
Peak memory 197588 kb
Host smart-e37a5d47-c972-4416-a105-9685979e242a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597934595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.597934595
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.3153223637
Short name T989
Test name
Test status
Simulation time 68164055151 ps
CPU time 191.82 seconds
Started Jun 25 05:15:14 PM PDT 24
Finished Jun 25 05:18:27 PM PDT 24
Peak memory 199888 kb
Host smart-9ab5c750-72c2-4652-aa82-74e5dd846bcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3153223637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3153223637
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.571632858
Short name T920
Test name
Test status
Simulation time 1209041346 ps
CPU time 0.92 seconds
Started Jun 25 05:15:08 PM PDT 24
Finished Jun 25 05:15:09 PM PDT 24
Peak memory 195512 kb
Host smart-5d9ec581-80aa-4e6c-9b5c-914e28a4f0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571632858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.571632858
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_perf.1466582615
Short name T711
Test name
Test status
Simulation time 6391207044 ps
CPU time 325.88 seconds
Started Jun 25 05:15:04 PM PDT 24
Finished Jun 25 05:20:31 PM PDT 24
Peak memory 199764 kb
Host smart-a8456643-865c-4970-85fe-e1a825551bdd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1466582615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1466582615
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.4250640546
Short name T1062
Test name
Test status
Simulation time 7278924410 ps
CPU time 18.89 seconds
Started Jun 25 05:15:02 PM PDT 24
Finished Jun 25 05:15:22 PM PDT 24
Peak memory 199372 kb
Host smart-771ff568-d06d-41dc-bcfe-2747c74f5180
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4250640546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.4250640546
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.2452597734
Short name T621
Test name
Test status
Simulation time 30507953511 ps
CPU time 23.75 seconds
Started Jun 25 05:15:00 PM PDT 24
Finished Jun 25 05:15:25 PM PDT 24
Peak memory 196032 kb
Host smart-65c75569-1061-4923-9c5d-d29d704c9964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452597734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2452597734
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.2072880001
Short name T637
Test name
Test status
Simulation time 146252208 ps
CPU time 0.82 seconds
Started Jun 25 05:15:04 PM PDT 24
Finished Jun 25 05:15:06 PM PDT 24
Peak memory 196984 kb
Host smart-215637e2-1daf-40eb-8084-518e1fe29d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072880001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.2072880001
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.325412919
Short name T419
Test name
Test status
Simulation time 61731786204 ps
CPU time 67.14 seconds
Started Jun 25 05:15:09 PM PDT 24
Finished Jun 25 05:16:17 PM PDT 24
Peak memory 199880 kb
Host smart-bdc4f0b9-c20c-43e6-a546-771118248110
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325412919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.325412919
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.1897110017
Short name T1008
Test name
Test status
Simulation time 1987748724 ps
CPU time 2.01 seconds
Started Jun 25 05:15:08 PM PDT 24
Finished Jun 25 05:15:10 PM PDT 24
Peak memory 198516 kb
Host smart-21fcf8b5-7b8a-41dd-8b93-8451b6d021e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897110017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.1897110017
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.3049732690
Short name T424
Test name
Test status
Simulation time 48602664398 ps
CPU time 28.27 seconds
Started Jun 25 05:15:04 PM PDT 24
Finished Jun 25 05:15:34 PM PDT 24
Peak memory 199752 kb
Host smart-00676fca-c2e7-422d-adc9-a7fca5733e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049732690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.3049732690
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.2396213340
Short name T382
Test name
Test status
Simulation time 40081009 ps
CPU time 0.58 seconds
Started Jun 25 05:15:11 PM PDT 24
Finished Jun 25 05:15:13 PM PDT 24
Peak memory 195700 kb
Host smart-34435def-759f-444d-b8f6-c446db322cb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396213340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2396213340
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.897787881
Short name T947
Test name
Test status
Simulation time 77769515991 ps
CPU time 20.8 seconds
Started Jun 25 05:15:09 PM PDT 24
Finished Jun 25 05:15:30 PM PDT 24
Peak memory 199788 kb
Host smart-e80abef3-6c7d-4b4d-9df3-c3dadfc1c35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897787881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.897787881
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.3219092695
Short name T257
Test name
Test status
Simulation time 94018236720 ps
CPU time 271.86 seconds
Started Jun 25 05:15:10 PM PDT 24
Finished Jun 25 05:19:43 PM PDT 24
Peak memory 199780 kb
Host smart-e539eaae-5a6c-4f13-af0e-42601178fb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219092695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3219092695
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.1783376474
Short name T130
Test name
Test status
Simulation time 67303637683 ps
CPU time 20.43 seconds
Started Jun 25 05:15:11 PM PDT 24
Finished Jun 25 05:15:32 PM PDT 24
Peak memory 199904 kb
Host smart-d7fdba5a-9e4a-4888-a29c-c5565605e11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783376474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.1783376474
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.1071906892
Short name T831
Test name
Test status
Simulation time 16305546807 ps
CPU time 7.2 seconds
Started Jun 25 05:15:12 PM PDT 24
Finished Jun 25 05:15:20 PM PDT 24
Peak memory 199884 kb
Host smart-7708bc2c-68a5-4b07-a8f5-4a47b3cedded
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071906892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1071906892
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.3214762085
Short name T327
Test name
Test status
Simulation time 156290762807 ps
CPU time 362.28 seconds
Started Jun 25 05:15:11 PM PDT 24
Finished Jun 25 05:21:15 PM PDT 24
Peak memory 199876 kb
Host smart-0b66bb98-33f4-4adb-89a5-1c0d1f61ffaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3214762085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.3214762085
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.265651883
Short name T843
Test name
Test status
Simulation time 8459676026 ps
CPU time 8.05 seconds
Started Jun 25 05:15:09 PM PDT 24
Finished Jun 25 05:15:19 PM PDT 24
Peak memory 198208 kb
Host smart-b80a89a1-5bb8-45a6-b610-f239e7e38855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265651883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.265651883
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.3655291430
Short name T510
Test name
Test status
Simulation time 19192431907 ps
CPU time 14.23 seconds
Started Jun 25 05:15:11 PM PDT 24
Finished Jun 25 05:15:27 PM PDT 24
Peak memory 196588 kb
Host smart-966fe342-cb99-4c93-a9de-33aa157182bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655291430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.3655291430
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.3067181732
Short name T420
Test name
Test status
Simulation time 7669411870 ps
CPU time 104.52 seconds
Started Jun 25 05:15:12 PM PDT 24
Finished Jun 25 05:16:58 PM PDT 24
Peak memory 199840 kb
Host smart-8a1aa1c8-2bf2-4fdf-9e7e-1cda793391ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3067181732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3067181732
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.3626417200
Short name T824
Test name
Test status
Simulation time 3407199258 ps
CPU time 27.93 seconds
Started Jun 25 05:15:10 PM PDT 24
Finished Jun 25 05:15:39 PM PDT 24
Peak memory 198016 kb
Host smart-e0bb2c4b-9b2c-4830-804c-7e59c15640a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3626417200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3626417200
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.2521626544
Short name T144
Test name
Test status
Simulation time 42381173239 ps
CPU time 24.85 seconds
Started Jun 25 05:15:11 PM PDT 24
Finished Jun 25 05:15:37 PM PDT 24
Peak memory 199828 kb
Host smart-4c20744a-c386-4d52-a705-312abdde1b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521626544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2521626544
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.2277167877
Short name T1012
Test name
Test status
Simulation time 401079802 ps
CPU time 1.26 seconds
Started Jun 25 05:15:15 PM PDT 24
Finished Jun 25 05:15:17 PM PDT 24
Peak memory 195328 kb
Host smart-427ca1ba-6619-4528-86c8-10c9da2bf0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277167877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2277167877
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2432997511
Short name T316
Test name
Test status
Simulation time 6051274291 ps
CPU time 17.12 seconds
Started Jun 25 05:15:09 PM PDT 24
Finished Jun 25 05:15:27 PM PDT 24
Peak memory 199780 kb
Host smart-cc669246-2671-40fa-9c9d-5361e7f2acc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432997511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2432997511
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.2821995194
Short name T773
Test name
Test status
Simulation time 1023225705 ps
CPU time 3.18 seconds
Started Jun 25 05:15:09 PM PDT 24
Finished Jun 25 05:15:13 PM PDT 24
Peak memory 198164 kb
Host smart-c2f662e8-38f5-4603-a700-8c991f14444a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821995194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2821995194
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2660396937
Short name T730
Test name
Test status
Simulation time 52868137053 ps
CPU time 32.58 seconds
Started Jun 25 05:15:15 PM PDT 24
Finished Jun 25 05:15:48 PM PDT 24
Peak memory 199912 kb
Host smart-5235e34b-67fa-473f-8fa5-504c3307927b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660396937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2660396937
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.2288831471
Short name T853
Test name
Test status
Simulation time 46321835 ps
CPU time 0.53 seconds
Started Jun 25 05:15:18 PM PDT 24
Finished Jun 25 05:15:20 PM PDT 24
Peak memory 195228 kb
Host smart-b4734f13-9b35-4bd3-a51f-8913d992bf66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288831471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.2288831471
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2078170295
Short name T429
Test name
Test status
Simulation time 25452104310 ps
CPU time 22.17 seconds
Started Jun 25 05:15:14 PM PDT 24
Finished Jun 25 05:15:37 PM PDT 24
Peak memory 199904 kb
Host smart-19dc24b0-edae-47b6-892c-9b1fd01e457a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078170295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2078170295
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.70487981
Short name T753
Test name
Test status
Simulation time 56507732326 ps
CPU time 85.24 seconds
Started Jun 25 05:15:12 PM PDT 24
Finished Jun 25 05:16:38 PM PDT 24
Peak memory 199856 kb
Host smart-9b190b08-a9d4-4e9e-aab0-54c3c86b5a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70487981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.70487981
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.1773179920
Short name T965
Test name
Test status
Simulation time 24307675893 ps
CPU time 37.88 seconds
Started Jun 25 05:15:06 PM PDT 24
Finished Jun 25 05:15:44 PM PDT 24
Peak memory 199920 kb
Host smart-27ee217e-d95d-45ae-a40c-a075d0157acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773179920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.1773179920
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2117474355
Short name T525
Test name
Test status
Simulation time 20432819647 ps
CPU time 8.9 seconds
Started Jun 25 05:15:12 PM PDT 24
Finished Jun 25 05:15:22 PM PDT 24
Peak memory 198972 kb
Host smart-934228f8-bfb5-413d-b02e-2d15233d87d2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117474355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2117474355
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.917387705
Short name T803
Test name
Test status
Simulation time 98667491658 ps
CPU time 234.28 seconds
Started Jun 25 05:15:17 PM PDT 24
Finished Jun 25 05:19:12 PM PDT 24
Peak memory 199872 kb
Host smart-5e0f0d70-fa50-4b4f-9a9d-4a6674c50bc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=917387705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.917387705
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.334417470
Short name T1037
Test name
Test status
Simulation time 2842085611 ps
CPU time 2.31 seconds
Started Jun 25 05:15:11 PM PDT 24
Finished Jun 25 05:15:15 PM PDT 24
Peak memory 198104 kb
Host smart-2b1d9bb6-d16e-4981-85a3-2e201c3eba30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334417470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.334417470
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_perf.1832416350
Short name T696
Test name
Test status
Simulation time 37811613169 ps
CPU time 193.21 seconds
Started Jun 25 05:15:12 PM PDT 24
Finished Jun 25 05:18:26 PM PDT 24
Peak memory 199808 kb
Host smart-2090032e-3acb-4eb0-967b-2239b691d3e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1832416350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1832416350
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.4139091324
Short name T355
Test name
Test status
Simulation time 3685275071 ps
CPU time 16.48 seconds
Started Jun 25 05:15:09 PM PDT 24
Finished Jun 25 05:15:26 PM PDT 24
Peak memory 198224 kb
Host smart-0ac11ce1-765d-417c-a19c-934cd3d1dd50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4139091324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.4139091324
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.2422165401
Short name T931
Test name
Test status
Simulation time 404203166396 ps
CPU time 51.71 seconds
Started Jun 25 05:15:11 PM PDT 24
Finished Jun 25 05:16:04 PM PDT 24
Peak memory 199904 kb
Host smart-8a61d9f2-0855-4630-857e-1cd2137661a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422165401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2422165401
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3012184022
Short name T938
Test name
Test status
Simulation time 5469186372 ps
CPU time 4.92 seconds
Started Jun 25 05:15:09 PM PDT 24
Finished Jun 25 05:15:15 PM PDT 24
Peak memory 195892 kb
Host smart-cfe8d2a1-f7e0-4401-96f8-4a3b10bf067a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012184022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3012184022
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.2774956565
Short name T11
Test name
Test status
Simulation time 440702251 ps
CPU time 1.34 seconds
Started Jun 25 05:15:10 PM PDT 24
Finished Jun 25 05:15:12 PM PDT 24
Peak memory 198420 kb
Host smart-942abd55-8aa5-4edc-8cf8-68cf03751067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774956565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2774956565
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.1741805470
Short name T160
Test name
Test status
Simulation time 517969409523 ps
CPU time 135.5 seconds
Started Jun 25 05:15:18 PM PDT 24
Finished Jun 25 05:17:35 PM PDT 24
Peak memory 199764 kb
Host smart-985c0c02-b758-4f61-8e80-5c9688d6f58a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741805470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1741805470
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.1915005780
Short name T860
Test name
Test status
Simulation time 6741169654 ps
CPU time 33.34 seconds
Started Jun 25 05:15:12 PM PDT 24
Finished Jun 25 05:15:46 PM PDT 24
Peak memory 199888 kb
Host smart-42d9648a-bd4d-49aa-8b0d-75dc8009549d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915005780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1915005780
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.763511460
Short name T644
Test name
Test status
Simulation time 70437303181 ps
CPU time 31.66 seconds
Started Jun 25 05:15:11 PM PDT 24
Finished Jun 25 05:15:44 PM PDT 24
Peak memory 199928 kb
Host smart-fd3b05fc-019a-41f6-80ac-08ebd5934a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763511460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.763511460
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.2466921085
Short name T1085
Test name
Test status
Simulation time 19484453 ps
CPU time 0.55 seconds
Started Jun 25 05:15:18 PM PDT 24
Finished Jun 25 05:15:20 PM PDT 24
Peak memory 194208 kb
Host smart-437cd6a2-3f31-492e-bf5e-6d6fa0fe6f42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466921085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2466921085
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.4171360049
Short name T950
Test name
Test status
Simulation time 36564681470 ps
CPU time 14.47 seconds
Started Jun 25 05:15:19 PM PDT 24
Finished Jun 25 05:15:35 PM PDT 24
Peak memory 199804 kb
Host smart-8e8c65eb-d43b-44db-b02d-4448ef113f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171360049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.4171360049
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3438655645
Short name T992
Test name
Test status
Simulation time 114213235779 ps
CPU time 52.3 seconds
Started Jun 25 05:15:25 PM PDT 24
Finished Jun 25 05:16:19 PM PDT 24
Peak memory 199816 kb
Host smart-34a715ae-4819-4d38-952c-0bffd29f198a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438655645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3438655645
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.590738712
Short name T982
Test name
Test status
Simulation time 47738471273 ps
CPU time 20.02 seconds
Started Jun 25 05:15:16 PM PDT 24
Finished Jun 25 05:15:37 PM PDT 24
Peak memory 199908 kb
Host smart-791722de-5da9-43fd-b0ec-1dc36152889f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590738712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.590738712
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.515462184
Short name T647
Test name
Test status
Simulation time 10432328228 ps
CPU time 4.92 seconds
Started Jun 25 05:15:18 PM PDT 24
Finished Jun 25 05:15:24 PM PDT 24
Peak memory 197520 kb
Host smart-3cea8cf9-99b1-4a5e-a9b4-be2e1a57fef1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515462184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.515462184
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.3204562567
Short name T539
Test name
Test status
Simulation time 110084542896 ps
CPU time 625.26 seconds
Started Jun 25 05:15:20 PM PDT 24
Finished Jun 25 05:25:47 PM PDT 24
Peak memory 199896 kb
Host smart-a16df717-74a4-4d8e-a70e-978cfa5b1eef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3204562567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3204562567
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.1682449832
Short name T845
Test name
Test status
Simulation time 1661468416 ps
CPU time 3 seconds
Started Jun 25 05:15:18 PM PDT 24
Finished Jun 25 05:15:22 PM PDT 24
Peak memory 195328 kb
Host smart-c3ebb37e-640c-41fb-bfba-5177ec7efaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682449832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.1682449832
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_perf.1577001184
Short name T959
Test name
Test status
Simulation time 14285379540 ps
CPU time 819.95 seconds
Started Jun 25 05:15:24 PM PDT 24
Finished Jun 25 05:29:05 PM PDT 24
Peak memory 199880 kb
Host smart-e48c6321-ef0d-466f-b1e8-e1c2484a9480
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1577001184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1577001184
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.854458878
Short name T771
Test name
Test status
Simulation time 6237025616 ps
CPU time 3.63 seconds
Started Jun 25 05:15:16 PM PDT 24
Finished Jun 25 05:15:21 PM PDT 24
Peak memory 198080 kb
Host smart-72277f6d-dbb0-4723-9d0f-0e1baa5f4a63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=854458878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.854458878
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.880227147
Short name T542
Test name
Test status
Simulation time 128564943634 ps
CPU time 89.84 seconds
Started Jun 25 05:15:19 PM PDT 24
Finished Jun 25 05:16:50 PM PDT 24
Peak memory 199808 kb
Host smart-ff14995e-b16d-4449-b6f4-537096d5ce78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880227147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.880227147
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.3305227372
Short name T534
Test name
Test status
Simulation time 5929097074 ps
CPU time 1.24 seconds
Started Jun 25 05:15:19 PM PDT 24
Finished Jun 25 05:15:21 PM PDT 24
Peak memory 195980 kb
Host smart-d26a2758-1158-4ece-9fa7-4d384de44bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305227372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3305227372
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.3242260634
Short name T265
Test name
Test status
Simulation time 6282746075 ps
CPU time 22.88 seconds
Started Jun 25 05:15:18 PM PDT 24
Finished Jun 25 05:15:41 PM PDT 24
Peak memory 199892 kb
Host smart-4239242f-8f8a-4c11-8d2c-48e85b5b1884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242260634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.3242260634
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.1428709110
Short name T984
Test name
Test status
Simulation time 129912234070 ps
CPU time 556.26 seconds
Started Jun 25 05:15:19 PM PDT 24
Finished Jun 25 05:24:37 PM PDT 24
Peak memory 216372 kb
Host smart-e3829314-a42c-4f99-8499-f57d7a8022fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428709110 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.1428709110
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3206248217
Short name T667
Test name
Test status
Simulation time 7382541783 ps
CPU time 13.75 seconds
Started Jun 25 05:15:20 PM PDT 24
Finished Jun 25 05:15:35 PM PDT 24
Peak memory 199836 kb
Host smart-ac2e0da4-2ecb-4b42-aae3-97f65d837d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206248217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3206248217
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.3476181698
Short name T891
Test name
Test status
Simulation time 189180649883 ps
CPU time 72.98 seconds
Started Jun 25 05:15:25 PM PDT 24
Finished Jun 25 05:16:39 PM PDT 24
Peak memory 199908 kb
Host smart-f657f47c-ccb2-4d11-8f8b-dccbd404b6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476181698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.3476181698
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.1667729681
Short name T800
Test name
Test status
Simulation time 44518352 ps
CPU time 0.57 seconds
Started Jun 25 05:15:30 PM PDT 24
Finished Jun 25 05:15:31 PM PDT 24
Peak memory 195432 kb
Host smart-b70db943-fcce-4af1-b12e-05b4645e97ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667729681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1667729681
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.707715112
Short name T935
Test name
Test status
Simulation time 51366033325 ps
CPU time 19.72 seconds
Started Jun 25 05:15:17 PM PDT 24
Finished Jun 25 05:15:37 PM PDT 24
Peak memory 199796 kb
Host smart-efae7f6f-6c18-4d07-aa35-a3249150a5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707715112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.707715112
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3887746873
Short name T694
Test name
Test status
Simulation time 64412434465 ps
CPU time 421.18 seconds
Started Jun 25 05:15:19 PM PDT 24
Finished Jun 25 05:22:21 PM PDT 24
Peak memory 199896 kb
Host smart-89fb14df-8e7e-42f6-b7bf-2540dc53c28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887746873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3887746873
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.3048156438
Short name T795
Test name
Test status
Simulation time 119949461785 ps
CPU time 152.44 seconds
Started Jun 25 05:15:18 PM PDT 24
Finished Jun 25 05:17:52 PM PDT 24
Peak memory 199896 kb
Host smart-b824cbb3-109b-444a-99df-848189ec0905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048156438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.3048156438
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.657688966
Short name T833
Test name
Test status
Simulation time 186739200453 ps
CPU time 510.2 seconds
Started Jun 25 05:15:27 PM PDT 24
Finished Jun 25 05:23:59 PM PDT 24
Peak memory 199816 kb
Host smart-5c09c155-8886-44be-801e-18da51a41454
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=657688966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.657688966
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.3708652476
Short name T455
Test name
Test status
Simulation time 8384343498 ps
CPU time 15.11 seconds
Started Jun 25 05:15:28 PM PDT 24
Finished Jun 25 05:15:44 PM PDT 24
Peak memory 199896 kb
Host smart-1abd1893-a02b-41dd-a5dd-77dc99c20944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708652476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3708652476
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_perf.2645343603
Short name T297
Test name
Test status
Simulation time 14964246105 ps
CPU time 663.82 seconds
Started Jun 25 05:15:26 PM PDT 24
Finished Jun 25 05:26:31 PM PDT 24
Peak memory 199804 kb
Host smart-96c9ea62-4051-4c55-bc39-e50f1472898f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2645343603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2645343603
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.1871225915
Short name T383
Test name
Test status
Simulation time 4839797389 ps
CPU time 9.17 seconds
Started Jun 25 05:15:18 PM PDT 24
Finished Jun 25 05:15:29 PM PDT 24
Peak memory 199056 kb
Host smart-59d14961-f2f6-40aa-b1fc-367dd425ef1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1871225915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1871225915
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.2673476139
Short name T970
Test name
Test status
Simulation time 4609862471 ps
CPU time 1.62 seconds
Started Jun 25 05:15:25 PM PDT 24
Finished Jun 25 05:15:27 PM PDT 24
Peak memory 196136 kb
Host smart-a4bd371b-0c2a-4f86-8f2f-01ca2417affe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673476139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2673476139
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.2851056154
Short name T940
Test name
Test status
Simulation time 463339782 ps
CPU time 1.65 seconds
Started Jun 25 05:15:20 PM PDT 24
Finished Jun 25 05:15:23 PM PDT 24
Peak memory 199472 kb
Host smart-c0c7e46c-5e9a-4925-80bb-6f4567915da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851056154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2851056154
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.3914398826
Short name T251
Test name
Test status
Simulation time 367295767174 ps
CPU time 200.34 seconds
Started Jun 25 05:15:28 PM PDT 24
Finished Jun 25 05:18:50 PM PDT 24
Peak memory 199856 kb
Host smart-3a1ed337-5538-4216-9fb7-67c090f3a6a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914398826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.3914398826
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.1309248039
Short name T648
Test name
Test status
Simulation time 1576015245 ps
CPU time 1.63 seconds
Started Jun 25 05:15:25 PM PDT 24
Finished Jun 25 05:15:28 PM PDT 24
Peak memory 198564 kb
Host smart-956d7ece-c8c1-4c0c-aaa8-460f2ddf281e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309248039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1309248039
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.4192448811
Short name T440
Test name
Test status
Simulation time 104674896827 ps
CPU time 116.67 seconds
Started Jun 25 05:15:20 PM PDT 24
Finished Jun 25 05:17:18 PM PDT 24
Peak memory 199908 kb
Host smart-6d34e579-8ee5-4215-a1b3-cdb6ca61a196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192448811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.4192448811
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3077647396
Short name T357
Test name
Test status
Simulation time 63883667 ps
CPU time 0.59 seconds
Started Jun 25 05:15:28 PM PDT 24
Finished Jun 25 05:15:30 PM PDT 24
Peak memory 195528 kb
Host smart-75afb1dc-760b-4083-a8df-1858c4843618
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077647396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3077647396
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.998511634
Short name T697
Test name
Test status
Simulation time 84943212024 ps
CPU time 40.97 seconds
Started Jun 25 05:15:28 PM PDT 24
Finished Jun 25 05:16:10 PM PDT 24
Peak memory 199928 kb
Host smart-833097d8-42ae-4665-9e07-f947dcabd029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998511634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.998511634
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.86465365
Short name T557
Test name
Test status
Simulation time 108924375688 ps
CPU time 28.35 seconds
Started Jun 25 05:15:26 PM PDT 24
Finished Jun 25 05:15:55 PM PDT 24
Peak memory 199612 kb
Host smart-7a4fc5a7-67fe-42db-83bb-122c95ed568a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86465365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.86465365
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.1598080065
Short name T123
Test name
Test status
Simulation time 43263855944 ps
CPU time 20.7 seconds
Started Jun 25 05:15:28 PM PDT 24
Finished Jun 25 05:15:50 PM PDT 24
Peak memory 199836 kb
Host smart-7c9ed187-289a-47b3-a6dc-bdc3d6bfb7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598080065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.1598080065
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.1714316435
Short name T544
Test name
Test status
Simulation time 15797191190 ps
CPU time 20.81 seconds
Started Jun 25 05:15:29 PM PDT 24
Finished Jun 25 05:15:51 PM PDT 24
Peak memory 196820 kb
Host smart-c21fa876-82d0-4e04-842d-03c6eebb4db4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714316435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.1714316435
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.3714513253
Short name T707
Test name
Test status
Simulation time 83806608849 ps
CPU time 505.86 seconds
Started Jun 25 05:15:28 PM PDT 24
Finished Jun 25 05:23:55 PM PDT 24
Peak memory 199884 kb
Host smart-a66c2421-011f-4639-9932-b49dc3f9eeaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3714513253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3714513253
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.1033945457
Short name T1001
Test name
Test status
Simulation time 7972100169 ps
CPU time 3.96 seconds
Started Jun 25 05:15:28 PM PDT 24
Finished Jun 25 05:15:33 PM PDT 24
Peak memory 199800 kb
Host smart-04ab7b16-9492-41d9-9d5f-782101c56e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033945457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1033945457
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_perf.1176212128
Short name T541
Test name
Test status
Simulation time 10312421930 ps
CPU time 399.66 seconds
Started Jun 25 05:15:30 PM PDT 24
Finished Jun 25 05:22:11 PM PDT 24
Peak memory 199812 kb
Host smart-9a5e78e5-0f18-426c-808b-a19eb56d7e5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1176212128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.1176212128
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.3393824532
Short name T401
Test name
Test status
Simulation time 2522750107 ps
CPU time 18.19 seconds
Started Jun 25 05:15:30 PM PDT 24
Finished Jun 25 05:15:49 PM PDT 24
Peak memory 197860 kb
Host smart-348f3b47-7c97-47b0-a9ee-2ca849f09fde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3393824532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3393824532
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.1790376558
Short name T569
Test name
Test status
Simulation time 58411930500 ps
CPU time 25.03 seconds
Started Jun 25 05:15:27 PM PDT 24
Finished Jun 25 05:15:53 PM PDT 24
Peak memory 199480 kb
Host smart-e9699168-c708-4b73-b5e6-977213644b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790376558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.1790376558
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.2223622493
Short name T695
Test name
Test status
Simulation time 39400029995 ps
CPU time 23.07 seconds
Started Jun 25 05:15:27 PM PDT 24
Finished Jun 25 05:15:52 PM PDT 24
Peak memory 195700 kb
Host smart-05263e31-32d2-4528-b4b6-6635e18c15e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223622493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2223622493
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2076938617
Short name T509
Test name
Test status
Simulation time 562846799 ps
CPU time 1.46 seconds
Started Jun 25 05:15:32 PM PDT 24
Finished Jun 25 05:15:34 PM PDT 24
Peak memory 199608 kb
Host smart-7e1c0077-6a8f-4be6-900c-85fcee46a3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076938617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2076938617
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.1296449681
Short name T713
Test name
Test status
Simulation time 180700627838 ps
CPU time 331.92 seconds
Started Jun 25 05:15:29 PM PDT 24
Finished Jun 25 05:21:02 PM PDT 24
Peak memory 199868 kb
Host smart-38c95ae2-90f7-4764-8535-9f9a48a4b698
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296449681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.1296449681
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.3685173071
Short name T206
Test name
Test status
Simulation time 162603748024 ps
CPU time 351.61 seconds
Started Jun 25 05:15:28 PM PDT 24
Finished Jun 25 05:21:21 PM PDT 24
Peak memory 216332 kb
Host smart-a0beb7a3-63f6-40a3-a3b0-4954e8b38b21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685173071 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.3685173071
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2482484512
Short name T967
Test name
Test status
Simulation time 8577657044 ps
CPU time 7.28 seconds
Started Jun 25 05:15:28 PM PDT 24
Finished Jun 25 05:15:36 PM PDT 24
Peak memory 199152 kb
Host smart-0b619b11-22a8-4808-9c68-d64e9e0960bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482484512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2482484512
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.576016715
Short name T306
Test name
Test status
Simulation time 194899194221 ps
CPU time 43.07 seconds
Started Jun 25 05:15:32 PM PDT 24
Finished Jun 25 05:16:15 PM PDT 24
Peak memory 199832 kb
Host smart-d70241f4-ef87-47b9-b389-083eaa52ecda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576016715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.576016715
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.3894406143
Short name T776
Test name
Test status
Simulation time 10609072 ps
CPU time 0.58 seconds
Started Jun 25 05:15:37 PM PDT 24
Finished Jun 25 05:15:39 PM PDT 24
Peak memory 195152 kb
Host smart-f4af8264-52fa-4162-9eff-04ca8c26ade7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894406143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3894406143
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.3463452750
Short name T301
Test name
Test status
Simulation time 41680928741 ps
CPU time 34.01 seconds
Started Jun 25 05:15:28 PM PDT 24
Finished Jun 25 05:16:03 PM PDT 24
Peak memory 199844 kb
Host smart-7918d204-7012-4b8c-b8fd-590ad32a1fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463452750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.3463452750
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.1691348915
Short name T808
Test name
Test status
Simulation time 110365761342 ps
CPU time 253.97 seconds
Started Jun 25 05:15:27 PM PDT 24
Finished Jun 25 05:19:43 PM PDT 24
Peak memory 199836 kb
Host smart-dc0aa7b6-f7cf-420d-9081-e0a38bd13d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691348915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1691348915
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.2804878303
Short name T202
Test name
Test status
Simulation time 15383824701 ps
CPU time 16.75 seconds
Started Jun 25 05:15:39 PM PDT 24
Finished Jun 25 05:15:57 PM PDT 24
Peak memory 199892 kb
Host smart-178dfdae-ea9d-4a01-9fe8-3fcb74d9a046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804878303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2804878303
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.38788846
Short name T720
Test name
Test status
Simulation time 43033651473 ps
CPU time 35.63 seconds
Started Jun 25 05:15:37 PM PDT 24
Finished Jun 25 05:16:14 PM PDT 24
Peak memory 199852 kb
Host smart-dd600c3a-018d-4a60-8581-0ef12db218e2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38788846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.38788846
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.2979899388
Short name T604
Test name
Test status
Simulation time 71525850592 ps
CPU time 169.28 seconds
Started Jun 25 05:15:37 PM PDT 24
Finished Jun 25 05:18:28 PM PDT 24
Peak memory 199804 kb
Host smart-93268b31-7525-4a9c-848d-a116b83b531e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2979899388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.2979899388
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.4278978920
Short name T739
Test name
Test status
Simulation time 5110323219 ps
CPU time 9.2 seconds
Started Jun 25 05:15:39 PM PDT 24
Finished Jun 25 05:15:50 PM PDT 24
Peak memory 198876 kb
Host smart-017e7345-bef8-40ad-8032-67cbaac7f52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278978920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.4278978920
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_perf.1264212256
Short name T612
Test name
Test status
Simulation time 17976399152 ps
CPU time 150.03 seconds
Started Jun 25 05:15:38 PM PDT 24
Finished Jun 25 05:18:10 PM PDT 24
Peak memory 199876 kb
Host smart-ffc8f9e3-66a7-4db4-8cf6-da3d23a70dbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1264212256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1264212256
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2528903626
Short name T1004
Test name
Test status
Simulation time 7175422582 ps
CPU time 50.46 seconds
Started Jun 25 05:15:37 PM PDT 24
Finished Jun 25 05:16:28 PM PDT 24
Peak memory 198868 kb
Host smart-eb0dec62-aa48-4118-bdb0-d311af12ab9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2528903626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2528903626
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.1429128325
Short name T960
Test name
Test status
Simulation time 16861302341 ps
CPU time 23.98 seconds
Started Jun 25 05:15:37 PM PDT 24
Finished Jun 25 05:16:03 PM PDT 24
Peak memory 199336 kb
Host smart-b044d427-ae49-46dc-a7bf-471e0162298e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429128325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1429128325
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.1105419136
Short name T22
Test name
Test status
Simulation time 3212411154 ps
CPU time 4.66 seconds
Started Jun 25 05:15:39 PM PDT 24
Finished Jun 25 05:15:45 PM PDT 24
Peak memory 195920 kb
Host smart-707bf153-7db9-4d8b-869a-c09ab62ddc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105419136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1105419136
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.2515325654
Short name T317
Test name
Test status
Simulation time 696947657 ps
CPU time 1.67 seconds
Started Jun 25 05:15:26 PM PDT 24
Finished Jun 25 05:15:29 PM PDT 24
Peak memory 199812 kb
Host smart-3c61e28e-713f-45e9-b47f-0b574da2cf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515325654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.2515325654
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.4252843298
Short name T760
Test name
Test status
Simulation time 4097106255 ps
CPU time 2.59 seconds
Started Jun 25 05:15:40 PM PDT 24
Finished Jun 25 05:15:44 PM PDT 24
Peak memory 199732 kb
Host smart-7006d3cc-38ad-4b99-a38d-63d342365fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252843298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.4252843298
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1185072453
Short name T514
Test name
Test status
Simulation time 110844738221 ps
CPU time 40.67 seconds
Started Jun 25 05:15:29 PM PDT 24
Finished Jun 25 05:16:11 PM PDT 24
Peak memory 199912 kb
Host smart-89e40aa6-c639-4827-863f-10d78b460335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185072453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1185072453
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.1530032058
Short name T571
Test name
Test status
Simulation time 179634762 ps
CPU time 0.54 seconds
Started Jun 25 05:15:36 PM PDT 24
Finished Jun 25 05:15:38 PM PDT 24
Peak memory 195504 kb
Host smart-33a16cb3-06e4-4d92-a313-72d5c8347c2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530032058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1530032058
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.4247951170
Short name T701
Test name
Test status
Simulation time 119488605964 ps
CPU time 40.86 seconds
Started Jun 25 05:15:37 PM PDT 24
Finished Jun 25 05:16:20 PM PDT 24
Peak memory 199800 kb
Host smart-1db0bc8f-dc41-48af-af00-fdff72deba5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247951170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.4247951170
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.4009381143
Short name T272
Test name
Test status
Simulation time 84424615885 ps
CPU time 112.8 seconds
Started Jun 25 05:15:38 PM PDT 24
Finished Jun 25 05:17:33 PM PDT 24
Peak memory 199828 kb
Host smart-bd4840a6-7269-425c-b510-13040c6c75b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009381143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.4009381143
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.1229499502
Short name T765
Test name
Test status
Simulation time 30142483277 ps
CPU time 29.63 seconds
Started Jun 25 05:15:37 PM PDT 24
Finished Jun 25 05:16:09 PM PDT 24
Peak memory 198828 kb
Host smart-9a031606-be99-47f7-b818-57e66206dab9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229499502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1229499502
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.2080868900
Short name T565
Test name
Test status
Simulation time 96740610355 ps
CPU time 358.27 seconds
Started Jun 25 05:15:41 PM PDT 24
Finished Jun 25 05:21:40 PM PDT 24
Peak memory 199764 kb
Host smart-90b1ec3b-aebd-4904-9deb-6208b78cd2e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2080868900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2080868900
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.2364985582
Short name T670
Test name
Test status
Simulation time 1223360537 ps
CPU time 3.92 seconds
Started Jun 25 05:15:40 PM PDT 24
Finished Jun 25 05:15:45 PM PDT 24
Peak memory 197784 kb
Host smart-9700c4f9-d8a9-4219-ac9e-802b0db80acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364985582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2364985582
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_perf.1115625206
Short name T290
Test name
Test status
Simulation time 5984915059 ps
CPU time 244.88 seconds
Started Jun 25 05:15:39 PM PDT 24
Finished Jun 25 05:19:45 PM PDT 24
Peak memory 199904 kb
Host smart-b1e9312c-d4de-47ad-bab4-4e26ecff4de2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1115625206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1115625206
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.2580806261
Short name T531
Test name
Test status
Simulation time 5701913190 ps
CPU time 25.82 seconds
Started Jun 25 05:15:42 PM PDT 24
Finished Jun 25 05:16:09 PM PDT 24
Peak memory 198692 kb
Host smart-33fd21ee-1ecb-4f2b-818c-da2e50c081a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2580806261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2580806261
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.2968432455
Short name T409
Test name
Test status
Simulation time 68100091382 ps
CPU time 100.1 seconds
Started Jun 25 05:15:41 PM PDT 24
Finished Jun 25 05:17:22 PM PDT 24
Peak memory 199840 kb
Host smart-ddae1007-4a6a-45b0-9e07-d35303f67af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968432455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.2968432455
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.733384967
Short name T547
Test name
Test status
Simulation time 4316624691 ps
CPU time 6.1 seconds
Started Jun 25 05:15:37 PM PDT 24
Finished Jun 25 05:15:45 PM PDT 24
Peak memory 196332 kb
Host smart-37a62ec2-c88c-42c6-8bfa-2a69098954b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733384967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.733384967
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.2739314669
Short name T770
Test name
Test status
Simulation time 888479698 ps
CPU time 6.36 seconds
Started Jun 25 05:15:38 PM PDT 24
Finished Jun 25 05:15:47 PM PDT 24
Peak memory 199172 kb
Host smart-08dfa4b5-bd88-4473-a53f-9d1adc0a7a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739314669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.2739314669
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.4278364310
Short name T631
Test name
Test status
Simulation time 512822100693 ps
CPU time 238.71 seconds
Started Jun 25 05:15:40 PM PDT 24
Finished Jun 25 05:19:40 PM PDT 24
Peak memory 199836 kb
Host smart-09a08dc1-d79a-4695-95bf-0ed70b3eb074
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278364310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.4278364310
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.1676209666
Short name T109
Test name
Test status
Simulation time 68607961603 ps
CPU time 990.65 seconds
Started Jun 25 05:15:37 PM PDT 24
Finished Jun 25 05:32:10 PM PDT 24
Peak memory 224676 kb
Host smart-7ff76ad1-25c5-45dc-a7c6-18e53d2cdf1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676209666 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.1676209666
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2016670727
Short name T775
Test name
Test status
Simulation time 6456054212 ps
CPU time 15.98 seconds
Started Jun 25 05:15:37 PM PDT 24
Finished Jun 25 05:15:55 PM PDT 24
Peak memory 199780 kb
Host smart-8f1c36ea-a5f6-4eba-b50b-677e2cda8da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016670727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2016670727
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.3405027809
Short name T658
Test name
Test status
Simulation time 47176414183 ps
CPU time 19.91 seconds
Started Jun 25 05:15:40 PM PDT 24
Finished Jun 25 05:16:01 PM PDT 24
Peak memory 199652 kb
Host smart-19c73ff8-dc88-4632-a03e-9e59f30830d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405027809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.3405027809
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.434834181
Short name T495
Test name
Test status
Simulation time 21933636 ps
CPU time 0.55 seconds
Started Jun 25 05:15:46 PM PDT 24
Finished Jun 25 05:15:48 PM PDT 24
Peak memory 194864 kb
Host smart-c76522f4-4ffa-4dca-87a1-e6a6bee8835c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434834181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.434834181
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1748341096
Short name T1027
Test name
Test status
Simulation time 33331752828 ps
CPU time 62.75 seconds
Started Jun 25 05:15:38 PM PDT 24
Finished Jun 25 05:16:42 PM PDT 24
Peak memory 199812 kb
Host smart-4526586b-dfa5-4527-9105-0125ee838b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748341096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1748341096
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.2555570943
Short name T822
Test name
Test status
Simulation time 19746301912 ps
CPU time 34.19 seconds
Started Jun 25 05:15:37 PM PDT 24
Finished Jun 25 05:16:13 PM PDT 24
Peak memory 199852 kb
Host smart-f9cbce6d-d46e-4a66-878a-00962cf95a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555570943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2555570943
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.35992219
Short name T752
Test name
Test status
Simulation time 89046626900 ps
CPU time 34.76 seconds
Started Jun 25 05:15:38 PM PDT 24
Finished Jun 25 05:16:15 PM PDT 24
Peak memory 199860 kb
Host smart-4a64e73e-6aba-48cb-952c-70c53fa9d2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35992219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.35992219
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.1141114519
Short name T105
Test name
Test status
Simulation time 81391949843 ps
CPU time 58.22 seconds
Started Jun 25 05:15:44 PM PDT 24
Finished Jun 25 05:16:43 PM PDT 24
Peak memory 199832 kb
Host smart-78b8cc9f-505f-4094-b2bc-403653c9b055
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141114519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1141114519
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.2164968924
Short name T453
Test name
Test status
Simulation time 58588067614 ps
CPU time 139.44 seconds
Started Jun 25 05:15:48 PM PDT 24
Finished Jun 25 05:18:09 PM PDT 24
Peak memory 199868 kb
Host smart-53a71884-6095-4bf2-a24a-fc5784bc5161
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2164968924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2164968924
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1905794010
Short name T672
Test name
Test status
Simulation time 4301204995 ps
CPU time 5.05 seconds
Started Jun 25 05:15:48 PM PDT 24
Finished Jun 25 05:15:55 PM PDT 24
Peak memory 199744 kb
Host smart-c4f17c84-e8b9-428d-8654-a480bfb3c94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905794010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1905794010
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_perf.1327949787
Short name T386
Test name
Test status
Simulation time 10162213013 ps
CPU time 128.44 seconds
Started Jun 25 05:15:44 PM PDT 24
Finished Jun 25 05:17:53 PM PDT 24
Peak memory 199836 kb
Host smart-d5ad9525-d3c1-4684-b764-98da791ca1ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1327949787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.1327949787
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.3432758269
Short name T677
Test name
Test status
Simulation time 2426806735 ps
CPU time 17.77 seconds
Started Jun 25 05:15:45 PM PDT 24
Finished Jun 25 05:16:04 PM PDT 24
Peak memory 197996 kb
Host smart-de4ab40c-7530-4dc4-b056-e450b5e67780
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3432758269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.3432758269
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.1445720201
Short name T7
Test name
Test status
Simulation time 137936099213 ps
CPU time 24.51 seconds
Started Jun 25 05:15:47 PM PDT 24
Finished Jun 25 05:16:13 PM PDT 24
Peak memory 199768 kb
Host smart-61dedd45-4c94-4621-81d1-15152c8116d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445720201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1445720201
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.2525024643
Short name T508
Test name
Test status
Simulation time 3551962128 ps
CPU time 2.11 seconds
Started Jun 25 05:15:45 PM PDT 24
Finished Jun 25 05:15:48 PM PDT 24
Peak memory 196136 kb
Host smart-956ccbc3-b4b2-44c4-a413-7fcf55328ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525024643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.2525024643
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.1067608476
Short name T421
Test name
Test status
Simulation time 11093148797 ps
CPU time 43.85 seconds
Started Jun 25 05:15:37 PM PDT 24
Finished Jun 25 05:16:23 PM PDT 24
Peak memory 199488 kb
Host smart-a94ff7c2-dec7-4948-b788-eeba47d31aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067608476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.1067608476
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.249258062
Short name T971
Test name
Test status
Simulation time 69683186337 ps
CPU time 853.63 seconds
Started Jun 25 05:15:45 PM PDT 24
Finished Jun 25 05:29:59 PM PDT 24
Peak memory 199892 kb
Host smart-fa386b3b-745b-4ae3-ab58-4468d69aae2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249258062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.249258062
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.3341576632
Short name T593
Test name
Test status
Simulation time 288304444 ps
CPU time 1.35 seconds
Started Jun 25 05:15:45 PM PDT 24
Finished Jun 25 05:15:47 PM PDT 24
Peak memory 198480 kb
Host smart-01bd535b-446e-4118-84c9-8a5ef81b33fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341576632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3341576632
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.2003766459
Short name T921
Test name
Test status
Simulation time 141782674096 ps
CPU time 43.8 seconds
Started Jun 25 05:15:38 PM PDT 24
Finished Jun 25 05:16:23 PM PDT 24
Peak memory 199932 kb
Host smart-821d77d3-a1b7-4a0b-ad9b-96e8d188da74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003766459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2003766459
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.2979614058
Short name T790
Test name
Test status
Simulation time 26070425 ps
CPU time 0.55 seconds
Started Jun 25 05:15:49 PM PDT 24
Finished Jun 25 05:15:51 PM PDT 24
Peak memory 195224 kb
Host smart-72c92512-6b94-4426-85f5-996eddf6f8b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979614058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2979614058
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.2775620873
Short name T295
Test name
Test status
Simulation time 27710987653 ps
CPU time 24.01 seconds
Started Jun 25 05:15:47 PM PDT 24
Finished Jun 25 05:16:13 PM PDT 24
Peak memory 199844 kb
Host smart-d3ffb8d5-1b8e-4b6a-85d4-574067c9fd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775620873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.2775620873
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.2413387953
Short name T809
Test name
Test status
Simulation time 39753714046 ps
CPU time 30.9 seconds
Started Jun 25 05:15:47 PM PDT 24
Finished Jun 25 05:16:20 PM PDT 24
Peak memory 199884 kb
Host smart-41953382-6961-4ebb-b084-34e63243fa28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413387953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2413387953
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.4213164721
Short name T978
Test name
Test status
Simulation time 12175712432 ps
CPU time 21.25 seconds
Started Jun 25 05:15:47 PM PDT 24
Finished Jun 25 05:16:10 PM PDT 24
Peak memory 199884 kb
Host smart-77509f88-25e2-4d58-b293-a9f3f3c24c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213164721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.4213164721
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.668129606
Short name T1051
Test name
Test status
Simulation time 72071349758 ps
CPU time 57.88 seconds
Started Jun 25 05:15:48 PM PDT 24
Finished Jun 25 05:16:48 PM PDT 24
Peak memory 199348 kb
Host smart-8d484e23-46bc-4fba-bda0-37c569c323c7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668129606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.668129606
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.335092043
Short name T491
Test name
Test status
Simulation time 75079563299 ps
CPU time 207.83 seconds
Started Jun 25 05:15:47 PM PDT 24
Finished Jun 25 05:19:16 PM PDT 24
Peak memory 199800 kb
Host smart-7599e3e3-b41c-4545-85dd-f480936335e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=335092043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.335092043
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.3533358781
Short name T365
Test name
Test status
Simulation time 9748491039 ps
CPU time 18.13 seconds
Started Jun 25 05:15:48 PM PDT 24
Finished Jun 25 05:16:07 PM PDT 24
Peak memory 199312 kb
Host smart-b71db48c-69e1-4077-a11e-f24bfc19110a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533358781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.3533358781
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_perf.244150658
Short name T1072
Test name
Test status
Simulation time 9779316306 ps
CPU time 313.78 seconds
Started Jun 25 05:15:49 PM PDT 24
Finished Jun 25 05:21:04 PM PDT 24
Peak memory 199816 kb
Host smart-894775ac-b1d9-470b-b43f-e8578442226b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=244150658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.244150658
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.614949482
Short name T703
Test name
Test status
Simulation time 3971208528 ps
CPU time 6.42 seconds
Started Jun 25 05:15:45 PM PDT 24
Finished Jun 25 05:15:53 PM PDT 24
Peak memory 198768 kb
Host smart-1004f112-991f-450f-ba60-7058df414a9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=614949482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.614949482
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3747794462
Short name T777
Test name
Test status
Simulation time 24546674660 ps
CPU time 11.41 seconds
Started Jun 25 05:15:48 PM PDT 24
Finished Jun 25 05:16:01 PM PDT 24
Peak memory 199832 kb
Host smart-6d1951c8-73eb-4b98-b896-86e7d29fa65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747794462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3747794462
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.3617754452
Short name T679
Test name
Test status
Simulation time 24696006689 ps
CPU time 10.23 seconds
Started Jun 25 05:15:45 PM PDT 24
Finished Jun 25 05:15:57 PM PDT 24
Peak memory 196324 kb
Host smart-76f4bb1c-0489-4ca7-940a-c1f4ecdc225f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617754452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3617754452
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.21949868
Short name T1009
Test name
Test status
Simulation time 461646148 ps
CPU time 1.2 seconds
Started Jun 25 05:15:44 PM PDT 24
Finished Jun 25 05:15:46 PM PDT 24
Peak memory 198636 kb
Host smart-086759a8-5211-4b4c-8a70-bec784298b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21949868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.21949868
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.2544484408
Short name T578
Test name
Test status
Simulation time 231445128191 ps
CPU time 98.87 seconds
Started Jun 25 05:15:48 PM PDT 24
Finished Jun 25 05:17:28 PM PDT 24
Peak memory 199748 kb
Host smart-974b51d9-294c-451f-9b00-9a9b5aacca50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544484408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2544484408
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.318963111
Short name T990
Test name
Test status
Simulation time 450361999 ps
CPU time 2.46 seconds
Started Jun 25 05:15:45 PM PDT 24
Finished Jun 25 05:15:49 PM PDT 24
Peak memory 198620 kb
Host smart-541a0b57-e004-426f-acca-4dac3ed35a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318963111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.318963111
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2968280259
Short name T412
Test name
Test status
Simulation time 144374144454 ps
CPU time 135.89 seconds
Started Jun 25 05:15:45 PM PDT 24
Finished Jun 25 05:18:02 PM PDT 24
Peak memory 199904 kb
Host smart-631fc75a-bd2e-4087-9df8-e7714164cb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968280259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2968280259
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.1693405384
Short name T554
Test name
Test status
Simulation time 33890753 ps
CPU time 0.62 seconds
Started Jun 25 05:12:44 PM PDT 24
Finished Jun 25 05:12:46 PM PDT 24
Peak memory 194128 kb
Host smart-7905ce2d-7140-4a28-b3de-8cf4225b2ed4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693405384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.1693405384
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.3939584130
Short name T832
Test name
Test status
Simulation time 104448825229 ps
CPU time 291.22 seconds
Started Jun 25 05:12:46 PM PDT 24
Finished Jun 25 05:17:39 PM PDT 24
Peak memory 199884 kb
Host smart-ec2ba7f1-451e-465d-8b5e-84c5a8ff5fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939584130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.3939584130
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.387688819
Short name T549
Test name
Test status
Simulation time 104280102416 ps
CPU time 53.56 seconds
Started Jun 25 05:12:43 PM PDT 24
Finished Jun 25 05:13:38 PM PDT 24
Peak memory 199828 kb
Host smart-60853d3b-d55b-4bb1-bc4c-79cf847b078c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387688819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.387688819
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.2924592559
Short name T651
Test name
Test status
Simulation time 25450436285 ps
CPU time 10.28 seconds
Started Jun 25 05:12:44 PM PDT 24
Finished Jun 25 05:12:56 PM PDT 24
Peak memory 199628 kb
Host smart-acd6f299-5f5d-4fef-9836-6005d312886a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924592559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.2924592559
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.3769047552
Short name T1059
Test name
Test status
Simulation time 5354117687 ps
CPU time 6.71 seconds
Started Jun 25 05:12:42 PM PDT 24
Finished Jun 25 05:12:51 PM PDT 24
Peak memory 199740 kb
Host smart-738cb025-680b-4a2e-a8a5-53655b32340a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769047552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3769047552
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.1034632265
Short name T1033
Test name
Test status
Simulation time 126148865537 ps
CPU time 1300.89 seconds
Started Jun 25 05:12:42 PM PDT 24
Finished Jun 25 05:34:25 PM PDT 24
Peak memory 199768 kb
Host smart-8ebf528c-70a4-41e9-a43f-50b698ffe8f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1034632265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1034632265
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.827380623
Short name T618
Test name
Test status
Simulation time 5943877660 ps
CPU time 10.74 seconds
Started Jun 25 05:12:43 PM PDT 24
Finished Jun 25 05:12:56 PM PDT 24
Peak memory 199808 kb
Host smart-2979c3db-9e06-4919-9af3-47948466511d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827380623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.827380623
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_perf.3214869406
Short name T849
Test name
Test status
Simulation time 16576820186 ps
CPU time 1015.98 seconds
Started Jun 25 05:12:43 PM PDT 24
Finished Jun 25 05:29:41 PM PDT 24
Peak memory 199744 kb
Host smart-2259d284-07dd-4a1c-a3f6-cfbe31a41729
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3214869406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3214869406
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1384697915
Short name T19
Test name
Test status
Simulation time 2425972903 ps
CPU time 6.82 seconds
Started Jun 25 05:12:44 PM PDT 24
Finished Jun 25 05:12:53 PM PDT 24
Peak memory 197968 kb
Host smart-0bbf156e-270c-43fe-ad31-127b89ae2c50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1384697915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1384697915
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.2011409741
Short name T986
Test name
Test status
Simulation time 84142199509 ps
CPU time 113.44 seconds
Started Jun 25 05:12:42 PM PDT 24
Finished Jun 25 05:14:37 PM PDT 24
Peak memory 199868 kb
Host smart-2dae7035-d882-40e3-9dc3-4747a9205154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011409741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.2011409741
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1647091215
Short name T875
Test name
Test status
Simulation time 37547680730 ps
CPU time 59.61 seconds
Started Jun 25 05:12:48 PM PDT 24
Finished Jun 25 05:13:48 PM PDT 24
Peak memory 196636 kb
Host smart-cf5f35dc-414e-42c4-9636-01d347b6851a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647091215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1647091215
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.48732288
Short name T653
Test name
Test status
Simulation time 5349615661 ps
CPU time 25.09 seconds
Started Jun 25 05:12:46 PM PDT 24
Finished Jun 25 05:13:13 PM PDT 24
Peak memory 199848 kb
Host smart-13ad858e-aa48-4b56-a727-97bbdba39aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48732288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.48732288
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.240643301
Short name T452
Test name
Test status
Simulation time 932529651 ps
CPU time 1.75 seconds
Started Jun 25 05:12:45 PM PDT 24
Finished Jun 25 05:12:49 PM PDT 24
Peak memory 198176 kb
Host smart-8171d0ef-a909-4bff-89ce-7125a7478c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240643301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.240643301
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.3179923779
Short name T810
Test name
Test status
Simulation time 70593578705 ps
CPU time 76.33 seconds
Started Jun 25 05:12:46 PM PDT 24
Finished Jun 25 05:14:04 PM PDT 24
Peak memory 199868 kb
Host smart-96b3d300-96aa-49ed-af73-3591005cf743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179923779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.3179923779
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.31243171
Short name T3
Test name
Test status
Simulation time 132266783708 ps
CPU time 186.36 seconds
Started Jun 25 05:15:47 PM PDT 24
Finished Jun 25 05:18:54 PM PDT 24
Peak memory 200176 kb
Host smart-58b0afc0-6d68-4825-a980-1b9ca036d5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31243171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.31243171
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.2733432030
Short name T417
Test name
Test status
Simulation time 9865978882 ps
CPU time 15.12 seconds
Started Jun 25 05:15:47 PM PDT 24
Finished Jun 25 05:16:03 PM PDT 24
Peak memory 199836 kb
Host smart-6e497d1c-6091-4794-a551-5073816a4360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733432030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2733432030
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.3498071996
Short name T794
Test name
Test status
Simulation time 19168677720 ps
CPU time 221.85 seconds
Started Jun 25 05:15:46 PM PDT 24
Finished Jun 25 05:19:29 PM PDT 24
Peak memory 215676 kb
Host smart-72298c17-e2f9-4fd0-97ef-6d58489dc18e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498071996 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.3498071996
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.3915908409
Short name T953
Test name
Test status
Simulation time 123774380579 ps
CPU time 165.44 seconds
Started Jun 25 05:15:48 PM PDT 24
Finished Jun 25 05:18:35 PM PDT 24
Peak memory 199800 kb
Host smart-28e63628-44a4-42f6-aff4-33019329bd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915908409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3915908409
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.307148425
Short name T842
Test name
Test status
Simulation time 52768151922 ps
CPU time 201.44 seconds
Started Jun 25 05:15:47 PM PDT 24
Finished Jun 25 05:19:10 PM PDT 24
Peak memory 208148 kb
Host smart-83e70cde-a88e-4e31-a50a-24d2d6fac81b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307148425 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.307148425
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1183026790
Short name T584
Test name
Test status
Simulation time 34766425749 ps
CPU time 50.75 seconds
Started Jun 25 05:15:47 PM PDT 24
Finished Jun 25 05:16:40 PM PDT 24
Peak memory 199736 kb
Host smart-b5f70287-6413-45db-8da0-cfd901c0607c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183026790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1183026790
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.2121013776
Short name T899
Test name
Test status
Simulation time 20028601491 ps
CPU time 249.71 seconds
Started Jun 25 05:15:52 PM PDT 24
Finished Jun 25 05:20:02 PM PDT 24
Peak memory 215424 kb
Host smart-430bd4e6-2406-4b95-a3ce-f960155aaf1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121013776 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.2121013776
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.1775897444
Short name T781
Test name
Test status
Simulation time 84588378612 ps
CPU time 35.57 seconds
Started Jun 25 05:16:00 PM PDT 24
Finished Jun 25 05:16:37 PM PDT 24
Peak memory 199652 kb
Host smart-0accbd95-5973-4b01-aac2-ee527cb523d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775897444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1775897444
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.1792168734
Short name T684
Test name
Test status
Simulation time 73547354367 ps
CPU time 398.11 seconds
Started Jun 25 05:15:53 PM PDT 24
Finished Jun 25 05:22:32 PM PDT 24
Peak memory 216464 kb
Host smart-ad3d1164-62bb-49d1-8909-47892e2079b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792168734 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.1792168734
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.2111690429
Short name T708
Test name
Test status
Simulation time 21984228335 ps
CPU time 35.96 seconds
Started Jun 25 05:15:54 PM PDT 24
Finished Jun 25 05:16:32 PM PDT 24
Peak memory 199748 kb
Host smart-6965ef68-aa26-4e15-8313-06c446f9118f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111690429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.2111690429
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.1516093685
Short name T94
Test name
Test status
Simulation time 183301267573 ps
CPU time 504.53 seconds
Started Jun 25 05:15:53 PM PDT 24
Finished Jun 25 05:24:19 PM PDT 24
Peak memory 216408 kb
Host smart-5b7c23a1-d270-4a77-b6ac-33baca91d8cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516093685 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.1516093685
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.1170571013
Short name T505
Test name
Test status
Simulation time 41745728882 ps
CPU time 80.65 seconds
Started Jun 25 05:15:56 PM PDT 24
Finished Jun 25 05:17:18 PM PDT 24
Peak memory 199768 kb
Host smart-0bf5a5fe-e663-438c-b089-23c822626e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170571013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.1170571013
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2648664737
Short name T33
Test name
Test status
Simulation time 7411864335 ps
CPU time 18.98 seconds
Started Jun 25 05:15:56 PM PDT 24
Finished Jun 25 05:16:17 PM PDT 24
Peak memory 216204 kb
Host smart-b9cc2b1d-65c3-4a08-abb5-5615927e0fa9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648664737 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2648664737
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.874765825
Short name T99
Test name
Test status
Simulation time 84832536947 ps
CPU time 39.04 seconds
Started Jun 25 05:16:02 PM PDT 24
Finished Jun 25 05:16:42 PM PDT 24
Peak memory 199764 kb
Host smart-e83f341d-7b5e-4cf4-88d0-15dcc00fa8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874765825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.874765825
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.1135519351
Short name T214
Test name
Test status
Simulation time 541294427288 ps
CPU time 1563.06 seconds
Started Jun 25 05:15:54 PM PDT 24
Finished Jun 25 05:41:59 PM PDT 24
Peak memory 232476 kb
Host smart-55775cbf-4da3-43f4-bf02-5dce1d5f43f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135519351 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.1135519351
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.411752596
Short name T574
Test name
Test status
Simulation time 19675417394 ps
CPU time 33.78 seconds
Started Jun 25 05:15:55 PM PDT 24
Finished Jun 25 05:16:30 PM PDT 24
Peak memory 199900 kb
Host smart-0ef345d1-4b66-4cd4-8b36-7301e1dee0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411752596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.411752596
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.2479325494
Short name T15
Test name
Test status
Simulation time 39609023868 ps
CPU time 232.91 seconds
Started Jun 25 05:15:54 PM PDT 24
Finished Jun 25 05:19:48 PM PDT 24
Peak memory 216372 kb
Host smart-61a8196c-4457-47db-938c-4ac407c5bf90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479325494 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.2479325494
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.1998368605
Short name T885
Test name
Test status
Simulation time 30974143 ps
CPU time 0.55 seconds
Started Jun 25 05:12:58 PM PDT 24
Finished Jun 25 05:13:01 PM PDT 24
Peak memory 194128 kb
Host smart-ec919332-530d-460c-8ba2-6773f5f3dc15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998368605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.1998368605
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.3677777541
Short name T98
Test name
Test status
Simulation time 16020893968 ps
CPU time 24.42 seconds
Started Jun 25 05:12:43 PM PDT 24
Finished Jun 25 05:13:10 PM PDT 24
Peak memory 199916 kb
Host smart-fdf6a8aa-045f-49fc-b437-7f538f359478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677777541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3677777541
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.4145235293
Short name T1021
Test name
Test status
Simulation time 49714918656 ps
CPU time 76.63 seconds
Started Jun 25 05:12:46 PM PDT 24
Finished Jun 25 05:14:04 PM PDT 24
Peak memory 199820 kb
Host smart-ec416743-0c9a-453d-858b-053af224f19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145235293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.4145235293
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.3013020819
Short name T116
Test name
Test status
Simulation time 24467718755 ps
CPU time 52.35 seconds
Started Jun 25 05:12:44 PM PDT 24
Finished Jun 25 05:13:39 PM PDT 24
Peak memory 199920 kb
Host smart-a34fab75-2c70-4fa1-a053-170172ad886b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013020819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.3013020819
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.1422073200
Short name T462
Test name
Test status
Simulation time 123387718940 ps
CPU time 189.24 seconds
Started Jun 25 05:12:45 PM PDT 24
Finished Jun 25 05:15:56 PM PDT 24
Peak memory 199884 kb
Host smart-ca08e13a-ba1a-4075-929d-264854fa7d79
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422073200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1422073200
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.4120445590
Short name T813
Test name
Test status
Simulation time 83765634901 ps
CPU time 102.75 seconds
Started Jun 25 05:13:00 PM PDT 24
Finished Jun 25 05:14:45 PM PDT 24
Peak memory 199888 kb
Host smart-6f444e8b-35aa-480f-aea5-bb0ed2fab9a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4120445590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.4120445590
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.3160456369
Short name T351
Test name
Test status
Simulation time 6372851246 ps
CPU time 5.65 seconds
Started Jun 25 05:12:45 PM PDT 24
Finished Jun 25 05:12:52 PM PDT 24
Peak memory 199792 kb
Host smart-6a746056-84c0-4f34-8664-27578ec9e249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160456369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.3160456369
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_perf.2061366079
Short name T1044
Test name
Test status
Simulation time 16737571111 ps
CPU time 197.79 seconds
Started Jun 25 05:12:42 PM PDT 24
Finished Jun 25 05:16:02 PM PDT 24
Peak memory 199804 kb
Host smart-5078042e-9d44-4706-81ed-44cca9ef55e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2061366079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.2061366079
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.4072041273
Short name T710
Test name
Test status
Simulation time 3566211899 ps
CPU time 26.72 seconds
Started Jun 25 05:12:46 PM PDT 24
Finished Jun 25 05:13:15 PM PDT 24
Peak memory 198116 kb
Host smart-02556a72-fab3-477b-8300-563f257292d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4072041273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.4072041273
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1436041500
Short name T1081
Test name
Test status
Simulation time 86032097809 ps
CPU time 30.71 seconds
Started Jun 25 05:12:45 PM PDT 24
Finished Jun 25 05:13:18 PM PDT 24
Peak memory 199904 kb
Host smart-1851fcb4-f30d-4313-b8c5-1c9568ad378a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436041500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1436041500
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.2662486647
Short name T1076
Test name
Test status
Simulation time 5298649836 ps
CPU time 8.71 seconds
Started Jun 25 05:12:42 PM PDT 24
Finished Jun 25 05:12:53 PM PDT 24
Peak memory 195944 kb
Host smart-6730bae2-1d7a-47ed-aa3d-7f0650463bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662486647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2662486647
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.1370235181
Short name T966
Test name
Test status
Simulation time 5866262906 ps
CPU time 18.66 seconds
Started Jun 25 05:12:44 PM PDT 24
Finished Jun 25 05:13:05 PM PDT 24
Peak memory 199260 kb
Host smart-1587c6fd-4c35-4fcf-8fb8-afdbcd1ffdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370235181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.1370235181
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.2688405844
Short name T457
Test name
Test status
Simulation time 208133882178 ps
CPU time 239.33 seconds
Started Jun 25 05:12:56 PM PDT 24
Finished Jun 25 05:16:57 PM PDT 24
Peak memory 199880 kb
Host smart-8a39bfdf-6742-4159-bb5c-9ec7eb42dc9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688405844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2688405844
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.2158819896
Short name T552
Test name
Test status
Simulation time 208803525111 ps
CPU time 530.69 seconds
Started Jun 25 05:12:59 PM PDT 24
Finished Jun 25 05:21:52 PM PDT 24
Peak memory 216432 kb
Host smart-3033ba8f-7fbd-458d-a6e5-f01defd4df51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158819896 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.2158819896
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.98519935
Short name T331
Test name
Test status
Simulation time 7981621156 ps
CPU time 8.33 seconds
Started Jun 25 05:12:43 PM PDT 24
Finished Jun 25 05:12:54 PM PDT 24
Peak memory 199916 kb
Host smart-42751fce-3a66-4b43-baae-a98b27379d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98519935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.98519935
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.2374311998
Short name T282
Test name
Test status
Simulation time 72254597212 ps
CPU time 94.45 seconds
Started Jun 25 05:12:45 PM PDT 24
Finished Jun 25 05:14:21 PM PDT 24
Peak memory 199820 kb
Host smart-01fd817d-d3cf-4c7a-bd21-0b7e1445977a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374311998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2374311998
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.475086838
Short name T897
Test name
Test status
Simulation time 92101960286 ps
CPU time 167.12 seconds
Started Jun 25 05:15:53 PM PDT 24
Finished Jun 25 05:18:41 PM PDT 24
Peak memory 199904 kb
Host smart-5b7f813c-1904-47ff-b9ed-22ecff03b530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475086838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.475086838
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.1452926941
Short name T588
Test name
Test status
Simulation time 216425058649 ps
CPU time 18.38 seconds
Started Jun 25 05:15:54 PM PDT 24
Finished Jun 25 05:16:14 PM PDT 24
Peak memory 199644 kb
Host smart-f2cb891e-de90-4a21-ba4d-b3c259eb99db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452926941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1452926941
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.3038339995
Short name T242
Test name
Test status
Simulation time 194416126843 ps
CPU time 178.48 seconds
Started Jun 25 05:15:54 PM PDT 24
Finished Jun 25 05:18:55 PM PDT 24
Peak memory 216440 kb
Host smart-478574ca-79b3-4a8b-9d4c-219b637819fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038339995 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.3038339995
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.3577193920
Short name T945
Test name
Test status
Simulation time 95434511397 ps
CPU time 139.35 seconds
Started Jun 25 05:15:53 PM PDT 24
Finished Jun 25 05:18:13 PM PDT 24
Peak memory 199896 kb
Host smart-430c5ef9-2b11-413a-8ad6-12a0e391e4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577193920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3577193920
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.2763700688
Short name T1066
Test name
Test status
Simulation time 286482463405 ps
CPU time 460.29 seconds
Started Jun 25 05:15:54 PM PDT 24
Finished Jun 25 05:23:36 PM PDT 24
Peak memory 216392 kb
Host smart-870a8640-a03e-4e26-bb2d-204d5e2b1233
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763700688 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.2763700688
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.494898542
Short name T180
Test name
Test status
Simulation time 21709691965 ps
CPU time 51.47 seconds
Started Jun 25 05:16:02 PM PDT 24
Finished Jun 25 05:16:55 PM PDT 24
Peak memory 199312 kb
Host smart-944e620f-741c-4fac-9930-28edc341c8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494898542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.494898542
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.976392640
Short name T985
Test name
Test status
Simulation time 64468693167 ps
CPU time 44.02 seconds
Started Jun 25 05:16:02 PM PDT 24
Finished Jun 25 05:16:47 PM PDT 24
Peak memory 199796 kb
Host smart-5ffa57ea-6649-433e-a665-06ec10ab64a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976392640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.976392640
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.2546164146
Short name T951
Test name
Test status
Simulation time 177217184290 ps
CPU time 66.42 seconds
Started Jun 25 05:15:56 PM PDT 24
Finished Jun 25 05:17:03 PM PDT 24
Peak memory 199756 kb
Host smart-779238c3-1b6c-4f3a-a15c-ef82dbd961b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546164146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2546164146
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.3042346530
Short name T216
Test name
Test status
Simulation time 17524143891 ps
CPU time 45.6 seconds
Started Jun 25 05:15:55 PM PDT 24
Finished Jun 25 05:16:42 PM PDT 24
Peak memory 199924 kb
Host smart-d023c7c3-9fa9-4d2c-8f34-e23ede50718c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042346530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3042346530
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.751794214
Short name T1049
Test name
Test status
Simulation time 280342641200 ps
CPU time 474.79 seconds
Started Jun 25 05:15:55 PM PDT 24
Finished Jun 25 05:23:51 PM PDT 24
Peak memory 216472 kb
Host smart-00a2df0f-59c2-40ad-ab45-4f34c9aa8194
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751794214 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.751794214
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.1179807494
Short name T344
Test name
Test status
Simulation time 24772368979 ps
CPU time 34.78 seconds
Started Jun 25 05:15:55 PM PDT 24
Finished Jun 25 05:16:31 PM PDT 24
Peak memory 199848 kb
Host smart-590ff914-6202-4511-a376-4325012a01cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179807494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1179807494
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.1174328441
Short name T57
Test name
Test status
Simulation time 92862334768 ps
CPU time 2529.92 seconds
Started Jun 25 05:15:55 PM PDT 24
Finished Jun 25 05:58:06 PM PDT 24
Peak memory 216448 kb
Host smart-99f4d989-14ce-4f67-a3e4-cb89e38d3968
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174328441 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.1174328441
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.549711439
Short name T208
Test name
Test status
Simulation time 102071202144 ps
CPU time 39.75 seconds
Started Jun 25 05:15:54 PM PDT 24
Finished Jun 25 05:16:35 PM PDT 24
Peak memory 199928 kb
Host smart-1298e3bd-520c-43ec-a58a-abe8b4ec65b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549711439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.549711439
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.2544089536
Short name T110
Test name
Test status
Simulation time 362326444077 ps
CPU time 943.84 seconds
Started Jun 25 05:16:13 PM PDT 24
Finished Jun 25 05:31:57 PM PDT 24
Peak memory 216308 kb
Host smart-985f5500-1450-4344-887e-3406163198c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544089536 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.2544089536
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.3376920231
Short name T816
Test name
Test status
Simulation time 27785245369 ps
CPU time 20.8 seconds
Started Jun 25 05:16:01 PM PDT 24
Finished Jun 25 05:16:23 PM PDT 24
Peak memory 199844 kb
Host smart-ed48b352-a6b3-4c4d-af11-49d04ae764f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376920231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3376920231
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.24567807
Short name T732
Test name
Test status
Simulation time 25923911319 ps
CPU time 401.91 seconds
Started Jun 25 05:16:02 PM PDT 24
Finished Jun 25 05:22:46 PM PDT 24
Peak memory 208276 kb
Host smart-943ff000-ecb3-4b39-832a-b5dffa4838f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24567807 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.24567807
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.2883270084
Short name T358
Test name
Test status
Simulation time 11726948 ps
CPU time 0.57 seconds
Started Jun 25 05:12:57 PM PDT 24
Finished Jun 25 05:13:00 PM PDT 24
Peak memory 195220 kb
Host smart-a1bf2b25-b244-4e51-ab55-1130120c54d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883270084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2883270084
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.1760609842
Short name T274
Test name
Test status
Simulation time 29700360143 ps
CPU time 27.27 seconds
Started Jun 25 05:12:55 PM PDT 24
Finished Jun 25 05:13:24 PM PDT 24
Peak memory 199800 kb
Host smart-d849479b-479a-4ff9-8971-d3f2d2cedb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760609842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.1760609842
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.1786075663
Short name T866
Test name
Test status
Simulation time 176562360095 ps
CPU time 67.48 seconds
Started Jun 25 05:12:53 PM PDT 24
Finished Jun 25 05:14:01 PM PDT 24
Peak memory 199788 kb
Host smart-98d91bfa-76ed-4228-aed9-559e6429cdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786075663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1786075663
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.584226138
Short name T1086
Test name
Test status
Simulation time 31247424895 ps
CPU time 55.91 seconds
Started Jun 25 05:12:55 PM PDT 24
Finished Jun 25 05:13:52 PM PDT 24
Peak memory 199864 kb
Host smart-196c9716-c007-4a7c-96c7-686da4b0070a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584226138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.584226138
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.331648021
Short name T511
Test name
Test status
Simulation time 414565150114 ps
CPU time 401.06 seconds
Started Jun 25 05:12:55 PM PDT 24
Finished Jun 25 05:19:38 PM PDT 24
Peak memory 199232 kb
Host smart-4a10ab86-e7de-4729-82d0-99d2867cfe16
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331648021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.331648021
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.1300107670
Short name T372
Test name
Test status
Simulation time 107999164561 ps
CPU time 542.87 seconds
Started Jun 25 05:12:57 PM PDT 24
Finished Jun 25 05:22:02 PM PDT 24
Peak memory 199892 kb
Host smart-7c6a7e84-5e58-4d98-93f3-73f14de10dc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1300107670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.1300107670
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.2890552
Short name T485
Test name
Test status
Simulation time 5995823820 ps
CPU time 14.67 seconds
Started Jun 25 05:12:57 PM PDT 24
Finished Jun 25 05:13:13 PM PDT 24
Peak memory 198804 kb
Host smart-92f3739c-1b02-4c14-b061-663d2cbe494b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2890552
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_perf.2167074663
Short name T286
Test name
Test status
Simulation time 11301004220 ps
CPU time 579.49 seconds
Started Jun 25 05:12:56 PM PDT 24
Finished Jun 25 05:22:38 PM PDT 24
Peak memory 199824 kb
Host smart-0e3204f5-b0b9-4fcd-b0d4-d814d8e47614
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2167074663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2167074663
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.918718186
Short name T18
Test name
Test status
Simulation time 4743093626 ps
CPU time 17.57 seconds
Started Jun 25 05:12:55 PM PDT 24
Finished Jun 25 05:13:13 PM PDT 24
Peak memory 198192 kb
Host smart-88d1ca6a-36d7-4284-b8bf-6157b72195c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=918718186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.918718186
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.3585952886
Short name T617
Test name
Test status
Simulation time 105320977129 ps
CPU time 79.46 seconds
Started Jun 25 05:12:57 PM PDT 24
Finished Jun 25 05:14:18 PM PDT 24
Peak memory 199596 kb
Host smart-49a72f56-f154-4d08-89b7-8b915a07bb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585952886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3585952886
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3091423511
Short name T271
Test name
Test status
Simulation time 3917663934 ps
CPU time 6.58 seconds
Started Jun 25 05:12:59 PM PDT 24
Finished Jun 25 05:13:08 PM PDT 24
Peak memory 196348 kb
Host smart-e30bfd93-2146-4055-bbbe-6459757901a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091423511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3091423511
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.1925071910
Short name T302
Test name
Test status
Simulation time 11110807303 ps
CPU time 59.33 seconds
Started Jun 25 05:12:53 PM PDT 24
Finished Jun 25 05:13:53 PM PDT 24
Peak memory 199720 kb
Host smart-f8911182-e122-407c-9aff-4e8257b61e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925071910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1925071910
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.715414088
Short name T825
Test name
Test status
Simulation time 829260327 ps
CPU time 1.62 seconds
Started Jun 25 05:12:59 PM PDT 24
Finished Jun 25 05:13:03 PM PDT 24
Peak memory 198332 kb
Host smart-1b560a06-ee8d-4fae-803f-a0f67d65f1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715414088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.715414088
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.3415203857
Short name T480
Test name
Test status
Simulation time 542057028 ps
CPU time 1.15 seconds
Started Jun 25 05:12:55 PM PDT 24
Finished Jun 25 05:12:57 PM PDT 24
Peak memory 196636 kb
Host smart-e1ae1ff8-57f8-41a9-8f7f-c369741717a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415203857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.3415203857
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2059144868
Short name T783
Test name
Test status
Simulation time 15594218628 ps
CPU time 7.18 seconds
Started Jun 25 05:16:01 PM PDT 24
Finished Jun 25 05:16:09 PM PDT 24
Peak memory 199624 kb
Host smart-81f307c5-c13a-47c2-9e96-18c80f8b3ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059144868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2059144868
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.343432192
Short name T197
Test name
Test status
Simulation time 141654096717 ps
CPU time 214.47 seconds
Started Jun 25 05:16:03 PM PDT 24
Finished Jun 25 05:19:38 PM PDT 24
Peak memory 199848 kb
Host smart-a66c6cd8-5161-4fd8-9edd-699b2da214c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343432192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.343432192
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.1833628256
Short name T52
Test name
Test status
Simulation time 155088116348 ps
CPU time 450.07 seconds
Started Jun 25 05:16:01 PM PDT 24
Finished Jun 25 05:23:33 PM PDT 24
Peak memory 212240 kb
Host smart-40fcd3a6-c4ab-417e-a972-093b3be6aad6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833628256 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.1833628256
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.3703332268
Short name T844
Test name
Test status
Simulation time 124820232102 ps
CPU time 444.04 seconds
Started Jun 25 05:16:02 PM PDT 24
Finished Jun 25 05:23:28 PM PDT 24
Peak memory 216408 kb
Host smart-e27d80a0-3bf1-4770-9294-3d63798f9b55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703332268 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.3703332268
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.1671188044
Short name T192
Test name
Test status
Simulation time 138435224126 ps
CPU time 78.34 seconds
Started Jun 25 05:16:01 PM PDT 24
Finished Jun 25 05:17:21 PM PDT 24
Peak memory 199896 kb
Host smart-dfc99134-ec62-49da-a505-5e5c9931190f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671188044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.1671188044
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.152904708
Short name T590
Test name
Test status
Simulation time 308756473653 ps
CPU time 235.24 seconds
Started Jun 25 05:16:02 PM PDT 24
Finished Jun 25 05:19:59 PM PDT 24
Peak memory 199868 kb
Host smart-40576d22-9df9-47aa-a815-49d0b69c43b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152904708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.152904708
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.4014452181
Short name T108
Test name
Test status
Simulation time 22231323320 ps
CPU time 389.98 seconds
Started Jun 25 05:16:01 PM PDT 24
Finished Jun 25 05:22:32 PM PDT 24
Peak memory 215468 kb
Host smart-6f34ecf9-d07a-422f-b2e8-23945c6412ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014452181 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.4014452181
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.976746043
Short name T882
Test name
Test status
Simulation time 9703698166 ps
CPU time 19.38 seconds
Started Jun 25 05:16:07 PM PDT 24
Finished Jun 25 05:16:27 PM PDT 24
Peak memory 199852 kb
Host smart-8045c4e3-9166-4218-b786-dbffc9eb63c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976746043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.976746043
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.907952713
Short name T158
Test name
Test status
Simulation time 10984989522 ps
CPU time 19.64 seconds
Started Jun 25 05:16:02 PM PDT 24
Finished Jun 25 05:16:23 PM PDT 24
Peak memory 199792 kb
Host smart-d8b5e27d-3dc9-461b-a38b-7e34f9347b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907952713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.907952713
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.3270058460
Short name T780
Test name
Test status
Simulation time 82131810579 ps
CPU time 36.22 seconds
Started Jun 25 05:16:00 PM PDT 24
Finished Jun 25 05:16:37 PM PDT 24
Peak memory 199896 kb
Host smart-b398bbf5-e7ff-4a1a-a171-58ee7d9d4aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270058460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3270058460
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.283893349
Short name T333
Test name
Test status
Simulation time 61233411385 ps
CPU time 51.39 seconds
Started Jun 25 05:16:02 PM PDT 24
Finished Jun 25 05:16:54 PM PDT 24
Peak memory 199924 kb
Host smart-960a9035-6bc1-4528-9746-7cdf74bcdc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283893349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.283893349
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.1563650284
Short name T1079
Test name
Test status
Simulation time 55372390272 ps
CPU time 523.75 seconds
Started Jun 25 05:16:14 PM PDT 24
Finished Jun 25 05:24:58 PM PDT 24
Peak memory 215928 kb
Host smart-d7c05cf6-7541-448b-a20d-a670a60454af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563650284 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.1563650284
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.880288281
Short name T148
Test name
Test status
Simulation time 69949404783 ps
CPU time 28.38 seconds
Started Jun 25 05:16:01 PM PDT 24
Finished Jun 25 05:16:31 PM PDT 24
Peak memory 199860 kb
Host smart-1abb6a3e-43b9-43fd-a259-c9bee924b5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880288281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.880288281
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.3486576741
Short name T319
Test name
Test status
Simulation time 29986830642 ps
CPU time 228.99 seconds
Started Jun 25 05:16:02 PM PDT 24
Finished Jun 25 05:19:53 PM PDT 24
Peak memory 208264 kb
Host smart-447f2723-3f25-4269-a4a5-94aeac535761
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486576741 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.3486576741
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.891029836
Short name T964
Test name
Test status
Simulation time 40752318 ps
CPU time 0.55 seconds
Started Jun 25 05:12:58 PM PDT 24
Finished Jun 25 05:13:01 PM PDT 24
Peak memory 195216 kb
Host smart-bddd5077-414c-4b4a-bfdd-21053beb9d0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891029836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.891029836
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.1489151046
Short name T139
Test name
Test status
Simulation time 69328388509 ps
CPU time 37.84 seconds
Started Jun 25 05:12:57 PM PDT 24
Finished Jun 25 05:13:36 PM PDT 24
Peak memory 200092 kb
Host smart-20da2fcb-1108-48e0-83a6-50146dab9af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489151046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.1489151046
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1270542777
Short name T664
Test name
Test status
Simulation time 23146124390 ps
CPU time 58.3 seconds
Started Jun 25 05:12:59 PM PDT 24
Finished Jun 25 05:14:00 PM PDT 24
Peak memory 199820 kb
Host smart-a4c271ed-1c7e-491a-acd0-35773ef6bea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270542777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1270542777
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3931238263
Short name T41
Test name
Test status
Simulation time 17411026384 ps
CPU time 15.92 seconds
Started Jun 25 05:12:54 PM PDT 24
Finished Jun 25 05:13:11 PM PDT 24
Peak memory 199744 kb
Host smart-fd33baa9-d4a7-41d1-9d04-f04d349e6e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931238263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3931238263
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3062415051
Short name T878
Test name
Test status
Simulation time 38623925633 ps
CPU time 5.04 seconds
Started Jun 25 05:13:01 PM PDT 24
Finished Jun 25 05:13:08 PM PDT 24
Peak memory 197680 kb
Host smart-81409c94-2933-40a7-9823-1f80768c34c0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062415051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3062415051
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.794490983
Short name T47
Test name
Test status
Simulation time 84536095839 ps
CPU time 871.12 seconds
Started Jun 25 05:12:58 PM PDT 24
Finished Jun 25 05:27:31 PM PDT 24
Peak memory 199848 kb
Host smart-b030ecf2-dbf6-4b30-8033-c8d797eb114c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=794490983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.794490983
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.2896856795
Short name T507
Test name
Test status
Simulation time 1698379865 ps
CPU time 5.86 seconds
Started Jun 25 05:12:56 PM PDT 24
Finished Jun 25 05:13:03 PM PDT 24
Peak memory 198716 kb
Host smart-2d9a3d3a-e7bc-4847-bb9a-3a555b397a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896856795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2896856795
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_perf.1865050605
Short name T613
Test name
Test status
Simulation time 6504330238 ps
CPU time 350.09 seconds
Started Jun 25 05:12:55 PM PDT 24
Finished Jun 25 05:18:47 PM PDT 24
Peak memory 199816 kb
Host smart-59fb1e64-382e-4163-a408-ea47e9e4de36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1865050605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.1865050605
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.3655734632
Short name T838
Test name
Test status
Simulation time 6793659608 ps
CPU time 14.99 seconds
Started Jun 25 05:12:57 PM PDT 24
Finished Jun 25 05:13:14 PM PDT 24
Peak memory 199204 kb
Host smart-5e092b6e-428c-48f2-8546-a7c24ecb42fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3655734632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3655734632
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.2065131736
Short name T141
Test name
Test status
Simulation time 103638518392 ps
CPU time 23.72 seconds
Started Jun 25 05:12:55 PM PDT 24
Finished Jun 25 05:13:20 PM PDT 24
Peak memory 199832 kb
Host smart-14477f81-71d1-47f9-b025-956829828a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065131736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2065131736
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.1583815154
Short name T579
Test name
Test status
Simulation time 1898642793 ps
CPU time 3.84 seconds
Started Jun 25 05:12:59 PM PDT 24
Finished Jun 25 05:13:06 PM PDT 24
Peak memory 195316 kb
Host smart-1e784096-8b5a-4b2c-be4d-e6c72a110d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583815154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1583815154
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.3838841016
Short name T1080
Test name
Test status
Simulation time 695476081 ps
CPU time 3.67 seconds
Started Jun 25 05:12:58 PM PDT 24
Finished Jun 25 05:13:04 PM PDT 24
Peak memory 199540 kb
Host smart-9efb9397-9420-4b34-aa0b-b18f1a47583e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838841016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3838841016
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.816382519
Short name T762
Test name
Test status
Simulation time 1708694374 ps
CPU time 2.54 seconds
Started Jun 25 05:12:57 PM PDT 24
Finished Jun 25 05:13:02 PM PDT 24
Peak memory 198492 kb
Host smart-a729704c-c741-4486-9f21-eb876cf828de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816382519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.816382519
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.4276878461
Short name T736
Test name
Test status
Simulation time 1855251157 ps
CPU time 3.04 seconds
Started Jun 25 05:12:56 PM PDT 24
Finished Jun 25 05:13:01 PM PDT 24
Peak memory 196508 kb
Host smart-73f58fd0-6441-40a7-89fd-74adb0992aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276878461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.4276878461
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.3887025660
Short name T596
Test name
Test status
Simulation time 20768063797 ps
CPU time 32.86 seconds
Started Jun 25 05:16:12 PM PDT 24
Finished Jun 25 05:16:46 PM PDT 24
Peak memory 199716 kb
Host smart-1fd83d3b-3c3d-4081-9281-b6edfb3923f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887025660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.3887025660
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.1087656906
Short name T334
Test name
Test status
Simulation time 55336093653 ps
CPU time 517.7 seconds
Started Jun 25 05:16:02 PM PDT 24
Finished Jun 25 05:24:41 PM PDT 24
Peak memory 216492 kb
Host smart-11627d30-2458-4a7d-a43f-468cc930b8e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087656906 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.1087656906
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.3373813290
Short name T738
Test name
Test status
Simulation time 106847566431 ps
CPU time 136.23 seconds
Started Jun 25 05:16:10 PM PDT 24
Finished Jun 25 05:18:27 PM PDT 24
Peak memory 199904 kb
Host smart-b0545f7b-2dbe-4db0-a705-2bb9331f7019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373813290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3373813290
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.32464975
Short name T1000
Test name
Test status
Simulation time 34303992323 ps
CPU time 54.3 seconds
Started Jun 25 05:16:17 PM PDT 24
Finished Jun 25 05:17:12 PM PDT 24
Peak memory 199688 kb
Host smart-d572c925-9ddc-4196-a64e-622de6af72c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32464975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.32464975
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.288923791
Short name T877
Test name
Test status
Simulation time 115660972988 ps
CPU time 439.69 seconds
Started Jun 25 05:16:18 PM PDT 24
Finished Jun 25 05:23:38 PM PDT 24
Peak memory 211920 kb
Host smart-5c690b4b-3700-480a-8835-492ce359334b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288923791 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.288923791
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.885555202
Short name T1020
Test name
Test status
Simulation time 49804092034 ps
CPU time 992.89 seconds
Started Jun 25 05:16:10 PM PDT 24
Finished Jun 25 05:32:44 PM PDT 24
Peak memory 213872 kb
Host smart-ff6aabcd-3fbd-4f5e-af52-948bcda6e62c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885555202 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.885555202
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.2520760861
Short name T45
Test name
Test status
Simulation time 58210378893 ps
CPU time 126.76 seconds
Started Jun 25 05:16:18 PM PDT 24
Finished Jun 25 05:18:26 PM PDT 24
Peak memory 199700 kb
Host smart-b8bbbe6d-4af8-485b-8a4a-5e2713053d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520760861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2520760861
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.2215978234
Short name T977
Test name
Test status
Simulation time 356993594389 ps
CPU time 274.14 seconds
Started Jun 25 05:16:10 PM PDT 24
Finished Jun 25 05:20:46 PM PDT 24
Peak memory 216344 kb
Host smart-7cee34e7-3fed-4156-8c9b-b8b851fa38cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215978234 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.2215978234
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.3498896363
Short name T174
Test name
Test status
Simulation time 37922397054 ps
CPU time 60.67 seconds
Started Jun 25 05:16:10 PM PDT 24
Finished Jun 25 05:17:13 PM PDT 24
Peak memory 199904 kb
Host smart-c8a12e4e-90fb-4abe-b062-c68299b7813b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498896363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3498896363
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.3936468774
Short name T107
Test name
Test status
Simulation time 98760015496 ps
CPU time 942.53 seconds
Started Jun 25 05:16:10 PM PDT 24
Finished Jun 25 05:31:54 PM PDT 24
Peak memory 216280 kb
Host smart-a0e48a87-f82e-4efe-ba70-ba7e61e942a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936468774 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.3936468774
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.4075410232
Short name T222
Test name
Test status
Simulation time 111695897834 ps
CPU time 21.54 seconds
Started Jun 25 05:16:11 PM PDT 24
Finished Jun 25 05:16:34 PM PDT 24
Peak memory 199800 kb
Host smart-e6e72716-72e1-45d1-b406-ac9ac756cb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075410232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.4075410232
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.2161733288
Short name T95
Test name
Test status
Simulation time 17461582537 ps
CPU time 250.58 seconds
Started Jun 25 05:16:11 PM PDT 24
Finished Jun 25 05:20:23 PM PDT 24
Peak memory 215268 kb
Host smart-fd0a2dd0-9ec2-4c70-b7cc-aa77d0ea5aab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161733288 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.2161733288
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.3571698802
Short name T243
Test name
Test status
Simulation time 130504584489 ps
CPU time 109.85 seconds
Started Jun 25 05:16:17 PM PDT 24
Finished Jun 25 05:18:08 PM PDT 24
Peak memory 199740 kb
Host smart-c18ccf1e-8203-4014-939e-8d4df13f5583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571698802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3571698802
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.2947277148
Short name T31
Test name
Test status
Simulation time 48877575334 ps
CPU time 127.56 seconds
Started Jun 25 05:16:11 PM PDT 24
Finished Jun 25 05:18:20 PM PDT 24
Peak memory 215972 kb
Host smart-c943a484-8f7a-425f-a1ea-f979041f2465
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947277148 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.2947277148
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.757416558
Short name T147
Test name
Test status
Simulation time 74607813517 ps
CPU time 26.2 seconds
Started Jun 25 05:16:12 PM PDT 24
Finished Jun 25 05:16:39 PM PDT 24
Peak memory 199748 kb
Host smart-e93da7fa-2a23-43ea-80b4-49673804493a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757416558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.757416558
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.2475715859
Short name T1056
Test name
Test status
Simulation time 15405132726 ps
CPU time 22.42 seconds
Started Jun 25 05:16:10 PM PDT 24
Finished Jun 25 05:16:34 PM PDT 24
Peak memory 199852 kb
Host smart-86951274-d283-41ca-9abf-93bc717009e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475715859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2475715859
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.2525641962
Short name T943
Test name
Test status
Simulation time 34560785 ps
CPU time 0.55 seconds
Started Jun 25 05:12:56 PM PDT 24
Finished Jun 25 05:12:58 PM PDT 24
Peak memory 195512 kb
Host smart-37a48d8f-ffbb-4c63-b899-d9bdb3fc0206
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525641962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2525641962
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.1261262958
Short name T313
Test name
Test status
Simulation time 205774818693 ps
CPU time 119.2 seconds
Started Jun 25 05:12:59 PM PDT 24
Finished Jun 25 05:15:02 PM PDT 24
Peak memory 199912 kb
Host smart-5fd69475-2b76-468a-8061-e729e9b739d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261262958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.1261262958
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.2802720768
Short name T464
Test name
Test status
Simulation time 229273966135 ps
CPU time 80.55 seconds
Started Jun 25 05:12:56 PM PDT 24
Finished Jun 25 05:14:18 PM PDT 24
Peak memory 199628 kb
Host smart-c221ef7a-b5cb-45da-9a19-bb1de93631a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802720768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2802720768
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.2887278445
Short name T185
Test name
Test status
Simulation time 70015648543 ps
CPU time 19.06 seconds
Started Jun 25 05:12:58 PM PDT 24
Finished Jun 25 05:13:19 PM PDT 24
Peak memory 199832 kb
Host smart-a12c1e64-9d0c-4a6e-a07f-6b76e6f66e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887278445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.2887278445
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.1565246908
Short name T12
Test name
Test status
Simulation time 59461628688 ps
CPU time 96.52 seconds
Started Jun 25 05:12:55 PM PDT 24
Finished Jun 25 05:14:32 PM PDT 24
Peak memory 199780 kb
Host smart-32de2d1b-1239-49bc-89df-a67e670cb078
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565246908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.1565246908
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.981348069
Short name T454
Test name
Test status
Simulation time 70316085401 ps
CPU time 294.7 seconds
Started Jun 25 05:12:55 PM PDT 24
Finished Jun 25 05:17:51 PM PDT 24
Peak memory 199744 kb
Host smart-70a1ecfb-3414-4e21-b09c-95317cb178fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=981348069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.981348069
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1452810806
Short name T378
Test name
Test status
Simulation time 1909253360 ps
CPU time 2.91 seconds
Started Jun 25 05:12:58 PM PDT 24
Finished Jun 25 05:13:03 PM PDT 24
Peak memory 196056 kb
Host smart-32f48a7d-b556-49b9-9b40-850f0b7083fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452810806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1452810806
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_perf.1415072737
Short name T698
Test name
Test status
Simulation time 5849145568 ps
CPU time 348.09 seconds
Started Jun 25 05:12:57 PM PDT 24
Finished Jun 25 05:18:47 PM PDT 24
Peak memory 199856 kb
Host smart-e7b7a325-fbd9-48fd-b299-b6f02dac482d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1415072737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1415072737
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.1567588437
Short name T955
Test name
Test status
Simulation time 4044114506 ps
CPU time 8.25 seconds
Started Jun 25 05:12:56 PM PDT 24
Finished Jun 25 05:13:05 PM PDT 24
Peak memory 198948 kb
Host smart-b61d9ebb-2ccb-4e8e-ab83-4f4882783880
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1567588437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1567588437
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.3350042660
Short name T46
Test name
Test status
Simulation time 88247610899 ps
CPU time 187.11 seconds
Started Jun 25 05:12:57 PM PDT 24
Finished Jun 25 05:16:06 PM PDT 24
Peak memory 199892 kb
Host smart-a38218c9-5435-48c3-a36a-35bfd95a82af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350042660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3350042660
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.3951827728
Short name T502
Test name
Test status
Simulation time 43843098449 ps
CPU time 70.58 seconds
Started Jun 25 05:12:59 PM PDT 24
Finished Jun 25 05:14:12 PM PDT 24
Peak memory 195856 kb
Host smart-1f7ab86b-0b32-4825-ac88-21001ad97f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951827728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.3951827728
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.3629172204
Short name T1028
Test name
Test status
Simulation time 459249450 ps
CPU time 3.13 seconds
Started Jun 25 05:13:00 PM PDT 24
Finished Jun 25 05:13:06 PM PDT 24
Peak memory 198288 kb
Host smart-8f6f1d34-acd3-485f-af64-f9c94bf8f370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629172204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3629172204
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.4259211879
Short name T329
Test name
Test status
Simulation time 188960569261 ps
CPU time 64.09 seconds
Started Jun 25 05:12:59 PM PDT 24
Finished Jun 25 05:14:05 PM PDT 24
Peak memory 199860 kb
Host smart-cf40e9e6-d062-45f4-9d7f-cb22dd3654df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259211879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.4259211879
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.3884801873
Short name T335
Test name
Test status
Simulation time 80068623663 ps
CPU time 1625.46 seconds
Started Jun 25 05:12:56 PM PDT 24
Finished Jun 25 05:40:03 PM PDT 24
Peak memory 216412 kb
Host smart-05e976d2-1cdc-4de5-9e4e-d7182eb2242b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884801873 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.3884801873
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.457744163
Short name T1030
Test name
Test status
Simulation time 439591245 ps
CPU time 1.36 seconds
Started Jun 25 05:12:55 PM PDT 24
Finished Jun 25 05:12:57 PM PDT 24
Peak memory 197380 kb
Host smart-dcbb4e40-94e7-48fe-9706-950b5e1cea17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457744163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.457744163
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.1559181070
Short name T323
Test name
Test status
Simulation time 99290461275 ps
CPU time 36.91 seconds
Started Jun 25 05:12:55 PM PDT 24
Finished Jun 25 05:13:33 PM PDT 24
Peak memory 199848 kb
Host smart-a877eea2-e127-41fa-810f-001a9ffc5122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559181070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.1559181070
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2152602173
Short name T933
Test name
Test status
Simulation time 28457898255 ps
CPU time 5.36 seconds
Started Jun 25 05:16:10 PM PDT 24
Finished Jun 25 05:16:17 PM PDT 24
Peak memory 199876 kb
Host smart-7f411b46-edb2-47d5-a40c-23d4abdda226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152602173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2152602173
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.2659745126
Short name T887
Test name
Test status
Simulation time 63050205893 ps
CPU time 152.69 seconds
Started Jun 25 05:16:09 PM PDT 24
Finished Jun 25 05:18:43 PM PDT 24
Peak memory 199860 kb
Host smart-4fc1a26b-b5c5-4716-88a4-3d7b473ac916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659745126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2659745126
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.2738727961
Short name T93
Test name
Test status
Simulation time 124954421240 ps
CPU time 169.33 seconds
Started Jun 25 05:16:12 PM PDT 24
Finished Jun 25 05:19:02 PM PDT 24
Peak memory 215760 kb
Host smart-5797ac83-299a-43c4-8fcb-ef701d3b9019
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738727961 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.2738727961
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.1003014047
Short name T784
Test name
Test status
Simulation time 118312664779 ps
CPU time 176.83 seconds
Started Jun 25 05:16:10 PM PDT 24
Finished Jun 25 05:19:08 PM PDT 24
Peak memory 199888 kb
Host smart-127ff0ff-97b8-4f65-a4cb-fb283a23635c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003014047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.1003014047
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.567467533
Short name T398
Test name
Test status
Simulation time 102286895765 ps
CPU time 40.57 seconds
Started Jun 25 05:16:10 PM PDT 24
Finished Jun 25 05:16:53 PM PDT 24
Peak memory 199656 kb
Host smart-3a61b0b7-d6cf-432e-a661-633db30e2872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567467533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.567467533
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.2797963401
Short name T1017
Test name
Test status
Simulation time 12893273058 ps
CPU time 109.99 seconds
Started Jun 25 05:16:11 PM PDT 24
Finished Jun 25 05:18:02 PM PDT 24
Peak memory 215460 kb
Host smart-1c63b366-ae8f-4aaf-894b-22b2125002fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797963401 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.2797963401
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.1352554224
Short name T291
Test name
Test status
Simulation time 22352895252 ps
CPU time 13.85 seconds
Started Jun 25 05:16:10 PM PDT 24
Finished Jun 25 05:16:26 PM PDT 24
Peak memory 199904 kb
Host smart-ef5a9fd6-8299-4c33-a46c-4c0216ca4ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352554224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.1352554224
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.2223894167
Short name T169
Test name
Test status
Simulation time 41272698858 ps
CPU time 18.55 seconds
Started Jun 25 05:16:11 PM PDT 24
Finished Jun 25 05:16:31 PM PDT 24
Peak memory 199888 kb
Host smart-49b8fa10-184d-4049-bafd-8f33ac14ba25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223894167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.2223894167
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.4086275502
Short name T346
Test name
Test status
Simulation time 181213273880 ps
CPU time 28.62 seconds
Started Jun 25 05:16:22 PM PDT 24
Finished Jun 25 05:16:51 PM PDT 24
Peak memory 199940 kb
Host smart-ffe37b49-a2ae-4c09-81c0-013252dbc3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086275502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.4086275502
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.618646432
Short name T870
Test name
Test status
Simulation time 30095331261 ps
CPU time 248.42 seconds
Started Jun 25 05:16:18 PM PDT 24
Finished Jun 25 05:20:27 PM PDT 24
Peak memory 215400 kb
Host smart-7a9db62a-9bb8-42ca-bff9-3f4ccc66dca4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618646432 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.618646432
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.903924146
Short name T787
Test name
Test status
Simulation time 75560804881 ps
CPU time 57.15 seconds
Started Jun 25 05:16:21 PM PDT 24
Finished Jun 25 05:17:19 PM PDT 24
Peak memory 199764 kb
Host smart-05edf1bb-3c63-451f-a8d7-c95fad55beaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903924146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.903924146
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1856206154
Short name T122
Test name
Test status
Simulation time 56187556976 ps
CPU time 49.7 seconds
Started Jun 25 05:16:19 PM PDT 24
Finished Jun 25 05:17:10 PM PDT 24
Peak memory 199904 kb
Host smart-16c70938-f37c-432c-9314-5a8385b77f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856206154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1856206154
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.3121291146
Short name T54
Test name
Test status
Simulation time 289954604301 ps
CPU time 1482.58 seconds
Started Jun 25 05:16:18 PM PDT 24
Finished Jun 25 05:41:02 PM PDT 24
Peak memory 224612 kb
Host smart-c55f91a5-11d2-4577-b6f5-2e0478e4297e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121291146 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3121291146
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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