Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101032	1			T1	14		T2	37		T3	18
all_values[1]	101032	1			T1	14		T2	37		T3	18
all_values[2]	101032	1			T1	14		T2	37		T3	18
all_values[3]	101032	1			T1	14		T2	37		T3	18
all_values[4]	101032	1			T1	14		T2	37		T3	18
all_values[5]	101032	1			T1	14		T2	37		T3	18
all_values[6]	101032	1			T1	14		T2	37		T3	18
all_values[7]	101032	1			T1	14		T2	37		T3	18
all_values[8]	101032	1			T1	14		T2	37		T3	18

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

448792

1

T1

66

T2

198

T3

38

auto[1]

460496

1

T1

60

T2

135

T3

124

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

827045

1

T1

114

T2

330

T3

123

auto[1]

82243

1

T1

12

T2

3

T3

39

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	28604	1			T1	8		T2	27		T3	1
all_values[0]	auto[0]	auto[1]	21323	1			T1	6		T2	1		T3	13
all_values[0]	auto[1]	auto[0]	30643	1			T2	9		T5	5		T7	7
all_values[0]	auto[1]	auto[1]	20462	1			T3	4		T5	4		T6	2
all_values[1]	auto[0]	auto[0]	48616	1			T1	2		T2	28		T3	1
all_values[1]	auto[0]	auto[1]	1380	1			T6	5		T7	8		T9	2
all_values[1]	auto[1]	auto[0]	49523	1			T1	12		T2	9		T3	17
all_values[1]	auto[1]	auto[1]	1513	1			T9	8		T15	1		T11	4
all_values[2]	auto[0]	auto[0]	48215	1			T1	5		T2	31		T3	1
all_values[2]	auto[0]	auto[1]	2310	1			T1	2		T2	1		T3	3
all_values[2]	auto[1]	auto[0]	48560	1			T1	5		T2	5		T3	12
all_values[2]	auto[1]	auto[1]	1947	1			T1	2		T3	2		T4	1
all_values[3]	auto[0]	auto[0]	53302	1			T1	6		T2	32		T3	4
all_values[3]	auto[0]	auto[1]	236	1			T6	3		T9	1		T70	1
all_values[3]	auto[1]	auto[0]	47226	1			T1	8		T2	5		T3	14
all_values[3]	auto[1]	auto[1]	268	1			T4	1		T9	2		T12	3
all_values[4]	auto[0]	auto[0]	48357	1			T1	5		T2	7		T3	1
all_values[4]	auto[0]	auto[1]	334	1			T9	5		T12	6		T13	1
all_values[4]	auto[1]	auto[0]	51952	1			T1	9		T2	30		T3	17
all_values[4]	auto[1]	auto[1]	389	1			T11	3		T12	3		T70	2
all_values[5]	auto[0]	auto[0]	47620	1			T1	7		T2	9		T3	5
all_values[5]	auto[0]	auto[1]	163	1			T13	4		T16	8		T30	2
all_values[5]	auto[1]	auto[0]	53104	1			T1	7		T2	28		T3	13
all_values[5]	auto[1]	auto[1]	145	1			T12	1		T13	2		T16	2
all_values[6]	auto[0]	auto[0]	46893	1			T1	6		T3	2		T4	10
all_values[6]	auto[0]	auto[1]	157	1			T12	1		T13	2		T20	2
all_values[6]	auto[1]	auto[0]	53841	1			T1	8		T2	37		T3	16
all_values[6]	auto[1]	auto[1]	141	1			T12	2		T13	2		T20	1
all_values[7]	auto[0]	auto[0]	50539	1			T1	7		T2	31		T3	3
all_values[7]	auto[0]	auto[1]	302	1			T12	4		T14	1		T13	1
all_values[7]	auto[1]	auto[0]	49867	1			T1	7		T2	6		T3	15
all_values[7]	auto[1]	auto[1]	324	1			T9	4		T12	1		T13	8
all_values[8]	auto[0]	auto[0]	35069	1			T1	12		T2	30		T3	1
all_values[8]	auto[0]	auto[1]	15372	1			T2	1		T3	3		T4	2
all_values[8]	auto[1]	auto[0]	35114	1			T2	6		T4	1		T5	7
all_values[8]	auto[1]	auto[1]	15477	1			T1	2		T3	14		T4	10