Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2207

1

T1

1

T2

1

T3

1

auto[UartRx]

2207

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4003	1			T1	2		T2	2		T3	2
values[1]	25	1			T12	1		T45	2		T92	1
values[2]	44	1			T31	1		T33	1		T35	1
values[3]	29	1			T16	1		T30	2		T35	1
values[4]	40	1			T16	3		T32	1		T33	1
values[5]	36	1			T30	1		T32	1		T33	1
values[6]	43	1			T15	1		T16	1		T30	2
values[7]	41	1			T12	2		T20	1		T16	1
values[8]	37	1			T15	1		T12	1		T16	2
values[9]	52	1			T15	2		T12	2		T20	1
values[10]	50	1			T12	2		T16	1		T30	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2057	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	5	1			T12	1		T45	1		T307	1
auto[UartTx]	values[2]	14	1			T187	1		T308	1		T309	1
auto[UartTx]	values[3]	16	1			T45	1		T253	1		T304	1
auto[UartTx]	values[4]	17	1			T16	1		T32	1		T34	1
auto[UartTx]	values[5]	16	1			T33	1		T310	1		T304	1
auto[UartTx]	values[6]	10	1			T16	1		T30	1		T188	1
auto[UartTx]	values[7]	14	1			T264	1		T92	1		T94	1
auto[UartTx]	values[8]	10	1			T12	1		T16	1		T44	1
auto[UartTx]	values[9]	21	1			T15	1		T30	2		T187	1
auto[UartTx]	values[10]	22	1			T12	1		T16	1		T264	1
auto[UartRx]	values[0]	1946	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	20	1			T45	1		T92	1		T308	1
auto[UartRx]	values[2]	30	1			T31	1		T33	1		T35	1
auto[UartRx]	values[3]	13	1			T16	1		T30	2		T35	1
auto[UartRx]	values[4]	23	1			T16	2		T33	1		T187	1
auto[UartRx]	values[5]	20	1			T30	1		T32	1		T176	1
auto[UartRx]	values[6]	33	1			T15	1		T30	1		T31	2
auto[UartRx]	values[7]	27	1			T12	2		T20	1		T16	1
auto[UartRx]	values[8]	27	1			T15	1		T16	1		T31	1
auto[UartRx]	values[9]	31	1			T15	1		T12	2		T20	1
auto[UartRx]	values[10]	28	1			T12	1		T30	1		T32	1