Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2056	1			T1	3		T3	1		T4	2
auto[BaudRate115200]	1629	1			T1	3		T3	1		T5	2
auto[BaudRate230400]	1562	1			T1	2		T3	2		T5	2
auto[BaudRate128Kbps]	1670	1			T1	3		T3	2		T4	2
auto[BaudRate256Kbps]	1743	1			T1	4		T2	2		T3	1
auto[BaudRate1Mbps]	1496	1			T1	2		T2	1		T4	1
auto[BaudRate1p5Mbps]	1109	1			T1	2		T2	1		T3	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	945	1			T6	9		T8	8		T234	8
freqs[25]	951	1			T1	19		T3	8		T116	5
freqs[48]	383	1			T4	6		T19	45		T242	7
freqs[50]	564	1			T14	6		T293	2		T311	18
freqs[100]	1201	1			T2	4		T15	18		T104	8

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	189	1			T6	2		T8	2		T170	1
auto[BaudRate9600]	freqs[25]	153	1			T1	3		T3	1		T132	1
auto[BaudRate9600]	freqs[48]	56	1			T4	2		T19	3		T247	1
auto[BaudRate9600]	freqs[50]	93	1			T311	3		T35	2		T252	1
auto[BaudRate9600]	freqs[100]	239	1			T15	1		T105	3		T102	1
auto[BaudRate115200]	freqs[24]	125	1			T6	1		T8	1		T234	1
auto[BaudRate115200]	freqs[25]	134	1			T1	3		T3	1		T116	1
auto[BaudRate115200]	freqs[48]	35	1			T242	2		T287	5		T147	1
auto[BaudRate115200]	freqs[50]	92	1			T14	2		T35	1		T252	2
auto[BaudRate115200]	freqs[100]	161	1			T15	1		T104	2		T238	1
auto[BaudRate230400]	freqs[24]	135	1			T8	1		T234	1		T31	3
auto[BaudRate230400]	freqs[25]	145	1			T1	2		T3	2		T116	1
auto[BaudRate230400]	freqs[48]	51	1			T19	3		T242	2		T312	1
auto[BaudRate230400]	freqs[50]	63	1			T14	1		T311	6		T298	1
auto[BaudRate230400]	freqs[100]	148	1			T15	1		T105	3		T161	2
auto[BaudRate128Kbps]	freqs[24]	141	1			T6	1		T8	1		T234	2
auto[BaudRate128Kbps]	freqs[25]	151	1			T1	3		T3	2		T116	1
auto[BaudRate128Kbps]	freqs[48]	46	1			T4	2		T19	6		T312	3
auto[BaudRate128Kbps]	freqs[50]	90	1			T14	1		T293	1		T311	3
auto[BaudRate128Kbps]	freqs[100]	145	1			T15	5		T104	2		T238	1
auto[BaudRate256Kbps]	freqs[24]	150	1			T6	2		T8	1		T234	2
auto[BaudRate256Kbps]	freqs[25]	148	1			T1	4		T3	1		T289	1
auto[BaudRate256Kbps]	freqs[48]	58	1			T4	1		T19	6		T313	1
auto[BaudRate256Kbps]	freqs[50]	97	1			T293	1		T311	3		T35	2
auto[BaudRate256Kbps]	freqs[100]	175	1			T2	2		T15	1		T104	2
auto[BaudRate1Mbps]	freqs[24]	130	1			T6	2		T8	1		T234	1
auto[BaudRate1Mbps]	freqs[25]	149	1			T1	2		T116	2		T314	3
auto[BaudRate1Mbps]	freqs[48]	67	1			T4	1		T19	15		T242	3
auto[BaudRate1Mbps]	freqs[50]	68	1			T14	2		T35	1		T252	6
auto[BaudRate1Mbps]	freqs[100]	150	1			T2	1		T15	1		T104	1
auto[BaudRate1p5Mbps]	freqs[25]	71	1			T1	2		T3	1		T314	1
auto[BaudRate1p5Mbps]	freqs[48]	70	1			T19	12		T247	1		T192	1
auto[BaudRate1p5Mbps]	freqs[50]	61	1			T311	3		T252	1		T315	2
auto[BaudRate1p5Mbps]	freqs[100]	183	1			T2	1		T15	8		T104	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded