Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.43	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	9	121	93.08

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	9	121	93.08	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	31041847	1			T1	350		T2	114618		T3	16
all_levels[1]	181049	1			T1	16		T2	2683		T6	1
all_levels[2]	1885	1			T1	7		T5	1		T6	1
all_levels[3]	900	1			T1	5		T6	2		T7	2
all_levels[4]	629	1			T1	4		T5	1		T6	1
all_levels[5]	479	1			T1	1		T5	1		T7	2
all_levels[6]	374	1			T1	2		T7	2		T15	1
all_levels[7]	297	1			T3	1		T10	2		T15	1
all_levels[8]	259	1			T12	4		T23	1		T37	1
all_levels[9]	268	1			T10	1		T23	2		T38	1
all_levels[10]	220	1			T101	3		T104	1		T100	2
all_levels[11]	192	1			T12	1		T38	1		T104	1
all_levels[12]	148	1			T23	1		T101	1		T104	1
all_levels[13]	144	1			T12	1		T23	2		T38	1
all_levels[14]	116	1			T7	1		T12	1		T23	2
all_levels[15]	113	1			T7	1		T23	3		T100	2
all_levels[16]	93	1			T3	1		T12	1		T101	2
all_levels[17]	110	1			T6	1		T104	1		T100	1
all_levels[18]	76	1			T12	2		T23	2		T101	1
all_levels[19]	90	1			T6	1		T23	1		T104	1
all_levels[20]	88	1			T23	1		T101	1		T104	1
all_levels[21]	58	1			T23	3		T100	1		T109	2
all_levels[22]	57	1			T104	1		T100	1		T16	1
all_levels[23]	63	1			T104	1		T100	1		T16	1
all_levels[24]	54	1			T3	2		T23	1		T105	1
all_levels[25]	47	1			T23	1		T110	2		T111	1
all_levels[26]	42	1			T12	1		T38	1		T109	1
all_levels[27]	40	1			T12	1		T16	1		T109	1
all_levels[28]	46	1			T16	1		T112	1		T103	1
all_levels[29]	32	1			T7	1		T23	1		T112	1
all_levels[30]	42	1			T23	1		T38	1		T104	2
all_levels[31]	34	1			T23	2		T16	1		T112	1
all_levels[32]	29	1			T113	1		T114	1		T115	1
all_levels[33]	27	1			T23	1		T116	1		T117	1
all_levels[34]	21	1			T7	1		T34	1		T118	2
all_levels[35]	19	1			T113	2		T119	2		T120	1
all_levels[36]	18	1			T7	1		T12	1		T38	1
all_levels[37]	25	1			T16	1		T121	1		T122	2
all_levels[38]	19	1			T106	3		T123	1		T124	1
all_levels[39]	24	1			T38	1		T123	1		T125	2
all_levels[40]	15	1			T12	1		T110	1		T126	1
all_levels[41]	22	1			T116	1		T127	2		T128	2
all_levels[42]	15	1			T38	1		T116	1		T129	2
all_levels[43]	24	1			T121	1		T130	1		T131	1
all_levels[44]	21	1			T12	1		T132	2		T133	1
all_levels[45]	13	1			T121	1		T134	1		T135	1
all_levels[46]	7	1			T132	1		T130	1		T136	1
all_levels[47]	7	1			T126	1		T137	1		T138	1
all_levels[48]	19	1			T38	1		T40	2		T34	1
all_levels[49]	13	1			T43	1		T139	1		T130	1
all_levels[50]	13	1			T140	1		T128	1		T141	1
all_levels[51]	4	1			T142	1		T143	1		T144	1
all_levels[52]	10	1			T128	1		T94	1		T145	1
all_levels[53]	11	1			T146	1		T126	1		T129	1
all_levels[54]	10	1			T127	1		T147	1		T148	1
all_levels[55]	7	1			T149	1		T140	1		T150	1
all_levels[56]	6	1			T151	1		T152	1		T153	1
all_levels[57]	14	1			T105	1		T154	1		T155	4
all_levels[58]	3	1			T116	1		T156	1		T157	1
all_levels[59]	12	1			T158	1		T159	1		T160	2
all_levels[60]	8	1			T161	1		T162	1		T163	1
all_levels[61]	6	1			T127	1		T151	1		T126	2
all_levels[62]	10	1			T7	1		T16	2		T164	1
all_levels[63]	13	1			T124	1		T115	1		T165	1
all_levels[64]	83	1			T112	1		T166	3		T125	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31226156

1

T1

385

T2

117301

T3

12

auto[1]

4284

1

T3

8

T4

6

T6

8

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	9	121	93.08	9

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[33]]	[auto[1]]	0	1	1
[all_levels[40]]	[auto[1]]	0	1	1
[all_levels[46] , all_levels[47]]	[auto[1]]	--	--	2
[all_levels[51] , all_levels[52]]	[auto[1]]	--	--	2
[all_levels[54]]	[auto[1]]	0	1	1
[all_levels[56]]	[auto[1]]	0	1	1
[all_levels[58]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	31037976	1			T1	350		T2	114618		T3	9
all_levels[0]	auto[1]	3871	1			T3	7		T4	6		T6	8
all_levels[1]	auto[0]	180966	1			T1	16		T2	2683		T6	1
all_levels[1]	auto[1]	83	1			T104	1		T106	2		T167	2
all_levels[2]	auto[0]	1867	1			T1	7		T5	1		T6	1
all_levels[2]	auto[1]	18	1			T98	2		T168	1		T169	1
all_levels[3]	auto[0]	880	1			T1	5		T6	2		T7	2
all_levels[3]	auto[1]	20	1			T23	1		T170	1		T171	1
all_levels[4]	auto[0]	613	1			T1	4		T5	1		T6	1
all_levels[4]	auto[1]	16	1			T102	2		T172	1		T45	1
all_levels[5]	auto[0]	458	1			T1	1		T5	1		T7	2
all_levels[5]	auto[1]	21	1			T106	1		T102	1		T151	1
all_levels[6]	auto[0]	361	1			T1	2		T7	2		T15	1
all_levels[6]	auto[1]	13	1			T23	1		T173	1		T174	1
all_levels[7]	auto[0]	285	1			T3	1		T10	2		T15	1
all_levels[7]	auto[1]	12	1			T132	2		T147	1		T175	2
all_levels[8]	auto[0]	254	1			T12	4		T23	1		T37	1
all_levels[8]	auto[1]	5	1			T104	1		T176	1		T177	1
all_levels[9]	auto[0]	262	1			T10	1		T23	2		T38	1
all_levels[9]	auto[1]	6	1			T171	1		T178	2		T175	1
all_levels[10]	auto[0]	205	1			T101	3		T104	1		T100	2
all_levels[10]	auto[1]	15	1			T16	1		T179	2		T180	1
all_levels[11]	auto[0]	171	1			T12	1		T38	1		T104	1
all_levels[11]	auto[1]	21	1			T123	3		T181	3		T182	3
all_levels[12]	auto[0]	141	1			T23	1		T101	1		T104	1
all_levels[12]	auto[1]	7	1			T183	1		T184	1		T185	1
all_levels[13]	auto[0]	135	1			T12	1		T23	2		T38	1
all_levels[13]	auto[1]	9	1			T127	1		T186	1		T187	1
all_levels[14]	auto[0]	107	1			T7	1		T12	1		T23	1
all_levels[14]	auto[1]	9	1			T23	1		T105	2		T167	2
all_levels[15]	auto[0]	108	1			T7	1		T23	3		T100	2
all_levels[15]	auto[1]	5	1			T105	1		T111	1		T188	1
all_levels[16]	auto[0]	87	1			T3	1		T12	1		T101	2
all_levels[16]	auto[1]	6	1			T189	1		T187	2		T190	1
all_levels[17]	auto[0]	97	1			T6	1		T104	1		T100	1
all_levels[17]	auto[1]	13	1			T191	1		T172	1		T148	1
all_levels[18]	auto[0]	67	1			T12	2		T23	2		T101	1
all_levels[18]	auto[1]	9	1			T139	2		T192	1		T182	1
all_levels[19]	auto[0]	76	1			T6	1		T23	1		T104	1
all_levels[19]	auto[1]	14	1			T191	1		T149	1		T193	1
all_levels[20]	auto[0]	77	1			T23	1		T101	1		T104	1
all_levels[20]	auto[1]	11	1			T121	1		T194	1		T195	1
all_levels[21]	auto[0]	55	1			T23	3		T100	1		T109	2
all_levels[21]	auto[1]	3	1			T122	1		T196	1		T197	1
all_levels[22]	auto[0]	56	1			T104	1		T100	1		T16	1
all_levels[22]	auto[1]	1	1			T121	1		-	-		-	-
all_levels[23]	auto[0]	59	1			T104	1		T100	1		T16	1
all_levels[23]	auto[1]	4	1			T121	1		T196	1		T198	1
all_levels[24]	auto[0]	46	1			T3	1		T23	1		T105	1
all_levels[24]	auto[1]	8	1			T3	1		T45	2		T199	2
all_levels[25]	auto[0]	44	1			T23	1		T110	1		T111	1
all_levels[25]	auto[1]	3	1			T110	1		T200	2		-	-
all_levels[26]	auto[0]	38	1			T12	1		T38	1		T109	1
all_levels[26]	auto[1]	4	1			T201	2		T202	2		-	-
all_levels[27]	auto[0]	38	1			T12	1		T16	1		T109	1
all_levels[27]	auto[1]	2	1			T203	1		T204	1		-	-
all_levels[28]	auto[0]	41	1			T16	1		T112	1		T103	1
all_levels[28]	auto[1]	5	1			T45	3		T205	1		T206	1
all_levels[29]	auto[0]	27	1			T7	1		T23	1		T112	1
all_levels[29]	auto[1]	5	1			T207	2		T208	3		-	-
all_levels[30]	auto[0]	40	1			T23	1		T38	1		T104	2
all_levels[30]	auto[1]	2	1			T98	1		T209	1		-	-
all_levels[31]	auto[0]	33	1			T23	2		T16	1		T112	1
all_levels[31]	auto[1]	1	1			T210	1		-	-		-	-
all_levels[32]	auto[0]	25	1			T113	1		T114	1		T115	1
all_levels[32]	auto[1]	4	1			T211	1		T212	1		T213	1
all_levels[33]	auto[0]	27	1			T23	1		T116	1		T117	1
all_levels[34]	auto[0]	20	1			T7	1		T34	1		T118	1
all_levels[34]	auto[1]	1	1			T118	1		-	-		-	-
all_levels[35]	auto[0]	18	1			T113	2		T119	1		T120	1
all_levels[35]	auto[1]	1	1			T119	1		-	-		-	-
all_levels[36]	auto[0]	17	1			T7	1		T12	1		T38	1
all_levels[36]	auto[1]	1	1			T214	1		-	-		-	-
all_levels[37]	auto[0]	24	1			T16	1		T121	1		T122	1
all_levels[37]	auto[1]	1	1			T122	1		-	-		-	-
all_levels[38]	auto[0]	15	1			T106	1		T123	1		T124	1
all_levels[38]	auto[1]	4	1			T106	2		T215	2		-	-
all_levels[39]	auto[0]	22	1			T38	1		T123	1		T125	2
all_levels[39]	auto[1]	2	1			T216	1		T217	1		-	-
all_levels[40]	auto[0]	15	1			T12	1		T110	1		T126	1
all_levels[41]	auto[0]	19	1			T116	1		T127	1		T128	2
all_levels[41]	auto[1]	3	1			T127	1		T218	2		-	-
all_levels[42]	auto[0]	14	1			T38	1		T116	1		T129	2
all_levels[42]	auto[1]	1	1			T219	1		-	-		-	-
all_levels[43]	auto[0]	23	1			T121	1		T130	1		T131	1
all_levels[43]	auto[1]	1	1			T220	1		-	-		-	-
all_levels[44]	auto[0]	18	1			T12	1		T132	1		T133	1
all_levels[44]	auto[1]	3	1			T132	1		T211	1		T221	1
all_levels[45]	auto[0]	11	1			T121	1		T134	1		T135	1
all_levels[45]	auto[1]	2	1			T184	2		-	-		-	-
all_levels[46]	auto[0]	7	1			T132	1		T130	1		T136	1
all_levels[47]	auto[0]	7	1			T126	1		T137	1		T138	1
all_levels[48]	auto[0]	16	1			T38	1		T40	2		T34	1
all_levels[48]	auto[1]	3	1			T192	2		T222	1		-	-
all_levels[49]	auto[0]	12	1			T43	1		T139	1		T130	1
all_levels[49]	auto[1]	1	1			T223	1		-	-		-	-
all_levels[50]	auto[0]	11	1			T140	1		T128	1		T141	1
all_levels[50]	auto[1]	2	1			T144	2		-	-		-	-
all_levels[51]	auto[0]	4	1			T142	1		T143	1		T144	1
all_levels[52]	auto[0]	10	1			T128	1		T94	1		T145	1
all_levels[53]	auto[0]	10	1			T146	1		T126	1		T129	1
all_levels[53]	auto[1]	1	1			T206	1		-	-		-	-
all_levels[54]	auto[0]	10	1			T127	1		T147	1		T148	1
all_levels[55]	auto[0]	6	1			T149	1		T140	1		T150	1
all_levels[55]	auto[1]	1	1			T224	1		-	-		-	-
all_levels[56]	auto[0]	6	1			T151	1		T152	1		T153	1
all_levels[57]	auto[0]	9	1			T105	1		T154	1		T155	1
all_levels[57]	auto[1]	5	1			T155	3		T143	1		T225	1
all_levels[58]	auto[0]	3	1			T116	1		T156	1		T157	1
all_levels[59]	auto[0]	9	1			T158	1		T159	1		T160	1
all_levels[59]	auto[1]	3	1			T160	1		T226	1		T227	1
all_levels[60]	auto[0]	5	1			T161	1		T162	1		T163	1
all_levels[60]	auto[1]	3	1			T228	1		T229	2		-	-
all_levels[61]	auto[0]	5	1			T127	1		T151	1		T126	1
all_levels[61]	auto[1]	1	1			T126	1		-	-		-	-
all_levels[62]	auto[0]	7	1			T7	1		T16	1		T164	1
all_levels[62]	auto[1]	3	1			T16	1		T230	2		-	-
all_levels[63]	auto[0]	10	1			T124	1		T115	1		T165	1
all_levels[63]	auto[1]	3	1			T231	1		T232	2		-	-
all_levels[64]	auto[0]	71	1			T112	1		T166	3		T125	1
all_levels[64]	auto[1]	12	1			T202	3		T141	1		T233	1