Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101032	1			T1	14		T2	37		T3	18
all_pins[1]	101032	1			T1	14		T2	37		T3	18
all_pins[2]	101032	1			T1	14		T2	37		T3	18
all_pins[3]	101032	1			T1	14		T2	37		T3	18
all_pins[4]	101032	1			T1	14		T2	37		T3	18
all_pins[5]	101032	1			T1	14		T2	37		T3	18
all_pins[6]	101032	1			T1	14		T2	37		T3	18
all_pins[7]	101032	1			T1	14		T2	37		T3	18
all_pins[8]	101032	1			T1	14		T2	37		T3	18

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	867773	1			T1	122		T2	333		T3	142
values[0x1]	41515	1			T1	4		T3	20		T4	12
transitions[0x0=>0x1]	32629	1			T1	4		T3	18		T4	11
transitions[0x1=>0x0]	32436	1			T1	4		T3	17		T4	12

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	80504	1			T1	14		T2	37		T3	14
all_pins[0]	values[0x1]	20528	1			T3	4		T5	4		T6	2
all_pins[0]	transitions[0x0=>0x1]	20064	1			T3	4		T5	4		T6	2
all_pins[0]	transitions[0x1=>0x0]	1045	1			T15	1		T12	2		T23	2
all_pins[1]	values[0x0]	99523	1			T1	14		T2	37		T3	18
all_pins[1]	values[0x1]	1509	1			T9	8		T15	1		T11	4
all_pins[1]	transitions[0x0=>0x1]	1436	1			T9	8		T15	1		T11	4
all_pins[1]	transitions[0x1=>0x0]	1932	1			T1	2		T3	2		T4	1
all_pins[2]	values[0x0]	99027	1			T1	12		T2	37		T3	16
all_pins[2]	values[0x1]	2005	1			T1	2		T3	2		T4	1
all_pins[2]	transitions[0x0=>0x1]	1946	1			T1	2		T3	2		T4	1
all_pins[2]	transitions[0x1=>0x0]	209	1			T4	1		T9	2		T12	3
all_pins[3]	values[0x0]	100764	1			T1	14		T2	37		T3	18
all_pins[3]	values[0x1]	268	1			T4	1		T9	2		T12	3
all_pins[3]	transitions[0x0=>0x1]	225	1			T4	1		T9	2		T12	2
all_pins[3]	transitions[0x1=>0x0]	346	1			T11	3		T12	2		T70	2
all_pins[4]	values[0x0]	100643	1			T1	14		T2	37		T3	18
all_pins[4]	values[0x1]	389	1			T11	3		T12	3		T70	2
all_pins[4]	transitions[0x0=>0x1]	327	1			T11	3		T12	3		T70	2
all_pins[4]	transitions[0x1=>0x0]	122	1			T12	2		T13	2		T16	2
all_pins[5]	values[0x0]	100848	1			T1	14		T2	37		T3	18
all_pins[5]	values[0x1]	184	1			T12	2		T13	2		T16	2
all_pins[5]	transitions[0x0=>0x1]	148	1			T12	2		T13	2		T16	2
all_pins[5]	transitions[0x1=>0x0]	711	1			T6	1		T10	1		T12	2
all_pins[6]	values[0x0]	100285	1			T1	14		T2	37		T3	18
all_pins[6]	values[0x1]	747	1			T6	1		T10	1		T12	2
all_pins[6]	transitions[0x0=>0x1]	702	1			T6	1		T10	1		T12	2
all_pins[6]	transitions[0x1=>0x0]	279	1			T9	4		T12	1		T13	6
all_pins[7]	values[0x0]	100708	1			T1	14		T2	37		T3	18
all_pins[7]	values[0x1]	324	1			T9	4		T12	1		T13	8
all_pins[7]	transitions[0x0=>0x1]	169	1			T13	5		T234	1		T109	3
all_pins[7]	transitions[0x1=>0x0]	15406	1			T1	2		T3	14		T4	10
all_pins[8]	values[0x0]	85471	1			T1	12		T2	37		T3	4
all_pins[8]	values[0x1]	15561	1			T1	2		T3	14		T4	10
all_pins[8]	transitions[0x0=>0x1]	7612	1			T1	2		T3	12		T4	9
all_pins[8]	transitions[0x1=>0x0]	12386	1			T3	1		T5	4		T6	1