Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7662024	1			T1	136		T2	3484		T3	19
all_levels[1]	2027269	1			T1	19		T2	30		T7	13
all_levels[2]	521344	1			T1	13		T2	19		T7	9
all_levels[3]	432251	1			T1	12		T2	20		T4	2
all_levels[4]	317053	1			T1	8		T2	19		T7	18
all_levels[5]	206752	1			T1	8		T2	21		T4	3
all_levels[6]	429483	1			T1	11		T2	23		T4	1
all_levels[7]	338626	1			T1	12		T2	21		T4	3
all_levels[8]	795615	1			T1	94		T2	23		T4	1
all_levels[9]	355694	1			T1	5		T2	31		T4	1
all_levels[10]	367034	1			T1	2		T2	20		T4	2
all_levels[11]	284407	1			T1	9		T2	23		T4	1
all_levels[12]	232647	1			T2	20		T4	2		T7	9
all_levels[13]	190462	1			T1	5		T2	19		T7	4
all_levels[14]	180223	1			T2	22		T4	1		T7	2
all_levels[15]	243821	1			T1	11		T2	23		T3	1
all_levels[16]	275511	1			T2	22		T4	2		T7	2
all_levels[17]	181862	1			T2	22		T4	1		T5	1
all_levels[18]	186374	1			T1	2		T2	18		T5	3
all_levels[19]	435536	1			T2	20		T8	1		T15	13
all_levels[20]	196165	1			T1	2		T2	19		T4	1
all_levels[21]	189302	1			T2	26		T4	2		T5	5
all_levels[22]	295386	1			T2	29		T4	2		T7	1
all_levels[23]	176973	1			T1	4		T2	18		T7	2
all_levels[24]	195542	1			T1	6		T2	22		T5	4
all_levels[25]	174863	1			T1	4		T2	24		T4	1
all_levels[26]	179415	1			T2	20		T4	1		T5	1
all_levels[27]	164557	1			T1	1		T2	25		T4	1
all_levels[28]	351728	1			T2	22		T4	1		T7	2
all_levels[29]	345681	1			T2	28		T5	3		T15	10
all_levels[30]	159826	1			T2	22		T4	1		T5	5
all_levels[31]	604943	1			T1	3		T2	953		T5	14
all_levels[32]	12531761	1			T1	18		T2	112194		T5	14

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31226156

1

T1

385

T2

117301

T3

12

auto[1]

3974

1

T2

1

T3

8

T4

4

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7659727	1			T1	136		T2	3484		T3	11
all_levels[0]	auto[1]	2297	1			T3	8		T4	4		T6	5
all_levels[1]	auto[0]	2026996	1			T1	19		T2	30		T7	12
all_levels[1]	auto[1]	273	1			T7	1		T12	1		T38	1
all_levels[2]	auto[0]	521308	1			T1	13		T2	19		T7	9
all_levels[2]	auto[1]	36	1			T104	1		T192	1		T277	1
all_levels[3]	auto[0]	432160	1			T1	12		T2	20		T4	2
all_levels[3]	auto[1]	91	1			T10	1		T12	9		T104	1
all_levels[4]	auto[0]	317021	1			T1	8		T2	19		T7	18
all_levels[4]	auto[1]	32	1			T238	4		T187	2		T271	2
all_levels[5]	auto[0]	206712	1			T1	8		T2	21		T4	3
all_levels[5]	auto[1]	40	1			T104	1		T105	1		T102	1
all_levels[6]	auto[0]	429447	1			T1	11		T2	23		T4	1
all_levels[6]	auto[1]	36	1			T23	1		T41	2		T102	2
all_levels[7]	auto[0]	338542	1			T1	12		T2	21		T4	3
all_levels[7]	auto[1]	84	1			T86	2		T166	2		T286	6
all_levels[8]	auto[0]	795595	1			T1	94		T2	23		T4	1
all_levels[8]	auto[1]	20	1			T189	1		T261	1		T168	2
all_levels[9]	auto[0]	355673	1			T1	5		T2	31		T4	1
all_levels[9]	auto[1]	21	1			T170	1		T260	2		T183	1
all_levels[10]	auto[0]	367015	1			T1	2		T2	20		T4	2
all_levels[10]	auto[1]	19	1			T105	1		T244	2		T85	2
all_levels[11]	auto[0]	284375	1			T1	9		T2	23		T4	1
all_levels[11]	auto[1]	32	1			T16	1		T280	2		T317	1
all_levels[12]	auto[0]	232613	1			T2	20		T4	2		T7	9
all_levels[12]	auto[1]	34	1			T127	1		T285	1		T201	1
all_levels[13]	auto[0]	190431	1			T1	5		T2	19		T7	4
all_levels[13]	auto[1]	31	1			T16	1		T187	2		T318	2
all_levels[14]	auto[0]	180204	1			T2	22		T4	1		T7	2
all_levels[14]	auto[1]	19	1			T23	1		T194	1		T142	1
all_levels[15]	auto[0]	243744	1			T1	11		T2	23		T3	1
all_levels[15]	auto[1]	77	1			T86	1		T280	2		T45	1
all_levels[16]	auto[0]	275494	1			T2	22		T4	2		T7	2
all_levels[16]	auto[1]	17	1			T111	1		T177	2		T319	1
all_levels[17]	auto[0]	181848	1			T2	22		T4	1		T5	1
all_levels[17]	auto[1]	14	1			T256	1		T201	2		T136	1
all_levels[18]	auto[0]	186351	1			T1	2		T2	18		T5	3
all_levels[18]	auto[1]	23	1			T12	1		T121	1		T194	1
all_levels[19]	auto[0]	435518	1			T2	20		T8	1		T15	13
all_levels[19]	auto[1]	18	1			T171	1		T86	1		T89	2
all_levels[20]	auto[0]	196133	1			T1	2		T2	19		T4	1
all_levels[20]	auto[1]	32	1			T103	1		T320	1		T321	1
all_levels[21]	auto[0]	189275	1			T2	26		T4	2		T5	5
all_levels[21]	auto[1]	27	1			T170	1		T152	1		T318	3
all_levels[22]	auto[0]	295366	1			T2	29		T4	2		T7	1
all_levels[22]	auto[1]	20	1			T139	1		T257	2		T195	4
all_levels[23]	auto[0]	176957	1			T1	4		T2	18		T7	2
all_levels[23]	auto[1]	16	1			T23	2		T42	1		T111	1
all_levels[24]	auto[0]	195502	1			T1	6		T2	22		T5	4
all_levels[24]	auto[1]	40	1			T85	2		T125	1		T322	2
all_levels[25]	auto[0]	174848	1			T1	4		T2	24		T4	1
all_levels[25]	auto[1]	15	1			T110	1		T151	1		T188	1
all_levels[26]	auto[0]	179384	1			T2	20		T4	1		T5	1
all_levels[26]	auto[1]	31	1			T171	3		T257	1		T117	1
all_levels[27]	auto[0]	164545	1			T1	1		T2	25		T4	1
all_levels[27]	auto[1]	12	1			T89	1		T261	1		T323	1
all_levels[28]	auto[0]	351707	1			T2	22		T4	1		T7	2
all_levels[28]	auto[1]	21	1			T122	1		T167	1		T186	2
all_levels[29]	auto[0]	345667	1			T2	28		T5	3		T15	10
all_levels[29]	auto[1]	14	1			T238	3		T126	1		T284	1
all_levels[30]	auto[0]	159806	1			T2	22		T4	1		T5	5
all_levels[30]	auto[1]	20	1			T16	2		T141	2		T324	1
all_levels[31]	auto[0]	604923	1			T1	3		T2	953		T5	14
all_levels[31]	auto[1]	20	1			T167	1		T45	2		T325	1
all_levels[32]	auto[0]	12531269	1			T1	18		T2	112193		T5	14
all_levels[32]	auto[1]	492	1			T2	1		T6	2		T8	2