Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	666	1			T12	7		T13	11		T20	4
all_values[1]	666	1			T12	7		T13	11		T20	4
all_values[2]	666	1			T12	7		T13	11		T20	4
all_values[3]	666	1			T12	7		T13	11		T20	4
all_values[4]	666	1			T12	7		T13	11		T20	4
all_values[5]	666	1			T12	7		T13	11		T20	4
all_values[6]	666	1			T12	7		T13	11		T20	4
all_values[7]	666	1			T12	7		T13	11		T20	4
all_values[8]	666	1			T12	7		T13	11		T20	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3243

1

T12

35

T13

47

T20

26

auto[1]

2751

1

T12

28

T13

52

T20

10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1934

1

T12

21

T13

31

T20

15

auto[1]

4060

1

T12

42

T13

68

T20

21

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3480

1

T12

36

T13

58

T20

25

auto[1]

2514

1

T12

27

T13

41

T20

11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	219	1			T12	4		T13	6		T20	1
all_values[0]	auto[0]	auto[1]	auto[1]	169	1			T13	1		T20	1		T16	3
all_values[0]	auto[1]	auto[0]	auto[1]	154	1			T12	2		T13	1		T20	2
all_values[0]	auto[1]	auto[1]	auto[1]	124	1			T12	1		T13	3		T16	3
all_values[1]	auto[0]	auto[0]	auto[0]	195	1			T12	1		T13	2		T20	1
all_values[1]	auto[0]	auto[1]	auto[0]	179	1			T12	3		T13	4		T20	2
all_values[1]	auto[1]	auto[0]	auto[1]	153	1			T12	3		T13	2		T20	1
all_values[1]	auto[1]	auto[1]	auto[1]	139	1			T13	3		T16	3		T34	4
all_values[2]	auto[0]	auto[0]	auto[0]	156	1			T12	2		T13	2		T20	2
all_values[2]	auto[0]	auto[0]	auto[1]	51	1			T16	1		T91	2		T92	1
all_values[2]	auto[0]	auto[1]	auto[0]	112	1			T12	4		T13	1		T30	1
all_values[2]	auto[0]	auto[1]	auto[1]	70	1			T13	2		T20	1		T16	3
all_values[2]	auto[1]	auto[0]	auto[1]	156	1			T12	1		T13	1		T20	1
all_values[2]	auto[1]	auto[1]	auto[1]	121	1			T13	5		T16	4		T30	1
all_values[3]	auto[0]	auto[0]	auto[0]	140	1			T12	1		T13	2		T20	1
all_values[3]	auto[0]	auto[0]	auto[1]	57	1			T13	1		T20	2		T16	1
all_values[3]	auto[0]	auto[1]	auto[0]	100	1			T13	3		T16	2		T30	2
all_values[3]	auto[0]	auto[1]	auto[1]	66	1			T12	1		T13	1		T44	1
all_values[3]	auto[1]	auto[0]	auto[1]	169	1			T12	4		T13	3		T20	1
all_values[3]	auto[1]	auto[1]	auto[1]	134	1			T12	1		T13	1		T16	4
all_values[4]	auto[0]	auto[0]	auto[0]	130	1			T13	2		T20	1		T16	3
all_values[4]	auto[0]	auto[0]	auto[1]	60	1			T12	1		T16	3		T30	1
all_values[4]	auto[0]	auto[1]	auto[0]	134	1			T12	1		T13	1		T16	2
all_values[4]	auto[0]	auto[1]	auto[1]	62	1			T12	1		T13	3		T20	1
all_values[4]	auto[1]	auto[0]	auto[1]	149	1			T12	2		T13	1		T20	2
all_values[4]	auto[1]	auto[1]	auto[1]	131	1			T12	2		T13	4		T16	5
all_values[5]	auto[0]	auto[0]	auto[0]	155	1			T12	1		T13	5		T20	2
all_values[5]	auto[0]	auto[0]	auto[1]	76	1			T13	2		T16	3		T34	4
all_values[5]	auto[0]	auto[1]	auto[0]	107	1			T12	3		T20	2		T16	1
all_values[5]	auto[0]	auto[1]	auto[1]	67	1			T13	1		T34	3		T44	2
all_values[5]	auto[1]	auto[0]	auto[1]	160	1			T12	2		T13	3		T16	6
all_values[5]	auto[1]	auto[1]	auto[1]	101	1			T12	1		T16	2		T34	1
all_values[6]	auto[0]	auto[0]	auto[0]	160	1			T12	1		T13	2		T16	6
all_values[6]	auto[0]	auto[0]	auto[1]	70	1			T13	1		T20	1		T16	1
all_values[6]	auto[0]	auto[1]	auto[0]	113	1			T12	1		T13	4		T30	2
all_values[6]	auto[0]	auto[1]	auto[1]	59	1			T12	2		T13	2		T16	2
all_values[6]	auto[1]	auto[0]	auto[1]	130	1			T12	2		T13	1		T20	2
all_values[6]	auto[1]	auto[1]	auto[1]	134	1			T12	1		T13	1		T20	1
all_values[7]	auto[0]	auto[0]	auto[0]	122	1			T12	1		T13	1		T20	2
all_values[7]	auto[0]	auto[0]	auto[1]	65	1			T12	1		T13	1		T16	1
all_values[7]	auto[0]	auto[1]	auto[0]	131	1			T12	2		T13	2		T20	2
all_values[7]	auto[0]	auto[1]	auto[1]	64	1			T12	1		T13	2		T34	2
all_values[7]	auto[1]	auto[0]	auto[1]	149	1			T12	1		T13	1		T16	2
all_values[7]	auto[1]	auto[1]	auto[1]	135	1			T12	1		T13	4		T16	3
all_values[8]	auto[0]	auto[0]	auto[1]	215	1			T12	2		T13	2		T20	3
all_values[8]	auto[0]	auto[1]	auto[1]	176	1			T12	2		T13	2		T16	5
all_values[8]	auto[1]	auto[0]	auto[1]	152	1			T12	3		T13	5		T20	1
all_values[8]	auto[1]	auto[1]	auto[1]	123	1			T13	2		T30	1		T34	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal