Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.12 99.10 97.65 100.00 98.38 100.00 99.57


Total test records in report: 1235
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T217 /workspace/coverage/default/51.uart_fifo_reset.3187955357 Jun 26 06:12:47 PM PDT 24 Jun 26 06:13:29 PM PDT 24 184226274914 ps
T1032 /workspace/coverage/default/154.uart_fifo_reset.912778907 Jun 26 06:13:30 PM PDT 24 Jun 26 06:13:47 PM PDT 24 23834922641 ps
T1033 /workspace/coverage/default/43.uart_smoke.3866814766 Jun 26 06:12:21 PM PDT 24 Jun 26 06:12:30 PM PDT 24 6009179980 ps
T1034 /workspace/coverage/default/242.uart_fifo_reset.2727876681 Jun 26 06:13:58 PM PDT 24 Jun 26 06:16:03 PM PDT 24 80963776481 ps
T1035 /workspace/coverage/default/47.uart_rx_oversample.2975623595 Jun 26 06:12:36 PM PDT 24 Jun 26 06:13:07 PM PDT 24 4022103872 ps
T1036 /workspace/coverage/default/11.uart_loopback.363533059 Jun 26 06:10:24 PM PDT 24 Jun 26 06:10:40 PM PDT 24 7761144222 ps
T1037 /workspace/coverage/default/18.uart_fifo_overflow.2701902617 Jun 26 06:10:50 PM PDT 24 Jun 26 06:12:47 PM PDT 24 60198914864 ps
T1038 /workspace/coverage/default/36.uart_perf.1312132755 Jun 26 06:11:53 PM PDT 24 Jun 26 06:23:56 PM PDT 24 12960427501 ps
T58 /workspace/coverage/default/2.uart_stress_all_with_rand_reset.832765782 Jun 26 06:10:14 PM PDT 24 Jun 26 06:20:31 PM PDT 24 78264890830 ps
T218 /workspace/coverage/default/22.uart_fifo_reset.4258414960 Jun 26 06:11:05 PM PDT 24 Jun 26 06:11:58 PM PDT 24 42834068787 ps
T1039 /workspace/coverage/default/4.uart_fifo_overflow.3449689756 Jun 26 06:10:13 PM PDT 24 Jun 26 06:11:08 PM PDT 24 30438705121 ps
T1040 /workspace/coverage/default/205.uart_fifo_reset.2235929703 Jun 26 06:13:44 PM PDT 24 Jun 26 06:14:08 PM PDT 24 16077643370 ps
T1041 /workspace/coverage/default/8.uart_rx_oversample.282817509 Jun 26 06:10:24 PM PDT 24 Jun 26 06:11:07 PM PDT 24 4358392959 ps
T1042 /workspace/coverage/default/31.uart_smoke.1373491206 Jun 26 06:11:39 PM PDT 24 Jun 26 06:11:44 PM PDT 24 466185702 ps
T1043 /workspace/coverage/default/11.uart_alert_test.662551277 Jun 26 06:10:38 PM PDT 24 Jun 26 06:10:40 PM PDT 24 36839714 ps
T1044 /workspace/coverage/default/21.uart_stress_all.2650198544 Jun 26 06:11:02 PM PDT 24 Jun 26 06:13:29 PM PDT 24 98071270380 ps
T1045 /workspace/coverage/default/186.uart_fifo_reset.2452558250 Jun 26 06:13:33 PM PDT 24 Jun 26 06:13:45 PM PDT 24 15963978047 ps
T1046 /workspace/coverage/default/281.uart_fifo_reset.3828842325 Jun 26 06:14:09 PM PDT 24 Jun 26 06:15:22 PM PDT 24 45807065675 ps
T1047 /workspace/coverage/default/35.uart_fifo_overflow.3953690816 Jun 26 06:11:51 PM PDT 24 Jun 26 06:12:37 PM PDT 24 41161724310 ps
T1048 /workspace/coverage/default/41.uart_alert_test.1386121341 Jun 26 06:12:13 PM PDT 24 Jun 26 06:12:15 PM PDT 24 34544489 ps
T1049 /workspace/coverage/default/38.uart_loopback.3568735149 Jun 26 06:12:07 PM PDT 24 Jun 26 06:12:10 PM PDT 24 434181025 ps
T1050 /workspace/coverage/default/26.uart_fifo_overflow.1942889458 Jun 26 06:11:16 PM PDT 24 Jun 26 06:13:09 PM PDT 24 77116507746 ps
T224 /workspace/coverage/default/24.uart_fifo_reset.2235926071 Jun 26 06:11:38 PM PDT 24 Jun 26 06:12:24 PM PDT 24 134280225703 ps
T1051 /workspace/coverage/default/20.uart_fifo_full.2034736103 Jun 26 06:10:57 PM PDT 24 Jun 26 06:12:59 PM PDT 24 156308953940 ps
T1052 /workspace/coverage/default/185.uart_fifo_reset.2584830407 Jun 26 06:13:35 PM PDT 24 Jun 26 06:14:15 PM PDT 24 237520469715 ps
T1053 /workspace/coverage/default/30.uart_long_xfer_wo_dly.1066859888 Jun 26 06:11:39 PM PDT 24 Jun 26 06:17:08 PM PDT 24 111673742824 ps
T1054 /workspace/coverage/default/41.uart_stress_all.3676735455 Jun 26 06:12:10 PM PDT 24 Jun 26 06:18:45 PM PDT 24 62353693729 ps
T1055 /workspace/coverage/default/18.uart_alert_test.3672703127 Jun 26 06:10:54 PM PDT 24 Jun 26 06:10:57 PM PDT 24 11642371 ps
T1056 /workspace/coverage/default/29.uart_fifo_reset.2194316291 Jun 26 06:11:27 PM PDT 24 Jun 26 06:12:02 PM PDT 24 16920697596 ps
T1057 /workspace/coverage/default/3.uart_tx_rx.3086410775 Jun 26 06:10:11 PM PDT 24 Jun 26 06:11:34 PM PDT 24 46058294007 ps
T1058 /workspace/coverage/default/1.uart_stress_all.3760299582 Jun 26 06:10:11 PM PDT 24 Jun 26 06:11:13 PM PDT 24 138620979174 ps
T1059 /workspace/coverage/default/294.uart_fifo_reset.4157679485 Jun 26 06:14:18 PM PDT 24 Jun 26 06:14:59 PM PDT 24 49267652425 ps
T1060 /workspace/coverage/default/7.uart_intr.4961943 Jun 26 06:10:29 PM PDT 24 Jun 26 06:10:53 PM PDT 24 20810792493 ps
T1061 /workspace/coverage/default/29.uart_stress_all_with_rand_reset.3423394608 Jun 26 06:11:32 PM PDT 24 Jun 26 06:17:48 PM PDT 24 240126538818 ps
T1062 /workspace/coverage/default/41.uart_fifo_reset.2048891902 Jun 26 06:12:14 PM PDT 24 Jun 26 06:12:52 PM PDT 24 20344497109 ps
T1063 /workspace/coverage/default/133.uart_fifo_reset.378210822 Jun 26 06:13:22 PM PDT 24 Jun 26 06:13:38 PM PDT 24 31967247674 ps
T1064 /workspace/coverage/default/44.uart_rx_oversample.2781244591 Jun 26 06:12:20 PM PDT 24 Jun 26 06:12:33 PM PDT 24 5431326261 ps
T1065 /workspace/coverage/default/200.uart_fifo_reset.2297406054 Jun 26 06:13:43 PM PDT 24 Jun 26 06:15:17 PM PDT 24 57318359879 ps
T1066 /workspace/coverage/default/172.uart_fifo_reset.1602364074 Jun 26 06:13:35 PM PDT 24 Jun 26 06:13:54 PM PDT 24 40159379143 ps
T1067 /workspace/coverage/default/34.uart_smoke.3769703068 Jun 26 06:11:49 PM PDT 24 Jun 26 06:11:52 PM PDT 24 554205750 ps
T1068 /workspace/coverage/default/48.uart_fifo_full.2051414836 Jun 26 06:12:36 PM PDT 24 Jun 26 06:13:55 PM PDT 24 51987159849 ps
T1069 /workspace/coverage/default/224.uart_fifo_reset.1506038299 Jun 26 06:13:49 PM PDT 24 Jun 26 06:14:21 PM PDT 24 21846345090 ps
T1070 /workspace/coverage/default/30.uart_stress_all.983823037 Jun 26 06:11:39 PM PDT 24 Jun 26 06:15:30 PM PDT 24 1108866932589 ps
T1071 /workspace/coverage/default/35.uart_loopback.978667425 Jun 26 06:11:53 PM PDT 24 Jun 26 06:11:59 PM PDT 24 6104431731 ps
T1072 /workspace/coverage/default/5.uart_loopback.1368589437 Jun 26 06:10:26 PM PDT 24 Jun 26 06:10:36 PM PDT 24 4798249289 ps
T1073 /workspace/coverage/default/40.uart_tx_ovrd.2492436638 Jun 26 06:12:05 PM PDT 24 Jun 26 06:12:08 PM PDT 24 1893024139 ps
T1074 /workspace/coverage/default/4.uart_fifo_reset.3661184238 Jun 26 06:10:10 PM PDT 24 Jun 26 06:13:08 PM PDT 24 96578211502 ps
T1075 /workspace/coverage/default/14.uart_alert_test.3934584039 Jun 26 06:10:51 PM PDT 24 Jun 26 06:10:55 PM PDT 24 12594958 ps
T1076 /workspace/coverage/default/16.uart_fifo_reset.3306150949 Jun 26 06:10:44 PM PDT 24 Jun 26 06:11:43 PM PDT 24 196721287694 ps
T1077 /workspace/coverage/default/47.uart_long_xfer_wo_dly.676742902 Jun 26 06:12:39 PM PDT 24 Jun 26 06:14:52 PM PDT 24 83820249082 ps
T1078 /workspace/coverage/default/33.uart_fifo_reset.4067778130 Jun 26 06:11:49 PM PDT 24 Jun 26 06:12:22 PM PDT 24 20011147603 ps
T1079 /workspace/coverage/default/20.uart_perf.1790628360 Jun 26 06:10:58 PM PDT 24 Jun 26 06:21:02 PM PDT 24 11235008102 ps
T1080 /workspace/coverage/default/8.uart_rx_start_bit_filter.2547523605 Jun 26 06:10:29 PM PDT 24 Jun 26 06:10:32 PM PDT 24 1562541410 ps
T1081 /workspace/coverage/default/0.uart_tx_rx.3328775908 Jun 26 06:10:02 PM PDT 24 Jun 26 06:10:19 PM PDT 24 33880643916 ps
T1082 /workspace/coverage/default/19.uart_perf.3660554441 Jun 26 06:10:58 PM PDT 24 Jun 26 06:14:18 PM PDT 24 16186388958 ps
T1083 /workspace/coverage/default/217.uart_fifo_reset.3597825061 Jun 26 06:13:51 PM PDT 24 Jun 26 06:15:41 PM PDT 24 154885313347 ps
T1084 /workspace/coverage/default/48.uart_perf.3733885401 Jun 26 06:12:39 PM PDT 24 Jun 26 06:13:24 PM PDT 24 3435317678 ps
T1085 /workspace/coverage/default/1.uart_rx_start_bit_filter.2189381828 Jun 26 06:10:03 PM PDT 24 Jun 26 06:10:18 PM PDT 24 28929905659 ps
T1086 /workspace/coverage/default/45.uart_rx_start_bit_filter.869204961 Jun 26 06:12:29 PM PDT 24 Jun 26 06:12:35 PM PDT 24 2895900918 ps
T1087 /workspace/coverage/default/161.uart_fifo_reset.3500881058 Jun 26 06:13:32 PM PDT 24 Jun 26 06:13:47 PM PDT 24 7800203489 ps
T1088 /workspace/coverage/default/45.uart_long_xfer_wo_dly.871239838 Jun 26 06:12:30 PM PDT 24 Jun 26 06:25:05 PM PDT 24 114407259038 ps
T1089 /workspace/coverage/default/2.uart_stress_all.1778132005 Jun 26 06:10:14 PM PDT 24 Jun 26 06:12:34 PM PDT 24 262665670779 ps
T1090 /workspace/coverage/default/29.uart_tx_ovrd.3294862187 Jun 26 06:11:31 PM PDT 24 Jun 26 06:11:34 PM PDT 24 963888944 ps
T1091 /workspace/coverage/default/27.uart_tx_ovrd.1434408724 Jun 26 06:11:21 PM PDT 24 Jun 26 06:11:43 PM PDT 24 7239808845 ps
T1092 /workspace/coverage/default/15.uart_stress_all.2888730722 Jun 26 06:10:50 PM PDT 24 Jun 26 06:11:35 PM PDT 24 105347372865 ps
T1093 /workspace/coverage/default/16.uart_stress_all_with_rand_reset.1364763485 Jun 26 06:10:52 PM PDT 24 Jun 26 06:23:03 PM PDT 24 50696906895 ps
T1094 /workspace/coverage/default/21.uart_fifo_reset.4137287361 Jun 26 06:10:59 PM PDT 24 Jun 26 06:12:05 PM PDT 24 40031912465 ps
T1095 /workspace/coverage/default/280.uart_fifo_reset.3694268680 Jun 26 06:14:10 PM PDT 24 Jun 26 06:14:27 PM PDT 24 85896222547 ps
T1096 /workspace/coverage/default/13.uart_fifo_reset.1724506656 Jun 26 06:10:46 PM PDT 24 Jun 26 06:12:59 PM PDT 24 102501176745 ps
T1097 /workspace/coverage/default/38.uart_perf.3557998486 Jun 26 06:12:00 PM PDT 24 Jun 26 06:13:20 PM PDT 24 23145167389 ps
T71 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3919414527 Jun 26 05:53:18 PM PDT 24 Jun 26 05:53:20 PM PDT 24 68905584 ps
T1098 /workspace/coverage/cover_reg_top/29.uart_intr_test.2830909698 Jun 26 05:53:46 PM PDT 24 Jun 26 05:53:49 PM PDT 24 27611988 ps
T61 /workspace/coverage/cover_reg_top/17.uart_csr_rw.3291881461 Jun 26 05:53:35 PM PDT 24 Jun 26 05:53:37 PM PDT 24 24308386 ps
T1099 /workspace/coverage/cover_reg_top/48.uart_intr_test.2516266202 Jun 26 05:53:43 PM PDT 24 Jun 26 05:53:45 PM PDT 24 59946987 ps
T1100 /workspace/coverage/cover_reg_top/4.uart_intr_test.3368431591 Jun 26 05:53:10 PM PDT 24 Jun 26 05:53:12 PM PDT 24 46943684 ps
T1101 /workspace/coverage/cover_reg_top/39.uart_intr_test.3426131519 Jun 26 05:53:41 PM PDT 24 Jun 26 05:53:42 PM PDT 24 42229618 ps
T53 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3911255271 Jun 26 05:53:03 PM PDT 24 Jun 26 05:53:07 PM PDT 24 1647695324 ps
T1102 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.973650108 Jun 26 05:53:03 PM PDT 24 Jun 26 05:53:05 PM PDT 24 24033537 ps
T1103 /workspace/coverage/cover_reg_top/19.uart_tl_errors.1898713463 Jun 26 05:53:35 PM PDT 24 Jun 26 05:53:37 PM PDT 24 27807773 ps
T62 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3115003552 Jun 26 05:53:36 PM PDT 24 Jun 26 05:53:38 PM PDT 24 56217994 ps
T1104 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3657224057 Jun 26 05:53:11 PM PDT 24 Jun 26 05:53:13 PM PDT 24 79902753 ps
T1105 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.977862029 Jun 26 05:53:36 PM PDT 24 Jun 26 05:53:37 PM PDT 24 37307864 ps
T1106 /workspace/coverage/cover_reg_top/5.uart_tl_errors.3549720798 Jun 26 05:53:10 PM PDT 24 Jun 26 05:53:13 PM PDT 24 38979579 ps
T1107 /workspace/coverage/cover_reg_top/9.uart_intr_test.2798325110 Jun 26 05:53:20 PM PDT 24 Jun 26 05:53:23 PM PDT 24 70990462 ps
T72 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3535412911 Jun 26 05:52:55 PM PDT 24 Jun 26 05:52:57 PM PDT 24 86470028 ps
T1108 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.181460390 Jun 26 05:53:12 PM PDT 24 Jun 26 05:53:16 PM PDT 24 86800053 ps
T73 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3977860642 Jun 26 05:53:27 PM PDT 24 Jun 26 05:53:30 PM PDT 24 210966812 ps
T75 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2483956563 Jun 26 05:53:29 PM PDT 24 Jun 26 05:53:32 PM PDT 24 316905622 ps
T63 /workspace/coverage/cover_reg_top/18.uart_csr_rw.328557497 Jun 26 05:53:35 PM PDT 24 Jun 26 05:53:37 PM PDT 24 19129005 ps
T1109 /workspace/coverage/cover_reg_top/15.uart_intr_test.3681940989 Jun 26 05:53:26 PM PDT 24 Jun 26 05:53:29 PM PDT 24 11832780 ps
T1110 /workspace/coverage/cover_reg_top/38.uart_intr_test.4180099012 Jun 26 05:53:43 PM PDT 24 Jun 26 05:53:44 PM PDT 24 58518351 ps
T1111 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3804882072 Jun 26 05:53:11 PM PDT 24 Jun 26 05:53:13 PM PDT 24 13013233 ps
T64 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2842701740 Jun 26 05:52:57 PM PDT 24 Jun 26 05:52:59 PM PDT 24 57012587 ps
T1112 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3061665665 Jun 26 05:53:19 PM PDT 24 Jun 26 05:53:21 PM PDT 24 75353558 ps
T1113 /workspace/coverage/cover_reg_top/30.uart_intr_test.3822617801 Jun 26 05:53:44 PM PDT 24 Jun 26 05:53:46 PM PDT 24 15443295 ps
T77 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2644947979 Jun 26 05:53:06 PM PDT 24 Jun 26 05:53:08 PM PDT 24 881644894 ps
T1114 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.659189005 Jun 26 05:53:01 PM PDT 24 Jun 26 05:53:03 PM PDT 24 16377673 ps
T78 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3270218717 Jun 26 05:53:11 PM PDT 24 Jun 26 05:53:14 PM PDT 24 177492837 ps
T1115 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.650586692 Jun 26 05:53:35 PM PDT 24 Jun 26 05:53:36 PM PDT 24 93199117 ps
T1116 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2119276764 Jun 26 05:53:18 PM PDT 24 Jun 26 05:53:20 PM PDT 24 608981887 ps
T65 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.122217596 Jun 26 05:53:04 PM PDT 24 Jun 26 05:53:06 PM PDT 24 12200967 ps
T1117 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2253825012 Jun 26 05:53:26 PM PDT 24 Jun 26 05:53:29 PM PDT 24 165862251 ps
T1118 /workspace/coverage/cover_reg_top/32.uart_intr_test.512695119 Jun 26 05:53:41 PM PDT 24 Jun 26 05:53:43 PM PDT 24 13158176 ps
T1119 /workspace/coverage/cover_reg_top/9.uart_csr_rw.2191456762 Jun 26 05:53:18 PM PDT 24 Jun 26 05:53:20 PM PDT 24 63960993 ps
T1120 /workspace/coverage/cover_reg_top/13.uart_tl_errors.2526490085 Jun 26 05:53:20 PM PDT 24 Jun 26 05:53:24 PM PDT 24 74982231 ps
T66 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.38358794 Jun 26 05:53:13 PM PDT 24 Jun 26 05:53:16 PM PDT 24 145237532 ps
T59 /workspace/coverage/cover_reg_top/13.uart_csr_rw.1853733170 Jun 26 05:53:26 PM PDT 24 Jun 26 05:53:28 PM PDT 24 20701226 ps
T1121 /workspace/coverage/cover_reg_top/0.uart_csr_rw.195918095 Jun 26 05:52:56 PM PDT 24 Jun 26 05:52:58 PM PDT 24 16108684 ps
T1122 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1786634472 Jun 26 05:53:33 PM PDT 24 Jun 26 05:53:34 PM PDT 24 202096883 ps
T1123 /workspace/coverage/cover_reg_top/18.uart_tl_errors.411877713 Jun 26 05:53:32 PM PDT 24 Jun 26 05:53:35 PM PDT 24 38507547 ps
T67 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1869188632 Jun 26 05:53:26 PM PDT 24 Jun 26 05:53:29 PM PDT 24 19456460 ps
T1124 /workspace/coverage/cover_reg_top/2.uart_tl_errors.3065672877 Jun 26 05:53:02 PM PDT 24 Jun 26 05:53:05 PM PDT 24 46076085 ps
T1125 /workspace/coverage/cover_reg_top/14.uart_intr_test.295371722 Jun 26 05:53:26 PM PDT 24 Jun 26 05:53:28 PM PDT 24 66949604 ps
T1126 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3033481026 Jun 26 05:53:27 PM PDT 24 Jun 26 05:53:29 PM PDT 24 426406824 ps
T1127 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1170449209 Jun 26 05:53:18 PM PDT 24 Jun 26 05:53:20 PM PDT 24 288048807 ps
T1128 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3052523566 Jun 26 05:53:26 PM PDT 24 Jun 26 05:53:29 PM PDT 24 18865604 ps
T1129 /workspace/coverage/cover_reg_top/12.uart_tl_errors.696963273 Jun 26 05:53:22 PM PDT 24 Jun 26 05:53:26 PM PDT 24 65188841 ps
T76 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1912800093 Jun 26 05:52:54 PM PDT 24 Jun 26 05:52:56 PM PDT 24 171008898 ps
T68 /workspace/coverage/cover_reg_top/8.uart_csr_rw.3540264479 Jun 26 05:53:18 PM PDT 24 Jun 26 05:53:20 PM PDT 24 49340363 ps
T1130 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.138015198 Jun 26 05:53:46 PM PDT 24 Jun 26 05:53:48 PM PDT 24 52501607 ps
T1131 /workspace/coverage/cover_reg_top/26.uart_intr_test.2066269266 Jun 26 05:53:44 PM PDT 24 Jun 26 05:53:47 PM PDT 24 39374240 ps
T79 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1074211370 Jun 26 05:53:46 PM PDT 24 Jun 26 05:53:49 PM PDT 24 96694547 ps
T69 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.200582362 Jun 26 05:53:26 PM PDT 24 Jun 26 05:53:28 PM PDT 24 25949335 ps
T1132 /workspace/coverage/cover_reg_top/40.uart_intr_test.3745240049 Jun 26 05:53:42 PM PDT 24 Jun 26 05:53:44 PM PDT 24 15764282 ps
T1133 /workspace/coverage/cover_reg_top/7.uart_tl_errors.4136683210 Jun 26 05:53:11 PM PDT 24 Jun 26 05:53:15 PM PDT 24 143361816 ps
T74 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1932014701 Jun 26 05:53:23 PM PDT 24 Jun 26 05:53:26 PM PDT 24 270824609 ps
T1134 /workspace/coverage/cover_reg_top/5.uart_intr_test.2772823636 Jun 26 05:53:11 PM PDT 24 Jun 26 05:53:14 PM PDT 24 25905665 ps
T1135 /workspace/coverage/cover_reg_top/44.uart_intr_test.4240222887 Jun 26 05:53:42 PM PDT 24 Jun 26 05:53:44 PM PDT 24 18996535 ps
T1136 /workspace/coverage/cover_reg_top/7.uart_intr_test.397090544 Jun 26 05:53:11 PM PDT 24 Jun 26 05:53:14 PM PDT 24 42597606 ps
T1137 /workspace/coverage/cover_reg_top/10.uart_csr_rw.2672238344 Jun 26 05:53:20 PM PDT 24 Jun 26 05:53:22 PM PDT 24 41065370 ps
T1138 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.520297115 Jun 26 05:52:56 PM PDT 24 Jun 26 05:52:58 PM PDT 24 12557292 ps
T1139 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.11070070 Jun 26 05:53:00 PM PDT 24 Jun 26 05:53:02 PM PDT 24 56238543 ps
T1140 /workspace/coverage/cover_reg_top/21.uart_intr_test.2590624836 Jun 26 05:53:44 PM PDT 24 Jun 26 05:53:46 PM PDT 24 18864490 ps
T108 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3818361838 Jun 26 05:53:11 PM PDT 24 Jun 26 05:53:13 PM PDT 24 190681186 ps
T1141 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3487208594 Jun 26 05:53:38 PM PDT 24 Jun 26 05:53:39 PM PDT 24 48095636 ps
T1142 /workspace/coverage/cover_reg_top/15.uart_csr_rw.1470912978 Jun 26 05:53:26 PM PDT 24 Jun 26 05:53:28 PM PDT 24 14445559 ps
T1143 /workspace/coverage/cover_reg_top/12.uart_csr_rw.1643626802 Jun 26 05:53:23 PM PDT 24 Jun 26 05:53:26 PM PDT 24 57057159 ps
T60 /workspace/coverage/cover_reg_top/7.uart_csr_rw.2450770302 Jun 26 05:53:11 PM PDT 24 Jun 26 05:53:14 PM PDT 24 16606760 ps
T1144 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3960389931 Jun 26 05:53:11 PM PDT 24 Jun 26 05:53:16 PM PDT 24 3558227296 ps
T1145 /workspace/coverage/cover_reg_top/20.uart_intr_test.3118325945 Jun 26 05:53:45 PM PDT 24 Jun 26 05:53:47 PM PDT 24 29342605 ps
T1146 /workspace/coverage/cover_reg_top/34.uart_intr_test.172813529 Jun 26 05:53:46 PM PDT 24 Jun 26 05:53:48 PM PDT 24 13919659 ps
T1147 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.13965251 Jun 26 05:53:01 PM PDT 24 Jun 26 05:53:03 PM PDT 24 44741874 ps
T1148 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3126935169 Jun 26 05:53:12 PM PDT 24 Jun 26 05:53:15 PM PDT 24 20332384 ps
T1149 /workspace/coverage/cover_reg_top/15.uart_tl_errors.4194846910 Jun 26 05:53:27 PM PDT 24 Jun 26 05:53:31 PM PDT 24 244966269 ps
T54 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.322291290 Jun 26 05:52:57 PM PDT 24 Jun 26 05:52:59 PM PDT 24 15058474 ps
T1150 /workspace/coverage/cover_reg_top/3.uart_csr_rw.1162976173 Jun 26 05:53:02 PM PDT 24 Jun 26 05:53:04 PM PDT 24 11763670 ps
T1151 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2371539434 Jun 26 05:53:10 PM PDT 24 Jun 26 05:53:13 PM PDT 24 45263682 ps
T1152 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2259800164 Jun 26 05:53:32 PM PDT 24 Jun 26 05:53:34 PM PDT 24 43825608 ps
T55 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2620810386 Jun 26 05:53:01 PM PDT 24 Jun 26 05:53:04 PM PDT 24 34600554 ps
T1153 /workspace/coverage/cover_reg_top/0.uart_tl_errors.1019349976 Jun 26 05:52:57 PM PDT 24 Jun 26 05:53:00 PM PDT 24 379572807 ps
T1154 /workspace/coverage/cover_reg_top/43.uart_intr_test.332943460 Jun 26 05:53:45 PM PDT 24 Jun 26 05:53:48 PM PDT 24 50070509 ps
T1155 /workspace/coverage/cover_reg_top/25.uart_intr_test.4046019343 Jun 26 05:53:42 PM PDT 24 Jun 26 05:53:43 PM PDT 24 20842979 ps
T1156 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1700493374 Jun 26 05:53:02 PM PDT 24 Jun 26 05:53:04 PM PDT 24 36287799 ps
T1157 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1442908018 Jun 26 05:53:01 PM PDT 24 Jun 26 05:53:03 PM PDT 24 177064567 ps
T1158 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1279815585 Jun 26 05:53:11 PM PDT 24 Jun 26 05:53:14 PM PDT 24 31824796 ps
T1159 /workspace/coverage/cover_reg_top/14.uart_tl_errors.2309893216 Jun 26 05:53:28 PM PDT 24 Jun 26 05:53:31 PM PDT 24 387101690 ps
T1160 /workspace/coverage/cover_reg_top/49.uart_intr_test.3229738014 Jun 26 05:53:42 PM PDT 24 Jun 26 05:53:44 PM PDT 24 25153334 ps
T1161 /workspace/coverage/cover_reg_top/13.uart_intr_test.1911566101 Jun 26 05:53:29 PM PDT 24 Jun 26 05:53:31 PM PDT 24 10819299 ps
T1162 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2857121514 Jun 26 05:53:11 PM PDT 24 Jun 26 05:53:14 PM PDT 24 14021299 ps
T1163 /workspace/coverage/cover_reg_top/1.uart_tl_errors.1274050932 Jun 26 05:52:56 PM PDT 24 Jun 26 05:52:58 PM PDT 24 59540917 ps
T1164 /workspace/coverage/cover_reg_top/37.uart_intr_test.2203069013 Jun 26 05:53:43 PM PDT 24 Jun 26 05:53:45 PM PDT 24 45667094 ps
T1165 /workspace/coverage/cover_reg_top/16.uart_intr_test.3755130585 Jun 26 05:53:34 PM PDT 24 Jun 26 05:53:36 PM PDT 24 15825875 ps
T1166 /workspace/coverage/cover_reg_top/16.uart_csr_rw.3537251519 Jun 26 05:53:36 PM PDT 24 Jun 26 05:53:37 PM PDT 24 14292740 ps
T1167 /workspace/coverage/cover_reg_top/17.uart_intr_test.882032035 Jun 26 05:53:34 PM PDT 24 Jun 26 05:53:36 PM PDT 24 21279164 ps
T1168 /workspace/coverage/cover_reg_top/11.uart_intr_test.3572929257 Jun 26 05:53:23 PM PDT 24 Jun 26 05:53:26 PM PDT 24 12515523 ps
T1169 /workspace/coverage/cover_reg_top/11.uart_tl_errors.3042897963 Jun 26 05:53:19 PM PDT 24 Jun 26 05:53:21 PM PDT 24 69002655 ps
T1170 /workspace/coverage/cover_reg_top/24.uart_intr_test.1878447376 Jun 26 05:53:45 PM PDT 24 Jun 26 05:53:47 PM PDT 24 25808884 ps
T80 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3029891293 Jun 26 05:53:03 PM PDT 24 Jun 26 05:53:06 PM PDT 24 53009526 ps
T1171 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.969882102 Jun 26 05:53:20 PM PDT 24 Jun 26 05:53:23 PM PDT 24 55213977 ps
T1172 /workspace/coverage/cover_reg_top/8.uart_tl_errors.661681375 Jun 26 05:53:20 PM PDT 24 Jun 26 05:53:25 PM PDT 24 587542128 ps
T1173 /workspace/coverage/cover_reg_top/36.uart_intr_test.1112411400 Jun 26 05:53:44 PM PDT 24 Jun 26 05:53:45 PM PDT 24 41457579 ps
T1174 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2221025077 Jun 26 05:53:22 PM PDT 24 Jun 26 05:53:25 PM PDT 24 41259063 ps
T1175 /workspace/coverage/cover_reg_top/11.uart_csr_rw.1924157690 Jun 26 05:53:20 PM PDT 24 Jun 26 05:53:23 PM PDT 24 13216637 ps
T1176 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.354737813 Jun 26 05:53:20 PM PDT 24 Jun 26 05:53:23 PM PDT 24 30172141 ps
T1177 /workspace/coverage/cover_reg_top/10.uart_intr_test.530098522 Jun 26 05:53:19 PM PDT 24 Jun 26 05:53:22 PM PDT 24 149164661 ps
T1178 /workspace/coverage/cover_reg_top/31.uart_intr_test.4235601904 Jun 26 05:53:46 PM PDT 24 Jun 26 05:53:49 PM PDT 24 66622655 ps
T1179 /workspace/coverage/cover_reg_top/12.uart_intr_test.675143670 Jun 26 05:53:19 PM PDT 24 Jun 26 05:53:21 PM PDT 24 31088708 ps
T1180 /workspace/coverage/cover_reg_top/45.uart_intr_test.2809280299 Jun 26 05:53:45 PM PDT 24 Jun 26 05:53:47 PM PDT 24 25499486 ps
T1181 /workspace/coverage/cover_reg_top/19.uart_intr_test.486385165 Jun 26 05:53:43 PM PDT 24 Jun 26 05:53:44 PM PDT 24 19820030 ps
T1182 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1705753915 Jun 26 05:53:12 PM PDT 24 Jun 26 05:53:16 PM PDT 24 96023252 ps
T1183 /workspace/coverage/cover_reg_top/14.uart_csr_rw.417773043 Jun 26 05:53:27 PM PDT 24 Jun 26 05:53:29 PM PDT 24 14422298 ps
T1184 /workspace/coverage/cover_reg_top/16.uart_tl_errors.936530612 Jun 26 05:53:27 PM PDT 24 Jun 26 05:53:30 PM PDT 24 31880295 ps
T1185 /workspace/coverage/cover_reg_top/1.uart_intr_test.405058848 Jun 26 05:52:54 PM PDT 24 Jun 26 05:52:55 PM PDT 24 27959423 ps
T1186 /workspace/coverage/cover_reg_top/23.uart_intr_test.2451336537 Jun 26 05:53:44 PM PDT 24 Jun 26 05:53:46 PM PDT 24 16506699 ps
T1187 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.915589185 Jun 26 05:53:36 PM PDT 24 Jun 26 05:53:38 PM PDT 24 1078766094 ps
T1188 /workspace/coverage/cover_reg_top/33.uart_intr_test.515420773 Jun 26 05:53:44 PM PDT 24 Jun 26 05:53:46 PM PDT 24 11384276 ps
T1189 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1705550481 Jun 26 05:53:01 PM PDT 24 Jun 26 05:53:03 PM PDT 24 15426282 ps
T1190 /workspace/coverage/cover_reg_top/5.uart_csr_rw.2465911905 Jun 26 05:53:10 PM PDT 24 Jun 26 05:53:11 PM PDT 24 50110732 ps
T1191 /workspace/coverage/cover_reg_top/46.uart_intr_test.2813577823 Jun 26 05:53:46 PM PDT 24 Jun 26 05:53:49 PM PDT 24 26388361 ps
T1192 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2196373310 Jun 26 05:53:00 PM PDT 24 Jun 26 05:53:01 PM PDT 24 21690064 ps
T1193 /workspace/coverage/cover_reg_top/4.uart_csr_rw.3308072785 Jun 26 05:53:11 PM PDT 24 Jun 26 05:53:13 PM PDT 24 14908616 ps
T1194 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.951044487 Jun 26 05:53:34 PM PDT 24 Jun 26 05:53:36 PM PDT 24 103252302 ps
T1195 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3125157753 Jun 26 05:53:22 PM PDT 24 Jun 26 05:53:25 PM PDT 24 18366407 ps
T1196 /workspace/coverage/cover_reg_top/8.uart_intr_test.4079876731 Jun 26 05:53:20 PM PDT 24 Jun 26 05:53:22 PM PDT 24 14686003 ps
T1197 /workspace/coverage/cover_reg_top/9.uart_tl_errors.1153487941 Jun 26 05:53:19 PM PDT 24 Jun 26 05:53:22 PM PDT 24 95515714 ps
T1198 /workspace/coverage/cover_reg_top/3.uart_tl_errors.433478917 Jun 26 05:53:02 PM PDT 24 Jun 26 05:53:06 PM PDT 24 40739809 ps
T1199 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2166127165 Jun 26 05:53:11 PM PDT 24 Jun 26 05:53:14 PM PDT 24 189864604 ps
T1200 /workspace/coverage/cover_reg_top/3.uart_intr_test.357864871 Jun 26 05:53:05 PM PDT 24 Jun 26 05:53:06 PM PDT 24 21375772 ps
T1201 /workspace/coverage/cover_reg_top/27.uart_intr_test.2859589240 Jun 26 05:53:45 PM PDT 24 Jun 26 05:53:47 PM PDT 24 11078494 ps
T1202 /workspace/coverage/cover_reg_top/28.uart_intr_test.1082500592 Jun 26 05:53:43 PM PDT 24 Jun 26 05:53:45 PM PDT 24 14235731 ps
T1203 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1513127329 Jun 26 05:53:04 PM PDT 24 Jun 26 05:53:06 PM PDT 24 18743042 ps
T1204 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3476153069 Jun 26 05:53:18 PM PDT 24 Jun 26 05:53:20 PM PDT 24 32232701 ps
T1205 /workspace/coverage/cover_reg_top/10.uart_tl_errors.1733957230 Jun 26 05:53:20 PM PDT 24 Jun 26 05:53:23 PM PDT 24 51418072 ps
T1206 /workspace/coverage/cover_reg_top/18.uart_intr_test.2389732110 Jun 26 05:53:36 PM PDT 24 Jun 26 05:53:38 PM PDT 24 30480505 ps
T1207 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1630239220 Jun 26 05:53:23 PM PDT 24 Jun 26 05:53:26 PM PDT 24 107723670 ps
T1208 /workspace/coverage/cover_reg_top/47.uart_intr_test.3183891054 Jun 26 05:53:46 PM PDT 24 Jun 26 05:53:49 PM PDT 24 47860735 ps
T1209 /workspace/coverage/cover_reg_top/0.uart_intr_test.4109608366 Jun 26 05:53:00 PM PDT 24 Jun 26 05:53:02 PM PDT 24 16854085 ps
T1210 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3701571644 Jun 26 05:53:16 PM PDT 24 Jun 26 05:53:18 PM PDT 24 17721874 ps
T1211 /workspace/coverage/cover_reg_top/42.uart_intr_test.4157329345 Jun 26 05:53:43 PM PDT 24 Jun 26 05:53:45 PM PDT 24 16748546 ps
T1212 /workspace/coverage/cover_reg_top/35.uart_intr_test.3379612794 Jun 26 05:55:08 PM PDT 24 Jun 26 05:55:12 PM PDT 24 16035921 ps
T1213 /workspace/coverage/cover_reg_top/41.uart_intr_test.1904896274 Jun 26 05:53:44 PM PDT 24 Jun 26 05:53:47 PM PDT 24 27588630 ps
T1214 /workspace/coverage/cover_reg_top/4.uart_tl_errors.2336444755 Jun 26 05:53:12 PM PDT 24 Jun 26 05:53:16 PM PDT 24 95650313 ps
T1215 /workspace/coverage/cover_reg_top/6.uart_intr_test.1323408418 Jun 26 05:53:12 PM PDT 24 Jun 26 05:53:15 PM PDT 24 31015224 ps
T1216 /workspace/coverage/cover_reg_top/6.uart_tl_errors.1624507349 Jun 26 05:53:10 PM PDT 24 Jun 26 05:53:12 PM PDT 24 51844378 ps
T1217 /workspace/coverage/cover_reg_top/1.uart_csr_rw.1735804454 Jun 26 05:52:57 PM PDT 24 Jun 26 05:52:59 PM PDT 24 18915811 ps
T1218 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3293870016 Jun 26 05:53:22 PM PDT 24 Jun 26 05:53:25 PM PDT 24 190170799 ps
T1219 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1650148573 Jun 26 05:53:19 PM PDT 24 Jun 26 05:53:21 PM PDT 24 82881018 ps
T1220 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2318526096 Jun 26 05:53:02 PM PDT 24 Jun 26 05:53:04 PM PDT 24 40937374 ps
T1221 /workspace/coverage/cover_reg_top/2.uart_csr_rw.822466267 Jun 26 05:53:01 PM PDT 24 Jun 26 05:53:02 PM PDT 24 15352019 ps
T1222 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1924802818 Jun 26 05:53:28 PM PDT 24 Jun 26 05:53:30 PM PDT 24 13437131 ps
T1223 /workspace/coverage/cover_reg_top/22.uart_intr_test.2340297710 Jun 26 05:53:44 PM PDT 24 Jun 26 05:53:46 PM PDT 24 15064137 ps
T1224 /workspace/coverage/cover_reg_top/17.uart_tl_errors.3682424596 Jun 26 05:53:33 PM PDT 24 Jun 26 05:53:36 PM PDT 24 187669355 ps
T1225 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.335903644 Jun 26 05:52:55 PM PDT 24 Jun 26 05:52:57 PM PDT 24 23346967 ps
T1226 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2361569366 Jun 26 05:53:02 PM PDT 24 Jun 26 05:53:04 PM PDT 24 17657970 ps
T1227 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.4275921169 Jun 26 05:53:46 PM PDT 24 Jun 26 05:53:49 PM PDT 24 111501683 ps
T1228 /workspace/coverage/cover_reg_top/19.uart_csr_rw.280176729 Jun 26 05:53:44 PM PDT 24 Jun 26 05:53:46 PM PDT 24 106441661 ps
T1229 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.437380605 Jun 26 05:53:19 PM PDT 24 Jun 26 05:53:21 PM PDT 24 85903059 ps
T1230 /workspace/coverage/cover_reg_top/2.uart_intr_test.4228835417 Jun 26 05:53:02 PM PDT 24 Jun 26 05:53:04 PM PDT 24 14315108 ps
T1231 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3086909407 Jun 26 05:53:12 PM PDT 24 Jun 26 05:53:15 PM PDT 24 34915643 ps
T1232 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1397275169 Jun 26 05:53:20 PM PDT 24 Jun 26 05:53:22 PM PDT 24 19960568 ps
T1233 /workspace/coverage/cover_reg_top/6.uart_csr_rw.3202561972 Jun 26 05:53:12 PM PDT 24 Jun 26 05:53:15 PM PDT 24 55697956 ps
T1234 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.4293629609 Jun 26 05:53:37 PM PDT 24 Jun 26 05:53:39 PM PDT 24 72233360 ps
T56 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2052028269 Jun 26 05:52:58 PM PDT 24 Jun 26 05:53:01 PM PDT 24 213669448 ps
T57 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1206544987 Jun 26 05:53:02 PM PDT 24 Jun 26 05:53:06 PM PDT 24 260152726 ps
T1235 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.810012765 Jun 26 05:53:11 PM PDT 24 Jun 26 05:53:13 PM PDT 24 37034482 ps

Test location /workspace/coverage/default/13.uart_intr.2197849415
Short name T9
Test name
Test status
Simulation time 40529697278 ps
CPU time 21.39 seconds
Started Jun 26 06:10:32 PM PDT 24
Finished Jun 26 06:10:56 PM PDT 24
Peak memory 199880 kb
Host smart-324eb810-6480-4c3f-bd8b-bdfe95ca1fdb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197849415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2197849415
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.2027871575
Short name T16
Test name
Test status
Simulation time 192303435262 ps
CPU time 1728.5 seconds
Started Jun 26 06:11:59 PM PDT 24
Finished Jun 26 06:40:50 PM PDT 24
Peak memory 224708 kb
Host smart-abe4cdb9-bcac-4d03-b286-8470beedde5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027871575 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.2027871575
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.1679855447
Short name T12
Test name
Test status
Simulation time 88714805149 ps
CPU time 1424.84 seconds
Started Jun 26 06:12:55 PM PDT 24
Finished Jun 26 06:36:43 PM PDT 24
Peak memory 216520 kb
Host smart-37cfa957-ecfa-42b8-bc94-873c3f3fb9bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679855447 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.1679855447
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.2116125963
Short name T45
Test name
Test status
Simulation time 249288673513 ps
CPU time 1102.63 seconds
Started Jun 26 06:11:09 PM PDT 24
Finished Jun 26 06:29:32 PM PDT 24
Peak memory 216096 kb
Host smart-6a3be4ac-2ba6-4ae6-9a86-0cc5e77a83b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116125963 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.2116125963
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.1735699133
Short name T34
Test name
Test status
Simulation time 382455653142 ps
CPU time 972.89 seconds
Started Jun 26 06:13:05 PM PDT 24
Finished Jun 26 06:29:19 PM PDT 24
Peak memory 216468 kb
Host smart-f7e49c35-d929-4d19-b5ed-acb7998f1409
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735699133 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.1735699133
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.98894151
Short name T7
Test name
Test status
Simulation time 141562254373 ps
CPU time 130.33 seconds
Started Jun 26 06:10:05 PM PDT 24
Finished Jun 26 06:12:17 PM PDT 24
Peak memory 199988 kb
Host smart-bd44a262-b843-495a-a8bb-7030d344d49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98894151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.98894151
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_stress_all.3630140514
Short name T23
Test name
Test status
Simulation time 117247997239 ps
CPU time 722.14 seconds
Started Jun 26 06:10:25 PM PDT 24
Finished Jun 26 06:22:30 PM PDT 24
Peak memory 199916 kb
Host smart-3a8cf8dd-6caf-4a14-a203-9ff8824f62be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630140514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3630140514
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_sec_cm.231384550
Short name T27
Test name
Test status
Simulation time 72212851 ps
CPU time 0.85 seconds
Started Jun 26 06:10:02 PM PDT 24
Finished Jun 26 06:10:04 PM PDT 24
Peak memory 218436 kb
Host smart-b405d14e-f739-400d-a6c4-6cb62a9801e7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231384550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.231384550
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/36.uart_stress_all.260772721
Short name T105
Test name
Test status
Simulation time 102583507151 ps
CPU time 516.87 seconds
Started Jun 26 06:11:53 PM PDT 24
Finished Jun 26 06:20:31 PM PDT 24
Peak memory 199888 kb
Host smart-013cf0d0-cf96-4037-b2e5-bbd26a611cc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260772721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.260772721
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1167211189
Short name T94
Test name
Test status
Simulation time 1450525728705 ps
CPU time 458.49 seconds
Started Jun 26 06:10:44 PM PDT 24
Finished Jun 26 06:18:24 PM PDT 24
Peak memory 216436 kb
Host smart-0bd0b010-4958-4273-a165-eeabf769a4d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167211189 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1167211189
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_stress_all.2313014097
Short name T129
Test name
Test status
Simulation time 506644052148 ps
CPU time 628.36 seconds
Started Jun 26 06:10:22 PM PDT 24
Finished Jun 26 06:20:53 PM PDT 24
Peak memory 199896 kb
Host smart-8e26e9f7-c286-44fa-8815-d587917b65e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313014097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2313014097
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_fifo_full.785468646
Short name T243
Test name
Test status
Simulation time 109536324678 ps
CPU time 49.58 seconds
Started Jun 26 06:10:16 PM PDT 24
Finished Jun 26 06:11:08 PM PDT 24
Peak memory 199912 kb
Host smart-0d1b0025-832e-4845-870b-ad5c648a08b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785468646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.785468646
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_stress_all.2401148417
Short name T166
Test name
Test status
Simulation time 103222313987 ps
CPU time 258.96 seconds
Started Jun 26 06:12:29 PM PDT 24
Finished Jun 26 06:16:49 PM PDT 24
Peak memory 199768 kb
Host smart-aea35799-286f-443e-8524-2187f3eae930
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401148417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2401148417
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.407473215
Short name T170
Test name
Test status
Simulation time 129180278787 ps
CPU time 160.4 seconds
Started Jun 26 06:13:18 PM PDT 24
Finished Jun 26 06:16:00 PM PDT 24
Peak memory 200004 kb
Host smart-a1e254f9-9552-4aab-8b0b-a2cbbaa1bfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407473215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.407473215
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.1183886465
Short name T112
Test name
Test status
Simulation time 67234063737 ps
CPU time 71.11 seconds
Started Jun 26 06:12:32 PM PDT 24
Finished Jun 26 06:13:44 PM PDT 24
Peak memory 199764 kb
Host smart-64446ced-8ef3-4549-b461-6b86c8349fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183886465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1183886465
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3919414527
Short name T71
Test name
Test status
Simulation time 68905584 ps
CPU time 0.97 seconds
Started Jun 26 05:53:18 PM PDT 24
Finished Jun 26 05:53:20 PM PDT 24
Peak memory 199324 kb
Host smart-99c7af27-8dca-4dd1-acc2-a7642053ce43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919414527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3919414527
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.3012844411
Short name T121
Test name
Test status
Simulation time 114443253790 ps
CPU time 45.56 seconds
Started Jun 26 06:13:36 PM PDT 24
Finished Jun 26 06:14:22 PM PDT 24
Peak memory 199984 kb
Host smart-fc46af29-6896-4901-bb8f-16f48e8ab234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012844411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.3012844411
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_tx_rx.2806203288
Short name T1
Test name
Test status
Simulation time 90559430399 ps
CPU time 37.83 seconds
Started Jun 26 06:10:19 PM PDT 24
Finished Jun 26 06:10:59 PM PDT 24
Peak memory 199924 kb
Host smart-19d345f3-38ae-4d92-88be-67b047c1eb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806203288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.2806203288
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.2432740906
Short name T187
Test name
Test status
Simulation time 55644771554 ps
CPU time 628.21 seconds
Started Jun 26 06:12:47 PM PDT 24
Finished Jun 26 06:23:16 PM PDT 24
Peak memory 216556 kb
Host smart-7334e0be-cfae-4e61-bbed-d7f6d24530ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432740906 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.2432740906
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_alert_test.2984092188
Short name T349
Test name
Test status
Simulation time 14949728 ps
CPU time 0.62 seconds
Started Jun 26 06:10:09 PM PDT 24
Finished Jun 26 06:10:13 PM PDT 24
Peak memory 195304 kb
Host smart-21f8efe3-269f-4989-913c-2fa8de75b2e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984092188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2984092188
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.4174057568
Short name T92
Test name
Test status
Simulation time 137963916472 ps
CPU time 440.12 seconds
Started Jun 26 06:13:00 PM PDT 24
Finished Jun 26 06:20:21 PM PDT 24
Peak memory 216496 kb
Host smart-99a2a0b2-b1d0-4a7d-85cf-91877116a935
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174057568 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.4174057568
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.2626870334
Short name T33
Test name
Test status
Simulation time 120171629718 ps
CPU time 367.05 seconds
Started Jun 26 06:13:03 PM PDT 24
Finished Jun 26 06:19:11 PM PDT 24
Peak memory 216412 kb
Host smart-c45d11e8-e5c7-47bb-b43d-0c0de9f25151
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626870334 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.2626870334
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.15554571
Short name T127
Test name
Test status
Simulation time 141151386449 ps
CPU time 39.33 seconds
Started Jun 26 06:13:02 PM PDT 24
Finished Jun 26 06:13:42 PM PDT 24
Peak memory 200032 kb
Host smart-01d31c7b-40fd-493d-b175-52b35867a89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15554571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.15554571
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.933906830
Short name T44
Test name
Test status
Simulation time 62662871471 ps
CPU time 677.84 seconds
Started Jun 26 06:10:18 PM PDT 24
Finished Jun 26 06:21:39 PM PDT 24
Peak memory 215672 kb
Host smart-f8ebb58d-adce-4d1d-abe6-0bcdae5c7390
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933906830 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.933906830
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2052028269
Short name T56
Test name
Test status
Simulation time 213669448 ps
CPU time 2.36 seconds
Started Jun 26 05:52:58 PM PDT 24
Finished Jun 26 05:53:01 PM PDT 24
Peak memory 198372 kb
Host smart-0c6b94f3-0eae-4404-bc3d-1ebcb9a77b93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052028269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2052028269
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2842701740
Short name T64
Test name
Test status
Simulation time 57012587 ps
CPU time 0.65 seconds
Started Jun 26 05:52:57 PM PDT 24
Finished Jun 26 05:52:59 PM PDT 24
Peak memory 196072 kb
Host smart-668a9b47-5c98-47a8-af07-3ff99f74d666
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842701740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.2842701740
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/default/10.uart_perf.1442090193
Short name T255
Test name
Test status
Simulation time 29830959453 ps
CPU time 875.24 seconds
Started Jun 26 06:10:33 PM PDT 24
Finished Jun 26 06:25:11 PM PDT 24
Peak memory 199872 kb
Host smart-b58271b5-2a50-4e38-a58e-22105b936699
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1442090193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.1442090193
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/0.uart_perf.2512318252
Short name T242
Test name
Test status
Simulation time 8126864072 ps
CPU time 166.49 seconds
Started Jun 26 06:10:11 PM PDT 24
Finished Jun 26 06:13:01 PM PDT 24
Peak memory 199932 kb
Host smart-778ea25f-9fb9-4f33-9f79-2b33a5d34af0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2512318252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2512318252
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.2405908983
Short name T86
Test name
Test status
Simulation time 134667536049 ps
CPU time 199.93 seconds
Started Jun 26 06:13:00 PM PDT 24
Finished Jun 26 06:16:21 PM PDT 24
Peak memory 199960 kb
Host smart-91d9cb72-d613-4c8d-968c-2429912dd8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405908983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2405908983
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.3386656373
Short name T160
Test name
Test status
Simulation time 164139818495 ps
CPU time 259.47 seconds
Started Jun 26 06:13:48 PM PDT 24
Finished Jun 26 06:18:08 PM PDT 24
Peak memory 199920 kb
Host smart-f873ca97-be4d-4222-bef0-4f9aa4dba426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386656373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.3386656373
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_stress_all.2190790713
Short name T228
Test name
Test status
Simulation time 251231244763 ps
CPU time 127.71 seconds
Started Jun 26 06:10:50 PM PDT 24
Finished Jun 26 06:13:01 PM PDT 24
Peak memory 199928 kb
Host smart-1050f91a-2fde-4c72-8e7b-ce7f2c968cc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190790713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2190790713
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_fifo_full.3327019353
Short name T267
Test name
Test status
Simulation time 238011779073 ps
CPU time 555.6 seconds
Started Jun 26 06:10:37 PM PDT 24
Finished Jun 26 06:19:54 PM PDT 24
Peak memory 199916 kb
Host smart-3a68a170-4c04-4106-8b5f-22e76e9a9148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327019353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.3327019353
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.2016005588
Short name T30
Test name
Test status
Simulation time 87643671905 ps
CPU time 1248.56 seconds
Started Jun 26 06:12:13 PM PDT 24
Finished Jun 26 06:33:02 PM PDT 24
Peak memory 224708 kb
Host smart-509ad6ad-d385-4f71-b76f-1b4af755bf06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016005588 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.2016005588
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.4015529552
Short name T144
Test name
Test status
Simulation time 55575018872 ps
CPU time 89.55 seconds
Started Jun 26 06:10:50 PM PDT 24
Finished Jun 26 06:12:22 PM PDT 24
Peak memory 200004 kb
Host smart-ff9c61ba-24a7-4a0c-bc00-21a3ae3a85af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015529552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.4015529552
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.798989184
Short name T152
Test name
Test status
Simulation time 117877792638 ps
CPU time 51.57 seconds
Started Jun 26 06:10:46 PM PDT 24
Finished Jun 26 06:11:39 PM PDT 24
Peak memory 200016 kb
Host smart-94d7c1c7-0a72-4913-a106-9b682ef94a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798989184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.798989184
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_tx_rx.3302574807
Short name T287
Test name
Test status
Simulation time 27825754667 ps
CPU time 24.57 seconds
Started Jun 26 06:12:21 PM PDT 24
Finished Jun 26 06:12:47 PM PDT 24
Peak memory 199984 kb
Host smart-41ce30a9-f759-451e-9ad9-564f6955044f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302574807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3302574807
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2483956563
Short name T75
Test name
Test status
Simulation time 316905622 ps
CPU time 1.28 seconds
Started Jun 26 05:53:29 PM PDT 24
Finished Jun 26 05:53:32 PM PDT 24
Peak memory 199748 kb
Host smart-019ee804-a3f0-4e5d-97b5-1d51c861e275
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483956563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2483956563
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.1742587078
Short name T149
Test name
Test status
Simulation time 92841839410 ps
CPU time 67.45 seconds
Started Jun 26 06:13:22 PM PDT 24
Finished Jun 26 06:14:31 PM PDT 24
Peak memory 199944 kb
Host smart-a83efab3-daa3-4295-a69d-005fab1d8a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742587078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.1742587078
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.404599685
Short name T3
Test name
Test status
Simulation time 29786436400 ps
CPU time 14.92 seconds
Started Jun 26 06:13:21 PM PDT 24
Finished Jun 26 06:13:38 PM PDT 24
Peak memory 199936 kb
Host smart-fac5769c-0d6b-42c0-af42-541a4edcd793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404599685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.404599685
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.640386582
Short name T261
Test name
Test status
Simulation time 91782424498 ps
CPU time 226.42 seconds
Started Jun 26 06:13:26 PM PDT 24
Finished Jun 26 06:17:13 PM PDT 24
Peak memory 200020 kb
Host smart-f0ba8650-dd51-4b9a-9dc5-abe17d3d3086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640386582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.640386582
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.1744619294
Short name T119
Test name
Test status
Simulation time 50077269903 ps
CPU time 22.78 seconds
Started Jun 26 06:13:56 PM PDT 24
Finished Jun 26 06:14:19 PM PDT 24
Peak memory 199776 kb
Host smart-b8ce6e2b-a6c7-4dd5-9f58-3fc28f406315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744619294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1744619294
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3298605573
Short name T236
Test name
Test status
Simulation time 71431090306 ps
CPU time 122.07 seconds
Started Jun 26 06:11:50 PM PDT 24
Finished Jun 26 06:13:53 PM PDT 24
Peak memory 199940 kb
Host smart-8effa83e-342e-41dd-951a-0c6d6b543fe7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3298605573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3298605573
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.2303353300
Short name T213
Test name
Test status
Simulation time 206531795812 ps
CPU time 1284.68 seconds
Started Jun 26 06:10:31 PM PDT 24
Finished Jun 26 06:31:59 PM PDT 24
Peak memory 216620 kb
Host smart-463cb10e-defd-4b64-ab96-ac40a1f51b6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303353300 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.2303353300
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.4071030050
Short name T183
Test name
Test status
Simulation time 22875764223 ps
CPU time 48.9 seconds
Started Jun 26 06:13:30 PM PDT 24
Finished Jun 26 06:14:20 PM PDT 24
Peak memory 199900 kb
Host smart-f737749e-a567-460f-b226-07f16f8805d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071030050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.4071030050
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.4206324928
Short name T116
Test name
Test status
Simulation time 43990916749 ps
CPU time 19.23 seconds
Started Jun 26 06:10:51 PM PDT 24
Finished Jun 26 06:11:13 PM PDT 24
Peak memory 199992 kb
Host smart-d8fa5bab-2af1-4f17-91a0-d1dffd04e163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206324928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.4206324928
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.3063342575
Short name T232
Test name
Test status
Simulation time 90621180029 ps
CPU time 71.85 seconds
Started Jun 26 06:13:34 PM PDT 24
Finished Jun 26 06:14:47 PM PDT 24
Peak memory 199940 kb
Host smart-784b3c53-2e56-452a-9019-e4b98dec7c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063342575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3063342575
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.2766038565
Short name T724
Test name
Test status
Simulation time 121149247218 ps
CPU time 150.57 seconds
Started Jun 26 06:13:40 PM PDT 24
Finished Jun 26 06:16:11 PM PDT 24
Peak memory 199904 kb
Host smart-f03a0370-3e3c-437d-81be-6be967978afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766038565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2766038565
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.71471564
Short name T192
Test name
Test status
Simulation time 100415386604 ps
CPU time 78.01 seconds
Started Jun 26 06:13:57 PM PDT 24
Finished Jun 26 06:15:15 PM PDT 24
Peak memory 199832 kb
Host smart-e30292eb-c516-4e77-8ac3-9c805b42dc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71471564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.71471564
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3535412911
Short name T72
Test name
Test status
Simulation time 86470028 ps
CPU time 1.4 seconds
Started Jun 26 05:52:55 PM PDT 24
Finished Jun 26 05:52:57 PM PDT 24
Peak memory 199740 kb
Host smart-6e10ff7a-b24d-48a6-b24a-24358260c3ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535412911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3535412911
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2349943984
Short name T716
Test name
Test status
Simulation time 337681299538 ps
CPU time 123.33 seconds
Started Jun 26 06:13:17 PM PDT 24
Finished Jun 26 06:15:22 PM PDT 24
Peak memory 200008 kb
Host smart-dd7ed364-f8a2-4375-899a-425c67f89e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349943984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2349943984
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3339745875
Short name T202
Test name
Test status
Simulation time 72018613225 ps
CPU time 27.67 seconds
Started Jun 26 06:13:37 PM PDT 24
Finished Jun 26 06:14:05 PM PDT 24
Peak memory 199944 kb
Host smart-87e24e53-71dc-4a50-bb64-2536584703d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339745875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3339745875
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.3438832967
Short name T122
Test name
Test status
Simulation time 22577785238 ps
CPU time 37.95 seconds
Started Jun 26 06:13:42 PM PDT 24
Finished Jun 26 06:14:21 PM PDT 24
Peak memory 199948 kb
Host smart-2738d39d-96f9-464f-91ca-8524463cbc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438832967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3438832967
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.4046904061
Short name T171
Test name
Test status
Simulation time 11203445193 ps
CPU time 14.32 seconds
Started Jun 26 06:13:43 PM PDT 24
Finished Jun 26 06:13:59 PM PDT 24
Peak memory 199712 kb
Host smart-cba49b66-8a76-46ac-8aa5-27d57e550e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046904061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.4046904061
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.2589266288
Short name T211
Test name
Test status
Simulation time 20857966384 ps
CPU time 13.9 seconds
Started Jun 26 06:14:09 PM PDT 24
Finished Jun 26 06:14:23 PM PDT 24
Peak memory 199964 kb
Host smart-4ebc1de2-9cee-401c-b87b-9d3de2ffb833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589266288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2589266288
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.3187955357
Short name T217
Test name
Test status
Simulation time 184226274914 ps
CPU time 40.42 seconds
Started Jun 26 06:12:47 PM PDT 24
Finished Jun 26 06:13:29 PM PDT 24
Peak memory 199736 kb
Host smart-4ce05869-32b6-4746-b508-6a141070a0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187955357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.3187955357
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.183106032
Short name T118
Test name
Test status
Simulation time 52127909370 ps
CPU time 84.79 seconds
Started Jun 26 06:13:03 PM PDT 24
Finished Jun 26 06:14:29 PM PDT 24
Peak memory 200004 kb
Host smart-b7406d74-da26-431b-bdd3-60ff05502a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183106032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.183106032
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.3541323475
Short name T214
Test name
Test status
Simulation time 16561434515 ps
CPU time 27.79 seconds
Started Jun 26 06:10:02 PM PDT 24
Finished Jun 26 06:10:32 PM PDT 24
Peak memory 199788 kb
Host smart-3c574317-341e-4823-855f-5669adc8183c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541323475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3541323475
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.543466566
Short name T106
Test name
Test status
Simulation time 101512512968 ps
CPU time 26.48 seconds
Started Jun 26 06:13:17 PM PDT 24
Finished Jun 26 06:13:45 PM PDT 24
Peak memory 200000 kb
Host smart-21307630-0bc4-4c73-a83e-d16d1694d1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543466566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.543466566
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_tx_rx.3798162611
Short name T273
Test name
Test status
Simulation time 175102670578 ps
CPU time 77.29 seconds
Started Jun 26 06:10:35 PM PDT 24
Finished Jun 26 06:11:54 PM PDT 24
Peak memory 199928 kb
Host smart-5c708b8f-bfe0-451e-aea2-c9b920fbb6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798162611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.3798162611
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.2076789999
Short name T682
Test name
Test status
Simulation time 140061289806 ps
CPU time 279.56 seconds
Started Jun 26 06:13:26 PM PDT 24
Finished Jun 26 06:18:07 PM PDT 24
Peak memory 199908 kb
Host smart-1c335112-241c-4121-8bfc-090fc10c7a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076789999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2076789999
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.481015665
Short name T631
Test name
Test status
Simulation time 43849369823 ps
CPU time 44.4 seconds
Started Jun 26 06:13:30 PM PDT 24
Finished Jun 26 06:14:15 PM PDT 24
Peak memory 199912 kb
Host smart-d6d08d13-9eb8-438e-aac8-0f3c1b5f25a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481015665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.481015665
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.2419459574
Short name T512
Test name
Test status
Simulation time 59110079938 ps
CPU time 54.73 seconds
Started Jun 26 06:13:29 PM PDT 24
Finished Jun 26 06:14:25 PM PDT 24
Peak memory 200000 kb
Host smart-f7fe9c56-df50-40d3-8779-db894002541c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419459574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2419459574
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3440125964
Short name T206
Test name
Test status
Simulation time 137456036984 ps
CPU time 82.13 seconds
Started Jun 26 06:13:29 PM PDT 24
Finished Jun 26 06:14:52 PM PDT 24
Peak memory 199932 kb
Host smart-3604a681-a9ba-4e85-87f5-254204716492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440125964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3440125964
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.787329943
Short name T208
Test name
Test status
Simulation time 51436716449 ps
CPU time 39.25 seconds
Started Jun 26 06:13:35 PM PDT 24
Finished Jun 26 06:14:15 PM PDT 24
Peak memory 199960 kb
Host smart-3e1dd9bf-be66-4755-bc90-b34cab4a4a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787329943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.787329943
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.3780901713
Short name T677
Test name
Test status
Simulation time 107174882260 ps
CPU time 162.75 seconds
Started Jun 26 06:13:41 PM PDT 24
Finished Jun 26 06:16:25 PM PDT 24
Peak memory 199864 kb
Host smart-98761f79-69ec-40ed-8b41-048edd588ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780901713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.3780901713
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.901699288
Short name T184
Test name
Test status
Simulation time 36677876377 ps
CPU time 79.01 seconds
Started Jun 26 06:13:51 PM PDT 24
Finished Jun 26 06:15:11 PM PDT 24
Peak memory 200008 kb
Host smart-ff68c29a-2863-4063-a33e-04f73ac54c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901699288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.901699288
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.276116446
Short name T203
Test name
Test status
Simulation time 25065992819 ps
CPU time 42.8 seconds
Started Jun 26 06:11:03 PM PDT 24
Finished Jun 26 06:11:48 PM PDT 24
Peak memory 199900 kb
Host smart-27d2bcb5-b3b0-4f24-89c3-07b8613a1696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276116446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.276116446
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.3087885833
Short name T143
Test name
Test status
Simulation time 13667261393 ps
CPU time 19.35 seconds
Started Jun 26 06:13:55 PM PDT 24
Finished Jun 26 06:14:16 PM PDT 24
Peak memory 199908 kb
Host smart-9dc9dd00-1ce9-441c-8c22-f5e7b3d2b6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087885833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.3087885833
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.2235926071
Short name T224
Test name
Test status
Simulation time 134280225703 ps
CPU time 44.79 seconds
Started Jun 26 06:11:38 PM PDT 24
Finished Jun 26 06:12:24 PM PDT 24
Peak memory 199948 kb
Host smart-80b5b8a7-77f6-442d-b806-913933292abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235926071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2235926071
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.628067113
Short name T220
Test name
Test status
Simulation time 80667677693 ps
CPU time 100.88 seconds
Started Jun 26 06:11:15 PM PDT 24
Finished Jun 26 06:12:58 PM PDT 24
Peak memory 199928 kb
Host smart-b4c415b6-77bb-4d4f-9e2b-030c717b63a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628067113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.628067113
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.3899130435
Short name T219
Test name
Test status
Simulation time 248395613890 ps
CPU time 95.36 seconds
Started Jun 26 06:14:09 PM PDT 24
Finished Jun 26 06:15:45 PM PDT 24
Peak memory 199884 kb
Host smart-78ef9a77-6a4e-49e7-8afb-d9d6cf7082c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899130435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3899130435
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3191768567
Short name T110
Test name
Test status
Simulation time 66521727567 ps
CPU time 105.47 seconds
Started Jun 26 06:12:31 PM PDT 24
Finished Jun 26 06:14:18 PM PDT 24
Peak memory 200012 kb
Host smart-a083d658-00d9-47bf-a804-7d09c4084216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191768567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3191768567
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.4176404395
Short name T223
Test name
Test status
Simulation time 59912217945 ps
CPU time 47.67 seconds
Started Jun 26 06:12:40 PM PDT 24
Finished Jun 26 06:13:29 PM PDT 24
Peak memory 199936 kb
Host smart-cfa7cf11-0470-4dfd-8ac8-78681eb187ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176404395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.4176404395
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_stress_all.3930101716
Short name T98
Test name
Test status
Simulation time 184924523147 ps
CPU time 311.4 seconds
Started Jun 26 06:10:22 PM PDT 24
Finished Jun 26 06:15:36 PM PDT 24
Peak memory 199916 kb
Host smart-561a7d65-0313-4226-b0fe-8ed9551bf308
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930101716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.3930101716
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.2886285050
Short name T126
Test name
Test status
Simulation time 115781824383 ps
CPU time 208.43 seconds
Started Jun 26 06:10:19 PM PDT 24
Finished Jun 26 06:13:50 PM PDT 24
Peak memory 199972 kb
Host smart-0b261703-35b7-4de5-969a-aed8d0dbed9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886285050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2886285050
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3071786521
Short name T210
Test name
Test status
Simulation time 74494157771 ps
CPU time 41.64 seconds
Started Jun 26 06:10:19 PM PDT 24
Finished Jun 26 06:11:04 PM PDT 24
Peak memory 199948 kb
Host smart-aeb4a613-97b3-4c12-9f06-8bd44acf96fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071786521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3071786521
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.520297115
Short name T1138
Test name
Test status
Simulation time 12557292 ps
CPU time 0.67 seconds
Started Jun 26 05:52:56 PM PDT 24
Finished Jun 26 05:52:58 PM PDT 24
Peak memory 195236 kb
Host smart-90710b0a-c25a-4faa-a8be-bc8c1cdf1838
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520297115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.520297115
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.322291290
Short name T54
Test name
Test status
Simulation time 15058474 ps
CPU time 0.67 seconds
Started Jun 26 05:52:57 PM PDT 24
Finished Jun 26 05:52:59 PM PDT 24
Peak memory 195752 kb
Host smart-b72ac0f4-55bb-434e-9123-b8e0127b9e47
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322291290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.322291290
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.11070070
Short name T1139
Test name
Test status
Simulation time 56238543 ps
CPU time 0.95 seconds
Started Jun 26 05:53:00 PM PDT 24
Finished Jun 26 05:53:02 PM PDT 24
Peak memory 200228 kb
Host smart-cf286f65-c981-4f85-9cd4-23bf74c87768
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11070070 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.11070070
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.195918095
Short name T1121
Test name
Test status
Simulation time 16108684 ps
CPU time 0.64 seconds
Started Jun 26 05:52:56 PM PDT 24
Finished Jun 26 05:52:58 PM PDT 24
Peak memory 195940 kb
Host smart-0c7fac86-5d9b-492d-9c66-b9a6afc42a62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195918095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.195918095
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.4109608366
Short name T1209
Test name
Test status
Simulation time 16854085 ps
CPU time 0.63 seconds
Started Jun 26 05:53:00 PM PDT 24
Finished Jun 26 05:53:02 PM PDT 24
Peak memory 194796 kb
Host smart-42ac0ff5-09ea-400d-991e-90e7b2c028bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109608366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.4109608366
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.1019349976
Short name T1153
Test name
Test status
Simulation time 379572807 ps
CPU time 1.82 seconds
Started Jun 26 05:52:57 PM PDT 24
Finished Jun 26 05:53:00 PM PDT 24
Peak memory 200452 kb
Host smart-5adf170b-9276-4565-83f6-25438b01733d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019349976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.1019349976
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1705550481
Short name T1189
Test name
Test status
Simulation time 15426282 ps
CPU time 0.78 seconds
Started Jun 26 05:53:01 PM PDT 24
Finished Jun 26 05:53:03 PM PDT 24
Peak memory 196748 kb
Host smart-1f724941-5c92-4d0e-befd-a0fc4a4bb2d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705550481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1705550481
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2620810386
Short name T55
Test name
Test status
Simulation time 34600554 ps
CPU time 1.43 seconds
Started Jun 26 05:53:01 PM PDT 24
Finished Jun 26 05:53:04 PM PDT 24
Peak memory 198192 kb
Host smart-576be604-9e24-491f-9e13-0ced9c1e87cf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620810386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2620810386
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.335903644
Short name T1225
Test name
Test status
Simulation time 23346967 ps
CPU time 0.56 seconds
Started Jun 26 05:52:55 PM PDT 24
Finished Jun 26 05:52:57 PM PDT 24
Peak memory 195792 kb
Host smart-d0320bde-b3e8-4078-8161-2609596d99c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335903644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.335903644
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.973650108
Short name T1102
Test name
Test status
Simulation time 24033537 ps
CPU time 0.83 seconds
Started Jun 26 05:53:03 PM PDT 24
Finished Jun 26 05:53:05 PM PDT 24
Peak memory 200052 kb
Host smart-36cba94f-b279-4556-a0f2-4e0ab05efd8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973650108 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.973650108
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.1735804454
Short name T1217
Test name
Test status
Simulation time 18915811 ps
CPU time 0.59 seconds
Started Jun 26 05:52:57 PM PDT 24
Finished Jun 26 05:52:59 PM PDT 24
Peak memory 195836 kb
Host smart-79c7d6c1-dfbe-496f-85a8-5d1c63528e94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735804454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.1735804454
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.405058848
Short name T1185
Test name
Test status
Simulation time 27959423 ps
CPU time 0.63 seconds
Started Jun 26 05:52:54 PM PDT 24
Finished Jun 26 05:52:55 PM PDT 24
Peak memory 194792 kb
Host smart-3aca1da5-1d7c-4d92-9d4c-f64c7dbbde4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405058848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.405058848
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1513127329
Short name T1203
Test name
Test status
Simulation time 18743042 ps
CPU time 0.76 seconds
Started Jun 26 05:53:04 PM PDT 24
Finished Jun 26 05:53:06 PM PDT 24
Peak memory 196296 kb
Host smart-bdcd85ef-3080-4411-a214-d74ab55f6442
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513127329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.1513127329
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.1274050932
Short name T1163
Test name
Test status
Simulation time 59540917 ps
CPU time 1.26 seconds
Started Jun 26 05:52:56 PM PDT 24
Finished Jun 26 05:52:58 PM PDT 24
Peak memory 200380 kb
Host smart-932f68dd-d29d-4e1d-8303-6681dc6c2ddf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274050932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1274050932
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1912800093
Short name T76
Test name
Test status
Simulation time 171008898 ps
CPU time 0.95 seconds
Started Jun 26 05:52:54 PM PDT 24
Finished Jun 26 05:52:56 PM PDT 24
Peak memory 199284 kb
Host smart-939dcdf6-da00-4ea8-98cd-423d2e8ca38e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912800093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1912800093
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.437380605
Short name T1229
Test name
Test status
Simulation time 85903059 ps
CPU time 0.73 seconds
Started Jun 26 05:53:19 PM PDT 24
Finished Jun 26 05:53:21 PM PDT 24
Peak memory 198144 kb
Host smart-fd7701ac-417a-41ff-97d6-2e86f59a3a99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437380605 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.437380605
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2672238344
Short name T1137
Test name
Test status
Simulation time 41065370 ps
CPU time 0.65 seconds
Started Jun 26 05:53:20 PM PDT 24
Finished Jun 26 05:53:22 PM PDT 24
Peak memory 196024 kb
Host smart-a0faa84f-c7c2-4154-af39-e7b45a618aae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672238344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2672238344
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.530098522
Short name T1177
Test name
Test status
Simulation time 149164661 ps
CPU time 0.59 seconds
Started Jun 26 05:53:19 PM PDT 24
Finished Jun 26 05:53:22 PM PDT 24
Peak memory 195024 kb
Host smart-b831d612-f576-4569-a89d-320426154176
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530098522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.530098522
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1650148573
Short name T1219
Test name
Test status
Simulation time 82881018 ps
CPU time 0.76 seconds
Started Jun 26 05:53:19 PM PDT 24
Finished Jun 26 05:53:21 PM PDT 24
Peak memory 198044 kb
Host smart-0ffde4e6-4eb6-4405-b74e-1761ca153fed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650148573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.1650148573
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.1733957230
Short name T1205
Test name
Test status
Simulation time 51418072 ps
CPU time 1.13 seconds
Started Jun 26 05:53:20 PM PDT 24
Finished Jun 26 05:53:23 PM PDT 24
Peak memory 200412 kb
Host smart-283e5cc5-4b9c-487b-bb3e-4783c573d0bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733957230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1733957230
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2119276764
Short name T1116
Test name
Test status
Simulation time 608981887 ps
CPU time 0.95 seconds
Started Jun 26 05:53:18 PM PDT 24
Finished Jun 26 05:53:20 PM PDT 24
Peak memory 199500 kb
Host smart-4c9aa535-a46b-455b-832c-0fc7941410da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119276764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2119276764
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.969882102
Short name T1171
Test name
Test status
Simulation time 55213977 ps
CPU time 1.23 seconds
Started Jun 26 05:53:20 PM PDT 24
Finished Jun 26 05:53:23 PM PDT 24
Peak memory 200380 kb
Host smart-9860f7dc-7919-450a-afdb-e06025d7450d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969882102 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.969882102
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.1924157690
Short name T1175
Test name
Test status
Simulation time 13216637 ps
CPU time 0.61 seconds
Started Jun 26 05:53:20 PM PDT 24
Finished Jun 26 05:53:23 PM PDT 24
Peak memory 196020 kb
Host smart-8e03d840-118d-44e6-aa69-437c006929f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924157690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1924157690
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.3572929257
Short name T1168
Test name
Test status
Simulation time 12515523 ps
CPU time 0.6 seconds
Started Jun 26 05:53:23 PM PDT 24
Finished Jun 26 05:53:26 PM PDT 24
Peak memory 194736 kb
Host smart-f3cdfcb9-fc3c-4430-ae7a-f6ee831cfc5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572929257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3572929257
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3125157753
Short name T1195
Test name
Test status
Simulation time 18366407 ps
CPU time 0.64 seconds
Started Jun 26 05:53:22 PM PDT 24
Finished Jun 26 05:53:25 PM PDT 24
Peak memory 195004 kb
Host smart-d0200e2f-885f-4d39-acd8-9af04aa47b0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125157753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.3125157753
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3042897963
Short name T1169
Test name
Test status
Simulation time 69002655 ps
CPU time 1.78 seconds
Started Jun 26 05:53:19 PM PDT 24
Finished Jun 26 05:53:21 PM PDT 24
Peak memory 200452 kb
Host smart-2974079e-ed2d-4059-a324-1d8116c0f81b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042897963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3042897963
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1932014701
Short name T74
Test name
Test status
Simulation time 270824609 ps
CPU time 1.27 seconds
Started Jun 26 05:53:23 PM PDT 24
Finished Jun 26 05:53:26 PM PDT 24
Peak memory 199660 kb
Host smart-44ae5269-53b7-4002-a38a-6c322142a648
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932014701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1932014701
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3476153069
Short name T1204
Test name
Test status
Simulation time 32232701 ps
CPU time 0.71 seconds
Started Jun 26 05:53:18 PM PDT 24
Finished Jun 26 05:53:20 PM PDT 24
Peak memory 198400 kb
Host smart-890bf2ad-74f6-4dd4-8143-342e027ae51e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476153069 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3476153069
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.1643626802
Short name T1143
Test name
Test status
Simulation time 57057159 ps
CPU time 0.63 seconds
Started Jun 26 05:53:23 PM PDT 24
Finished Jun 26 05:53:26 PM PDT 24
Peak memory 195780 kb
Host smart-22da2024-58ab-448a-93f2-1b22e6ddb3bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643626802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1643626802
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.675143670
Short name T1179
Test name
Test status
Simulation time 31088708 ps
CPU time 0.63 seconds
Started Jun 26 05:53:19 PM PDT 24
Finished Jun 26 05:53:21 PM PDT 24
Peak memory 194728 kb
Host smart-7e187602-6056-4a70-8547-d4f285e121b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675143670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.675143670
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3701571644
Short name T1210
Test name
Test status
Simulation time 17721874 ps
CPU time 0.62 seconds
Started Jun 26 05:53:16 PM PDT 24
Finished Jun 26 05:53:18 PM PDT 24
Peak memory 195824 kb
Host smart-c0753585-5385-497e-8c86-32a064803aeb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701571644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.3701571644
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.696963273
Short name T1129
Test name
Test status
Simulation time 65188841 ps
CPU time 1.47 seconds
Started Jun 26 05:53:22 PM PDT 24
Finished Jun 26 05:53:26 PM PDT 24
Peak memory 200356 kb
Host smart-ae6959c6-c13a-490a-8607-61676b4848c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696963273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.696963273
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3293870016
Short name T1218
Test name
Test status
Simulation time 190170799 ps
CPU time 0.96 seconds
Started Jun 26 05:53:22 PM PDT 24
Finished Jun 26 05:53:25 PM PDT 24
Peak memory 199208 kb
Host smart-bb7bf084-adc2-48cc-90a5-71f8a2956ceb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293870016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3293870016
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2253825012
Short name T1117
Test name
Test status
Simulation time 165862251 ps
CPU time 0.72 seconds
Started Jun 26 05:53:26 PM PDT 24
Finished Jun 26 05:53:29 PM PDT 24
Peak memory 199304 kb
Host smart-17c20148-85e7-4179-992d-4e7a39bbdd8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253825012 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2253825012
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.1853733170
Short name T59
Test name
Test status
Simulation time 20701226 ps
CPU time 0.6 seconds
Started Jun 26 05:53:26 PM PDT 24
Finished Jun 26 05:53:28 PM PDT 24
Peak memory 195752 kb
Host smart-8a79e9d3-05a9-4428-9662-4a9e48d6afc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853733170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1853733170
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.1911566101
Short name T1161
Test name
Test status
Simulation time 10819299 ps
CPU time 0.56 seconds
Started Jun 26 05:53:29 PM PDT 24
Finished Jun 26 05:53:31 PM PDT 24
Peak memory 194668 kb
Host smart-6c3c0d99-9789-4a3b-a2de-ecca7d221fbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911566101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1911566101
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.200582362
Short name T69
Test name
Test status
Simulation time 25949335 ps
CPU time 0.73 seconds
Started Jun 26 05:53:26 PM PDT 24
Finished Jun 26 05:53:28 PM PDT 24
Peak memory 197292 kb
Host smart-8691fcbe-2fd8-430b-b6ca-d1b78dd6718b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200582362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr
_outstanding.200582362
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.2526490085
Short name T1120
Test name
Test status
Simulation time 74982231 ps
CPU time 1.58 seconds
Started Jun 26 05:53:20 PM PDT 24
Finished Jun 26 05:53:24 PM PDT 24
Peak memory 200392 kb
Host smart-f257cca5-e5de-4115-a858-100cbb5fb083
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526490085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.2526490085
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3052523566
Short name T1128
Test name
Test status
Simulation time 18865604 ps
CPU time 0.95 seconds
Started Jun 26 05:53:26 PM PDT 24
Finished Jun 26 05:53:29 PM PDT 24
Peak memory 200240 kb
Host smart-4c397228-ec4c-4fbd-b2a6-401c014a9300
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052523566 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3052523566
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.417773043
Short name T1183
Test name
Test status
Simulation time 14422298 ps
CPU time 0.6 seconds
Started Jun 26 05:53:27 PM PDT 24
Finished Jun 26 05:53:29 PM PDT 24
Peak memory 195800 kb
Host smart-a202800c-2088-4b40-96fa-facb4196ca2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417773043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.417773043
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.295371722
Short name T1125
Test name
Test status
Simulation time 66949604 ps
CPU time 0.6 seconds
Started Jun 26 05:53:26 PM PDT 24
Finished Jun 26 05:53:28 PM PDT 24
Peak memory 194732 kb
Host smart-e3c9cd98-8201-45cc-8cbe-781eff1dd89f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295371722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.295371722
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1869188632
Short name T67
Test name
Test status
Simulation time 19456460 ps
CPU time 0.68 seconds
Started Jun 26 05:53:26 PM PDT 24
Finished Jun 26 05:53:29 PM PDT 24
Peak memory 196792 kb
Host smart-fc4115a0-6e0c-4351-bffd-d308f66009cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869188632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1869188632
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.2309893216
Short name T1159
Test name
Test status
Simulation time 387101690 ps
CPU time 1.95 seconds
Started Jun 26 05:53:28 PM PDT 24
Finished Jun 26 05:53:31 PM PDT 24
Peak memory 200432 kb
Host smart-caba447b-4637-4128-a4f2-42b91063ead3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309893216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2309893216
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3977860642
Short name T73
Test name
Test status
Simulation time 210966812 ps
CPU time 1.27 seconds
Started Jun 26 05:53:27 PM PDT 24
Finished Jun 26 05:53:30 PM PDT 24
Peak memory 199572 kb
Host smart-8c581890-1d2c-4cb4-b8ed-47401a5642ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977860642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3977860642
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3033481026
Short name T1126
Test name
Test status
Simulation time 426406824 ps
CPU time 1.31 seconds
Started Jun 26 05:53:27 PM PDT 24
Finished Jun 26 05:53:29 PM PDT 24
Peak memory 200444 kb
Host smart-10d5f6fe-6dc3-4a1e-948e-f40a8626479d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033481026 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3033481026
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1470912978
Short name T1142
Test name
Test status
Simulation time 14445559 ps
CPU time 0.61 seconds
Started Jun 26 05:53:26 PM PDT 24
Finished Jun 26 05:53:28 PM PDT 24
Peak memory 195816 kb
Host smart-c2278e59-2b41-49f4-9212-eb544e070166
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470912978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1470912978
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.3681940989
Short name T1109
Test name
Test status
Simulation time 11832780 ps
CPU time 0.57 seconds
Started Jun 26 05:53:26 PM PDT 24
Finished Jun 26 05:53:29 PM PDT 24
Peak memory 194736 kb
Host smart-aeeab0a9-2474-4cf2-9110-959594010257
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681940989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3681940989
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1924802818
Short name T1222
Test name
Test status
Simulation time 13437131 ps
CPU time 0.65 seconds
Started Jun 26 05:53:28 PM PDT 24
Finished Jun 26 05:53:30 PM PDT 24
Peak memory 196068 kb
Host smart-7aef486a-465f-4359-86b1-d1fe43385ad3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924802818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1924802818
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.4194846910
Short name T1149
Test name
Test status
Simulation time 244966269 ps
CPU time 2.12 seconds
Started Jun 26 05:53:27 PM PDT 24
Finished Jun 26 05:53:31 PM PDT 24
Peak memory 200340 kb
Host smart-95ac69bf-a4d3-462b-a9a5-d2f7d784c1d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194846910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.4194846910
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.4293629609
Short name T1234
Test name
Test status
Simulation time 72233360 ps
CPU time 0.75 seconds
Started Jun 26 05:53:37 PM PDT 24
Finished Jun 26 05:53:39 PM PDT 24
Peak memory 199128 kb
Host smart-255c16ff-aa6f-4ab6-b975-5fc2f6d8ee7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293629609 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.4293629609
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.3537251519
Short name T1166
Test name
Test status
Simulation time 14292740 ps
CPU time 0.66 seconds
Started Jun 26 05:53:36 PM PDT 24
Finished Jun 26 05:53:37 PM PDT 24
Peak memory 195776 kb
Host smart-1cfe16e6-8cca-4535-acaa-b09612b4b439
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537251519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3537251519
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.3755130585
Short name T1165
Test name
Test status
Simulation time 15825875 ps
CPU time 0.62 seconds
Started Jun 26 05:53:34 PM PDT 24
Finished Jun 26 05:53:36 PM PDT 24
Peak memory 194760 kb
Host smart-46944f4b-f2c2-47a7-a325-d34460ef8b8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755130585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3755130585
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3487208594
Short name T1141
Test name
Test status
Simulation time 48095636 ps
CPU time 0.63 seconds
Started Jun 26 05:53:38 PM PDT 24
Finished Jun 26 05:53:39 PM PDT 24
Peak memory 195992 kb
Host smart-7eb56dbb-3d4d-4f55-8afd-988cc8b1a978
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487208594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.3487208594
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.936530612
Short name T1184
Test name
Test status
Simulation time 31880295 ps
CPU time 1.34 seconds
Started Jun 26 05:53:27 PM PDT 24
Finished Jun 26 05:53:30 PM PDT 24
Peak memory 200384 kb
Host smart-2f98d9bf-0998-4970-b28f-f95ca08762c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936530612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.936530612
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.650586692
Short name T1115
Test name
Test status
Simulation time 93199117 ps
CPU time 0.99 seconds
Started Jun 26 05:53:35 PM PDT 24
Finished Jun 26 05:53:36 PM PDT 24
Peak memory 198988 kb
Host smart-2cb544cf-a894-412a-bd29-76d3e2c3c179
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650586692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.650586692
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1786634472
Short name T1122
Test name
Test status
Simulation time 202096883 ps
CPU time 0.74 seconds
Started Jun 26 05:53:33 PM PDT 24
Finished Jun 26 05:53:34 PM PDT 24
Peak memory 198592 kb
Host smart-9e80dade-08cc-45ce-9960-f6d9ce2de7d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786634472 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.1786634472
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.3291881461
Short name T61
Test name
Test status
Simulation time 24308386 ps
CPU time 0.59 seconds
Started Jun 26 05:53:35 PM PDT 24
Finished Jun 26 05:53:37 PM PDT 24
Peak memory 195664 kb
Host smart-3b099f60-f697-403b-b79c-8ad98aaed127
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291881461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3291881461
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.882032035
Short name T1167
Test name
Test status
Simulation time 21279164 ps
CPU time 0.59 seconds
Started Jun 26 05:53:34 PM PDT 24
Finished Jun 26 05:53:36 PM PDT 24
Peak memory 194720 kb
Host smart-9facd4bd-ae40-4b79-b2c1-7083ba3f0679
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882032035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.882032035
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3115003552
Short name T62
Test name
Test status
Simulation time 56217994 ps
CPU time 0.74 seconds
Started Jun 26 05:53:36 PM PDT 24
Finished Jun 26 05:53:38 PM PDT 24
Peak memory 197332 kb
Host smart-0be949f9-c5c1-4e39-b997-d150759f753e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115003552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.3115003552
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.3682424596
Short name T1224
Test name
Test status
Simulation time 187669355 ps
CPU time 2.37 seconds
Started Jun 26 05:53:33 PM PDT 24
Finished Jun 26 05:53:36 PM PDT 24
Peak memory 200376 kb
Host smart-bd2df729-20bd-4695-b652-1278d89b41e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682424596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3682424596
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2259800164
Short name T1152
Test name
Test status
Simulation time 43825608 ps
CPU time 0.89 seconds
Started Jun 26 05:53:32 PM PDT 24
Finished Jun 26 05:53:34 PM PDT 24
Peak memory 199232 kb
Host smart-204f237e-d89d-421a-b6d9-7c14034c6016
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259800164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2259800164
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.977862029
Short name T1105
Test name
Test status
Simulation time 37307864 ps
CPU time 0.64 seconds
Started Jun 26 05:53:36 PM PDT 24
Finished Jun 26 05:53:37 PM PDT 24
Peak memory 197512 kb
Host smart-fd15597f-6478-4acc-b2d0-5e561c9848c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977862029 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.977862029
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.328557497
Short name T63
Test name
Test status
Simulation time 19129005 ps
CPU time 0.62 seconds
Started Jun 26 05:53:35 PM PDT 24
Finished Jun 26 05:53:37 PM PDT 24
Peak memory 195972 kb
Host smart-8981ea25-a28b-4147-bc07-a4ca1de0aa1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328557497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.328557497
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.2389732110
Short name T1206
Test name
Test status
Simulation time 30480505 ps
CPU time 0.59 seconds
Started Jun 26 05:53:36 PM PDT 24
Finished Jun 26 05:53:38 PM PDT 24
Peak memory 194784 kb
Host smart-d102dc90-d008-4b44-888b-2419d5b09da5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389732110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.2389732110
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.951044487
Short name T1194
Test name
Test status
Simulation time 103252302 ps
CPU time 0.77 seconds
Started Jun 26 05:53:34 PM PDT 24
Finished Jun 26 05:53:36 PM PDT 24
Peak memory 196256 kb
Host smart-cd80d6ac-e20d-4092-b980-6a4604b89b11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951044487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr
_outstanding.951044487
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.411877713
Short name T1123
Test name
Test status
Simulation time 38507547 ps
CPU time 1.95 seconds
Started Jun 26 05:53:32 PM PDT 24
Finished Jun 26 05:53:35 PM PDT 24
Peak memory 200428 kb
Host smart-49e31fdf-7cec-4214-bb51-3caa1a822f2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411877713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.411877713
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.915589185
Short name T1187
Test name
Test status
Simulation time 1078766094 ps
CPU time 1.29 seconds
Started Jun 26 05:53:36 PM PDT 24
Finished Jun 26 05:53:38 PM PDT 24
Peak memory 199600 kb
Host smart-433016b8-9535-458c-b140-47d54e33ce11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915589185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.915589185
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.138015198
Short name T1130
Test name
Test status
Simulation time 52501607 ps
CPU time 0.71 seconds
Started Jun 26 05:53:46 PM PDT 24
Finished Jun 26 05:53:48 PM PDT 24
Peak memory 198376 kb
Host smart-ded55390-535c-4527-b3e6-fe465eb01845
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138015198 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.138015198
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.280176729
Short name T1228
Test name
Test status
Simulation time 106441661 ps
CPU time 0.62 seconds
Started Jun 26 05:53:44 PM PDT 24
Finished Jun 26 05:53:46 PM PDT 24
Peak memory 195944 kb
Host smart-ea499548-fc74-4a3e-a6e2-2f3663583b38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280176729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.280176729
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.486385165
Short name T1181
Test name
Test status
Simulation time 19820030 ps
CPU time 0.61 seconds
Started Jun 26 05:53:43 PM PDT 24
Finished Jun 26 05:53:44 PM PDT 24
Peak memory 194656 kb
Host smart-cc487b6a-9ab6-48dd-ab6e-541d72cdd474
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486385165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.486385165
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.4275921169
Short name T1227
Test name
Test status
Simulation time 111501683 ps
CPU time 0.76 seconds
Started Jun 26 05:53:46 PM PDT 24
Finished Jun 26 05:53:49 PM PDT 24
Peak memory 196264 kb
Host smart-474b4301-fac7-44b4-9569-a12098cdd4cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275921169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.4275921169
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.1898713463
Short name T1103
Test name
Test status
Simulation time 27807773 ps
CPU time 1.46 seconds
Started Jun 26 05:53:35 PM PDT 24
Finished Jun 26 05:53:37 PM PDT 24
Peak memory 200456 kb
Host smart-e473d4db-247b-4390-aaaa-00e0f836273c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898713463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.1898713463
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1074211370
Short name T79
Test name
Test status
Simulation time 96694547 ps
CPU time 0.97 seconds
Started Jun 26 05:53:46 PM PDT 24
Finished Jun 26 05:53:49 PM PDT 24
Peak memory 199420 kb
Host smart-506b516c-2c07-4abe-8c50-abe849cc6eeb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074211370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1074211370
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2196373310
Short name T1192
Test name
Test status
Simulation time 21690064 ps
CPU time 0.71 seconds
Started Jun 26 05:53:00 PM PDT 24
Finished Jun 26 05:53:01 PM PDT 24
Peak memory 195464 kb
Host smart-ff5fd756-b4ff-464f-9498-34ca647c319e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196373310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2196373310
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1206544987
Short name T57
Test name
Test status
Simulation time 260152726 ps
CPU time 1.59 seconds
Started Jun 26 05:53:02 PM PDT 24
Finished Jun 26 05:53:06 PM PDT 24
Peak memory 198084 kb
Host smart-1c3be0c9-73f7-43b7-b2c3-bf32702749c5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206544987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1206544987
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.13965251
Short name T1147
Test name
Test status
Simulation time 44741874 ps
CPU time 0.59 seconds
Started Jun 26 05:53:01 PM PDT 24
Finished Jun 26 05:53:03 PM PDT 24
Peak memory 195744 kb
Host smart-4656087e-b7be-4a30-aa25-c9178f4590fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13965251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.13965251
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1442908018
Short name T1157
Test name
Test status
Simulation time 177064567 ps
CPU time 1.4 seconds
Started Jun 26 05:53:01 PM PDT 24
Finished Jun 26 05:53:03 PM PDT 24
Peak memory 200476 kb
Host smart-e2e4ca7c-4f69-4cd4-a663-43c88a21f094
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442908018 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1442908018
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.822466267
Short name T1221
Test name
Test status
Simulation time 15352019 ps
CPU time 0.63 seconds
Started Jun 26 05:53:01 PM PDT 24
Finished Jun 26 05:53:02 PM PDT 24
Peak memory 196220 kb
Host smart-40464d29-377d-4946-b221-1f11501b5fa3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822466267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.822466267
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.4228835417
Short name T1230
Test name
Test status
Simulation time 14315108 ps
CPU time 0.62 seconds
Started Jun 26 05:53:02 PM PDT 24
Finished Jun 26 05:53:04 PM PDT 24
Peak memory 194784 kb
Host smart-67ec07ba-e7ab-41f6-b9f8-4a874229d029
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228835417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.4228835417
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2361569366
Short name T1226
Test name
Test status
Simulation time 17657970 ps
CPU time 0.64 seconds
Started Jun 26 05:53:02 PM PDT 24
Finished Jun 26 05:53:04 PM PDT 24
Peak memory 196040 kb
Host smart-5492f693-97ec-42c0-9ecd-ebe1ed7da669
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361569366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2361569366
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.3065672877
Short name T1124
Test name
Test status
Simulation time 46076085 ps
CPU time 1.25 seconds
Started Jun 26 05:53:02 PM PDT 24
Finished Jun 26 05:53:05 PM PDT 24
Peak memory 200352 kb
Host smart-5ad3d941-9446-403c-a60a-2f1fdc3353d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065672877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.3065672877
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2644947979
Short name T77
Test name
Test status
Simulation time 881644894 ps
CPU time 1.24 seconds
Started Jun 26 05:53:06 PM PDT 24
Finished Jun 26 05:53:08 PM PDT 24
Peak memory 199496 kb
Host smart-dad2ccf2-0e8a-461e-aa93-ad6bd177c14a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644947979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2644947979
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.3118325945
Short name T1145
Test name
Test status
Simulation time 29342605 ps
CPU time 0.55 seconds
Started Jun 26 05:53:45 PM PDT 24
Finished Jun 26 05:53:47 PM PDT 24
Peak memory 194756 kb
Host smart-16bb37bf-d8f2-4c74-9d6b-3d2523bdc0bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118325945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3118325945
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.2590624836
Short name T1140
Test name
Test status
Simulation time 18864490 ps
CPU time 0.56 seconds
Started Jun 26 05:53:44 PM PDT 24
Finished Jun 26 05:53:46 PM PDT 24
Peak memory 194788 kb
Host smart-cea439cf-5b7f-4c24-87cd-ceace26b368f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590624836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2590624836
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2340297710
Short name T1223
Test name
Test status
Simulation time 15064137 ps
CPU time 0.58 seconds
Started Jun 26 05:53:44 PM PDT 24
Finished Jun 26 05:53:46 PM PDT 24
Peak memory 194752 kb
Host smart-de6ed643-00da-4254-96c5-65047f65409f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340297710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2340297710
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2451336537
Short name T1186
Test name
Test status
Simulation time 16506699 ps
CPU time 0.54 seconds
Started Jun 26 05:53:44 PM PDT 24
Finished Jun 26 05:53:46 PM PDT 24
Peak memory 194756 kb
Host smart-174506a7-0d0a-4cf1-8a21-79ce122206b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451336537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2451336537
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.1878447376
Short name T1170
Test name
Test status
Simulation time 25808884 ps
CPU time 0.61 seconds
Started Jun 26 05:53:45 PM PDT 24
Finished Jun 26 05:53:47 PM PDT 24
Peak memory 194660 kb
Host smart-0d9e23fe-ab9c-49b0-8f63-de1b3ebc5346
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878447376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1878447376
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.4046019343
Short name T1155
Test name
Test status
Simulation time 20842979 ps
CPU time 0.57 seconds
Started Jun 26 05:53:42 PM PDT 24
Finished Jun 26 05:53:43 PM PDT 24
Peak memory 194784 kb
Host smart-dccbe8e1-db2a-44db-97eb-91a8fa6bde9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046019343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.4046019343
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.2066269266
Short name T1131
Test name
Test status
Simulation time 39374240 ps
CPU time 0.57 seconds
Started Jun 26 05:53:44 PM PDT 24
Finished Jun 26 05:53:47 PM PDT 24
Peak memory 195020 kb
Host smart-447674c6-b373-4fce-8d88-629f9202cfcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066269266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.2066269266
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.2859589240
Short name T1201
Test name
Test status
Simulation time 11078494 ps
CPU time 0.57 seconds
Started Jun 26 05:53:45 PM PDT 24
Finished Jun 26 05:53:47 PM PDT 24
Peak memory 194716 kb
Host smart-41f030ab-18c4-4aaa-816d-58623a815a43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859589240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.2859589240
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.1082500592
Short name T1202
Test name
Test status
Simulation time 14235731 ps
CPU time 0.58 seconds
Started Jun 26 05:53:43 PM PDT 24
Finished Jun 26 05:53:45 PM PDT 24
Peak memory 194792 kb
Host smart-47aa838f-b44e-4f78-8988-9ef623488af9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082500592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.1082500592
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.2830909698
Short name T1098
Test name
Test status
Simulation time 27611988 ps
CPU time 0.6 seconds
Started Jun 26 05:53:46 PM PDT 24
Finished Jun 26 05:53:49 PM PDT 24
Peak memory 194804 kb
Host smart-8de3dab0-b22b-4ca6-853c-375448a1a2e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830909698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2830909698
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1700493374
Short name T1156
Test name
Test status
Simulation time 36287799 ps
CPU time 0.83 seconds
Started Jun 26 05:53:02 PM PDT 24
Finished Jun 26 05:53:04 PM PDT 24
Peak memory 196660 kb
Host smart-e44559c5-6a80-464f-b7b9-73ffb73989aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700493374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1700493374
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3911255271
Short name T53
Test name
Test status
Simulation time 1647695324 ps
CPU time 2.75 seconds
Started Jun 26 05:53:03 PM PDT 24
Finished Jun 26 05:53:07 PM PDT 24
Peak memory 198460 kb
Host smart-2f092a7f-7fbb-49c4-95e7-261bf0158645
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911255271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3911255271
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.659189005
Short name T1114
Test name
Test status
Simulation time 16377673 ps
CPU time 0.58 seconds
Started Jun 26 05:53:01 PM PDT 24
Finished Jun 26 05:53:03 PM PDT 24
Peak memory 195824 kb
Host smart-9f7b150c-56bf-4b2c-98f9-c4828bf7f643
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659189005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.659189005
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2318526096
Short name T1220
Test name
Test status
Simulation time 40937374 ps
CPU time 0.82 seconds
Started Jun 26 05:53:02 PM PDT 24
Finished Jun 26 05:53:04 PM PDT 24
Peak memory 199332 kb
Host smart-e088d600-3493-43c9-a6cd-6f97abc2c5d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318526096 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.2318526096
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.1162976173
Short name T1150
Test name
Test status
Simulation time 11763670 ps
CPU time 0.61 seconds
Started Jun 26 05:53:02 PM PDT 24
Finished Jun 26 05:53:04 PM PDT 24
Peak memory 195812 kb
Host smart-bad195ce-66a8-4a05-8608-a835f6cc041b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162976173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.1162976173
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.357864871
Short name T1200
Test name
Test status
Simulation time 21375772 ps
CPU time 0.58 seconds
Started Jun 26 05:53:05 PM PDT 24
Finished Jun 26 05:53:06 PM PDT 24
Peak memory 194792 kb
Host smart-7947e32c-a1d9-4c6d-836b-80d4463d473a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357864871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.357864871
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.122217596
Short name T65
Test name
Test status
Simulation time 12200967 ps
CPU time 0.64 seconds
Started Jun 26 05:53:04 PM PDT 24
Finished Jun 26 05:53:06 PM PDT 24
Peak memory 195944 kb
Host smart-f03be2ee-d0ad-46ab-83f9-f7216044605a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122217596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_
outstanding.122217596
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.433478917
Short name T1198
Test name
Test status
Simulation time 40739809 ps
CPU time 1.98 seconds
Started Jun 26 05:53:02 PM PDT 24
Finished Jun 26 05:53:06 PM PDT 24
Peak memory 200424 kb
Host smart-2391fe88-90bd-4676-89a7-3de9bf9df824
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433478917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.433478917
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3029891293
Short name T80
Test name
Test status
Simulation time 53009526 ps
CPU time 1.06 seconds
Started Jun 26 05:53:03 PM PDT 24
Finished Jun 26 05:53:06 PM PDT 24
Peak memory 199600 kb
Host smart-91458b6a-5438-4e04-b80a-6a8d3e1a357f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029891293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3029891293
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.3822617801
Short name T1113
Test name
Test status
Simulation time 15443295 ps
CPU time 0.6 seconds
Started Jun 26 05:53:44 PM PDT 24
Finished Jun 26 05:53:46 PM PDT 24
Peak memory 194808 kb
Host smart-302d791c-9bdd-4bd0-89e3-372dbfd23bfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822617801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3822617801
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.4235601904
Short name T1178
Test name
Test status
Simulation time 66622655 ps
CPU time 0.59 seconds
Started Jun 26 05:53:46 PM PDT 24
Finished Jun 26 05:53:49 PM PDT 24
Peak memory 194780 kb
Host smart-80521120-9d40-432d-b9cf-e0a0f8d8fd23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235601904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.4235601904
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.512695119
Short name T1118
Test name
Test status
Simulation time 13158176 ps
CPU time 0.58 seconds
Started Jun 26 05:53:41 PM PDT 24
Finished Jun 26 05:53:43 PM PDT 24
Peak memory 194800 kb
Host smart-710f658f-a4b2-4b65-8ee3-59470179e909
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512695119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.512695119
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.515420773
Short name T1188
Test name
Test status
Simulation time 11384276 ps
CPU time 0.59 seconds
Started Jun 26 05:53:44 PM PDT 24
Finished Jun 26 05:53:46 PM PDT 24
Peak memory 194728 kb
Host smart-9b6a8218-5362-4ebb-af48-a48274b8e01b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515420773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.515420773
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.172813529
Short name T1146
Test name
Test status
Simulation time 13919659 ps
CPU time 0.58 seconds
Started Jun 26 05:53:46 PM PDT 24
Finished Jun 26 05:53:48 PM PDT 24
Peak memory 194820 kb
Host smart-2041228b-c998-45da-89e5-84c55468f43f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172813529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.172813529
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.3379612794
Short name T1212
Test name
Test status
Simulation time 16035921 ps
CPU time 0.59 seconds
Started Jun 26 05:55:08 PM PDT 24
Finished Jun 26 05:55:12 PM PDT 24
Peak memory 194716 kb
Host smart-a1f0407c-c7c2-4cb6-9888-3e678ed4cb0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379612794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3379612794
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.1112411400
Short name T1173
Test name
Test status
Simulation time 41457579 ps
CPU time 0.57 seconds
Started Jun 26 05:53:44 PM PDT 24
Finished Jun 26 05:53:45 PM PDT 24
Peak memory 194732 kb
Host smart-f4f4190f-89e7-4495-9e4b-5222788f9087
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112411400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1112411400
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.2203069013
Short name T1164
Test name
Test status
Simulation time 45667094 ps
CPU time 0.6 seconds
Started Jun 26 05:53:43 PM PDT 24
Finished Jun 26 05:53:45 PM PDT 24
Peak memory 194992 kb
Host smart-1285276e-7aaa-4f8b-ae2f-a90451588a04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203069013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2203069013
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.4180099012
Short name T1110
Test name
Test status
Simulation time 58518351 ps
CPU time 0.58 seconds
Started Jun 26 05:53:43 PM PDT 24
Finished Jun 26 05:53:44 PM PDT 24
Peak memory 194792 kb
Host smart-9dcc503b-ec03-4318-acfb-41d8a54e52f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180099012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.4180099012
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.3426131519
Short name T1101
Test name
Test status
Simulation time 42229618 ps
CPU time 0.62 seconds
Started Jun 26 05:53:41 PM PDT 24
Finished Jun 26 05:53:42 PM PDT 24
Peak memory 194812 kb
Host smart-6103000e-1efe-41a7-905d-afe7fec43e2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426131519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3426131519
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1279815585
Short name T1158
Test name
Test status
Simulation time 31824796 ps
CPU time 0.68 seconds
Started Jun 26 05:53:11 PM PDT 24
Finished Jun 26 05:53:14 PM PDT 24
Peak memory 195808 kb
Host smart-96d8e2c9-4467-4704-a953-f25bc3c3e554
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279815585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1279815585
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3960389931
Short name T1144
Test name
Test status
Simulation time 3558227296 ps
CPU time 2.57 seconds
Started Jun 26 05:53:11 PM PDT 24
Finished Jun 26 05:53:16 PM PDT 24
Peak memory 198428 kb
Host smart-89b558de-c6d2-459b-b0b9-b6e1dac14e27
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960389931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3960389931
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2857121514
Short name T1162
Test name
Test status
Simulation time 14021299 ps
CPU time 0.6 seconds
Started Jun 26 05:53:11 PM PDT 24
Finished Jun 26 05:53:14 PM PDT 24
Peak memory 195832 kb
Host smart-3b308be9-c825-4ccc-abd7-ae636b7c7aaa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857121514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2857121514
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3804882072
Short name T1111
Test name
Test status
Simulation time 13013233 ps
CPU time 0.67 seconds
Started Jun 26 05:53:11 PM PDT 24
Finished Jun 26 05:53:13 PM PDT 24
Peak memory 197372 kb
Host smart-a5027895-73cf-48ec-9adb-38351003ab75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804882072 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.3804882072
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.3308072785
Short name T1193
Test name
Test status
Simulation time 14908616 ps
CPU time 0.7 seconds
Started Jun 26 05:53:11 PM PDT 24
Finished Jun 26 05:53:13 PM PDT 24
Peak memory 195804 kb
Host smart-e96b610c-af44-4068-a425-52ce1e8e878a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308072785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3308072785
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.3368431591
Short name T1100
Test name
Test status
Simulation time 46943684 ps
CPU time 0.57 seconds
Started Jun 26 05:53:10 PM PDT 24
Finished Jun 26 05:53:12 PM PDT 24
Peak memory 194764 kb
Host smart-8e7526a8-a0b6-4e75-b68c-b38578c9b347
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368431591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.3368431591
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.38358794
Short name T66
Test name
Test status
Simulation time 145237532 ps
CPU time 0.74 seconds
Started Jun 26 05:53:13 PM PDT 24
Finished Jun 26 05:53:16 PM PDT 24
Peak memory 197908 kb
Host smart-8f05cff3-1d75-44c5-a26f-46311f817ea1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38358794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_o
utstanding.38358794
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.2336444755
Short name T1214
Test name
Test status
Simulation time 95650313 ps
CPU time 1.44 seconds
Started Jun 26 05:53:12 PM PDT 24
Finished Jun 26 05:53:16 PM PDT 24
Peak memory 200380 kb
Host smart-8096544a-f8b9-407f-a39e-dee040cb995b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336444755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2336444755
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2166127165
Short name T1199
Test name
Test status
Simulation time 189864604 ps
CPU time 0.95 seconds
Started Jun 26 05:53:11 PM PDT 24
Finished Jun 26 05:53:14 PM PDT 24
Peak memory 199600 kb
Host smart-85b882d1-79c9-48b9-9972-04ea5f3f3552
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166127165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2166127165
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3745240049
Short name T1132
Test name
Test status
Simulation time 15764282 ps
CPU time 0.59 seconds
Started Jun 26 05:53:42 PM PDT 24
Finished Jun 26 05:53:44 PM PDT 24
Peak memory 194724 kb
Host smart-87ad558e-f327-4d6c-bfe3-88feca65d1f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745240049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3745240049
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.1904896274
Short name T1213
Test name
Test status
Simulation time 27588630 ps
CPU time 0.64 seconds
Started Jun 26 05:53:44 PM PDT 24
Finished Jun 26 05:53:47 PM PDT 24
Peak memory 195032 kb
Host smart-b5a4f7e5-2a05-4f24-93c1-b08c56280339
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904896274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1904896274
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.4157329345
Short name T1211
Test name
Test status
Simulation time 16748546 ps
CPU time 0.6 seconds
Started Jun 26 05:53:43 PM PDT 24
Finished Jun 26 05:53:45 PM PDT 24
Peak memory 194824 kb
Host smart-6da854b5-dab9-46b2-8eb4-a8c176ce7623
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157329345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.4157329345
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.332943460
Short name T1154
Test name
Test status
Simulation time 50070509 ps
CPU time 0.64 seconds
Started Jun 26 05:53:45 PM PDT 24
Finished Jun 26 05:53:48 PM PDT 24
Peak memory 194792 kb
Host smart-f234b1c5-0996-4766-be6c-c95542ae7c26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332943460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.332943460
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.4240222887
Short name T1135
Test name
Test status
Simulation time 18996535 ps
CPU time 0.57 seconds
Started Jun 26 05:53:42 PM PDT 24
Finished Jun 26 05:53:44 PM PDT 24
Peak memory 194768 kb
Host smart-e63d5cb3-ed01-4d02-ba1c-d456509c4cf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240222887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.4240222887
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2809280299
Short name T1180
Test name
Test status
Simulation time 25499486 ps
CPU time 0.58 seconds
Started Jun 26 05:53:45 PM PDT 24
Finished Jun 26 05:53:47 PM PDT 24
Peak memory 194760 kb
Host smart-eb622dcb-e986-4530-9fb4-d96d8f8a2928
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809280299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2809280299
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2813577823
Short name T1191
Test name
Test status
Simulation time 26388361 ps
CPU time 0.65 seconds
Started Jun 26 05:53:46 PM PDT 24
Finished Jun 26 05:53:49 PM PDT 24
Peak memory 194664 kb
Host smart-c0f88f2b-fc0a-4dc3-8437-a3e5ce33a35c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813577823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2813577823
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.3183891054
Short name T1208
Test name
Test status
Simulation time 47860735 ps
CPU time 0.65 seconds
Started Jun 26 05:53:46 PM PDT 24
Finished Jun 26 05:53:49 PM PDT 24
Peak memory 194708 kb
Host smart-61ccc248-3166-4a3e-a24f-449b5c7f4218
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183891054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3183891054
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2516266202
Short name T1099
Test name
Test status
Simulation time 59946987 ps
CPU time 0.62 seconds
Started Jun 26 05:53:43 PM PDT 24
Finished Jun 26 05:53:45 PM PDT 24
Peak memory 194752 kb
Host smart-08aaef72-2366-4b61-9eb3-ca1f0eb17d63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516266202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2516266202
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3229738014
Short name T1160
Test name
Test status
Simulation time 25153334 ps
CPU time 0.58 seconds
Started Jun 26 05:53:42 PM PDT 24
Finished Jun 26 05:53:44 PM PDT 24
Peak memory 194732 kb
Host smart-63be5fe8-edf9-418c-8ab9-179f4d59f1d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229738014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3229738014
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2371539434
Short name T1151
Test name
Test status
Simulation time 45263682 ps
CPU time 1.27 seconds
Started Jun 26 05:53:10 PM PDT 24
Finished Jun 26 05:53:13 PM PDT 24
Peak memory 200460 kb
Host smart-06c28fbf-06b8-4991-9f90-bd17b67f4a98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371539434 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.2371539434
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.2465911905
Short name T1190
Test name
Test status
Simulation time 50110732 ps
CPU time 0.62 seconds
Started Jun 26 05:53:10 PM PDT 24
Finished Jun 26 05:53:11 PM PDT 24
Peak memory 195788 kb
Host smart-8f7dbaea-a1f2-43dc-b6ef-56a996ad2fdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465911905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2465911905
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.2772823636
Short name T1134
Test name
Test status
Simulation time 25905665 ps
CPU time 0.64 seconds
Started Jun 26 05:53:11 PM PDT 24
Finished Jun 26 05:53:14 PM PDT 24
Peak memory 194748 kb
Host smart-d61f8474-2b5d-40c6-807c-849c6dd9699c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772823636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2772823636
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3126935169
Short name T1148
Test name
Test status
Simulation time 20332384 ps
CPU time 0.69 seconds
Started Jun 26 05:53:12 PM PDT 24
Finished Jun 26 05:53:15 PM PDT 24
Peak memory 197180 kb
Host smart-f05bc6bd-7b0f-4a77-8558-cd9c8794d1ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126935169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.3126935169
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.3549720798
Short name T1106
Test name
Test status
Simulation time 38979579 ps
CPU time 1.14 seconds
Started Jun 26 05:53:10 PM PDT 24
Finished Jun 26 05:53:13 PM PDT 24
Peak memory 200420 kb
Host smart-6bd08a9a-aba7-49e3-ae51-c6e8c43315e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549720798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3549720798
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3818361838
Short name T108
Test name
Test status
Simulation time 190681186 ps
CPU time 0.93 seconds
Started Jun 26 05:53:11 PM PDT 24
Finished Jun 26 05:53:13 PM PDT 24
Peak memory 199192 kb
Host smart-e79b415b-9486-40a0-8f48-848899625442
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818361838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3818361838
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3657224057
Short name T1104
Test name
Test status
Simulation time 79902753 ps
CPU time 0.74 seconds
Started Jun 26 05:53:11 PM PDT 24
Finished Jun 26 05:53:13 PM PDT 24
Peak memory 199416 kb
Host smart-e7e7873e-e899-4cfe-83f9-cc3e47a726b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657224057 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.3657224057
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.3202561972
Short name T1233
Test name
Test status
Simulation time 55697956 ps
CPU time 0.59 seconds
Started Jun 26 05:53:12 PM PDT 24
Finished Jun 26 05:53:15 PM PDT 24
Peak memory 195804 kb
Host smart-c1663518-3735-4dd9-85a8-855b409b4c15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202561972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3202561972
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1323408418
Short name T1215
Test name
Test status
Simulation time 31015224 ps
CPU time 0.54 seconds
Started Jun 26 05:53:12 PM PDT 24
Finished Jun 26 05:53:15 PM PDT 24
Peak memory 195020 kb
Host smart-919f5bbb-1661-45af-b42a-324c7181cec7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323408418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1323408418
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3086909407
Short name T1231
Test name
Test status
Simulation time 34915643 ps
CPU time 0.63 seconds
Started Jun 26 05:53:12 PM PDT 24
Finished Jun 26 05:53:15 PM PDT 24
Peak memory 194852 kb
Host smart-0c6d8c96-959d-4713-b034-c7a2ab278bff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086909407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.3086909407
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1624507349
Short name T1216
Test name
Test status
Simulation time 51844378 ps
CPU time 1.18 seconds
Started Jun 26 05:53:10 PM PDT 24
Finished Jun 26 05:53:12 PM PDT 24
Peak memory 200396 kb
Host smart-f914bce7-a7c8-4853-9887-895b8d73f888
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624507349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1624507349
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1705753915
Short name T1182
Test name
Test status
Simulation time 96023252 ps
CPU time 0.95 seconds
Started Jun 26 05:53:12 PM PDT 24
Finished Jun 26 05:53:16 PM PDT 24
Peak memory 199208 kb
Host smart-e1b43f5c-84aa-40be-9f5b-13a8ddea0d1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705753915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.1705753915
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.181460390
Short name T1108
Test name
Test status
Simulation time 86800053 ps
CPU time 1.22 seconds
Started Jun 26 05:53:12 PM PDT 24
Finished Jun 26 05:53:16 PM PDT 24
Peak memory 200464 kb
Host smart-a3b4da5c-c977-4158-91f9-5d925337782d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181460390 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.181460390
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.2450770302
Short name T60
Test name
Test status
Simulation time 16606760 ps
CPU time 0.65 seconds
Started Jun 26 05:53:11 PM PDT 24
Finished Jun 26 05:53:14 PM PDT 24
Peak memory 196188 kb
Host smart-b667cbee-cbc8-46bb-b3e5-d285c30e13fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450770302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.2450770302
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.397090544
Short name T1136
Test name
Test status
Simulation time 42597606 ps
CPU time 0.56 seconds
Started Jun 26 05:53:11 PM PDT 24
Finished Jun 26 05:53:14 PM PDT 24
Peak memory 194828 kb
Host smart-b16a54c8-8fc6-4da6-a40c-f868e24b5a11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397090544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.397090544
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.810012765
Short name T1235
Test name
Test status
Simulation time 37034482 ps
CPU time 0.77 seconds
Started Jun 26 05:53:11 PM PDT 24
Finished Jun 26 05:53:13 PM PDT 24
Peak memory 197456 kb
Host smart-15dd8b01-a937-4788-8999-e5fc0e48aca2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810012765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_
outstanding.810012765
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.4136683210
Short name T1133
Test name
Test status
Simulation time 143361816 ps
CPU time 1.8 seconds
Started Jun 26 05:53:11 PM PDT 24
Finished Jun 26 05:53:15 PM PDT 24
Peak memory 200380 kb
Host smart-63d4adef-6877-42a2-a42f-dbc541904d73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136683210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.4136683210
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3270218717
Short name T78
Test name
Test status
Simulation time 177492837 ps
CPU time 0.96 seconds
Started Jun 26 05:53:11 PM PDT 24
Finished Jun 26 05:53:14 PM PDT 24
Peak memory 199508 kb
Host smart-9d3ee302-a5da-41e7-88b3-2dad44bd93b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270218717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3270218717
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3061665665
Short name T1112
Test name
Test status
Simulation time 75353558 ps
CPU time 0.79 seconds
Started Jun 26 05:53:19 PM PDT 24
Finished Jun 26 05:53:21 PM PDT 24
Peak memory 200064 kb
Host smart-a9e92784-6be3-42aa-9ccc-7fe0748688fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061665665 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.3061665665
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3540264479
Short name T68
Test name
Test status
Simulation time 49340363 ps
CPU time 0.63 seconds
Started Jun 26 05:53:18 PM PDT 24
Finished Jun 26 05:53:20 PM PDT 24
Peak memory 195896 kb
Host smart-607c6154-500a-4303-a468-231b9956fbe3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540264479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3540264479
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.4079876731
Short name T1196
Test name
Test status
Simulation time 14686003 ps
CPU time 0.58 seconds
Started Jun 26 05:53:20 PM PDT 24
Finished Jun 26 05:53:22 PM PDT 24
Peak memory 194800 kb
Host smart-cfd25161-c81b-4185-8e87-9557e38c5382
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079876731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.4079876731
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.354737813
Short name T1176
Test name
Test status
Simulation time 30172141 ps
CPU time 0.78 seconds
Started Jun 26 05:53:20 PM PDT 24
Finished Jun 26 05:53:23 PM PDT 24
Peak memory 197268 kb
Host smart-7049e0fd-47b6-4347-9d74-8f69265d3c0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354737813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_
outstanding.354737813
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.661681375
Short name T1172
Test name
Test status
Simulation time 587542128 ps
CPU time 2.55 seconds
Started Jun 26 05:53:20 PM PDT 24
Finished Jun 26 05:53:25 PM PDT 24
Peak memory 200300 kb
Host smart-09b2dcee-d8b6-4fc7-9672-5e25aa36f22d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661681375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.661681375
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2221025077
Short name T1174
Test name
Test status
Simulation time 41259063 ps
CPU time 0.95 seconds
Started Jun 26 05:53:22 PM PDT 24
Finished Jun 26 05:53:25 PM PDT 24
Peak memory 199472 kb
Host smart-dab3681d-72a5-4912-8022-6764e084c101
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221025077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2221025077
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1630239220
Short name T1207
Test name
Test status
Simulation time 107723670 ps
CPU time 0.84 seconds
Started Jun 26 05:53:23 PM PDT 24
Finished Jun 26 05:53:26 PM PDT 24
Peak memory 200192 kb
Host smart-42fef0a3-2e2f-4b1f-80fc-c7fdc798f0aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630239220 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1630239220
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.2191456762
Short name T1119
Test name
Test status
Simulation time 63960993 ps
CPU time 0.61 seconds
Started Jun 26 05:53:18 PM PDT 24
Finished Jun 26 05:53:20 PM PDT 24
Peak memory 195836 kb
Host smart-ae881813-1bc7-4fc2-b90e-e23dac9e8a93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191456762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2191456762
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.2798325110
Short name T1107
Test name
Test status
Simulation time 70990462 ps
CPU time 0.6 seconds
Started Jun 26 05:53:20 PM PDT 24
Finished Jun 26 05:53:23 PM PDT 24
Peak memory 195004 kb
Host smart-d32696b4-c368-4566-bb54-db4a87c466ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798325110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2798325110
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1397275169
Short name T1232
Test name
Test status
Simulation time 19960568 ps
CPU time 0.74 seconds
Started Jun 26 05:53:20 PM PDT 24
Finished Jun 26 05:53:22 PM PDT 24
Peak memory 197148 kb
Host smart-247cd2c4-ba79-4ce0-9803-408f5e71ecda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397275169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.1397275169
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1153487941
Short name T1197
Test name
Test status
Simulation time 95515714 ps
CPU time 1.36 seconds
Started Jun 26 05:53:19 PM PDT 24
Finished Jun 26 05:53:22 PM PDT 24
Peak memory 200452 kb
Host smart-720d384b-3471-45e2-bd72-33d665ea27bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153487941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1153487941
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1170449209
Short name T1127
Test name
Test status
Simulation time 288048807 ps
CPU time 1.06 seconds
Started Jun 26 05:53:18 PM PDT 24
Finished Jun 26 05:53:20 PM PDT 24
Peak memory 199216 kb
Host smart-0fd75760-a25e-417e-a99c-d903d9fd6483
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170449209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1170449209
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_fifo_full.2391604216
Short name T362
Test name
Test status
Simulation time 128211871348 ps
CPU time 89.03 seconds
Started Jun 26 06:09:59 PM PDT 24
Finished Jun 26 06:11:29 PM PDT 24
Peak memory 199776 kb
Host smart-dacc2845-a641-4574-9504-bff4efb1d697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391604216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2391604216
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_intr.1766490540
Short name T316
Test name
Test status
Simulation time 100048349606 ps
CPU time 40.32 seconds
Started Jun 26 06:10:14 PM PDT 24
Finished Jun 26 06:10:57 PM PDT 24
Peak memory 196136 kb
Host smart-d66db62d-3a03-40db-8f8a-7db8da1c4fce
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766490540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1766490540
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.1538335098
Short name T360
Test name
Test status
Simulation time 121078167087 ps
CPU time 198.17 seconds
Started Jun 26 06:10:04 PM PDT 24
Finished Jun 26 06:13:25 PM PDT 24
Peak memory 199940 kb
Host smart-47f56dbb-d13c-4a6f-973f-0c0bcd500cfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1538335098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1538335098
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.1111261203
Short name T634
Test name
Test status
Simulation time 2563085707 ps
CPU time 3.88 seconds
Started Jun 26 06:10:02 PM PDT 24
Finished Jun 26 06:10:07 PM PDT 24
Peak memory 197276 kb
Host smart-997fed4c-9bff-4ac6-b54b-582b9d1cb919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111261203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1111261203
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3888558305
Short name T399
Test name
Test status
Simulation time 6048930032 ps
CPU time 4.2 seconds
Started Jun 26 06:10:09 PM PDT 24
Finished Jun 26 06:10:17 PM PDT 24
Peak memory 199352 kb
Host smart-23a79d04-c23d-4d84-b7ca-d7a2f418d843
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3888558305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3888558305
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.3833447315
Short name T43
Test name
Test status
Simulation time 37915119397 ps
CPU time 15.3 seconds
Started Jun 26 06:10:12 PM PDT 24
Finished Jun 26 06:10:30 PM PDT 24
Peak memory 199924 kb
Host smart-79a0c7f0-6ce4-4118-aef5-0d6455303631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833447315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3833447315
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.755867922
Short name T628
Test name
Test status
Simulation time 38508397267 ps
CPU time 14.19 seconds
Started Jun 26 06:10:14 PM PDT 24
Finished Jun 26 06:10:31 PM PDT 24
Peak memory 196040 kb
Host smart-f5ab60fa-dbef-4881-9648-9134e3b35736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755867922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.755867922
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.1458331538
Short name T506
Test name
Test status
Simulation time 5967865759 ps
CPU time 22.09 seconds
Started Jun 26 06:10:18 PM PDT 24
Finished Jun 26 06:10:43 PM PDT 24
Peak memory 199712 kb
Host smart-94298dd3-efce-41eb-9f2d-2519b87a059c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458331538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1458331538
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.1298692852
Short name T629
Test name
Test status
Simulation time 241034267150 ps
CPU time 345.63 seconds
Started Jun 26 06:10:09 PM PDT 24
Finished Jun 26 06:15:58 PM PDT 24
Peak memory 199896 kb
Host smart-131e6e67-75f1-44d8-b329-f4999b122fdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298692852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1298692852
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.3533219458
Short name T52
Test name
Test status
Simulation time 353429551015 ps
CPU time 813.84 seconds
Started Jun 26 06:10:05 PM PDT 24
Finished Jun 26 06:23:41 PM PDT 24
Peak memory 216464 kb
Host smart-edc28aec-1fcf-4d4a-a209-a7ed42dbb73d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533219458 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.3533219458
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2009606783
Short name T293
Test name
Test status
Simulation time 1202447781 ps
CPU time 2.47 seconds
Started Jun 26 06:10:06 PM PDT 24
Finished Jun 26 06:10:11 PM PDT 24
Peak memory 198956 kb
Host smart-64a08d5b-df28-4db8-a858-1d2be8833d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009606783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2009606783
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.3328775908
Short name T1081
Test name
Test status
Simulation time 33880643916 ps
CPU time 15.4 seconds
Started Jun 26 06:10:02 PM PDT 24
Finished Jun 26 06:10:19 PM PDT 24
Peak memory 199928 kb
Host smart-e24fbf4c-b920-442e-9b1e-9892f7691e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328775908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3328775908
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.1336917882
Short name T622
Test name
Test status
Simulation time 24472076 ps
CPU time 0.57 seconds
Started Jun 26 06:10:24 PM PDT 24
Finished Jun 26 06:10:27 PM PDT 24
Peak memory 195304 kb
Host smart-bd1037ee-9b80-49e5-a45b-da910920c0a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336917882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.1336917882
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.1275235706
Short name T804
Test name
Test status
Simulation time 40088549902 ps
CPU time 61.8 seconds
Started Jun 26 06:10:18 PM PDT 24
Finished Jun 26 06:11:23 PM PDT 24
Peak memory 199952 kb
Host smart-75c3da49-3735-431f-9510-a08c8c802e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275235706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.1275235706
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.3515190863
Short name T908
Test name
Test status
Simulation time 39958653076 ps
CPU time 32.83 seconds
Started Jun 26 06:10:07 PM PDT 24
Finished Jun 26 06:10:44 PM PDT 24
Peak memory 199796 kb
Host smart-954cf526-9e60-4f74-9d19-d35ed669c354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515190863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3515190863
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.687535744
Short name T932
Test name
Test status
Simulation time 158743237024 ps
CPU time 219.49 seconds
Started Jun 26 06:10:08 PM PDT 24
Finished Jun 26 06:13:51 PM PDT 24
Peak memory 199876 kb
Host smart-32b4566e-efbd-4592-a06b-2cfba12ce8cc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687535744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.687535744
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.1871449550
Short name T2
Test name
Test status
Simulation time 65886098359 ps
CPU time 286.18 seconds
Started Jun 26 06:10:12 PM PDT 24
Finished Jun 26 06:15:01 PM PDT 24
Peak memory 199888 kb
Host smart-44069cfc-1ba1-41b4-9d32-325644443844
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1871449550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1871449550
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.3326594403
Short name T639
Test name
Test status
Simulation time 6923268099 ps
CPU time 30.91 seconds
Started Jun 26 06:10:17 PM PDT 24
Finished Jun 26 06:10:51 PM PDT 24
Peak memory 199876 kb
Host smart-76495055-f5c9-4bb4-801c-611ee94bcec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326594403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3326594403
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_perf.2569476870
Short name T756
Test name
Test status
Simulation time 23059768866 ps
CPU time 183.18 seconds
Started Jun 26 06:10:17 PM PDT 24
Finished Jun 26 06:13:23 PM PDT 24
Peak memory 199900 kb
Host smart-f45fe9b2-5893-48cc-ae86-f5e16153d570
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2569476870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2569476870
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.2994657147
Short name T989
Test name
Test status
Simulation time 7421037669 ps
CPU time 73.92 seconds
Started Jun 26 06:10:04 PM PDT 24
Finished Jun 26 06:11:21 PM PDT 24
Peak memory 199272 kb
Host smart-16dcab84-f34a-43c4-85ed-6205a4816d6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2994657147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2994657147
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.2004060363
Short name T14
Test name
Test status
Simulation time 47757644172 ps
CPU time 37.42 seconds
Started Jun 26 06:10:17 PM PDT 24
Finished Jun 26 06:10:57 PM PDT 24
Peak memory 199928 kb
Host smart-cc227cad-1abf-4683-9116-7a24d66ab1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004060363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2004060363
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.2189381828
Short name T1085
Test name
Test status
Simulation time 28929905659 ps
CPU time 12.23 seconds
Started Jun 26 06:10:03 PM PDT 24
Finished Jun 26 06:10:18 PM PDT 24
Peak memory 196624 kb
Host smart-bf9813ee-bbd0-4da6-aaab-0191fc16b287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189381828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2189381828
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.453247941
Short name T81
Test name
Test status
Simulation time 67362658 ps
CPU time 0.85 seconds
Started Jun 26 06:10:12 PM PDT 24
Finished Jun 26 06:10:16 PM PDT 24
Peak memory 218440 kb
Host smart-9d2d49a8-7a01-44e9-8ccf-63423242f565
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453247941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.453247941
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.4070863489
Short name T87
Test name
Test status
Simulation time 451051394 ps
CPU time 2.17 seconds
Started Jun 26 06:10:09 PM PDT 24
Finished Jun 26 06:10:15 PM PDT 24
Peak memory 198296 kb
Host smart-bd05dae0-9070-4dd8-ab39-baca74c10737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070863489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.4070863489
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.3760299582
Short name T1058
Test name
Test status
Simulation time 138620979174 ps
CPU time 59.75 seconds
Started Jun 26 06:10:11 PM PDT 24
Finished Jun 26 06:11:13 PM PDT 24
Peak memory 199748 kb
Host smart-c77e53ee-691f-49ab-b1aa-a9d638f43abc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760299582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3760299582
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.3258848288
Short name T17
Test name
Test status
Simulation time 1165470639 ps
CPU time 3.54 seconds
Started Jun 26 06:10:19 PM PDT 24
Finished Jun 26 06:10:25 PM PDT 24
Peak memory 198708 kb
Host smart-1937e12d-4488-4848-a599-0503c3f8d016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258848288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3258848288
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.724644953
Short name T519
Test name
Test status
Simulation time 239617374119 ps
CPU time 137.21 seconds
Started Jun 26 06:10:14 PM PDT 24
Finished Jun 26 06:12:34 PM PDT 24
Peak memory 199988 kb
Host smart-21000220-9581-48a9-906d-11096f3781df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724644953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.724644953
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.868884559
Short name T372
Test name
Test status
Simulation time 68311912 ps
CPU time 0.53 seconds
Started Jun 26 06:10:30 PM PDT 24
Finished Jun 26 06:10:32 PM PDT 24
Peak memory 195308 kb
Host smart-73a75d28-6b0a-4c91-87ef-6e5167225dcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868884559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.868884559
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.1493671708
Short name T897
Test name
Test status
Simulation time 62497390183 ps
CPU time 14.1 seconds
Started Jun 26 06:10:23 PM PDT 24
Finished Jun 26 06:10:40 PM PDT 24
Peak memory 199916 kb
Host smart-b764989d-fac1-473c-900d-f07bbd9a6e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493671708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.1493671708
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.934742630
Short name T910
Test name
Test status
Simulation time 96168581500 ps
CPU time 147.05 seconds
Started Jun 26 06:10:20 PM PDT 24
Finished Jun 26 06:12:50 PM PDT 24
Peak memory 199856 kb
Host smart-7c8364ed-d2e0-4ec9-bbbd-36c10ed8a064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934742630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.934742630
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.1369550787
Short name T929
Test name
Test status
Simulation time 59925156985 ps
CPU time 92.41 seconds
Started Jun 26 06:10:22 PM PDT 24
Finished Jun 26 06:11:57 PM PDT 24
Peak memory 199940 kb
Host smart-927ad52b-0b75-42e6-9191-fb55c8ac78a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369550787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1369550787
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.2075182342
Short name T306
Test name
Test status
Simulation time 35744929510 ps
CPU time 52.99 seconds
Started Jun 26 06:10:17 PM PDT 24
Finished Jun 26 06:11:13 PM PDT 24
Peak memory 197812 kb
Host smart-aaf608db-79a3-406d-b644-aeb624604520
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075182342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2075182342
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.824957264
Short name T439
Test name
Test status
Simulation time 100704296218 ps
CPU time 552.13 seconds
Started Jun 26 06:10:26 PM PDT 24
Finished Jun 26 06:19:42 PM PDT 24
Peak memory 200180 kb
Host smart-a3be61e3-3a88-43ad-aedf-ea0c5242961d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=824957264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.824957264
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.2377055806
Short name T347
Test name
Test status
Simulation time 8214258893 ps
CPU time 5.46 seconds
Started Jun 26 06:10:33 PM PDT 24
Finished Jun 26 06:10:41 PM PDT 24
Peak memory 199924 kb
Host smart-d72e6891-4b1b-41a2-aa9d-b0a7a9663ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377055806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2377055806
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.3319388446
Short name T906
Test name
Test status
Simulation time 4978330862 ps
CPU time 21.42 seconds
Started Jun 26 06:10:25 PM PDT 24
Finished Jun 26 06:10:50 PM PDT 24
Peak memory 198320 kb
Host smart-6af639bb-fda6-4da7-9719-a34ce25b7a4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3319388446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.3319388446
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.1724662770
Short name T883
Test name
Test status
Simulation time 15068237208 ps
CPU time 19.75 seconds
Started Jun 26 06:10:24 PM PDT 24
Finished Jun 26 06:10:48 PM PDT 24
Peak memory 199896 kb
Host smart-1ffd8711-c6b4-4601-be22-32e9f20cf614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724662770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1724662770
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.2590575835
Short name T651
Test name
Test status
Simulation time 44348350062 ps
CPU time 67.34 seconds
Started Jun 26 06:10:28 PM PDT 24
Finished Jun 26 06:11:38 PM PDT 24
Peak memory 195956 kb
Host smart-21d7cc65-5210-49cd-9226-d87bf12c3ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590575835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2590575835
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.2776686267
Short name T525
Test name
Test status
Simulation time 135638095 ps
CPU time 0.94 seconds
Started Jun 26 06:10:27 PM PDT 24
Finished Jun 26 06:10:31 PM PDT 24
Peak memory 197636 kb
Host smart-fae994db-8a9f-4bc2-bcb8-a236b866edd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776686267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2776686267
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.1454636446
Short name T482
Test name
Test status
Simulation time 12964382091 ps
CPU time 17.48 seconds
Started Jun 26 06:10:23 PM PDT 24
Finished Jun 26 06:10:43 PM PDT 24
Peak memory 199816 kb
Host smart-1465f72b-bf7b-47af-a169-9430ed541b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454636446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1454636446
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.4286210175
Short name T609
Test name
Test status
Simulation time 63454161392 ps
CPU time 112.28 seconds
Started Jun 26 06:10:29 PM PDT 24
Finished Jun 26 06:12:23 PM PDT 24
Peak memory 199940 kb
Host smart-5e4d6655-82cc-4705-a1fe-63eb6c871ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286210175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.4286210175
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.2507764913
Short name T415
Test name
Test status
Simulation time 40925953719 ps
CPU time 34.11 seconds
Started Jun 26 06:13:09 PM PDT 24
Finished Jun 26 06:13:45 PM PDT 24
Peak memory 199920 kb
Host smart-542b6ab2-d3bc-44e6-9af9-a881242df2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507764913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2507764913
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.1807397330
Short name T10
Test name
Test status
Simulation time 56294333554 ps
CPU time 79.33 seconds
Started Jun 26 06:13:11 PM PDT 24
Finished Jun 26 06:14:32 PM PDT 24
Peak memory 199884 kb
Host smart-3a6de9c5-e021-48ea-ae92-e3f535c1c98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807397330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.1807397330
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.2082706660
Short name T719
Test name
Test status
Simulation time 134751635080 ps
CPU time 182.86 seconds
Started Jun 26 06:13:09 PM PDT 24
Finished Jun 26 06:16:14 PM PDT 24
Peak memory 199948 kb
Host smart-f43cd302-fba9-4d31-9c8e-d24bfcd70314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082706660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2082706660
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.3346724697
Short name T765
Test name
Test status
Simulation time 113120869385 ps
CPU time 171.39 seconds
Started Jun 26 06:13:08 PM PDT 24
Finished Jun 26 06:16:02 PM PDT 24
Peak memory 199948 kb
Host smart-c454e582-b2b9-4a3c-a4dd-b356543d29d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346724697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.3346724697
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2059981804
Short name T531
Test name
Test status
Simulation time 338107073566 ps
CPU time 96.11 seconds
Started Jun 26 06:13:07 PM PDT 24
Finished Jun 26 06:14:45 PM PDT 24
Peak memory 200008 kb
Host smart-c5a0ebbe-9f96-483d-99ea-baa77b3fb661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059981804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2059981804
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3831151976
Short name T850
Test name
Test status
Simulation time 70365550777 ps
CPU time 34.64 seconds
Started Jun 26 06:13:08 PM PDT 24
Finished Jun 26 06:13:44 PM PDT 24
Peak memory 200008 kb
Host smart-26c36cfc-00c7-43fb-8cc4-13d68702ed60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831151976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3831151976
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.831110702
Short name T616
Test name
Test status
Simulation time 60387586032 ps
CPU time 12.42 seconds
Started Jun 26 06:13:10 PM PDT 24
Finished Jun 26 06:13:25 PM PDT 24
Peak memory 198880 kb
Host smart-8e14120a-4974-4e3d-9235-8b1362bd41c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831110702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.831110702
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.3123429695
Short name T227
Test name
Test status
Simulation time 49013102827 ps
CPU time 83.99 seconds
Started Jun 26 06:13:07 PM PDT 24
Finished Jun 26 06:14:31 PM PDT 24
Peak memory 200000 kb
Host smart-623efe23-f122-4108-9653-ad6768890dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123429695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.3123429695
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.3149389121
Short name T408
Test name
Test status
Simulation time 50194548080 ps
CPU time 19.49 seconds
Started Jun 26 06:13:16 PM PDT 24
Finished Jun 26 06:13:36 PM PDT 24
Peak memory 200000 kb
Host smart-83e48c79-c768-4324-8273-5e5601624ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149389121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3149389121
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.662551277
Short name T1043
Test name
Test status
Simulation time 36839714 ps
CPU time 0.58 seconds
Started Jun 26 06:10:38 PM PDT 24
Finished Jun 26 06:10:40 PM PDT 24
Peak memory 195320 kb
Host smart-3d3d6dda-3262-4e8b-a4f3-c771fe8273fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662551277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.662551277
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.3568471335
Short name T729
Test name
Test status
Simulation time 55003727810 ps
CPU time 77.68 seconds
Started Jun 26 06:10:26 PM PDT 24
Finished Jun 26 06:11:47 PM PDT 24
Peak memory 199944 kb
Host smart-74841e4c-2737-481d-b05a-bc1e3e55fe2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568471335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3568471335
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.3437746729
Short name T606
Test name
Test status
Simulation time 31392426572 ps
CPU time 68.12 seconds
Started Jun 26 06:10:24 PM PDT 24
Finished Jun 26 06:11:35 PM PDT 24
Peak memory 199940 kb
Host smart-42f124f0-ebaf-4fd3-a4a7-4fe2b74da2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437746729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3437746729
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2889462205
Short name T647
Test name
Test status
Simulation time 79917616121 ps
CPU time 29.72 seconds
Started Jun 26 06:10:25 PM PDT 24
Finished Jun 26 06:10:59 PM PDT 24
Peak memory 199712 kb
Host smart-eb5b9fe1-9a59-4949-b7e0-1822425c31b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889462205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2889462205
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.2076305522
Short name T240
Test name
Test status
Simulation time 22547206026 ps
CPU time 10.48 seconds
Started Jun 26 06:10:37 PM PDT 24
Finished Jun 26 06:10:49 PM PDT 24
Peak memory 199840 kb
Host smart-6661f44e-f0d2-4e9e-ae0c-cb4a8e341713
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076305522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2076305522
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.3542778230
Short name T39
Test name
Test status
Simulation time 92788448994 ps
CPU time 424.28 seconds
Started Jun 26 06:10:39 PM PDT 24
Finished Jun 26 06:17:44 PM PDT 24
Peak memory 199928 kb
Host smart-2a5b2b2f-c13c-41c4-9924-48c098ba5c85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3542778230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3542778230
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.363533059
Short name T1036
Test name
Test status
Simulation time 7761144222 ps
CPU time 11.73 seconds
Started Jun 26 06:10:24 PM PDT 24
Finished Jun 26 06:10:40 PM PDT 24
Peak memory 199936 kb
Host smart-3809186c-0380-46ac-904f-60fe5e4e17fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363533059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.363533059
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_perf.2557866852
Short name T726
Test name
Test status
Simulation time 8254762484 ps
CPU time 119.1 seconds
Started Jun 26 06:10:26 PM PDT 24
Finished Jun 26 06:12:29 PM PDT 24
Peak memory 199944 kb
Host smart-a90eaace-758d-4839-8501-eb5af609f0e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2557866852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2557866852
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.1122639337
Short name T625
Test name
Test status
Simulation time 4899357123 ps
CPU time 11.83 seconds
Started Jun 26 06:10:27 PM PDT 24
Finished Jun 26 06:10:41 PM PDT 24
Peak memory 199500 kb
Host smart-b7c741c5-3c95-4af0-911f-e7120c2ac921
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1122639337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1122639337
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.3970501727
Short name T905
Test name
Test status
Simulation time 46494104591 ps
CPU time 43.81 seconds
Started Jun 26 06:10:30 PM PDT 24
Finished Jun 26 06:11:16 PM PDT 24
Peak memory 199008 kb
Host smart-282bb84b-4555-4549-b7cf-1532ca2ecf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970501727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3970501727
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.905554081
Short name T626
Test name
Test status
Simulation time 2049165968 ps
CPU time 1.44 seconds
Started Jun 26 06:10:37 PM PDT 24
Finished Jun 26 06:10:39 PM PDT 24
Peak memory 195512 kb
Host smart-75b3d732-162c-4d5c-b498-b24e0c457d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905554081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.905554081
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.3488383354
Short name T543
Test name
Test status
Simulation time 692945635 ps
CPU time 2.59 seconds
Started Jun 26 06:10:28 PM PDT 24
Finished Jun 26 06:10:33 PM PDT 24
Peak memory 198480 kb
Host smart-40e87cba-3d05-4c50-8c1b-da292402c685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488383354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3488383354
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.590976435
Short name T253
Test name
Test status
Simulation time 18126823270 ps
CPU time 277.14 seconds
Started Jun 26 06:10:25 PM PDT 24
Finished Jun 26 06:15:05 PM PDT 24
Peak memory 208272 kb
Host smart-3d2b4297-2474-4567-80e1-7e0508315416
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590976435 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.590976435
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2356539825
Short name T711
Test name
Test status
Simulation time 7030560346 ps
CPU time 11.99 seconds
Started Jun 26 06:10:23 PM PDT 24
Finished Jun 26 06:10:38 PM PDT 24
Peak memory 199880 kb
Host smart-eadbfc9c-8c0b-45d5-be2b-823103297f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356539825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2356539825
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.80002700
Short name T570
Test name
Test status
Simulation time 33864222168 ps
CPU time 43.46 seconds
Started Jun 26 06:10:28 PM PDT 24
Finished Jun 26 06:11:14 PM PDT 24
Peak memory 199904 kb
Host smart-82fb32b6-0ba8-4653-960d-89c9f57ad189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80002700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.80002700
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.3402581022
Short name T353
Test name
Test status
Simulation time 16797070469 ps
CPU time 23.86 seconds
Started Jun 26 06:13:17 PM PDT 24
Finished Jun 26 06:13:42 PM PDT 24
Peak memory 199972 kb
Host smart-a004b709-279b-42ee-90c0-e0cb7b34db3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402581022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3402581022
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.2574925932
Short name T563
Test name
Test status
Simulation time 221216329733 ps
CPU time 70.28 seconds
Started Jun 26 06:14:15 PM PDT 24
Finished Jun 26 06:15:26 PM PDT 24
Peak memory 199856 kb
Host smart-b46cc588-bf95-4d61-94d5-9205f9149add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574925932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.2574925932
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.2151338142
Short name T548
Test name
Test status
Simulation time 42288698851 ps
CPU time 21.97 seconds
Started Jun 26 06:13:16 PM PDT 24
Finished Jun 26 06:13:39 PM PDT 24
Peak memory 200016 kb
Host smart-f266f645-754b-47db-9ce7-8f992f85d37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151338142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.2151338142
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.2019175758
Short name T151
Test name
Test status
Simulation time 54596090222 ps
CPU time 84.69 seconds
Started Jun 26 06:13:16 PM PDT 24
Finished Jun 26 06:14:42 PM PDT 24
Peak memory 199980 kb
Host smart-88986cef-b5b5-4fd7-8f8f-9ab4b0391820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019175758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2019175758
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.1832178679
Short name T413
Test name
Test status
Simulation time 86755458669 ps
CPU time 66.69 seconds
Started Jun 26 06:13:17 PM PDT 24
Finished Jun 26 06:14:25 PM PDT 24
Peak memory 200004 kb
Host smart-1c5d3a3d-6d5a-4d05-bc7e-b5e662df9ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832178679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1832178679
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.255776703
Short name T465
Test name
Test status
Simulation time 14276158550 ps
CPU time 14.26 seconds
Started Jun 26 06:13:19 PM PDT 24
Finished Jun 26 06:13:34 PM PDT 24
Peak memory 199900 kb
Host smart-18fd2cb1-f8a1-4172-b988-28da02123b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255776703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.255776703
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.3317963391
Short name T923
Test name
Test status
Simulation time 9342931989 ps
CPU time 10.76 seconds
Started Jun 26 06:13:17 PM PDT 24
Finished Jun 26 06:13:30 PM PDT 24
Peak memory 199996 kb
Host smart-e1022128-77c4-4f96-9457-967b98394ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317963391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3317963391
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.3662686487
Short name T490
Test name
Test status
Simulation time 22630166068 ps
CPU time 34.8 seconds
Started Jun 26 06:13:18 PM PDT 24
Finished Jun 26 06:13:54 PM PDT 24
Peak memory 199848 kb
Host smart-cc3b8e71-e4ab-43c2-9944-49977191ece4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662686487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.3662686487
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.3388456322
Short name T226
Test name
Test status
Simulation time 37290116923 ps
CPU time 18.94 seconds
Started Jun 26 06:13:14 PM PDT 24
Finished Jun 26 06:13:34 PM PDT 24
Peak memory 200000 kb
Host smart-73475969-9637-4713-a5b5-36047f1dac45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388456322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.3388456322
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.2174338819
Short name T987
Test name
Test status
Simulation time 104704091 ps
CPU time 0.56 seconds
Started Jun 26 06:10:30 PM PDT 24
Finished Jun 26 06:10:33 PM PDT 24
Peak memory 195520 kb
Host smart-bb9af3b8-dc90-4b40-91b0-4759cc103290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174338819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2174338819
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.1982685837
Short name T968
Test name
Test status
Simulation time 92274993189 ps
CPU time 33.41 seconds
Started Jun 26 06:10:27 PM PDT 24
Finished Jun 26 06:11:03 PM PDT 24
Peak memory 199980 kb
Host smart-e6caf0bf-2a68-4e4e-bf01-1ebd083d3752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982685837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.1982685837
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2580023745
Short name T451
Test name
Test status
Simulation time 58750373636 ps
CPU time 31.69 seconds
Started Jun 26 06:10:24 PM PDT 24
Finished Jun 26 06:10:59 PM PDT 24
Peak memory 199948 kb
Host smart-beb2da02-9231-4369-a1b8-5c03a312687d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580023745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2580023745
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2654960858
Short name T324
Test name
Test status
Simulation time 6611468581 ps
CPU time 11.23 seconds
Started Jun 26 06:10:26 PM PDT 24
Finished Jun 26 06:10:41 PM PDT 24
Peak memory 199952 kb
Host smart-76942dc3-9988-463e-a66d-5de518b5087e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654960858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2654960858
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.1856071968
Short name T1009
Test name
Test status
Simulation time 36118299151 ps
CPU time 62.93 seconds
Started Jun 26 06:10:24 PM PDT 24
Finished Jun 26 06:11:30 PM PDT 24
Peak memory 199880 kb
Host smart-273e67dd-a883-44d6-92e6-97ccd25c1df4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856071968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1856071968
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.943866387
Short name T584
Test name
Test status
Simulation time 122121202345 ps
CPU time 356.2 seconds
Started Jun 26 06:10:37 PM PDT 24
Finished Jun 26 06:16:36 PM PDT 24
Peak memory 199972 kb
Host smart-5e776853-14e6-42ba-b8ed-4eba26aa3290
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=943866387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.943866387
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.2909988491
Short name T611
Test name
Test status
Simulation time 2195089443 ps
CPU time 2.11 seconds
Started Jun 26 06:10:33 PM PDT 24
Finished Jun 26 06:10:37 PM PDT 24
Peak memory 198516 kb
Host smart-2c822186-9cdd-47e2-9059-69717e3a8493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909988491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2909988491
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_perf.3505462001
Short name T312
Test name
Test status
Simulation time 12830182451 ps
CPU time 413.31 seconds
Started Jun 26 06:10:37 PM PDT 24
Finished Jun 26 06:17:32 PM PDT 24
Peak memory 199900 kb
Host smart-77b61a87-0969-4ca7-92d5-b2eef8dfb657
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3505462001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3505462001
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.1067852842
Short name T791
Test name
Test status
Simulation time 5627286445 ps
CPU time 23.98 seconds
Started Jun 26 06:10:25 PM PDT 24
Finished Jun 26 06:10:52 PM PDT 24
Peak memory 198056 kb
Host smart-fe25d00a-0e49-4b01-abc8-2681ac6164de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1067852842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1067852842
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.2220477571
Short name T956
Test name
Test status
Simulation time 100621026224 ps
CPU time 64.09 seconds
Started Jun 26 06:10:33 PM PDT 24
Finished Jun 26 06:11:39 PM PDT 24
Peak memory 199924 kb
Host smart-84a060e6-bd7e-45a2-b89f-e3ac799d58fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220477571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2220477571
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.134161112
Short name T829
Test name
Test status
Simulation time 4090171283 ps
CPU time 2.23 seconds
Started Jun 26 06:10:43 PM PDT 24
Finished Jun 26 06:10:46 PM PDT 24
Peak memory 196328 kb
Host smart-c676842e-8831-426f-91c8-c5e1d96ba33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134161112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.134161112
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.3502016424
Short name T442
Test name
Test status
Simulation time 528775508 ps
CPU time 1.14 seconds
Started Jun 26 06:10:30 PM PDT 24
Finished Jun 26 06:10:33 PM PDT 24
Peak memory 197520 kb
Host smart-c2cd1912-a787-4ac0-a8a9-e83439cfea2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502016424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3502016424
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.705545216
Short name T619
Test name
Test status
Simulation time 142010071585 ps
CPU time 193.7 seconds
Started Jun 26 06:10:36 PM PDT 24
Finished Jun 26 06:13:52 PM PDT 24
Peak memory 199972 kb
Host smart-50ee0a3b-2c5e-427d-aac5-4e28fb4359c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705545216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.705545216
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3372242692
Short name T749
Test name
Test status
Simulation time 4851681898 ps
CPU time 1.5 seconds
Started Jun 26 06:10:38 PM PDT 24
Finished Jun 26 06:10:41 PM PDT 24
Peak memory 199792 kb
Host smart-88f998d5-83d8-4a7a-b463-0d34362f9658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372242692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3372242692
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.2085161702
Short name T529
Test name
Test status
Simulation time 60367356784 ps
CPU time 25.39 seconds
Started Jun 26 06:13:17 PM PDT 24
Finished Jun 26 06:13:44 PM PDT 24
Peak memory 199948 kb
Host smart-822712f8-3775-41c9-80ae-8287d55f1e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085161702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.2085161702
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.4139805986
Short name T886
Test name
Test status
Simulation time 193245851704 ps
CPU time 64.2 seconds
Started Jun 26 06:13:17 PM PDT 24
Finished Jun 26 06:14:23 PM PDT 24
Peak memory 199960 kb
Host smart-a6592a22-313e-4266-b22e-415020681733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139805986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.4139805986
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.2401851887
Short name T796
Test name
Test status
Simulation time 29323762228 ps
CPU time 21.68 seconds
Started Jun 26 06:13:20 PM PDT 24
Finished Jun 26 06:13:42 PM PDT 24
Peak memory 199952 kb
Host smart-931c455e-ca17-4c96-b62c-9b6a01c14e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401851887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.2401851887
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3736788221
Short name T173
Test name
Test status
Simulation time 31186848217 ps
CPU time 47.89 seconds
Started Jun 26 06:13:24 PM PDT 24
Finished Jun 26 06:14:14 PM PDT 24
Peak memory 199912 kb
Host smart-9aaa1aad-e6f0-4014-8238-edca072e4bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736788221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3736788221
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1904164654
Short name T38
Test name
Test status
Simulation time 28780756582 ps
CPU time 44.12 seconds
Started Jun 26 06:13:21 PM PDT 24
Finished Jun 26 06:14:07 PM PDT 24
Peak memory 199940 kb
Host smart-d2ed79fb-26d5-4c44-bee6-87ae87c41897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904164654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1904164654
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.2998432189
Short name T153
Test name
Test status
Simulation time 312177195092 ps
CPU time 21.55 seconds
Started Jun 26 06:13:22 PM PDT 24
Finished Jun 26 06:13:45 PM PDT 24
Peak memory 199844 kb
Host smart-dcefc733-ca0a-4e2c-9de0-b63ce2cd1306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998432189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2998432189
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.4155259395
Short name T169
Test name
Test status
Simulation time 110171752003 ps
CPU time 189.93 seconds
Started Jun 26 06:13:22 PM PDT 24
Finished Jun 26 06:16:34 PM PDT 24
Peak memory 200004 kb
Host smart-dd09caed-7b05-4043-a6ea-a1bacd4e765c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155259395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.4155259395
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2850435525
Short name T197
Test name
Test status
Simulation time 137309938910 ps
CPU time 34.52 seconds
Started Jun 26 06:13:23 PM PDT 24
Finished Jun 26 06:13:59 PM PDT 24
Peak memory 199924 kb
Host smart-8d1a49c2-f19c-4b61-904b-e61c582d7bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850435525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2850435525
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.2972143300
Short name T902
Test name
Test status
Simulation time 55025716 ps
CPU time 0.57 seconds
Started Jun 26 06:10:33 PM PDT 24
Finished Jun 26 06:10:36 PM PDT 24
Peak memory 195284 kb
Host smart-0685a202-e891-4a74-8a6c-5533b319cdf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972143300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2972143300
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.661850172
Short name T992
Test name
Test status
Simulation time 175641696374 ps
CPU time 267.5 seconds
Started Jun 26 06:10:41 PM PDT 24
Finished Jun 26 06:15:10 PM PDT 24
Peak memory 199920 kb
Host smart-77bdd87c-0591-46db-a32f-29400b9518c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661850172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.661850172
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2808488287
Short name T514
Test name
Test status
Simulation time 15008860074 ps
CPU time 20.38 seconds
Started Jun 26 06:10:32 PM PDT 24
Finished Jun 26 06:10:55 PM PDT 24
Peak memory 199976 kb
Host smart-c9299994-5ece-4247-8406-6f4ec14402be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808488287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2808488287
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1724506656
Short name T1096
Test name
Test status
Simulation time 102501176745 ps
CPU time 131.54 seconds
Started Jun 26 06:10:46 PM PDT 24
Finished Jun 26 06:12:59 PM PDT 24
Peak memory 199912 kb
Host smart-59a320d3-791d-4b30-8663-b7b9b304f0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724506656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1724506656
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3740069981
Short name T901
Test name
Test status
Simulation time 43112273953 ps
CPU time 134.3 seconds
Started Jun 26 06:10:37 PM PDT 24
Finished Jun 26 06:12:53 PM PDT 24
Peak memory 199920 kb
Host smart-c8739e23-ebdc-4572-96aa-37a74333a42b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3740069981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3740069981
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.3505769753
Short name T665
Test name
Test status
Simulation time 3737653362 ps
CPU time 2.29 seconds
Started Jun 26 06:10:34 PM PDT 24
Finished Jun 26 06:10:39 PM PDT 24
Peak memory 197668 kb
Host smart-6a7fc8a0-b5e6-4dba-b19a-aaddbdc84078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505769753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3505769753
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_perf.79037893
Short name T518
Test name
Test status
Simulation time 6528880440 ps
CPU time 73.85 seconds
Started Jun 26 06:10:51 PM PDT 24
Finished Jun 26 06:12:08 PM PDT 24
Peak memory 200184 kb
Host smart-62d82617-c786-49bc-b3b8-f875f12dcaa0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=79037893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.79037893
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.1135381097
Short name T853
Test name
Test status
Simulation time 6215019766 ps
CPU time 21.51 seconds
Started Jun 26 06:10:31 PM PDT 24
Finished Jun 26 06:10:55 PM PDT 24
Peak memory 198932 kb
Host smart-69bcced0-f417-4bd5-92ba-de87273f4f49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1135381097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.1135381097
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.2694533135
Short name T671
Test name
Test status
Simulation time 10537135372 ps
CPU time 15.29 seconds
Started Jun 26 06:10:30 PM PDT 24
Finished Jun 26 06:10:48 PM PDT 24
Peak memory 198524 kb
Host smart-08539f1d-8678-43f2-85d0-bcc0dfd739e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694533135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2694533135
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.2159638736
Short name T385
Test name
Test status
Simulation time 4806321912 ps
CPU time 2.48 seconds
Started Jun 26 06:10:33 PM PDT 24
Finished Jun 26 06:10:38 PM PDT 24
Peak memory 196216 kb
Host smart-5552bf66-a53c-4562-8c62-aaa34132a5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159638736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2159638736
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.1451317891
Short name T961
Test name
Test status
Simulation time 494829164 ps
CPU time 1.42 seconds
Started Jun 26 06:10:39 PM PDT 24
Finished Jun 26 06:10:42 PM PDT 24
Peak memory 198820 kb
Host smart-9c1b1c15-fda7-4550-9653-3b1aa3797531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451317891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1451317891
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.1206911317
Short name T282
Test name
Test status
Simulation time 50163416647 ps
CPU time 352.85 seconds
Started Jun 26 06:10:33 PM PDT 24
Finished Jun 26 06:16:28 PM PDT 24
Peak memory 199720 kb
Host smart-5bfd570f-41d1-461b-b7fc-6f8a1a4396eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206911317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1206911317
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.1802130525
Short name T670
Test name
Test status
Simulation time 37264744346 ps
CPU time 701.8 seconds
Started Jun 26 06:10:34 PM PDT 24
Finished Jun 26 06:22:18 PM PDT 24
Peak memory 216364 kb
Host smart-fd83bfc7-4924-48ee-9ca9-b872015e424b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802130525 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.1802130525
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.2859817125
Short name T918
Test name
Test status
Simulation time 1600031417 ps
CPU time 1.98 seconds
Started Jun 26 06:10:38 PM PDT 24
Finished Jun 26 06:10:42 PM PDT 24
Peak memory 198484 kb
Host smart-90f44af3-963f-480c-b2d4-da67b15b1f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859817125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.2859817125
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.2440674892
Short name T823
Test name
Test status
Simulation time 108526521564 ps
CPU time 199.52 seconds
Started Jun 26 06:10:37 PM PDT 24
Finished Jun 26 06:13:59 PM PDT 24
Peak memory 199980 kb
Host smart-465bdd26-e2eb-4a19-ac0c-00d142c4c144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440674892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2440674892
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.1337556994
Short name T808
Test name
Test status
Simulation time 82127107428 ps
CPU time 34.05 seconds
Started Jun 26 06:13:26 PM PDT 24
Finished Jun 26 06:14:02 PM PDT 24
Peak memory 199888 kb
Host smart-5270415c-ff57-447b-a98d-05dbffcd5ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337556994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1337556994
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.691441348
Short name T476
Test name
Test status
Simulation time 116145002843 ps
CPU time 255.33 seconds
Started Jun 26 06:13:24 PM PDT 24
Finished Jun 26 06:17:41 PM PDT 24
Peak memory 199996 kb
Host smart-89107e63-c88f-4829-a652-bf8d398d923e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691441348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.691441348
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.3843509621
Short name T445
Test name
Test status
Simulation time 74117529135 ps
CPU time 162.51 seconds
Started Jun 26 06:13:23 PM PDT 24
Finished Jun 26 06:16:07 PM PDT 24
Peak memory 199836 kb
Host smart-ff0a33dc-3602-446f-96bf-26be46c2835e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843509621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3843509621
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.378210822
Short name T1063
Test name
Test status
Simulation time 31967247674 ps
CPU time 14.5 seconds
Started Jun 26 06:13:22 PM PDT 24
Finished Jun 26 06:13:38 PM PDT 24
Peak memory 199992 kb
Host smart-24053263-f040-44fe-b8ce-c45a3e4311bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378210822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.378210822
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.851350550
Short name T41
Test name
Test status
Simulation time 133124752827 ps
CPU time 99.88 seconds
Started Jun 26 06:13:22 PM PDT 24
Finished Jun 26 06:15:04 PM PDT 24
Peak memory 199956 kb
Host smart-086ec947-fb74-4aee-882f-4445d7ad8483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851350550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.851350550
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.3343783376
Short name T566
Test name
Test status
Simulation time 51072595849 ps
CPU time 18.87 seconds
Started Jun 26 06:13:22 PM PDT 24
Finished Jun 26 06:13:43 PM PDT 24
Peak memory 200004 kb
Host smart-82c4a68a-bf83-4cb8-958d-96a105eeb673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343783376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3343783376
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2446202316
Short name T801
Test name
Test status
Simulation time 55528941058 ps
CPU time 10.95 seconds
Started Jun 26 06:13:21 PM PDT 24
Finished Jun 26 06:13:34 PM PDT 24
Peak memory 199888 kb
Host smart-dc18e8ac-7560-43cc-a6c0-ad07b4c26a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446202316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2446202316
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.557597271
Short name T260
Test name
Test status
Simulation time 23434514462 ps
CPU time 45.32 seconds
Started Jun 26 06:13:21 PM PDT 24
Finished Jun 26 06:14:08 PM PDT 24
Peak memory 200020 kb
Host smart-6b183aa3-f1f3-4048-a997-bf913d0fab78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557597271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.557597271
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.3934584039
Short name T1075
Test name
Test status
Simulation time 12594958 ps
CPU time 0.56 seconds
Started Jun 26 06:10:51 PM PDT 24
Finished Jun 26 06:10:55 PM PDT 24
Peak memory 195332 kb
Host smart-79028ea9-ebd0-4315-8969-ada00f1e48fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934584039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3934584039
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.123081133
Short name T572
Test name
Test status
Simulation time 231257462549 ps
CPU time 89.65 seconds
Started Jun 26 06:10:36 PM PDT 24
Finished Jun 26 06:12:07 PM PDT 24
Peak memory 200020 kb
Host smart-b6823668-ac10-484c-bee1-b8f307998110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123081133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.123081133
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.2124956827
Short name T120
Test name
Test status
Simulation time 135868640708 ps
CPU time 108.99 seconds
Started Jun 26 06:10:38 PM PDT 24
Finished Jun 26 06:12:29 PM PDT 24
Peak memory 199944 kb
Host smart-304ef5f6-8b1c-4f95-88d9-f859a39459b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124956827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2124956827
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.2075581405
Short name T602
Test name
Test status
Simulation time 129084021850 ps
CPU time 100.67 seconds
Started Jun 26 06:10:33 PM PDT 24
Finished Jun 26 06:12:16 PM PDT 24
Peak memory 199956 kb
Host smart-f1ce303f-0be8-4453-a480-c476c2bcbf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075581405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.2075581405
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.4262085224
Short name T894
Test name
Test status
Simulation time 13079803496 ps
CPU time 4.68 seconds
Started Jun 26 06:10:31 PM PDT 24
Finished Jun 26 06:10:38 PM PDT 24
Peak memory 196372 kb
Host smart-b8305f62-3314-4aee-af66-f4aa7cbfe7e9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262085224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.4262085224
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.4061091755
Short name T738
Test name
Test status
Simulation time 220989801820 ps
CPU time 329.61 seconds
Started Jun 26 06:10:51 PM PDT 24
Finished Jun 26 06:16:24 PM PDT 24
Peak memory 199996 kb
Host smart-0e8a1414-47a3-4bb6-b39d-d87a32daaf28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4061091755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.4061091755
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.786351542
Short name T995
Test name
Test status
Simulation time 4783853097 ps
CPU time 8.68 seconds
Started Jun 26 06:10:35 PM PDT 24
Finished Jun 26 06:10:45 PM PDT 24
Peak memory 198032 kb
Host smart-d7e5305b-baa8-41e2-afac-5c7a2653a98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786351542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.786351542
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_perf.1494901884
Short name T731
Test name
Test status
Simulation time 14015043108 ps
CPU time 392.88 seconds
Started Jun 26 06:10:50 PM PDT 24
Finished Jun 26 06:17:26 PM PDT 24
Peak memory 199960 kb
Host smart-75b65373-60a0-49ce-9708-9c399fcd7593
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1494901884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1494901884
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.3040435456
Short name T775
Test name
Test status
Simulation time 4443223990 ps
CPU time 17.87 seconds
Started Jun 26 06:10:38 PM PDT 24
Finished Jun 26 06:10:57 PM PDT 24
Peak memory 199252 kb
Host smart-be8a7358-1934-4770-8ac0-c5ec840beca4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3040435456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.3040435456
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.3804741549
Short name T449
Test name
Test status
Simulation time 21789265649 ps
CPU time 31.32 seconds
Started Jun 26 06:10:38 PM PDT 24
Finished Jun 26 06:11:11 PM PDT 24
Peak memory 199960 kb
Host smart-b25b3005-de1f-49ec-b2c0-6f49f81fe593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804741549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.3804741549
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.4257883559
Short name T827
Test name
Test status
Simulation time 36785584556 ps
CPU time 15.3 seconds
Started Jun 26 06:10:35 PM PDT 24
Finished Jun 26 06:10:52 PM PDT 24
Peak memory 195900 kb
Host smart-2d4646d5-f2ab-4548-bb14-337d47689eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257883559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.4257883559
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.3868395639
Short name T420
Test name
Test status
Simulation time 5837097794 ps
CPU time 6.61 seconds
Started Jun 26 06:10:36 PM PDT 24
Finished Jun 26 06:10:44 PM PDT 24
Peak memory 199280 kb
Host smart-a1003e83-48ba-4ad1-a227-eda634c69074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868395639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3868395639
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.1558431365
Short name T701
Test name
Test status
Simulation time 38416065965 ps
CPU time 529.2 seconds
Started Jun 26 06:10:50 PM PDT 24
Finished Jun 26 06:19:42 PM PDT 24
Peak memory 216492 kb
Host smart-ef2472a8-8d82-43ab-96e1-2feb5461ddbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558431365 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.1558431365
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.492535973
Short name T878
Test name
Test status
Simulation time 959314592 ps
CPU time 6.36 seconds
Started Jun 26 06:10:36 PM PDT 24
Finished Jun 26 06:10:44 PM PDT 24
Peak memory 198456 kb
Host smart-c1bdfd87-19f9-42c9-ab9a-b319eaa1c2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492535973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.492535973
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.993698375
Short name T256
Test name
Test status
Simulation time 12487885264 ps
CPU time 7.16 seconds
Started Jun 26 06:10:28 PM PDT 24
Finished Jun 26 06:10:37 PM PDT 24
Peak memory 199964 kb
Host smart-298b0fcf-0614-4ccb-aba6-8c5eef207718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993698375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.993698375
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.3003459584
Short name T833
Test name
Test status
Simulation time 51376571734 ps
CPU time 54.77 seconds
Started Jun 26 06:13:20 PM PDT 24
Finished Jun 26 06:14:16 PM PDT 24
Peak memory 199972 kb
Host smart-1034461b-a41c-440b-af65-a5006c302919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003459584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3003459584
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.2695756406
Short name T400
Test name
Test status
Simulation time 15242968435 ps
CPU time 52.56 seconds
Started Jun 26 06:13:28 PM PDT 24
Finished Jun 26 06:14:21 PM PDT 24
Peak memory 199944 kb
Host smart-802059b3-75e7-4689-b089-bd98f6af4f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695756406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2695756406
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.218464096
Short name T371
Test name
Test status
Simulation time 41339617856 ps
CPU time 16.97 seconds
Started Jun 26 06:13:23 PM PDT 24
Finished Jun 26 06:13:42 PM PDT 24
Peak memory 199860 kb
Host smart-f7693ff1-2903-47dd-bb63-a67bb3e1424c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218464096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.218464096
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.3807248170
Short name T527
Test name
Test status
Simulation time 155393585724 ps
CPU time 1172.81 seconds
Started Jun 26 06:13:20 PM PDT 24
Finished Jun 26 06:32:54 PM PDT 24
Peak memory 199960 kb
Host smart-f749f20c-e441-4d74-929a-4b979c659830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807248170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3807248170
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.3745682579
Short name T893
Test name
Test status
Simulation time 10692876516 ps
CPU time 9.35 seconds
Started Jun 26 06:13:22 PM PDT 24
Finished Jun 26 06:13:34 PM PDT 24
Peak memory 199944 kb
Host smart-e6887cef-5ad6-471b-a1d2-231282adce4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745682579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.3745682579
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.524984184
Short name T128
Test name
Test status
Simulation time 113790171942 ps
CPU time 141.18 seconds
Started Jun 26 06:13:27 PM PDT 24
Finished Jun 26 06:15:49 PM PDT 24
Peak memory 199944 kb
Host smart-4a254995-66ef-4e8e-83ed-b82ded75eb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524984184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.524984184
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.4288332719
Short name T468
Test name
Test status
Simulation time 11487318706 ps
CPU time 5.53 seconds
Started Jun 26 06:13:21 PM PDT 24
Finished Jun 26 06:13:28 PM PDT 24
Peak memory 199884 kb
Host smart-18c0fa51-e04f-4592-982e-ed49cce63000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288332719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.4288332719
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.1646286858
Short name T687
Test name
Test status
Simulation time 129229598101 ps
CPU time 28.93 seconds
Started Jun 26 06:13:22 PM PDT 24
Finished Jun 26 06:13:52 PM PDT 24
Peak memory 199848 kb
Host smart-c2d137de-890c-4aba-8e13-93bc9df1cab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646286858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1646286858
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.692434129
Short name T101
Test name
Test status
Simulation time 29076752526 ps
CPU time 47.48 seconds
Started Jun 26 06:13:24 PM PDT 24
Finished Jun 26 06:14:13 PM PDT 24
Peak memory 199748 kb
Host smart-81be2328-b9b5-40f4-bcd6-00ba5db4c8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692434129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.692434129
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.2450230950
Short name T706
Test name
Test status
Simulation time 14640243 ps
CPU time 0.56 seconds
Started Jun 26 06:10:50 PM PDT 24
Finished Jun 26 06:10:53 PM PDT 24
Peak memory 195332 kb
Host smart-1749b932-a4d4-4c03-b335-e99bdab0646f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450230950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.2450230950
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.2934929810
Short name T115
Test name
Test status
Simulation time 30463449503 ps
CPU time 27.68 seconds
Started Jun 26 06:10:44 PM PDT 24
Finished Jun 26 06:11:14 PM PDT 24
Peak memory 199932 kb
Host smart-a316f6e1-6bb1-456f-b288-9ba57c08de02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934929810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2934929810
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_intr.1229585048
Short name T568
Test name
Test status
Simulation time 11258045417 ps
CPU time 18.97 seconds
Started Jun 26 06:10:45 PM PDT 24
Finished Jun 26 06:11:06 PM PDT 24
Peak memory 199980 kb
Host smart-a0db4755-3ae4-4d90-9964-e5009f2d255c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229585048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1229585048
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.79757207
Short name T337
Test name
Test status
Simulation time 165907963199 ps
CPU time 1186.33 seconds
Started Jun 26 06:10:42 PM PDT 24
Finished Jun 26 06:30:30 PM PDT 24
Peak memory 199860 kb
Host smart-2bcfacaa-591b-467a-9d2a-36d2f073f35e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=79757207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.79757207
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.4034820918
Short name T379
Test name
Test status
Simulation time 10693823495 ps
CPU time 29.98 seconds
Started Jun 26 06:10:37 PM PDT 24
Finished Jun 26 06:11:09 PM PDT 24
Peak memory 199660 kb
Host smart-8bb86566-4841-4cd3-a738-ec8943455e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034820918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.4034820918
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_perf.513586997
Short name T752
Test name
Test status
Simulation time 9757366142 ps
CPU time 568.46 seconds
Started Jun 26 06:10:38 PM PDT 24
Finished Jun 26 06:20:08 PM PDT 24
Peak memory 199920 kb
Host smart-0d4649f9-6226-452e-8840-f6d851f2508b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=513586997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.513586997
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.2497161980
Short name T694
Test name
Test status
Simulation time 1904937846 ps
CPU time 9.29 seconds
Started Jun 26 06:10:51 PM PDT 24
Finished Jun 26 06:11:03 PM PDT 24
Peak memory 198136 kb
Host smart-127f571a-88ce-4ba6-869d-9951284678c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2497161980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2497161980
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.3887051106
Short name T868
Test name
Test status
Simulation time 139039851708 ps
CPU time 122.56 seconds
Started Jun 26 06:10:39 PM PDT 24
Finished Jun 26 06:12:43 PM PDT 24
Peak memory 199992 kb
Host smart-1b8cc69d-6363-4d8d-8f80-c32587d409fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887051106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.3887051106
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.437551315
Short name T714
Test name
Test status
Simulation time 7104206997 ps
CPU time 3.15 seconds
Started Jun 26 06:10:51 PM PDT 24
Finished Jun 26 06:10:57 PM PDT 24
Peak memory 196204 kb
Host smart-d32435e0-2c3d-4e5b-9ef3-e16c95dd4b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437551315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.437551315
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.3591120107
Short name T470
Test name
Test status
Simulation time 5760881134 ps
CPU time 7.8 seconds
Started Jun 26 06:10:35 PM PDT 24
Finished Jun 26 06:10:44 PM PDT 24
Peak memory 199952 kb
Host smart-dcf81912-02db-45b1-ac0a-8155107b10a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591120107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3591120107
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.2888730722
Short name T1092
Test name
Test status
Simulation time 105347372865 ps
CPU time 41.6 seconds
Started Jun 26 06:10:50 PM PDT 24
Finished Jun 26 06:11:35 PM PDT 24
Peak memory 199936 kb
Host smart-aab99b29-39b1-49e4-b180-0b88d88fd22e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888730722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2888730722
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.166807619
Short name T877
Test name
Test status
Simulation time 439168637 ps
CPU time 1.87 seconds
Started Jun 26 06:10:50 PM PDT 24
Finished Jun 26 06:10:55 PM PDT 24
Peak memory 198576 kb
Host smart-4b0d7af1-30de-4b03-be1c-edd8d9b0fe15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166807619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.166807619
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3119726751
Short name T254
Test name
Test status
Simulation time 55446550006 ps
CPU time 22.75 seconds
Started Jun 26 06:10:41 PM PDT 24
Finished Jun 26 06:11:05 PM PDT 24
Peak memory 199948 kb
Host smart-1b74c8db-d21f-4450-b753-f6f05b3a20d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119726751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3119726751
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.2482788939
Short name T542
Test name
Test status
Simulation time 86687101869 ps
CPU time 22.74 seconds
Started Jun 26 06:13:22 PM PDT 24
Finished Jun 26 06:13:47 PM PDT 24
Peak memory 199944 kb
Host smart-be162e09-af73-4505-b3c4-5088130f23b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482788939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.2482788939
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.761427257
Short name T764
Test name
Test status
Simulation time 201572990773 ps
CPU time 62.48 seconds
Started Jun 26 06:13:21 PM PDT 24
Finished Jun 26 06:14:25 PM PDT 24
Peak memory 199996 kb
Host smart-2ffd676a-72df-4924-850a-a3cccf066a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761427257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.761427257
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.366850416
Short name T1027
Test name
Test status
Simulation time 17036770484 ps
CPU time 15.67 seconds
Started Jun 26 06:13:31 PM PDT 24
Finished Jun 26 06:13:48 PM PDT 24
Peak memory 199936 kb
Host smart-18dfd10d-be72-4469-86d8-c4f32a972b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366850416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.366850416
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.389470985
Short name T669
Test name
Test status
Simulation time 48457964982 ps
CPU time 21.35 seconds
Started Jun 26 06:13:31 PM PDT 24
Finished Jun 26 06:13:54 PM PDT 24
Peak memory 199984 kb
Host smart-95cafbb8-b9eb-41ab-ab94-a06b19641b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389470985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.389470985
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.912778907
Short name T1032
Test name
Test status
Simulation time 23834922641 ps
CPU time 15.81 seconds
Started Jun 26 06:13:30 PM PDT 24
Finished Jun 26 06:13:47 PM PDT 24
Peak memory 199368 kb
Host smart-c55dcda5-f445-402b-9757-2c567f0cea77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912778907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.912778907
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3135105256
Short name T421
Test name
Test status
Simulation time 174305621523 ps
CPU time 103.61 seconds
Started Jun 26 06:13:28 PM PDT 24
Finished Jun 26 06:15:13 PM PDT 24
Peak memory 199984 kb
Host smart-58b98949-5d72-4c63-b0ad-c6695f5bb2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135105256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3135105256
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1224469668
Short name T321
Test name
Test status
Simulation time 71203660393 ps
CPU time 312.12 seconds
Started Jun 26 06:13:30 PM PDT 24
Finished Jun 26 06:18:43 PM PDT 24
Peak memory 199936 kb
Host smart-78ee900e-48aa-45e5-a156-31ece2996db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224469668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1224469668
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.3885178051
Short name T513
Test name
Test status
Simulation time 8878151352 ps
CPU time 14.29 seconds
Started Jun 26 06:13:32 PM PDT 24
Finished Jun 26 06:13:47 PM PDT 24
Peak memory 199868 kb
Host smart-92c6d3d3-6008-45b5-bb3f-ad21a0f7e119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885178051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3885178051
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.169725998
Short name T903
Test name
Test status
Simulation time 11282710 ps
CPU time 0.57 seconds
Started Jun 26 06:10:49 PM PDT 24
Finished Jun 26 06:10:51 PM PDT 24
Peak memory 195232 kb
Host smart-de2a960e-1905-4240-891a-1d5fe882a10b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169725998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.169725998
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.3337444256
Short name T613
Test name
Test status
Simulation time 96833057406 ps
CPU time 34.03 seconds
Started Jun 26 06:10:52 PM PDT 24
Finished Jun 26 06:11:29 PM PDT 24
Peak memory 199936 kb
Host smart-6f0009f7-25fb-4b17-a95a-b46ae4785918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337444256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3337444256
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.544373488
Short name T150
Test name
Test status
Simulation time 1802912944 ps
CPU time 3.97 seconds
Started Jun 26 06:10:41 PM PDT 24
Finished Jun 26 06:10:46 PM PDT 24
Peak memory 198932 kb
Host smart-e42cf884-652e-4f9e-963e-87899c25aca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544373488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.544373488
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.3306150949
Short name T1076
Test name
Test status
Simulation time 196721287694 ps
CPU time 57.2 seconds
Started Jun 26 06:10:44 PM PDT 24
Finished Jun 26 06:11:43 PM PDT 24
Peak memory 199976 kb
Host smart-35003072-b9df-4c79-8756-085950e29f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306150949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3306150949
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.3873144006
Short name T1022
Test name
Test status
Simulation time 29628450748 ps
CPU time 10.87 seconds
Started Jun 26 06:10:42 PM PDT 24
Finished Jun 26 06:10:55 PM PDT 24
Peak memory 198440 kb
Host smart-3637d94a-9e99-45bc-b464-f4293e2e7465
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873144006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.3873144006
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.3816765292
Short name T803
Test name
Test status
Simulation time 88184004138 ps
CPU time 653.72 seconds
Started Jun 26 06:10:52 PM PDT 24
Finished Jun 26 06:21:48 PM PDT 24
Peak memory 199988 kb
Host smart-3e0b5d97-5202-4dfe-8192-41646c07aa05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3816765292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3816765292
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.3055785938
Short name T1014
Test name
Test status
Simulation time 84271064 ps
CPU time 0.74 seconds
Started Jun 26 06:10:51 PM PDT 24
Finished Jun 26 06:10:55 PM PDT 24
Peak memory 196840 kb
Host smart-a2109483-7813-4f8c-bf7c-5b105f57eaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055785938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3055785938
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.3874718617
Short name T1006
Test name
Test status
Simulation time 2039796123 ps
CPU time 2.14 seconds
Started Jun 26 06:10:40 PM PDT 24
Finished Jun 26 06:10:43 PM PDT 24
Peak memory 197516 kb
Host smart-3d973dce-3ec6-4096-9cb5-4c31560b4006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874718617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.3874718617
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.920151293
Short name T945
Test name
Test status
Simulation time 8593765232 ps
CPU time 472.36 seconds
Started Jun 26 06:10:51 PM PDT 24
Finished Jun 26 06:18:46 PM PDT 24
Peak memory 199976 kb
Host smart-eecae018-05cd-4619-87bd-6c6e4751b084
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=920151293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.920151293
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.4066804834
Short name T916
Test name
Test status
Simulation time 4315675364 ps
CPU time 10.83 seconds
Started Jun 26 06:10:50 PM PDT 24
Finished Jun 26 06:11:03 PM PDT 24
Peak memory 199072 kb
Host smart-5218bc78-8f58-40aa-9402-ce4a2abc6a8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4066804834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.4066804834
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.3610366852
Short name T650
Test name
Test status
Simulation time 7456292811 ps
CPU time 6.89 seconds
Started Jun 26 06:10:45 PM PDT 24
Finished Jun 26 06:10:53 PM PDT 24
Peak memory 196252 kb
Host smart-69377f11-92b4-4824-a19f-8f65b174da87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610366852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.3610366852
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.4046282966
Short name T390
Test name
Test status
Simulation time 134228120 ps
CPU time 0.85 seconds
Started Jun 26 06:10:46 PM PDT 24
Finished Jun 26 06:10:49 PM PDT 24
Peak memory 197132 kb
Host smart-6997637b-49c7-469d-97ed-d8bc6ce256ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046282966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.4046282966
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.848832361
Short name T733
Test name
Test status
Simulation time 134921666517 ps
CPU time 398.7 seconds
Started Jun 26 06:10:48 PM PDT 24
Finished Jun 26 06:17:28 PM PDT 24
Peak memory 199792 kb
Host smart-3593d5c1-c160-4a08-8fc6-c8b651e4e6fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848832361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.848832361
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.1364763485
Short name T1093
Test name
Test status
Simulation time 50696906895 ps
CPU time 728.48 seconds
Started Jun 26 06:10:52 PM PDT 24
Finished Jun 26 06:23:03 PM PDT 24
Peak memory 215616 kb
Host smart-d2126378-1840-4ce1-ba94-fee26b657d98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364763485 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.1364763485
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.1051034689
Short name T769
Test name
Test status
Simulation time 854521141 ps
CPU time 2.66 seconds
Started Jun 26 06:10:52 PM PDT 24
Finished Jun 26 06:10:57 PM PDT 24
Peak memory 199788 kb
Host smart-6a11c386-445f-4988-b3c8-7520bb2e4124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051034689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1051034689
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.756611149
Short name T691
Test name
Test status
Simulation time 118804254276 ps
CPU time 104.85 seconds
Started Jun 26 06:10:54 PM PDT 24
Finished Jun 26 06:12:41 PM PDT 24
Peak memory 199920 kb
Host smart-aebe312a-b8c9-4b5b-997e-d6cdd9275a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756611149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.756611149
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1865405992
Short name T147
Test name
Test status
Simulation time 15845384903 ps
CPU time 11.57 seconds
Started Jun 26 06:13:28 PM PDT 24
Finished Jun 26 06:13:40 PM PDT 24
Peak memory 199824 kb
Host smart-17d0a79f-398c-4604-a06e-6ee84702b0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865405992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1865405992
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.3500881058
Short name T1087
Test name
Test status
Simulation time 7800203489 ps
CPU time 14.29 seconds
Started Jun 26 06:13:32 PM PDT 24
Finished Jun 26 06:13:47 PM PDT 24
Peak memory 199612 kb
Host smart-2513d527-8d35-4eb8-8000-d1b5f11df826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500881058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3500881058
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1742839574
Short name T830
Test name
Test status
Simulation time 61734802494 ps
CPU time 41.44 seconds
Started Jun 26 06:13:30 PM PDT 24
Finished Jun 26 06:14:12 PM PDT 24
Peak memory 199920 kb
Host smart-8c8896a9-3957-45c4-aefc-0603b3902641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742839574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1742839574
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.2177018379
Short name T196
Test name
Test status
Simulation time 20307435049 ps
CPU time 32.95 seconds
Started Jun 26 06:13:26 PM PDT 24
Finished Jun 26 06:14:00 PM PDT 24
Peak memory 199888 kb
Host smart-858dff5b-59c7-4bc7-b654-2530b7eac121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177018379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2177018379
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.734785337
Short name T973
Test name
Test status
Simulation time 41864190569 ps
CPU time 60.7 seconds
Started Jun 26 06:13:29 PM PDT 24
Finished Jun 26 06:14:30 PM PDT 24
Peak memory 199956 kb
Host smart-929304f5-3746-433e-b0b0-32f05902e45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734785337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.734785337
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.1189540168
Short name T952
Test name
Test status
Simulation time 51375331509 ps
CPU time 90.5 seconds
Started Jun 26 06:13:31 PM PDT 24
Finished Jun 26 06:15:03 PM PDT 24
Peak memory 199928 kb
Host smart-0c5c74b1-cca7-43e9-8a8a-28c438ab0dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189540168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1189540168
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.3222053812
Short name T425
Test name
Test status
Simulation time 7855626945 ps
CPU time 16.34 seconds
Started Jun 26 06:13:31 PM PDT 24
Finished Jun 26 06:13:48 PM PDT 24
Peak memory 200004 kb
Host smart-0aeee0aa-f758-45c1-be29-f2b82cab6fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222053812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.3222053812
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.1233684916
Short name T318
Test name
Test status
Simulation time 149035045910 ps
CPU time 53.11 seconds
Started Jun 26 06:13:28 PM PDT 24
Finished Jun 26 06:14:22 PM PDT 24
Peak memory 199856 kb
Host smart-1c61240c-d4df-4d40-8803-4a80072fc234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233684916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1233684916
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.693290034
Short name T583
Test name
Test status
Simulation time 26200098 ps
CPU time 0.6 seconds
Started Jun 26 06:11:01 PM PDT 24
Finished Jun 26 06:11:03 PM PDT 24
Peak memory 195616 kb
Host smart-f9bdcd4f-9bcf-4e54-8651-22c2d97296d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693290034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.693290034
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.510435940
Short name T535
Test name
Test status
Simulation time 38069553982 ps
CPU time 52.43 seconds
Started Jun 26 06:10:50 PM PDT 24
Finished Jun 26 06:11:44 PM PDT 24
Peak memory 200008 kb
Host smart-59da4e85-9649-40e8-9a27-b86df3297027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510435940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.510435940
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.2170044632
Short name T1010
Test name
Test status
Simulation time 75794162584 ps
CPU time 48.34 seconds
Started Jun 26 06:10:51 PM PDT 24
Finished Jun 26 06:11:42 PM PDT 24
Peak memory 199840 kb
Host smart-c0667f4a-b7e3-4b86-8b63-cc6f7c9c6898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170044632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.2170044632
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2302036246
Short name T175
Test name
Test status
Simulation time 21382770928 ps
CPU time 26.53 seconds
Started Jun 26 06:10:43 PM PDT 24
Finished Jun 26 06:11:11 PM PDT 24
Peak memory 199980 kb
Host smart-775d43ca-b527-4802-9cff-91b25b3eef1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302036246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2302036246
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.3718037480
Short name T70
Test name
Test status
Simulation time 28924721792 ps
CPU time 44.55 seconds
Started Jun 26 06:10:51 PM PDT 24
Finished Jun 26 06:11:38 PM PDT 24
Peak memory 199656 kb
Host smart-e459fe71-b756-4525-98e1-c7eba5879bd1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718037480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3718037480
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.3883283616
Short name T405
Test name
Test status
Simulation time 78300507961 ps
CPU time 292.24 seconds
Started Jun 26 06:10:50 PM PDT 24
Finished Jun 26 06:15:45 PM PDT 24
Peak memory 199928 kb
Host smart-7b7c945d-500e-42a4-91f1-cf85f36d6654
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3883283616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3883283616
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.1172179505
Short name T889
Test name
Test status
Simulation time 9946437835 ps
CPU time 12.59 seconds
Started Jun 26 06:10:52 PM PDT 24
Finished Jun 26 06:11:08 PM PDT 24
Peak memory 199824 kb
Host smart-e00ea84f-40de-4751-b22c-4e7d2747e575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172179505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.1172179505
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_perf.4160515886
Short name T865
Test name
Test status
Simulation time 7656215526 ps
CPU time 417.67 seconds
Started Jun 26 06:10:42 PM PDT 24
Finished Jun 26 06:17:42 PM PDT 24
Peak memory 199920 kb
Host smart-9d9edfe6-e29b-4028-bb32-944ca4268d60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4160515886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.4160515886
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.2256694656
Short name T406
Test name
Test status
Simulation time 1482767738 ps
CPU time 5.43 seconds
Started Jun 26 06:10:48 PM PDT 24
Finished Jun 26 06:10:55 PM PDT 24
Peak memory 197984 kb
Host smart-d5c3f446-4dae-45ad-bf59-32215c8e395f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2256694656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2256694656
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.1910452091
Short name T810
Test name
Test status
Simulation time 4197663365 ps
CPU time 6.74 seconds
Started Jun 26 06:10:51 PM PDT 24
Finished Jun 26 06:11:01 PM PDT 24
Peak memory 196228 kb
Host smart-f6f3f117-0d17-4983-8ad9-cc614b7a4276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910452091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.1910452091
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.669614494
Short name T727
Test name
Test status
Simulation time 713497948 ps
CPU time 2.91 seconds
Started Jun 26 06:10:53 PM PDT 24
Finished Jun 26 06:10:59 PM PDT 24
Peak memory 199772 kb
Host smart-6fb632a5-1f4d-4c42-91fd-bf7ba3e38864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669614494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.669614494
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.1309326217
Short name T250
Test name
Test status
Simulation time 53932030493 ps
CPU time 92.25 seconds
Started Jun 26 06:10:50 PM PDT 24
Finished Jun 26 06:12:25 PM PDT 24
Peak memory 199936 kb
Host smart-af8a321a-9a04-4592-8c77-b4909a59dc1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309326217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1309326217
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.3694755405
Short name T841
Test name
Test status
Simulation time 1400789243 ps
CPU time 2.55 seconds
Started Jun 26 06:10:52 PM PDT 24
Finished Jun 26 06:10:58 PM PDT 24
Peak memory 198796 kb
Host smart-8b5f1854-d5dd-4315-98b5-70104d42cb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694755405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.3694755405
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.3927852471
Short name T862
Test name
Test status
Simulation time 14988317844 ps
CPU time 25.72 seconds
Started Jun 26 06:10:50 PM PDT 24
Finished Jun 26 06:11:17 PM PDT 24
Peak memory 199792 kb
Host smart-516c529a-3abf-4d1c-984e-a9b5de18b6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927852471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3927852471
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3924015791
Short name T817
Test name
Test status
Simulation time 69790679938 ps
CPU time 130.12 seconds
Started Jun 26 06:13:36 PM PDT 24
Finished Jun 26 06:15:47 PM PDT 24
Peak memory 199948 kb
Host smart-611299fb-91d9-4085-b080-5008686e76cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924015791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3924015791
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.1602364074
Short name T1066
Test name
Test status
Simulation time 40159379143 ps
CPU time 17.78 seconds
Started Jun 26 06:13:35 PM PDT 24
Finished Jun 26 06:13:54 PM PDT 24
Peak memory 199960 kb
Host smart-a57b2ccc-84cb-4e3b-bef9-dc75c0dfc796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602364074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1602364074
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2029425580
Short name T926
Test name
Test status
Simulation time 134116069542 ps
CPU time 56.83 seconds
Started Jun 26 06:13:37 PM PDT 24
Finished Jun 26 06:14:35 PM PDT 24
Peak memory 199860 kb
Host smart-674c3cd4-bbfb-4e72-85b8-a2e8c4c7780c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029425580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2029425580
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.2320925456
Short name T689
Test name
Test status
Simulation time 29180154686 ps
CPU time 48.26 seconds
Started Jun 26 06:13:39 PM PDT 24
Finished Jun 26 06:14:28 PM PDT 24
Peak memory 199720 kb
Host smart-a827ddee-672f-4769-bc41-4db4d7f30692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320925456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2320925456
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.1302002921
Short name T866
Test name
Test status
Simulation time 48291011127 ps
CPU time 48.39 seconds
Started Jun 26 06:13:32 PM PDT 24
Finished Jun 26 06:14:21 PM PDT 24
Peak memory 199904 kb
Host smart-d2c032c2-7bed-46f3-80e9-959d173b68ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302002921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1302002921
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.3724928929
Short name T915
Test name
Test status
Simulation time 24324367488 ps
CPU time 71.88 seconds
Started Jun 26 06:13:36 PM PDT 24
Finished Jun 26 06:14:49 PM PDT 24
Peak memory 200016 kb
Host smart-e0ea987f-3cca-4e34-9a40-12052ac839a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724928929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3724928929
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.3012105473
Short name T641
Test name
Test status
Simulation time 89610624873 ps
CPU time 56.69 seconds
Started Jun 26 06:13:37 PM PDT 24
Finished Jun 26 06:14:35 PM PDT 24
Peak memory 199904 kb
Host smart-33398d2e-b554-4366-9cdd-a723c00c9a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012105473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.3012105473
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1113903245
Short name T937
Test name
Test status
Simulation time 170311581776 ps
CPU time 228.98 seconds
Started Jun 26 06:13:40 PM PDT 24
Finished Jun 26 06:17:29 PM PDT 24
Peak memory 199980 kb
Host smart-8cad01f5-607f-41fc-9351-e40b55e88a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113903245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1113903245
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3672703127
Short name T1055
Test name
Test status
Simulation time 11642371 ps
CPU time 0.54 seconds
Started Jun 26 06:10:54 PM PDT 24
Finished Jun 26 06:10:57 PM PDT 24
Peak memory 195296 kb
Host smart-428ca18e-c424-4101-963f-6e0efb2b25f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672703127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3672703127
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.2335777848
Short name T730
Test name
Test status
Simulation time 108848526603 ps
CPU time 43.96 seconds
Started Jun 26 06:10:47 PM PDT 24
Finished Jun 26 06:11:32 PM PDT 24
Peak memory 200008 kb
Host smart-e7573dbe-a278-4970-90fe-fabc865eae8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335777848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2335777848
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2701902617
Short name T1037
Test name
Test status
Simulation time 60198914864 ps
CPU time 114.46 seconds
Started Jun 26 06:10:50 PM PDT 24
Finished Jun 26 06:12:47 PM PDT 24
Peak memory 199920 kb
Host smart-19990d6b-3e94-410f-9de1-3d5d16e2483d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701902617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2701902617
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.2604465083
Short name T180
Test name
Test status
Simulation time 64153554879 ps
CPU time 23.73 seconds
Started Jun 26 06:10:51 PM PDT 24
Finished Jun 26 06:11:18 PM PDT 24
Peak memory 199956 kb
Host smart-094525d8-5ef9-47ed-9fe1-2ae3dccb71e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604465083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2604465083
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.16460889
Short name T781
Test name
Test status
Simulation time 25693437652 ps
CPU time 10.56 seconds
Started Jun 26 06:10:54 PM PDT 24
Finished Jun 26 06:11:07 PM PDT 24
Peak memory 198752 kb
Host smart-58257298-5e94-4010-b02e-2828dd2af6b3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16460889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.16460889
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.2240571509
Short name T667
Test name
Test status
Simulation time 264784788468 ps
CPU time 275.24 seconds
Started Jun 26 06:11:04 PM PDT 24
Finished Jun 26 06:15:41 PM PDT 24
Peak memory 199940 kb
Host smart-f6837ea5-a3ad-46f8-bd82-ee4247bac3c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2240571509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.2240571509
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.1534296976
Short name T526
Test name
Test status
Simulation time 6348911536 ps
CPU time 11.79 seconds
Started Jun 26 06:11:03 PM PDT 24
Finished Jun 26 06:11:17 PM PDT 24
Peak memory 199684 kb
Host smart-23809edc-6c5b-43cd-9c48-3ce4e5e9c40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534296976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1534296976
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_perf.898898761
Short name T601
Test name
Test status
Simulation time 14520368565 ps
CPU time 883.16 seconds
Started Jun 26 06:10:54 PM PDT 24
Finished Jun 26 06:25:40 PM PDT 24
Peak memory 199924 kb
Host smart-bcea8b01-340f-49be-9538-3067cd2b027e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=898898761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.898898761
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.3306471221
Short name T725
Test name
Test status
Simulation time 5184016838 ps
CPU time 41.72 seconds
Started Jun 26 06:10:44 PM PDT 24
Finished Jun 26 06:11:27 PM PDT 24
Peak memory 198168 kb
Host smart-cb937ffd-6988-43b7-97d5-ff14e47d2684
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3306471221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3306471221
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.3701210623
Short name T37
Test name
Test status
Simulation time 16078399437 ps
CPU time 16.11 seconds
Started Jun 26 06:11:02 PM PDT 24
Finished Jun 26 06:11:19 PM PDT 24
Peak memory 200004 kb
Host smart-2ba590f6-323e-4fa6-b2f6-1e1d9f392acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701210623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.3701210623
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.3315619757
Short name T852
Test name
Test status
Simulation time 4450800295 ps
CPU time 1.47 seconds
Started Jun 26 06:10:52 PM PDT 24
Finished Jun 26 06:10:56 PM PDT 24
Peak memory 196024 kb
Host smart-2cf9781b-97ab-4eab-b543-d20924f5e026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315619757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3315619757
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.3374048780
Short name T552
Test name
Test status
Simulation time 912733722 ps
CPU time 2.3 seconds
Started Jun 26 06:10:54 PM PDT 24
Finished Jun 26 06:10:59 PM PDT 24
Peak memory 198360 kb
Host smart-adb869c0-c824-4ffd-983a-f060514ff8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374048780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.3374048780
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.3246345071
Short name T1025
Test name
Test status
Simulation time 120957462422 ps
CPU time 67.78 seconds
Started Jun 26 06:11:07 PM PDT 24
Finished Jun 26 06:12:16 PM PDT 24
Peak memory 199944 kb
Host smart-8a506d62-a9c8-4379-bb58-f1cc7627ee2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246345071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3246345071
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.184354238
Short name T759
Test name
Test status
Simulation time 27319055327 ps
CPU time 326.24 seconds
Started Jun 26 06:10:54 PM PDT 24
Finished Jun 26 06:16:22 PM PDT 24
Peak memory 208316 kb
Host smart-fc957e6b-e71c-46fa-85af-2a32bfaccc43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184354238 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.184354238
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.3248584276
Short name T364
Test name
Test status
Simulation time 445642445 ps
CPU time 1.53 seconds
Started Jun 26 06:10:56 PM PDT 24
Finished Jun 26 06:11:00 PM PDT 24
Peak memory 199124 kb
Host smart-2391c5c3-2365-4bca-819c-316a1aceaa50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248584276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3248584276
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.2223487593
Short name T269
Test name
Test status
Simulation time 46762300662 ps
CPU time 21.12 seconds
Started Jun 26 06:10:49 PM PDT 24
Finished Jun 26 06:11:12 PM PDT 24
Peak memory 199920 kb
Host smart-cc1ed54c-17c8-496e-a9c8-03960aea1953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223487593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2223487593
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2597885180
Short name T322
Test name
Test status
Simulation time 19148952273 ps
CPU time 28.76 seconds
Started Jun 26 06:13:37 PM PDT 24
Finished Jun 26 06:14:06 PM PDT 24
Peak memory 199968 kb
Host smart-3a7b2f59-19d6-459f-a34d-1f41aa5847c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597885180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2597885180
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.1519062267
Short name T182
Test name
Test status
Simulation time 27948085123 ps
CPU time 45.38 seconds
Started Jun 26 06:13:38 PM PDT 24
Finished Jun 26 06:14:24 PM PDT 24
Peak memory 199944 kb
Host smart-3aaf25fa-7142-404a-b5ca-d0f4fe9295bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519062267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1519062267
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.1292158943
Short name T806
Test name
Test status
Simulation time 90243947717 ps
CPU time 109.24 seconds
Started Jun 26 06:13:35 PM PDT 24
Finished Jun 26 06:15:25 PM PDT 24
Peak memory 200208 kb
Host smart-a46d76be-7574-4ba2-9c0f-bd072cc6848d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292158943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1292158943
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.3944845720
Short name T191
Test name
Test status
Simulation time 10794477723 ps
CPU time 18.35 seconds
Started Jun 26 06:13:33 PM PDT 24
Finished Jun 26 06:13:52 PM PDT 24
Peak memory 199988 kb
Host smart-d7649263-5e00-456f-b93d-7914aff6b583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944845720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3944845720
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.2584830407
Short name T1052
Test name
Test status
Simulation time 237520469715 ps
CPU time 38.19 seconds
Started Jun 26 06:13:35 PM PDT 24
Finished Jun 26 06:14:15 PM PDT 24
Peak memory 199860 kb
Host smart-46a98ede-57fc-4e2b-9c9b-1ba323c1a803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584830407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2584830407
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.2452558250
Short name T1045
Test name
Test status
Simulation time 15963978047 ps
CPU time 10.94 seconds
Started Jun 26 06:13:33 PM PDT 24
Finished Jun 26 06:13:45 PM PDT 24
Peak memory 200004 kb
Host smart-e0917687-d799-4b8e-bafe-a7258a7afd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452558250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2452558250
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.2742618227
Short name T174
Test name
Test status
Simulation time 23637278469 ps
CPU time 39.14 seconds
Started Jun 26 06:13:37 PM PDT 24
Finished Jun 26 06:14:17 PM PDT 24
Peak memory 199996 kb
Host smart-ad817745-8b43-4aff-a4a5-a07e05610ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742618227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2742618227
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.3966205396
Short name T772
Test name
Test status
Simulation time 52661145442 ps
CPU time 38.05 seconds
Started Jun 26 06:13:37 PM PDT 24
Finished Jun 26 06:14:16 PM PDT 24
Peak memory 199744 kb
Host smart-b8588baf-a607-48c9-8a83-65e7d8b8e285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966205396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3966205396
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.1064210472
Short name T580
Test name
Test status
Simulation time 15232258 ps
CPU time 0.55 seconds
Started Jun 26 06:10:55 PM PDT 24
Finished Jun 26 06:10:57 PM PDT 24
Peak memory 195196 kb
Host smart-eec6bea1-2bc4-4463-b8fc-31fb49d6c105
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064210472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1064210472
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.2747996943
Short name T418
Test name
Test status
Simulation time 113945381040 ps
CPU time 88.2 seconds
Started Jun 26 06:10:58 PM PDT 24
Finished Jun 26 06:12:28 PM PDT 24
Peak memory 199916 kb
Host smart-d892bf56-038b-46dd-936d-3ff6b99f65a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747996943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.2747996943
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.837471685
Short name T970
Test name
Test status
Simulation time 15587473625 ps
CPU time 24.25 seconds
Started Jun 26 06:10:57 PM PDT 24
Finished Jun 26 06:11:24 PM PDT 24
Peak memory 199956 kb
Host smart-84bdbf11-a3b4-48f5-a41d-98ceefbdf7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837471685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.837471685
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.1653751855
Short name T881
Test name
Test status
Simulation time 29435117527 ps
CPU time 41.34 seconds
Started Jun 26 06:10:51 PM PDT 24
Finished Jun 26 06:11:35 PM PDT 24
Peak memory 199956 kb
Host smart-ba9482ae-3e13-43f3-bd8b-57e407a9e8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653751855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.1653751855
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.2823676881
Short name T656
Test name
Test status
Simulation time 42185635450 ps
CPU time 8.17 seconds
Started Jun 26 06:11:04 PM PDT 24
Finished Jun 26 06:11:14 PM PDT 24
Peak memory 199920 kb
Host smart-4bc7212a-0cb2-46c5-b02e-9217dcb2760d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823676881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.2823676881
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.3920929485
Short name T994
Test name
Test status
Simulation time 145723525512 ps
CPU time 912.36 seconds
Started Jun 26 06:11:00 PM PDT 24
Finished Jun 26 06:26:14 PM PDT 24
Peak memory 199776 kb
Host smart-ac171c94-b2e5-41c2-b8d8-8821b1dca8c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3920929485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3920929485
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.2279115374
Short name T361
Test name
Test status
Simulation time 1920356131 ps
CPU time 1.63 seconds
Started Jun 26 06:10:57 PM PDT 24
Finished Jun 26 06:11:01 PM PDT 24
Peak memory 197088 kb
Host smart-cc5e5011-3263-408e-9037-2e96c8c7a44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279115374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2279115374
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_perf.3660554441
Short name T1082
Test name
Test status
Simulation time 16186388958 ps
CPU time 198.09 seconds
Started Jun 26 06:10:58 PM PDT 24
Finished Jun 26 06:14:18 PM PDT 24
Peak memory 199960 kb
Host smart-c16709a1-e423-409f-8031-6a9842319ad1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3660554441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3660554441
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.2569238032
Short name T814
Test name
Test status
Simulation time 2557046670 ps
CPU time 8.41 seconds
Started Jun 26 06:10:52 PM PDT 24
Finished Jun 26 06:11:04 PM PDT 24
Peak memory 197972 kb
Host smart-285d641d-1bbc-4f07-b171-13c8f669166c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2569238032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.2569238032
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.2539459666
Short name T145
Test name
Test status
Simulation time 147092099126 ps
CPU time 61.58 seconds
Started Jun 26 06:10:56 PM PDT 24
Finished Jun 26 06:11:59 PM PDT 24
Peak memory 199928 kb
Host smart-71f2fa6a-f8d2-49fe-af34-4f29b0a7968a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539459666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2539459666
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.2915600214
Short name T1005
Test name
Test status
Simulation time 4785885189 ps
CPU time 2.69 seconds
Started Jun 26 06:10:51 PM PDT 24
Finished Jun 26 06:10:57 PM PDT 24
Peak memory 196428 kb
Host smart-ca6f9d79-ac5b-4dd0-8852-9eb3ce7d56a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915600214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.2915600214
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.3413589946
Short name T550
Test name
Test status
Simulation time 464146977 ps
CPU time 1.86 seconds
Started Jun 26 06:11:02 PM PDT 24
Finished Jun 26 06:11:05 PM PDT 24
Peak memory 199508 kb
Host smart-2c930e0e-d72e-425e-8b7a-065c660d13e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413589946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.3413589946
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.350295132
Short name T847
Test name
Test status
Simulation time 772854998 ps
CPU time 2.21 seconds
Started Jun 26 06:11:02 PM PDT 24
Finished Jun 26 06:11:06 PM PDT 24
Peak memory 198812 kb
Host smart-306d4ecc-5883-4f44-80b7-90de1a2d2ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350295132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.350295132
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.3549250134
Short name T320
Test name
Test status
Simulation time 3710488862 ps
CPU time 5.94 seconds
Started Jun 26 06:10:50 PM PDT 24
Finished Jun 26 06:10:59 PM PDT 24
Peak memory 199576 kb
Host smart-6d8c348f-68a1-4a79-bdc5-7e0fabddf6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549250134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.3549250134
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.4131906817
Short name T758
Test name
Test status
Simulation time 163966380867 ps
CPU time 34.63 seconds
Started Jun 26 06:13:37 PM PDT 24
Finished Jun 26 06:14:13 PM PDT 24
Peak memory 199920 kb
Host smart-4e40f260-9aef-46e4-b414-c526d6fed6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131906817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.4131906817
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.461239139
Short name T565
Test name
Test status
Simulation time 94052800963 ps
CPU time 39.22 seconds
Started Jun 26 06:13:38 PM PDT 24
Finished Jun 26 06:14:18 PM PDT 24
Peak memory 199920 kb
Host smart-421bae8b-21cf-4cef-86ab-cb137d3e5451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461239139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.461239139
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2598186932
Short name T275
Test name
Test status
Simulation time 49296416780 ps
CPU time 25.22 seconds
Started Jun 26 06:13:37 PM PDT 24
Finished Jun 26 06:14:03 PM PDT 24
Peak memory 199996 kb
Host smart-6440e270-3f5b-45c9-a2d2-3ccd6b9bf447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598186932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2598186932
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.2685831230
Short name T111
Test name
Test status
Simulation time 152424359566 ps
CPU time 69.92 seconds
Started Jun 26 06:13:35 PM PDT 24
Finished Jun 26 06:14:46 PM PDT 24
Peak memory 199896 kb
Host smart-3a97547e-a00b-4339-a4be-e69b76c67c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685831230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.2685831230
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.1430708804
Short name T474
Test name
Test status
Simulation time 155243807449 ps
CPU time 11.43 seconds
Started Jun 26 06:13:35 PM PDT 24
Finished Jun 26 06:13:48 PM PDT 24
Peak memory 199392 kb
Host smart-28b4b390-08f9-462c-a938-9d7a707fd0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430708804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.1430708804
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.2868698935
Short name T556
Test name
Test status
Simulation time 70262146365 ps
CPU time 91.69 seconds
Started Jun 26 06:13:35 PM PDT 24
Finished Jun 26 06:15:08 PM PDT 24
Peak memory 199808 kb
Host smart-da8dab2e-765d-4457-93ce-2a9e640f91af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868698935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2868698935
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.53205436
Short name T559
Test name
Test status
Simulation time 126314959148 ps
CPU time 100.36 seconds
Started Jun 26 06:13:39 PM PDT 24
Finished Jun 26 06:15:20 PM PDT 24
Peak memory 199996 kb
Host smart-7a2d42fe-d030-498a-93c5-74e905b9336f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53205436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.53205436
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.1585816326
Short name T655
Test name
Test status
Simulation time 298110827527 ps
CPU time 129.91 seconds
Started Jun 26 06:13:34 PM PDT 24
Finished Jun 26 06:15:45 PM PDT 24
Peak memory 199876 kb
Host smart-cbeda943-6bef-4c15-afa9-3e57015cbb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585816326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.1585816326
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3495996906
Short name T1030
Test name
Test status
Simulation time 52370710584 ps
CPU time 15.89 seconds
Started Jun 26 06:13:40 PM PDT 24
Finished Jun 26 06:13:57 PM PDT 24
Peak memory 199956 kb
Host smart-7149b9f3-8c52-4bc1-adf8-3d650bbf0a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495996906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3495996906
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.3057517632
Short name T971
Test name
Test status
Simulation time 20407998098 ps
CPU time 11.18 seconds
Started Jun 26 06:13:40 PM PDT 24
Finished Jun 26 06:13:52 PM PDT 24
Peak memory 199988 kb
Host smart-5a9c289b-3a36-4a50-ac3c-cc4fb6241165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057517632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.3057517632
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.1413308979
Short name T532
Test name
Test status
Simulation time 14958787 ps
CPU time 0.57 seconds
Started Jun 26 06:10:12 PM PDT 24
Finished Jun 26 06:10:15 PM PDT 24
Peak memory 195296 kb
Host smart-3285d9d7-8a97-420e-ae04-decd1e9d2a1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413308979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1413308979
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.2888959309
Short name T163
Test name
Test status
Simulation time 42429563192 ps
CPU time 36.35 seconds
Started Jun 26 06:10:14 PM PDT 24
Finished Jun 26 06:10:54 PM PDT 24
Peak memory 199864 kb
Host smart-136bb45e-e5c7-4e57-926e-2a889ec9587b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888959309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2888959309
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.2916278657
Short name T593
Test name
Test status
Simulation time 129573697643 ps
CPU time 61.72 seconds
Started Jun 26 06:10:14 PM PDT 24
Finished Jun 26 06:11:19 PM PDT 24
Peak memory 199928 kb
Host smart-caa2227f-dd34-4405-8cd3-9cfada4e3683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916278657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.2916278657
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.972853010
Short name T230
Test name
Test status
Simulation time 11455558440 ps
CPU time 18.78 seconds
Started Jun 26 06:10:18 PM PDT 24
Finished Jun 26 06:10:40 PM PDT 24
Peak memory 199648 kb
Host smart-36464d99-2c59-44c6-a0f0-7b683031e48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972853010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.972853010
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.2893138835
Short name T292
Test name
Test status
Simulation time 65003338386 ps
CPU time 111.7 seconds
Started Jun 26 06:11:15 PM PDT 24
Finished Jun 26 06:13:08 PM PDT 24
Peak memory 199840 kb
Host smart-b39db744-4de3-4e85-a444-26a4d9090742
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893138835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2893138835
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.1722555401
Short name T314
Test name
Test status
Simulation time 145708564894 ps
CPU time 258.9 seconds
Started Jun 26 06:10:16 PM PDT 24
Finished Jun 26 06:14:37 PM PDT 24
Peak memory 199968 kb
Host smart-d84ce4cb-97fb-4fed-bf1f-e2439d675b07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1722555401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.1722555401
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.3138728907
Short name T617
Test name
Test status
Simulation time 3795088194 ps
CPU time 3.41 seconds
Started Jun 26 06:10:17 PM PDT 24
Finished Jun 26 06:10:23 PM PDT 24
Peak memory 195964 kb
Host smart-85998fc6-802b-44bd-988c-45bb0d23b3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138728907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.3138728907
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_perf.755011639
Short name T943
Test name
Test status
Simulation time 25155758337 ps
CPU time 122.59 seconds
Started Jun 26 06:10:24 PM PDT 24
Finished Jun 26 06:12:30 PM PDT 24
Peak memory 199900 kb
Host smart-042ede1e-fa8f-44e5-897c-121d2cac836b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=755011639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.755011639
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.961823598
Short name T365
Test name
Test status
Simulation time 4965246252 ps
CPU time 9.22 seconds
Started Jun 26 06:10:21 PM PDT 24
Finished Jun 26 06:10:33 PM PDT 24
Peak memory 198240 kb
Host smart-ac651e96-9e28-44d0-948b-823c9d99c39e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=961823598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.961823598
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.887177874
Short name T383
Test name
Test status
Simulation time 13860790099 ps
CPU time 25.68 seconds
Started Jun 26 06:10:12 PM PDT 24
Finished Jun 26 06:10:41 PM PDT 24
Peak memory 199768 kb
Host smart-894c5abc-d65a-4183-9a2c-7b8f18ea886e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887177874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.887177874
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.4025710481
Short name T569
Test name
Test status
Simulation time 2319884088 ps
CPU time 2.24 seconds
Started Jun 26 06:10:19 PM PDT 24
Finished Jun 26 06:10:24 PM PDT 24
Peak memory 195764 kb
Host smart-16a54c3f-032c-40aa-9269-78f924afcb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025710481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.4025710481
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.3504953931
Short name T28
Test name
Test status
Simulation time 233293177 ps
CPU time 0.85 seconds
Started Jun 26 06:10:12 PM PDT 24
Finished Jun 26 06:10:16 PM PDT 24
Peak memory 218312 kb
Host smart-146c347d-4d6c-4d05-bc57-d0e6e9ac6b36
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504953931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.3504953931
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.1571278419
Short name T459
Test name
Test status
Simulation time 314432947 ps
CPU time 1.2 seconds
Started Jun 26 06:10:08 PM PDT 24
Finished Jun 26 06:10:13 PM PDT 24
Peak memory 198344 kb
Host smart-e43c32f6-7c6c-47b2-a85d-53ed6c3e98a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571278419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1571278419
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.1778132005
Short name T1089
Test name
Test status
Simulation time 262665670779 ps
CPU time 135.87 seconds
Started Jun 26 06:10:14 PM PDT 24
Finished Jun 26 06:12:34 PM PDT 24
Peak memory 199940 kb
Host smart-12a9e421-9c82-4869-8b51-a01d7c4ddeb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778132005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1778132005
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.832765782
Short name T58
Test name
Test status
Simulation time 78264890830 ps
CPU time 614.25 seconds
Started Jun 26 06:10:14 PM PDT 24
Finished Jun 26 06:20:31 PM PDT 24
Peak memory 216592 kb
Host smart-3d266d6a-316c-4185-931c-da8646306361
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832765782 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.832765782
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.2523119560
Short name T279
Test name
Test status
Simulation time 2522457046 ps
CPU time 2.62 seconds
Started Jun 26 06:10:09 PM PDT 24
Finished Jun 26 06:10:16 PM PDT 24
Peak memory 198944 kb
Host smart-29496eeb-b8d4-4b7b-80fd-45fa4aab3c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523119560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.2523119560
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_alert_test.3793073434
Short name T488
Test name
Test status
Simulation time 123150150 ps
CPU time 0.58 seconds
Started Jun 26 06:11:05 PM PDT 24
Finished Jun 26 06:11:07 PM PDT 24
Peak memory 195232 kb
Host smart-37ebe75b-4fa1-456d-b283-608890cfbece
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793073434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3793073434
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.2034736103
Short name T1051
Test name
Test status
Simulation time 156308953940 ps
CPU time 119.59 seconds
Started Jun 26 06:10:57 PM PDT 24
Finished Jun 26 06:12:59 PM PDT 24
Peak memory 199880 kb
Host smart-1674de58-99ac-4065-9cd5-5925ee0bc39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034736103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.2034736103
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.3122124746
Short name T5
Test name
Test status
Simulation time 41817681313 ps
CPU time 54.92 seconds
Started Jun 26 06:10:56 PM PDT 24
Finished Jun 26 06:11:53 PM PDT 24
Peak memory 199796 kb
Host smart-19955ced-eeb8-4414-8bc1-4276a49c92a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122124746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3122124746
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2496090783
Short name T964
Test name
Test status
Simulation time 130940653231 ps
CPU time 24.66 seconds
Started Jun 26 06:11:00 PM PDT 24
Finished Jun 26 06:11:26 PM PDT 24
Peak memory 199892 kb
Host smart-cbde6025-d103-4090-8d65-8ab8e2ca6bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496090783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2496090783
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.3647244583
Short name T452
Test name
Test status
Simulation time 107702903186 ps
CPU time 27.51 seconds
Started Jun 26 06:10:56 PM PDT 24
Finished Jun 26 06:11:26 PM PDT 24
Peak memory 196948 kb
Host smart-6ad7ace9-55f9-441e-a476-0a3bcf2b5549
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647244583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3647244583
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.1714184290
Short name T403
Test name
Test status
Simulation time 61408907955 ps
CPU time 220.41 seconds
Started Jun 26 06:11:02 PM PDT 24
Finished Jun 26 06:14:44 PM PDT 24
Peak memory 200016 kb
Host smart-e0ebfdd5-bed7-4485-a1ad-b9a0b5b5eb3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1714184290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1714184290
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.3491959340
Short name T663
Test name
Test status
Simulation time 5173671024 ps
CPU time 4.9 seconds
Started Jun 26 06:10:58 PM PDT 24
Finished Jun 26 06:11:05 PM PDT 24
Peak memory 199724 kb
Host smart-71aa56b3-a915-4fb3-89d5-725ac1d2892d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491959340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.3491959340
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_perf.1790628360
Short name T1079
Test name
Test status
Simulation time 11235008102 ps
CPU time 602.26 seconds
Started Jun 26 06:10:58 PM PDT 24
Finished Jun 26 06:21:02 PM PDT 24
Peak memory 199864 kb
Host smart-c4ed805b-47e4-463f-8367-1fcdb7af0457
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1790628360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.1790628360
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.158701869
Short name T1013
Test name
Test status
Simulation time 4136678324 ps
CPU time 9.03 seconds
Started Jun 26 06:10:53 PM PDT 24
Finished Jun 26 06:11:05 PM PDT 24
Peak memory 198144 kb
Host smart-9121d8b5-2485-406b-bf1b-ae6558da2b9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=158701869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.158701869
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.4095185784
Short name T391
Test name
Test status
Simulation time 21806630458 ps
CPU time 30.16 seconds
Started Jun 26 06:10:55 PM PDT 24
Finished Jun 26 06:11:27 PM PDT 24
Peak memory 199968 kb
Host smart-1e349432-d279-4737-94ed-58b4af0e07be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095185784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.4095185784
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3725580090
Short name T574
Test name
Test status
Simulation time 39655057645 ps
CPU time 14.85 seconds
Started Jun 26 06:10:55 PM PDT 24
Finished Jun 26 06:11:12 PM PDT 24
Peak memory 195868 kb
Host smart-c718d081-b076-4b6f-b27d-7c0e3100c77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725580090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3725580090
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.858561604
Short name T587
Test name
Test status
Simulation time 290390844 ps
CPU time 1.02 seconds
Started Jun 26 06:10:55 PM PDT 24
Finished Jun 26 06:10:58 PM PDT 24
Peak memory 198188 kb
Host smart-87221297-4057-430e-8b6f-5627327abdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858561604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.858561604
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.301203741
Short name T499
Test name
Test status
Simulation time 1737520987 ps
CPU time 1.67 seconds
Started Jun 26 06:11:02 PM PDT 24
Finished Jun 26 06:11:06 PM PDT 24
Peak memory 198812 kb
Host smart-e2de0f18-541e-443e-8378-e82c23dd426b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301203741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.301203741
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.4074799227
Short name T874
Test name
Test status
Simulation time 29936508656 ps
CPU time 6.32 seconds
Started Jun 26 06:10:55 PM PDT 24
Finished Jun 26 06:11:04 PM PDT 24
Peak memory 196516 kb
Host smart-20fc6e77-1c07-4315-8fe5-0b17e0cd8631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074799227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.4074799227
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.2297406054
Short name T1065
Test name
Test status
Simulation time 57318359879 ps
CPU time 93.59 seconds
Started Jun 26 06:13:43 PM PDT 24
Finished Jun 26 06:15:17 PM PDT 24
Peak memory 199940 kb
Host smart-470a3ccf-5617-4ef8-9759-b89cdde188c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297406054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.2297406054
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.1945694469
Short name T1016
Test name
Test status
Simulation time 89372573166 ps
CPU time 15.69 seconds
Started Jun 26 06:13:41 PM PDT 24
Finished Jun 26 06:13:58 PM PDT 24
Peak memory 199908 kb
Host smart-5abefed5-f7e6-43d0-aabc-0428b63a1375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945694469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1945694469
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.2169844760
Short name T551
Test name
Test status
Simulation time 15599458340 ps
CPU time 22.16 seconds
Started Jun 26 06:13:39 PM PDT 24
Finished Jun 26 06:14:02 PM PDT 24
Peak memory 200008 kb
Host smart-1e2ba9f4-f303-4e7f-8ab7-9a7db253ff43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169844760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2169844760
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.1797485739
Short name T342
Test name
Test status
Simulation time 210712559649 ps
CPU time 16.96 seconds
Started Jun 26 06:13:42 PM PDT 24
Finished Jun 26 06:14:00 PM PDT 24
Peak memory 199736 kb
Host smart-761f526b-10be-4ca7-a7fb-74f6fcb0df30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797485739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.1797485739
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.2510211356
Short name T802
Test name
Test status
Simulation time 20753076316 ps
CPU time 39.43 seconds
Started Jun 26 06:13:41 PM PDT 24
Finished Jun 26 06:14:21 PM PDT 24
Peak memory 199944 kb
Host smart-3ed6688c-294a-4f4d-af3e-d1d47ec6a3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510211356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2510211356
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.2235929703
Short name T1040
Test name
Test status
Simulation time 16077643370 ps
CPU time 22.35 seconds
Started Jun 26 06:13:44 PM PDT 24
Finished Jun 26 06:14:08 PM PDT 24
Peak memory 199920 kb
Host smart-5f662f9a-04a7-4119-b50f-e48ebb3d7b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235929703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2235929703
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3750775582
Short name T750
Test name
Test status
Simulation time 207905320016 ps
CPU time 28.63 seconds
Started Jun 26 06:13:45 PM PDT 24
Finished Jun 26 06:14:15 PM PDT 24
Peak memory 199924 kb
Host smart-1ece8f97-49e4-433d-ae31-b1efa635d5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750775582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3750775582
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.339318847
Short name T177
Test name
Test status
Simulation time 111308403614 ps
CPU time 182.03 seconds
Started Jun 26 06:13:47 PM PDT 24
Finished Jun 26 06:16:51 PM PDT 24
Peak memory 199900 kb
Host smart-11a0cf38-b7a8-4373-bc65-ef73c3df27c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339318847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.339318847
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2111888264
Short name T755
Test name
Test status
Simulation time 77497798758 ps
CPU time 36.25 seconds
Started Jun 26 06:13:45 PM PDT 24
Finished Jun 26 06:14:22 PM PDT 24
Peak memory 199992 kb
Host smart-c8880016-6e62-4a96-832b-c83d44bbd7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111888264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2111888264
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.1917745888
Short name T826
Test name
Test status
Simulation time 14260410 ps
CPU time 0.64 seconds
Started Jun 26 06:11:05 PM PDT 24
Finished Jun 26 06:11:07 PM PDT 24
Peak memory 195272 kb
Host smart-63431640-589c-4401-bf81-988a5f8be99c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917745888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1917745888
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.4191460033
Short name T469
Test name
Test status
Simulation time 141229624218 ps
CPU time 46.29 seconds
Started Jun 26 06:10:54 PM PDT 24
Finished Jun 26 06:11:43 PM PDT 24
Peak memory 199916 kb
Host smart-fb2aaf99-b755-4c4b-8eb1-c4dc5ceaa9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191460033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.4191460033
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.3871035704
Short name T846
Test name
Test status
Simulation time 88588121091 ps
CPU time 131.27 seconds
Started Jun 26 06:11:03 PM PDT 24
Finished Jun 26 06:13:17 PM PDT 24
Peak memory 199220 kb
Host smart-c568635e-0ef5-4666-9f42-1245509c8297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871035704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3871035704
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.4137287361
Short name T1094
Test name
Test status
Simulation time 40031912465 ps
CPU time 64.78 seconds
Started Jun 26 06:10:59 PM PDT 24
Finished Jun 26 06:12:05 PM PDT 24
Peak memory 199964 kb
Host smart-c9b515bd-cff6-4b0b-a2cf-f58e67ab4c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137287361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.4137287361
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.688850259
Short name T245
Test name
Test status
Simulation time 50107200722 ps
CPU time 41.02 seconds
Started Jun 26 06:10:55 PM PDT 24
Finished Jun 26 06:11:38 PM PDT 24
Peak memory 199760 kb
Host smart-ef741355-a058-48cd-849b-d6a56c2676f6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688850259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.688850259
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.3636076267
Short name T664
Test name
Test status
Simulation time 128374678577 ps
CPU time 288.32 seconds
Started Jun 26 06:10:59 PM PDT 24
Finished Jun 26 06:15:49 PM PDT 24
Peak memory 199888 kb
Host smart-3fc1ee4a-e68e-4b09-80be-292ce3bd24a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3636076267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3636076267
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.3494603514
Short name T965
Test name
Test status
Simulation time 4941280877 ps
CPU time 10.94 seconds
Started Jun 26 06:11:05 PM PDT 24
Finished Jun 26 06:11:17 PM PDT 24
Peak memory 199208 kb
Host smart-27da60ac-f7bb-4849-ac26-aaf666081851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494603514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.3494603514
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_perf.2943187190
Short name T241
Test name
Test status
Simulation time 9355278305 ps
CPU time 539.45 seconds
Started Jun 26 06:11:00 PM PDT 24
Finished Jun 26 06:20:01 PM PDT 24
Peak memory 199900 kb
Host smart-1ac247af-375a-466e-b357-1e39188f2cfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2943187190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.2943187190
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3936389505
Short name T22
Test name
Test status
Simulation time 5513141428 ps
CPU time 6.74 seconds
Started Jun 26 06:10:55 PM PDT 24
Finished Jun 26 06:11:04 PM PDT 24
Peak memory 199768 kb
Host smart-e1981869-6a31-4826-9e58-d1bc10e18399
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3936389505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3936389505
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.1947160405
Short name T774
Test name
Test status
Simulation time 36845171062 ps
CPU time 52.68 seconds
Started Jun 26 06:11:00 PM PDT 24
Finished Jun 26 06:11:54 PM PDT 24
Peak memory 199936 kb
Host smart-58887565-67a8-4024-8809-6a499b8d5acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947160405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.1947160405
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.1134413431
Short name T270
Test name
Test status
Simulation time 35766541751 ps
CPU time 15.17 seconds
Started Jun 26 06:11:00 PM PDT 24
Finished Jun 26 06:11:16 PM PDT 24
Peak memory 196240 kb
Host smart-b68b0491-5a00-4d8a-8e23-d3fcaab3638d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134413431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1134413431
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.196281825
Short name T696
Test name
Test status
Simulation time 650310489 ps
CPU time 2.41 seconds
Started Jun 26 06:11:00 PM PDT 24
Finished Jun 26 06:11:03 PM PDT 24
Peak memory 199760 kb
Host smart-6f0ecbfe-58b6-44fe-9bad-26b148b9226c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196281825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.196281825
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.2650198544
Short name T1044
Test name
Test status
Simulation time 98071270380 ps
CPU time 144.23 seconds
Started Jun 26 06:11:02 PM PDT 24
Finished Jun 26 06:13:29 PM PDT 24
Peak memory 199892 kb
Host smart-ae93a719-522a-4512-8a11-6d581ee6d6b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650198544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2650198544
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.1013008566
Short name T50
Test name
Test status
Simulation time 42967259781 ps
CPU time 521.51 seconds
Started Jun 26 06:11:05 PM PDT 24
Finished Jun 26 06:19:48 PM PDT 24
Peak memory 216428 kb
Host smart-5182504a-9e5d-4083-9fb9-3d45723a2794
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013008566 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.1013008566
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.1403823830
Short name T637
Test name
Test status
Simulation time 391644092 ps
CPU time 1.89 seconds
Started Jun 26 06:11:00 PM PDT 24
Finished Jun 26 06:11:03 PM PDT 24
Peak memory 198732 kb
Host smart-646f9454-b7d8-4b2f-9ddc-a319bca75894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403823830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.1403823830
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.3456146413
Short name T317
Test name
Test status
Simulation time 44056532450 ps
CPU time 17 seconds
Started Jun 26 06:11:02 PM PDT 24
Finished Jun 26 06:11:21 PM PDT 24
Peak memory 200176 kb
Host smart-912fe5be-aa97-44ea-8e15-c814eaa0e04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456146413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3456146413
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.1517696855
Short name T1003
Test name
Test status
Simulation time 305253029862 ps
CPU time 30.99 seconds
Started Jun 26 06:13:51 PM PDT 24
Finished Jun 26 06:14:24 PM PDT 24
Peak memory 200208 kb
Host smart-4587635f-eed2-485f-b556-23693e4ff675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517696855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.1517696855
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.2390417767
Short name T967
Test name
Test status
Simulation time 110127537881 ps
CPU time 370.74 seconds
Started Jun 26 06:13:51 PM PDT 24
Finished Jun 26 06:20:04 PM PDT 24
Peak memory 200032 kb
Host smart-40c97e21-283d-4d61-a301-3320f3cedca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390417767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2390417767
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.3181493774
Short name T233
Test name
Test status
Simulation time 133952245369 ps
CPU time 50.46 seconds
Started Jun 26 06:13:51 PM PDT 24
Finished Jun 26 06:14:43 PM PDT 24
Peak memory 199960 kb
Host smart-897b0be7-ac96-44f9-8217-1b08c8cd6215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181493774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3181493774
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.908336710
Short name T585
Test name
Test status
Simulation time 28873218004 ps
CPU time 51.59 seconds
Started Jun 26 06:13:51 PM PDT 24
Finished Jun 26 06:14:44 PM PDT 24
Peak memory 199936 kb
Host smart-91484a7d-f962-42fb-b1c6-a44f99e912b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908336710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.908336710
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.3597825061
Short name T1083
Test name
Test status
Simulation time 154885313347 ps
CPU time 107.52 seconds
Started Jun 26 06:13:51 PM PDT 24
Finished Jun 26 06:15:41 PM PDT 24
Peak memory 199916 kb
Host smart-97e633f8-21a7-4831-9327-2cdccf20294c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597825061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.3597825061
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1024111861
Short name T89
Test name
Test status
Simulation time 119470759432 ps
CPU time 162.28 seconds
Started Jun 26 06:13:50 PM PDT 24
Finished Jun 26 06:16:33 PM PDT 24
Peak memory 200020 kb
Host smart-e2bb9161-30c9-45a9-abbc-75c05639b84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024111861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1024111861
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2532430792
Short name T895
Test name
Test status
Simulation time 85975305 ps
CPU time 0.53 seconds
Started Jun 26 06:11:11 PM PDT 24
Finished Jun 26 06:11:13 PM PDT 24
Peak memory 194252 kb
Host smart-8e299ac1-2284-483b-9130-c01d044bb519
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532430792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2532430792
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.3439276470
Short name T137
Test name
Test status
Simulation time 16156513470 ps
CPU time 15.16 seconds
Started Jun 26 06:11:11 PM PDT 24
Finished Jun 26 06:11:27 PM PDT 24
Peak memory 199916 kb
Host smart-0d535a7b-6d2c-4746-b4a2-314bea5d287f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439276470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3439276470
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.3133837810
Short name T295
Test name
Test status
Simulation time 172212728556 ps
CPU time 65.25 seconds
Started Jun 26 06:10:59 PM PDT 24
Finished Jun 26 06:12:06 PM PDT 24
Peak memory 200016 kb
Host smart-ad820c53-822c-45c8-b93f-4822f6b357e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133837810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3133837810
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.4258414960
Short name T218
Test name
Test status
Simulation time 42834068787 ps
CPU time 51.67 seconds
Started Jun 26 06:11:05 PM PDT 24
Finished Jun 26 06:11:58 PM PDT 24
Peak memory 199948 kb
Host smart-830077c2-e87c-4d42-94ba-4d9eba1d85a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258414960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.4258414960
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.4257238133
Short name T397
Test name
Test status
Simulation time 303352834691 ps
CPU time 217.02 seconds
Started Jun 26 06:10:57 PM PDT 24
Finished Jun 26 06:14:36 PM PDT 24
Peak memory 197724 kb
Host smart-90ad0bf1-651d-4b4f-a49b-972f55c9a7b5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257238133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.4257238133
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.3723936883
Short name T345
Test name
Test status
Simulation time 119635710332 ps
CPU time 748.67 seconds
Started Jun 26 06:11:20 PM PDT 24
Finished Jun 26 06:23:50 PM PDT 24
Peak memory 199980 kb
Host smart-397132cf-e611-42c0-8859-cb084b415fd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3723936883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3723936883
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.3995633849
Short name T779
Test name
Test status
Simulation time 10239783228 ps
CPU time 3.2 seconds
Started Jun 26 06:11:11 PM PDT 24
Finished Jun 26 06:11:16 PM PDT 24
Peak memory 199180 kb
Host smart-6aaaf2de-9ef9-4f3b-b1f3-c9c4e7b1b554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995633849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3995633849
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_perf.1693027649
Short name T491
Test name
Test status
Simulation time 22428222768 ps
CPU time 980.69 seconds
Started Jun 26 06:11:20 PM PDT 24
Finished Jun 26 06:27:42 PM PDT 24
Peak memory 199204 kb
Host smart-02f1a52e-3004-4f47-9b73-3b241892ea97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1693027649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1693027649
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.1340196190
Short name T654
Test name
Test status
Simulation time 1375917022 ps
CPU time 2.79 seconds
Started Jun 26 06:11:11 PM PDT 24
Finished Jun 26 06:11:15 PM PDT 24
Peak memory 197768 kb
Host smart-013ef4d1-5dc4-4b9d-a102-b538641b6ca7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1340196190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1340196190
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.33421227
Short name T576
Test name
Test status
Simulation time 37875527025 ps
CPU time 34.03 seconds
Started Jun 26 06:11:02 PM PDT 24
Finished Jun 26 06:11:38 PM PDT 24
Peak memory 199872 kb
Host smart-f5dac7bc-1808-4fbc-ba91-ed5c93266858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33421227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.33421227
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.2882106187
Short name T709
Test name
Test status
Simulation time 567902413 ps
CPU time 0.96 seconds
Started Jun 26 06:11:02 PM PDT 24
Finished Jun 26 06:11:04 PM PDT 24
Peak memory 195360 kb
Host smart-84bce1b0-a27e-4289-aa22-90a63f34b8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882106187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2882106187
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1743945219
Short name T805
Test name
Test status
Simulation time 772280660 ps
CPU time 1.19 seconds
Started Jun 26 06:11:03 PM PDT 24
Finished Jun 26 06:11:06 PM PDT 24
Peak memory 198608 kb
Host smart-bd24cdda-553a-4a7e-ac59-90663cfb30ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743945219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1743945219
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.916557723
Short name T748
Test name
Test status
Simulation time 1022869097 ps
CPU time 3.94 seconds
Started Jun 26 06:11:04 PM PDT 24
Finished Jun 26 06:11:10 PM PDT 24
Peak memory 199616 kb
Host smart-2d202055-9076-4588-84ff-2a09996d8462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916557723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.916557723
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3613152574
Short name T824
Test name
Test status
Simulation time 58280748276 ps
CPU time 56.19 seconds
Started Jun 26 06:11:02 PM PDT 24
Finished Jun 26 06:11:59 PM PDT 24
Peak memory 200140 kb
Host smart-d579fdf3-34a1-4304-9593-269f17e0b8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613152574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3613152574
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.3721262014
Short name T919
Test name
Test status
Simulation time 28384039372 ps
CPU time 37.51 seconds
Started Jun 26 06:13:51 PM PDT 24
Finished Jun 26 06:14:30 PM PDT 24
Peak memory 199904 kb
Host smart-0b39a4b7-08e2-4c91-8a8c-d8f7ec5285b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721262014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3721262014
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.149637926
Short name T123
Test name
Test status
Simulation time 186260219224 ps
CPU time 99.81 seconds
Started Jun 26 06:13:50 PM PDT 24
Finished Jun 26 06:15:31 PM PDT 24
Peak memory 199992 kb
Host smart-e5179323-217e-4d10-b23f-a5abb8715c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149637926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.149637926
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.3378153972
Short name T167
Test name
Test status
Simulation time 148804601174 ps
CPU time 440.35 seconds
Started Jun 26 06:13:51 PM PDT 24
Finished Jun 26 06:21:13 PM PDT 24
Peak memory 199984 kb
Host smart-aa02a68c-ac75-4483-a475-f2b94b9ecd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378153972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.3378153972
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.4086013418
Short name T754
Test name
Test status
Simulation time 17654565664 ps
CPU time 26.86 seconds
Started Jun 26 06:13:51 PM PDT 24
Finished Jun 26 06:14:19 PM PDT 24
Peak memory 199908 kb
Host smart-fdbb9422-1364-4aef-8b83-0ac2d0174081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086013418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.4086013418
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1506038299
Short name T1069
Test name
Test status
Simulation time 21846345090 ps
CPU time 31.68 seconds
Started Jun 26 06:13:49 PM PDT 24
Finished Jun 26 06:14:21 PM PDT 24
Peak memory 199772 kb
Host smart-ca7c1e4f-75b0-461f-9547-b8a56d495c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506038299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1506038299
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2541255888
Short name T928
Test name
Test status
Simulation time 22236855605 ps
CPU time 9.51 seconds
Started Jun 26 06:13:51 PM PDT 24
Finished Jun 26 06:14:03 PM PDT 24
Peak memory 199916 kb
Host smart-632edb5f-496e-4ec1-b773-f0daed42ad8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541255888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2541255888
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.537579100
Short name T891
Test name
Test status
Simulation time 198070459751 ps
CPU time 31.91 seconds
Started Jun 26 06:13:49 PM PDT 24
Finished Jun 26 06:14:23 PM PDT 24
Peak memory 199956 kb
Host smart-a7f9b4cb-e839-4de2-9af5-7b01b92b5e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537579100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.537579100
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.2519638037
Short name T1020
Test name
Test status
Simulation time 242557904373 ps
CPU time 63.18 seconds
Started Jun 26 06:13:55 PM PDT 24
Finished Jun 26 06:14:59 PM PDT 24
Peak memory 199972 kb
Host smart-fbaca8b0-d23c-4d72-80f7-0ef7a6ca9529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519638037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2519638037
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.2628530650
Short name T148
Test name
Test status
Simulation time 42936067149 ps
CPU time 40.21 seconds
Started Jun 26 06:13:59 PM PDT 24
Finished Jun 26 06:14:40 PM PDT 24
Peak memory 199984 kb
Host smart-89a80227-ec62-40b7-824b-1f9a7e48a733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628530650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2628530650
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.862077506
Short name T389
Test name
Test status
Simulation time 13993596 ps
CPU time 0.56 seconds
Started Jun 26 06:11:11 PM PDT 24
Finished Jun 26 06:11:13 PM PDT 24
Peak memory 195604 kb
Host smart-19131313-6bd9-40b1-92a1-50db3ea79507
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862077506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.862077506
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2877976543
Short name T549
Test name
Test status
Simulation time 37515031913 ps
CPU time 63.35 seconds
Started Jun 26 06:11:07 PM PDT 24
Finished Jun 26 06:12:12 PM PDT 24
Peak memory 199932 kb
Host smart-21b41428-7dc1-4e6a-88fc-f404c132d47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877976543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2877976543
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.204020076
Short name T653
Test name
Test status
Simulation time 319686775365 ps
CPU time 73.33 seconds
Started Jun 26 06:11:08 PM PDT 24
Finished Jun 26 06:12:22 PM PDT 24
Peak memory 199860 kb
Host smart-15bcade3-14b0-4628-8b44-2fe34f967127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204020076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.204020076
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_intr.4221494496
Short name T794
Test name
Test status
Simulation time 241616690902 ps
CPU time 149.98 seconds
Started Jun 26 06:11:01 PM PDT 24
Finished Jun 26 06:13:32 PM PDT 24
Peak memory 199576 kb
Host smart-fd69b8aa-e0ce-44de-9e82-71ae8fdcaf12
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221494496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.4221494496
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.3903421222
Short name T235
Test name
Test status
Simulation time 156414661720 ps
CPU time 1557.88 seconds
Started Jun 26 06:11:20 PM PDT 24
Finished Jun 26 06:37:20 PM PDT 24
Peak memory 199868 kb
Host smart-d0e435ff-21d5-488b-a7e8-cf3ea2283480
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3903421222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.3903421222
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.2578427426
Short name T588
Test name
Test status
Simulation time 7722480936 ps
CPU time 17.83 seconds
Started Jun 26 06:11:02 PM PDT 24
Finished Jun 26 06:11:22 PM PDT 24
Peak memory 199312 kb
Host smart-1a4ea5d1-9ed6-4be6-be86-1eb4c6615468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578427426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.2578427426
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_perf.2711450688
Short name T657
Test name
Test status
Simulation time 4949186271 ps
CPU time 179.74 seconds
Started Jun 26 06:11:03 PM PDT 24
Finished Jun 26 06:14:05 PM PDT 24
Peak memory 199936 kb
Host smart-47bbc912-c1e1-4926-99ab-cfc0845a98a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2711450688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.2711450688
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.2194359246
Short name T599
Test name
Test status
Simulation time 1479522345 ps
CPU time 5.61 seconds
Started Jun 26 06:11:04 PM PDT 24
Finished Jun 26 06:11:12 PM PDT 24
Peak memory 197876 kb
Host smart-2456f7f7-5ac9-4e84-ba88-f47507188e19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2194359246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.2194359246
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1084500995
Short name T673
Test name
Test status
Simulation time 25386255644 ps
CPU time 13.7 seconds
Started Jun 26 06:11:07 PM PDT 24
Finished Jun 26 06:11:22 PM PDT 24
Peak memory 199980 kb
Host smart-42a69f8b-99ad-4aa9-a5a7-2802bfd0fa62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084500995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1084500995
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2124650488
Short name T590
Test name
Test status
Simulation time 3418508636 ps
CPU time 6 seconds
Started Jun 26 06:11:05 PM PDT 24
Finished Jun 26 06:11:13 PM PDT 24
Peak memory 196424 kb
Host smart-a7079e88-299b-4da9-b05e-79f0f44a3762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124650488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2124650488
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.2577383190
Short name T480
Test name
Test status
Simulation time 507114042 ps
CPU time 2.98 seconds
Started Jun 26 06:11:04 PM PDT 24
Finished Jun 26 06:11:09 PM PDT 24
Peak memory 198880 kb
Host smart-30e06199-cae4-4b9f-9fe7-43e7ffbe0269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577383190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.2577383190
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.2856140095
Short name T816
Test name
Test status
Simulation time 281174237115 ps
CPU time 594.02 seconds
Started Jun 26 06:11:20 PM PDT 24
Finished Jun 26 06:21:15 PM PDT 24
Peak memory 199968 kb
Host smart-c7e90f70-f835-46c2-a9c9-ce906bdbd7bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856140095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.2856140095
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.3379713975
Short name T49
Test name
Test status
Simulation time 68967552279 ps
CPU time 257.15 seconds
Started Jun 26 06:11:07 PM PDT 24
Finished Jun 26 06:15:26 PM PDT 24
Peak memory 216480 kb
Host smart-bb6bbc55-8875-4b39-a676-1aec8463501d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379713975 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.3379713975
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.2063288583
Short name T462
Test name
Test status
Simulation time 2001134433 ps
CPU time 1.86 seconds
Started Jun 26 06:11:06 PM PDT 24
Finished Jun 26 06:11:09 PM PDT 24
Peak memory 199516 kb
Host smart-528da928-319f-432d-a983-627f1f8d0320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063288583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2063288583
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.2022123313
Short name T42
Test name
Test status
Simulation time 87435360754 ps
CPU time 31.55 seconds
Started Jun 26 06:11:03 PM PDT 24
Finished Jun 26 06:11:37 PM PDT 24
Peak memory 200204 kb
Host smart-85c66b7e-edb1-4669-8eaa-f850fb18d127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022123313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.2022123313
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.3437148504
Short name T900
Test name
Test status
Simulation time 39019792068 ps
CPU time 28.36 seconds
Started Jun 26 06:13:56 PM PDT 24
Finished Jun 26 06:14:25 PM PDT 24
Peak memory 199588 kb
Host smart-3c03d198-3d3b-44b7-9a57-7476dd238c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437148504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.3437148504
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3455504283
Short name T857
Test name
Test status
Simulation time 41725708740 ps
CPU time 17.82 seconds
Started Jun 26 06:14:02 PM PDT 24
Finished Jun 26 06:14:21 PM PDT 24
Peak memory 200000 kb
Host smart-45a860a2-5132-41c0-843e-1a29912883dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455504283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3455504283
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.2968016684
Short name T699
Test name
Test status
Simulation time 173917106605 ps
CPU time 42.42 seconds
Started Jun 26 06:13:55 PM PDT 24
Finished Jun 26 06:14:38 PM PDT 24
Peak memory 199976 kb
Host smart-bbbd4f8c-0399-43fc-8b77-4913dca0bcdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968016684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2968016684
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.1868043283
Short name T215
Test name
Test status
Simulation time 281403377099 ps
CPU time 37.74 seconds
Started Jun 26 06:13:57 PM PDT 24
Finished Jun 26 06:14:36 PM PDT 24
Peak memory 200020 kb
Host smart-02578f89-9614-408d-a742-8e6037cfce5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868043283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.1868043283
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.414285229
Short name T435
Test name
Test status
Simulation time 88154533133 ps
CPU time 17.68 seconds
Started Jun 26 06:13:59 PM PDT 24
Finished Jun 26 06:14:18 PM PDT 24
Peak memory 200008 kb
Host smart-5a98372c-5f5a-429b-ba9a-a09ab270b24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414285229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.414285229
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.2143924504
Short name T911
Test name
Test status
Simulation time 14133999590 ps
CPU time 24.2 seconds
Started Jun 26 06:13:58 PM PDT 24
Finished Jun 26 06:14:23 PM PDT 24
Peak memory 199920 kb
Host smart-69884d38-f3c0-49b6-9c08-0a116f72559f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143924504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.2143924504
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.3564286881
Short name T962
Test name
Test status
Simulation time 9011471502 ps
CPU time 14.7 seconds
Started Jun 26 06:13:58 PM PDT 24
Finished Jun 26 06:14:14 PM PDT 24
Peak memory 199964 kb
Host smart-a24dd880-9e29-4a59-8821-4b4b0f1adc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564286881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3564286881
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2327419278
Short name T231
Test name
Test status
Simulation time 225830143786 ps
CPU time 48.14 seconds
Started Jun 26 06:13:55 PM PDT 24
Finished Jun 26 06:14:44 PM PDT 24
Peak memory 199924 kb
Host smart-e39ffbc3-b9f2-4639-b3f6-253bb2f11c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327419278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2327419278
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.2131789845
Short name T742
Test name
Test status
Simulation time 13300980 ps
CPU time 0.54 seconds
Started Jun 26 06:11:21 PM PDT 24
Finished Jun 26 06:11:23 PM PDT 24
Peak memory 195600 kb
Host smart-a0d3cc2f-afa5-4306-9fa2-ff99357cd2c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131789845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.2131789845
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.3093023959
Short name T140
Test name
Test status
Simulation time 43025068682 ps
CPU time 13.82 seconds
Started Jun 26 06:11:20 PM PDT 24
Finished Jun 26 06:11:36 PM PDT 24
Peak memory 200000 kb
Host smart-a9cae094-8a5d-4738-8468-1e147e70c204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093023959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3093023959
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.4188349012
Short name T683
Test name
Test status
Simulation time 18530991529 ps
CPU time 14.16 seconds
Started Jun 26 06:11:20 PM PDT 24
Finished Jun 26 06:11:36 PM PDT 24
Peak memory 199552 kb
Host smart-81424f38-9f53-4189-a60c-4f4bde387cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188349012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.4188349012
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_intr.3863295345
Short name T913
Test name
Test status
Simulation time 42712687784 ps
CPU time 64.39 seconds
Started Jun 26 06:11:09 PM PDT 24
Finished Jun 26 06:12:15 PM PDT 24
Peak memory 199844 kb
Host smart-11f1c892-e7ea-4ae5-b254-32782870c91e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863295345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3863295345
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1917089739
Short name T697
Test name
Test status
Simulation time 153047519525 ps
CPU time 281.13 seconds
Started Jun 26 06:11:07 PM PDT 24
Finished Jun 26 06:15:50 PM PDT 24
Peak memory 199964 kb
Host smart-5a56c069-0b53-4ba7-b54e-fa2bb3830d0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1917089739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1917089739
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.842513422
Short name T363
Test name
Test status
Simulation time 340247056 ps
CPU time 1.14 seconds
Started Jun 26 06:11:11 PM PDT 24
Finished Jun 26 06:11:14 PM PDT 24
Peak memory 195980 kb
Host smart-81fd55e8-5cef-4eeb-8cb6-78342513b5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842513422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.842513422
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_perf.2031369114
Short name T382
Test name
Test status
Simulation time 4675074601 ps
CPU time 278.5 seconds
Started Jun 26 06:11:21 PM PDT 24
Finished Jun 26 06:16:01 PM PDT 24
Peak memory 199944 kb
Host smart-a185c1cd-dc60-401d-8b5b-56b54042aa08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2031369114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2031369114
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.3931953983
Short name T428
Test name
Test status
Simulation time 1915913466 ps
CPU time 9.88 seconds
Started Jun 26 06:11:10 PM PDT 24
Finished Jun 26 06:11:21 PM PDT 24
Peak memory 198068 kb
Host smart-2e4e175c-2719-4e65-b902-4bef0dab2683
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3931953983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3931953983
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.2755743116
Short name T158
Test name
Test status
Simulation time 52419778129 ps
CPU time 12.25 seconds
Started Jun 26 06:11:14 PM PDT 24
Finished Jun 26 06:11:28 PM PDT 24
Peak memory 199920 kb
Host smart-ce872f19-686b-463d-84fc-d134d0449593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755743116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.2755743116
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.2138223449
Short name T300
Test name
Test status
Simulation time 3967114167 ps
CPU time 1.43 seconds
Started Jun 26 06:11:11 PM PDT 24
Finished Jun 26 06:11:13 PM PDT 24
Peak memory 196456 kb
Host smart-8851b457-f52b-403b-af33-4586d7035dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138223449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2138223449
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.1532138602
Short name T860
Test name
Test status
Simulation time 544358575 ps
CPU time 1.89 seconds
Started Jun 26 06:11:21 PM PDT 24
Finished Jun 26 06:11:25 PM PDT 24
Peak memory 198204 kb
Host smart-466a8135-1117-4279-a76c-982f9aaee16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532138602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1532138602
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.1062840892
Short name T1004
Test name
Test status
Simulation time 123303317924 ps
CPU time 67.9 seconds
Started Jun 26 06:11:09 PM PDT 24
Finished Jun 26 06:12:18 PM PDT 24
Peak memory 199920 kb
Host smart-cc7c2e89-0984-4202-9010-730b26f87bdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062840892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.1062840892
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.590874542
Short name T960
Test name
Test status
Simulation time 6612928772 ps
CPU time 32.73 seconds
Started Jun 26 06:11:07 PM PDT 24
Finished Jun 26 06:11:41 PM PDT 24
Peak memory 199796 kb
Host smart-35518d53-69cc-4604-a9eb-2f96d7e1d909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590874542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.590874542
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.759597633
Short name T537
Test name
Test status
Simulation time 19730868120 ps
CPU time 5.37 seconds
Started Jun 26 06:11:09 PM PDT 24
Finished Jun 26 06:11:16 PM PDT 24
Peak memory 199976 kb
Host smart-410b3bed-788c-41e0-86c7-85dfac3241ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759597633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.759597633
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.2355065176
Short name T280
Test name
Test status
Simulation time 24088809617 ps
CPU time 23.66 seconds
Started Jun 26 06:13:55 PM PDT 24
Finished Jun 26 06:14:20 PM PDT 24
Peak memory 199996 kb
Host smart-15cfc0fd-f5bc-4fc3-a1a9-d6c912dbb209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355065176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2355065176
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3851283316
Short name T783
Test name
Test status
Simulation time 90215040491 ps
CPU time 129.11 seconds
Started Jun 26 06:13:57 PM PDT 24
Finished Jun 26 06:16:07 PM PDT 24
Peak memory 199916 kb
Host smart-276609ab-3103-4e06-8a98-f03ddf3e5bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851283316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3851283316
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.2727876681
Short name T1034
Test name
Test status
Simulation time 80963776481 ps
CPU time 123.88 seconds
Started Jun 26 06:13:58 PM PDT 24
Finished Jun 26 06:16:03 PM PDT 24
Peak memory 199916 kb
Host smart-8cf7693f-1439-4ca5-b412-f593e3936db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727876681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2727876681
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.836254751
Short name T547
Test name
Test status
Simulation time 81943289177 ps
CPU time 169.68 seconds
Started Jun 26 06:13:57 PM PDT 24
Finished Jun 26 06:16:47 PM PDT 24
Peak memory 199948 kb
Host smart-1fb2a6e5-98d3-43c0-867f-3000f0456e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836254751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.836254751
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.552430384
Short name T283
Test name
Test status
Simulation time 55056812765 ps
CPU time 44.95 seconds
Started Jun 26 06:13:56 PM PDT 24
Finished Jun 26 06:14:42 PM PDT 24
Peak memory 199916 kb
Host smart-71d7e9c9-1475-4dbf-b125-2a3b5ea1ef40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552430384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.552430384
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.3667061906
Short name T496
Test name
Test status
Simulation time 300515700653 ps
CPU time 146.05 seconds
Started Jun 26 06:13:59 PM PDT 24
Finished Jun 26 06:16:26 PM PDT 24
Peak memory 199916 kb
Host smart-3d152ea5-9eb2-4a65-9ec4-c3232808d504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667061906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3667061906
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.2368453994
Short name T494
Test name
Test status
Simulation time 128889561433 ps
CPU time 172.55 seconds
Started Jun 26 06:14:03 PM PDT 24
Finished Jun 26 06:16:57 PM PDT 24
Peak memory 199896 kb
Host smart-259a96be-7bc3-4572-99f1-04bfc82dcdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368453994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2368453994
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.1534228156
Short name T229
Test name
Test status
Simulation time 182453982801 ps
CPU time 74.98 seconds
Started Jun 26 06:14:00 PM PDT 24
Finished Jun 26 06:15:16 PM PDT 24
Peak memory 200032 kb
Host smart-ad24a36f-cf3d-46fe-bffb-3cb647b8bfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534228156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1534228156
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2963230122
Short name T277
Test name
Test status
Simulation time 19578668459 ps
CPU time 33.46 seconds
Started Jun 26 06:14:00 PM PDT 24
Finished Jun 26 06:14:35 PM PDT 24
Peak memory 199988 kb
Host smart-542e671b-5f72-4427-b28f-74cf1a495794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963230122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2963230122
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.3064949974
Short name T763
Test name
Test status
Simulation time 43428542 ps
CPU time 0.55 seconds
Started Jun 26 06:11:22 PM PDT 24
Finished Jun 26 06:11:25 PM PDT 24
Peak memory 195316 kb
Host smart-06f4c6d1-946f-4a91-80aa-70bf91da320b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064949974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.3064949974
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.4077389890
Short name T633
Test name
Test status
Simulation time 184164723292 ps
CPU time 286.4 seconds
Started Jun 26 06:11:22 PM PDT 24
Finished Jun 26 06:16:10 PM PDT 24
Peak memory 200000 kb
Host smart-79682c06-d037-40a0-9129-454eb23e8b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077389890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.4077389890
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.1993506104
Short name T458
Test name
Test status
Simulation time 33598810049 ps
CPU time 16.43 seconds
Started Jun 26 06:11:21 PM PDT 24
Finished Jun 26 06:11:40 PM PDT 24
Peak memory 200000 kb
Host smart-d1de9650-b42d-4db7-b249-a722d5f0dd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993506104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.1993506104
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.3659192761
Short name T178
Test name
Test status
Simulation time 58821807220 ps
CPU time 32.95 seconds
Started Jun 26 06:11:21 PM PDT 24
Finished Jun 26 06:11:56 PM PDT 24
Peak memory 200000 kb
Host smart-4a88cc7d-9f67-4b82-98fd-99e354c3621a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659192761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3659192761
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.503798308
Short name T443
Test name
Test status
Simulation time 40949116219 ps
CPU time 290.12 seconds
Started Jun 26 06:11:17 PM PDT 24
Finished Jun 26 06:16:08 PM PDT 24
Peak memory 199984 kb
Host smart-21253c16-eed0-42eb-bcde-d479227f5eaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=503798308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.503798308
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.1592438376
Short name T976
Test name
Test status
Simulation time 5255335192 ps
CPU time 4.12 seconds
Started Jun 26 06:11:11 PM PDT 24
Finished Jun 26 06:11:16 PM PDT 24
Peak memory 198656 kb
Host smart-f06a2ad0-54b7-4dce-b4f0-e50e26d6aff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592438376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1592438376
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_perf.2084915896
Short name T948
Test name
Test status
Simulation time 25466198478 ps
CPU time 671.85 seconds
Started Jun 26 06:11:19 PM PDT 24
Finished Jun 26 06:22:32 PM PDT 24
Peak memory 199984 kb
Host smart-db42b57b-e4b0-4dbb-b3eb-5b862ce808a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2084915896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2084915896
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.132460662
Short name T351
Test name
Test status
Simulation time 6274945102 ps
CPU time 13.94 seconds
Started Jun 26 06:11:20 PM PDT 24
Finished Jun 26 06:11:35 PM PDT 24
Peak memory 197856 kb
Host smart-8f69ff9b-57a0-48ef-8e16-32e1e2ce4129
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=132460662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.132460662
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.2891957545
Short name T925
Test name
Test status
Simulation time 91639750594 ps
CPU time 263.35 seconds
Started Jun 26 06:11:11 PM PDT 24
Finished Jun 26 06:15:35 PM PDT 24
Peak memory 199956 kb
Host smart-61fe931d-dd80-41ea-9a40-44361041cac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891957545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2891957545
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.2767582225
Short name T690
Test name
Test status
Simulation time 422702709 ps
CPU time 1.32 seconds
Started Jun 26 06:11:09 PM PDT 24
Finished Jun 26 06:11:11 PM PDT 24
Peak memory 195536 kb
Host smart-e34ad339-9487-4cbf-899f-b2a21ea9dac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767582225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.2767582225
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.520396265
Short name T898
Test name
Test status
Simulation time 5841596815 ps
CPU time 4.5 seconds
Started Jun 26 06:11:10 PM PDT 24
Finished Jun 26 06:11:16 PM PDT 24
Peak memory 199940 kb
Host smart-31ccfb4b-89e5-49df-8a56-689aaf57927c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520396265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.520396265
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.2320327002
Short name T13
Test name
Test status
Simulation time 54218117691 ps
CPU time 74.14 seconds
Started Jun 26 06:11:18 PM PDT 24
Finished Jun 26 06:12:33 PM PDT 24
Peak memory 199920 kb
Host smart-972ec802-d7fe-4d26-afbe-51c7e692672e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320327002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2320327002
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.855084958
Short name T309
Test name
Test status
Simulation time 82554034971 ps
CPU time 361.95 seconds
Started Jun 26 06:11:14 PM PDT 24
Finished Jun 26 06:17:17 PM PDT 24
Peak memory 216416 kb
Host smart-b27ba8b1-7ca8-4200-84e4-39ba49eb1643
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855084958 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.855084958
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.3274682958
Short name T377
Test name
Test status
Simulation time 596011728 ps
CPU time 1.56 seconds
Started Jun 26 06:11:22 PM PDT 24
Finished Jun 26 06:11:26 PM PDT 24
Peak memory 198412 kb
Host smart-f3432f74-ffc7-47e4-a5ad-0951cc59d689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274682958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3274682958
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.1627901848
Short name T715
Test name
Test status
Simulation time 15873523016 ps
CPU time 20.86 seconds
Started Jun 26 06:11:20 PM PDT 24
Finished Jun 26 06:11:42 PM PDT 24
Peak memory 199272 kb
Host smart-9ab665f3-30e8-4a09-b549-1f11c531644a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627901848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.1627901848
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.724135969
Short name T708
Test name
Test status
Simulation time 30366912628 ps
CPU time 12.04 seconds
Started Jun 26 06:14:05 PM PDT 24
Finished Jun 26 06:14:18 PM PDT 24
Peak memory 200008 kb
Host smart-871ef1e2-cc98-4e00-8c4e-6f37dea01489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724135969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.724135969
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.4281403550
Short name T732
Test name
Test status
Simulation time 152176699985 ps
CPU time 47.85 seconds
Started Jun 26 06:14:00 PM PDT 24
Finished Jun 26 06:14:49 PM PDT 24
Peak memory 199992 kb
Host smart-c44c1374-fd07-40ec-94eb-75a128fb14cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281403550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.4281403550
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.1580326321
Short name T205
Test name
Test status
Simulation time 30344712825 ps
CPU time 15.49 seconds
Started Jun 26 06:14:04 PM PDT 24
Finished Jun 26 06:14:21 PM PDT 24
Peak memory 199912 kb
Host smart-19c27d9e-2ddc-4293-aa8a-22ef9a7aada9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580326321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.1580326321
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.1141910546
Short name T189
Test name
Test status
Simulation time 108645766549 ps
CPU time 93.3 seconds
Started Jun 26 06:15:04 PM PDT 24
Finished Jun 26 06:16:38 PM PDT 24
Peak memory 199912 kb
Host smart-f9c4cc99-76d7-4430-801e-d20b04af6160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141910546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1141910546
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.2186354803
Short name T603
Test name
Test status
Simulation time 11224582187 ps
CPU time 16.69 seconds
Started Jun 26 06:14:03 PM PDT 24
Finished Jun 26 06:14:21 PM PDT 24
Peak memory 199936 kb
Host smart-8bbb0f49-03fd-4d45-9dd5-6d24ad37ea39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186354803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2186354803
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2959606356
Short name T225
Test name
Test status
Simulation time 27548001607 ps
CPU time 40.13 seconds
Started Jun 26 06:14:04 PM PDT 24
Finished Jun 26 06:14:46 PM PDT 24
Peak memory 199956 kb
Host smart-14f63330-1274-42a4-92af-bb5e988c7314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959606356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2959606356
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.3380157531
Short name T475
Test name
Test status
Simulation time 54185845095 ps
CPU time 66.69 seconds
Started Jun 26 06:14:05 PM PDT 24
Finished Jun 26 06:15:13 PM PDT 24
Peak memory 199984 kb
Host smart-9b45403c-4d85-4785-8647-428b4df7ef13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380157531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.3380157531
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.204097124
Short name T181
Test name
Test status
Simulation time 40899317921 ps
CPU time 66.15 seconds
Started Jun 26 06:14:01 PM PDT 24
Finished Jun 26 06:15:09 PM PDT 24
Peak memory 199804 kb
Host smart-da51fea5-f1a1-4bad-9c82-d7711344c9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204097124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.204097124
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.478044306
Short name T139
Test name
Test status
Simulation time 64571428462 ps
CPU time 171.61 seconds
Started Jun 26 06:14:06 PM PDT 24
Finished Jun 26 06:16:59 PM PDT 24
Peak memory 199936 kb
Host smart-213e3758-29b7-4443-8ef0-6a30c13b656e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478044306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.478044306
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.4155906861
Short name T705
Test name
Test status
Simulation time 142515346959 ps
CPU time 14.89 seconds
Started Jun 26 06:14:03 PM PDT 24
Finished Jun 26 06:14:20 PM PDT 24
Peak memory 199932 kb
Host smart-acded753-98fc-466c-99c9-677a69a76326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155906861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.4155906861
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.2151738654
Short name T712
Test name
Test status
Simulation time 21321911 ps
CPU time 0.59 seconds
Started Jun 26 06:11:17 PM PDT 24
Finished Jun 26 06:11:19 PM PDT 24
Peak memory 195240 kb
Host smart-063ab9e3-b287-4220-acc2-df4328825f76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151738654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.2151738654
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.207230872
Short name T909
Test name
Test status
Simulation time 52663895815 ps
CPU time 79.38 seconds
Started Jun 26 06:11:14 PM PDT 24
Finished Jun 26 06:12:34 PM PDT 24
Peak memory 199976 kb
Host smart-02711298-322a-439f-910d-df71527dee86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207230872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.207230872
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1942889458
Short name T1050
Test name
Test status
Simulation time 77116507746 ps
CPU time 110.95 seconds
Started Jun 26 06:11:16 PM PDT 24
Finished Jun 26 06:13:09 PM PDT 24
Peak memory 199852 kb
Host smart-99b309fb-3af1-4d92-b163-c5a4768ab952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942889458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1942889458
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3689891133
Short name T440
Test name
Test status
Simulation time 166704722381 ps
CPU time 19.59 seconds
Started Jun 26 06:11:14 PM PDT 24
Finished Jun 26 06:11:35 PM PDT 24
Peak memory 199904 kb
Host smart-85daff57-c8f4-448f-b607-7325c9c8ed58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689891133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3689891133
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.2053234393
Short name T248
Test name
Test status
Simulation time 174918048007 ps
CPU time 59.6 seconds
Started Jun 26 06:11:15 PM PDT 24
Finished Jun 26 06:12:16 PM PDT 24
Peak memory 199892 kb
Host smart-08fbb573-413f-41a6-b5b6-9c1a1a669fe7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053234393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.2053234393
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.3941555981
Short name T508
Test name
Test status
Simulation time 92263760458 ps
CPU time 137.73 seconds
Started Jun 26 06:11:13 PM PDT 24
Finished Jun 26 06:13:32 PM PDT 24
Peak memory 199944 kb
Host smart-4c2616e9-47b0-4551-85ba-81a0ac2bc75b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3941555981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.3941555981
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.1370059085
Short name T849
Test name
Test status
Simulation time 670117283 ps
CPU time 0.96 seconds
Started Jun 26 06:11:16 PM PDT 24
Finished Jun 26 06:11:18 PM PDT 24
Peak memory 195364 kb
Host smart-ea10b050-a415-4d48-bd63-ad2b8d51852b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370059085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1370059085
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_perf.758091959
Short name T999
Test name
Test status
Simulation time 17336468209 ps
CPU time 459.95 seconds
Started Jun 26 06:11:22 PM PDT 24
Finished Jun 26 06:19:04 PM PDT 24
Peak memory 199844 kb
Host smart-a41b8323-939b-4b52-a333-aa1582662094
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=758091959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.758091959
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.918090351
Short name T927
Test name
Test status
Simulation time 4374617998 ps
CPU time 9.44 seconds
Started Jun 26 06:11:18 PM PDT 24
Finished Jun 26 06:11:29 PM PDT 24
Peak memory 198196 kb
Host smart-736c8c64-75b6-49cf-a683-f4127e077e67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=918090351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.918090351
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.307330119
Short name T162
Test name
Test status
Simulation time 21422620935 ps
CPU time 8.82 seconds
Started Jun 26 06:11:15 PM PDT 24
Finished Jun 26 06:11:25 PM PDT 24
Peak memory 199840 kb
Host smart-463eb1db-c583-4ebc-a5dd-e9916390178e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307330119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.307330119
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.4265727872
Short name T871
Test name
Test status
Simulation time 1904368255 ps
CPU time 3.71 seconds
Started Jun 26 06:11:16 PM PDT 24
Finished Jun 26 06:11:21 PM PDT 24
Peak memory 195424 kb
Host smart-acd78244-f9ca-42d0-bdc0-021a3be736d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265727872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.4265727872
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.2536611855
Short name T334
Test name
Test status
Simulation time 6049030766 ps
CPU time 30.01 seconds
Started Jun 26 06:11:22 PM PDT 24
Finished Jun 26 06:11:54 PM PDT 24
Peak memory 199276 kb
Host smart-4ab26072-5114-470d-b051-b84fa5103571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536611855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2536611855
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.2134033756
Short name T307
Test name
Test status
Simulation time 43465651235 ps
CPU time 342.6 seconds
Started Jun 26 06:11:16 PM PDT 24
Finished Jun 26 06:17:00 PM PDT 24
Peak memory 216488 kb
Host smart-23b7ab0f-7ebe-462f-9474-989f8068073d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134033756 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.2134033756
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2768487975
Short name T845
Test name
Test status
Simulation time 1689958197 ps
CPU time 1.65 seconds
Started Jun 26 06:11:18 PM PDT 24
Finished Jun 26 06:11:21 PM PDT 24
Peak memory 198400 kb
Host smart-055b6584-0e2f-48c0-9912-64d6c0b36d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768487975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2768487975
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.87596546
Short name T486
Test name
Test status
Simulation time 55246287452 ps
CPU time 22.4 seconds
Started Jun 26 06:11:14 PM PDT 24
Finished Jun 26 06:11:37 PM PDT 24
Peak memory 199992 kb
Host smart-62f3a86a-ddd1-4af7-8b09-0f7893f63727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87596546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.87596546
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2172892138
Short name T207
Test name
Test status
Simulation time 156530992823 ps
CPU time 87.06 seconds
Started Jun 26 06:14:02 PM PDT 24
Finished Jun 26 06:15:30 PM PDT 24
Peak memory 199860 kb
Host smart-05a93920-4797-49b0-a340-82a9c3c97907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172892138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2172892138
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.3445225426
Short name T662
Test name
Test status
Simulation time 29417850081 ps
CPU time 20.32 seconds
Started Jun 26 06:14:03 PM PDT 24
Finished Jun 26 06:14:25 PM PDT 24
Peak memory 200012 kb
Host smart-1446d955-8cec-4c10-9865-44ae586d5d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445225426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.3445225426
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3246586649
Short name T222
Test name
Test status
Simulation time 237779985130 ps
CPU time 187.94 seconds
Started Jun 26 06:14:06 PM PDT 24
Finished Jun 26 06:17:15 PM PDT 24
Peak memory 199948 kb
Host smart-030064b1-495a-43ff-ae42-5b548195bd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246586649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3246586649
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.2047466288
Short name T567
Test name
Test status
Simulation time 165636483741 ps
CPU time 147.94 seconds
Started Jun 26 06:14:04 PM PDT 24
Finished Jun 26 06:16:33 PM PDT 24
Peak memory 200004 kb
Host smart-4ab6bf9c-0f68-4a93-88a5-434ff5f431e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047466288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2047466288
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.2428159880
Short name T507
Test name
Test status
Simulation time 63574571768 ps
CPU time 37.53 seconds
Started Jun 26 06:14:05 PM PDT 24
Finished Jun 26 06:14:44 PM PDT 24
Peak memory 199984 kb
Host smart-a4dfc4e8-d8f5-4ea7-bdd3-0e87ddd78116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428159880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2428159880
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.1276984527
Short name T193
Test name
Test status
Simulation time 29303416387 ps
CPU time 23.83 seconds
Started Jun 26 06:14:03 PM PDT 24
Finished Jun 26 06:14:28 PM PDT 24
Peak memory 199920 kb
Host smart-6cb48eee-3f91-4484-85f0-573c5135f1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276984527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1276984527
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.265246734
Short name T1002
Test name
Test status
Simulation time 157637089851 ps
CPU time 63.25 seconds
Started Jun 26 06:14:01 PM PDT 24
Finished Jun 26 06:15:06 PM PDT 24
Peak memory 199936 kb
Host smart-3276ef38-5b20-49b0-b2f5-b9438b46b521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265246734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.265246734
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.2758738369
Short name T199
Test name
Test status
Simulation time 22418411588 ps
CPU time 38.34 seconds
Started Jun 26 06:14:05 PM PDT 24
Finished Jun 26 06:14:45 PM PDT 24
Peak memory 199948 kb
Host smart-682ffb5f-f421-4486-9001-afe6606a5dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758738369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2758738369
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.631027467
Short name T492
Test name
Test status
Simulation time 6249150250 ps
CPU time 10.99 seconds
Started Jun 26 06:14:01 PM PDT 24
Finished Jun 26 06:14:14 PM PDT 24
Peak memory 199936 kb
Host smart-be81ecc2-9ff6-486a-8671-b6b96ab38c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631027467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.631027467
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2628007024
Short name T831
Test name
Test status
Simulation time 143778544405 ps
CPU time 365.65 seconds
Started Jun 26 06:14:04 PM PDT 24
Finished Jun 26 06:20:11 PM PDT 24
Peak memory 199912 kb
Host smart-d108c07e-f81e-49e9-a270-da764a2bdb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628007024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2628007024
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.695494497
Short name T632
Test name
Test status
Simulation time 28690975 ps
CPU time 0.51 seconds
Started Jun 26 06:11:21 PM PDT 24
Finished Jun 26 06:11:23 PM PDT 24
Peak memory 194296 kb
Host smart-29fd6284-3770-4e46-ba17-7711fb040845
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695494497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.695494497
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.624030696
Short name T605
Test name
Test status
Simulation time 61431357266 ps
CPU time 101.29 seconds
Started Jun 26 06:11:23 PM PDT 24
Finished Jun 26 06:13:07 PM PDT 24
Peak memory 200004 kb
Host smart-687f0da3-af93-48b7-8e21-a00938cefc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624030696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.624030696
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.1630743761
Short name T138
Test name
Test status
Simulation time 67739987019 ps
CPU time 32.42 seconds
Started Jun 26 06:11:17 PM PDT 24
Finished Jun 26 06:11:51 PM PDT 24
Peak memory 200004 kb
Host smart-967baeb8-ebd2-41e3-99ef-bbc02ea60e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630743761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1630743761
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_intr.577322668
Short name T955
Test name
Test status
Simulation time 56558098813 ps
CPU time 48.66 seconds
Started Jun 26 06:11:13 PM PDT 24
Finished Jun 26 06:12:02 PM PDT 24
Peak memory 199968 kb
Host smart-93050b99-376b-4eb6-a5f0-c36b28f2dc6f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577322668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.577322668
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.3469179616
Short name T430
Test name
Test status
Simulation time 205236568510 ps
CPU time 382.73 seconds
Started Jun 26 06:11:22 PM PDT 24
Finished Jun 26 06:17:47 PM PDT 24
Peak memory 199948 kb
Host smart-b94dcbb4-3ee7-430f-b1ad-f0d09698b399
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3469179616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.3469179616
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.2210813506
Short name T597
Test name
Test status
Simulation time 3752113019 ps
CPU time 2.59 seconds
Started Jun 26 06:11:20 PM PDT 24
Finished Jun 26 06:11:23 PM PDT 24
Peak memory 198508 kb
Host smart-016a1267-f81b-4ca4-9c8a-fc8178ae745f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210813506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2210813506
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_perf.30006963
Short name T723
Test name
Test status
Simulation time 13291746431 ps
CPU time 319.18 seconds
Started Jun 26 06:11:23 PM PDT 24
Finished Jun 26 06:16:44 PM PDT 24
Peak memory 199932 kb
Host smart-bde1103f-72ee-4cc0-b911-f7f7428f312a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=30006963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.30006963
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.3943018746
Short name T771
Test name
Test status
Simulation time 7306884298 ps
CPU time 66.22 seconds
Started Jun 26 06:11:17 PM PDT 24
Finished Jun 26 06:12:25 PM PDT 24
Peak memory 199036 kb
Host smart-362d8639-a822-4b69-bd26-933164c0b481
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3943018746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3943018746
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.2286021242
Short name T638
Test name
Test status
Simulation time 135406478447 ps
CPU time 157.84 seconds
Started Jun 26 06:11:23 PM PDT 24
Finished Jun 26 06:14:02 PM PDT 24
Peak memory 199904 kb
Host smart-349bee3d-4a11-447c-a404-b3cc60990b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286021242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2286021242
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.1451836411
Short name T1023
Test name
Test status
Simulation time 1413548975 ps
CPU time 1.69 seconds
Started Jun 26 06:11:17 PM PDT 24
Finished Jun 26 06:11:20 PM PDT 24
Peak memory 195408 kb
Host smart-f2250f01-6e87-45e8-8a8d-387688153889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451836411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1451836411
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.1768509363
Short name T301
Test name
Test status
Simulation time 905583920 ps
CPU time 1.84 seconds
Started Jun 26 06:11:15 PM PDT 24
Finished Jun 26 06:11:19 PM PDT 24
Peak memory 199524 kb
Host smart-50f509a7-cfac-4e36-bda0-3d6e2410124c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768509363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1768509363
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.2339653620
Short name T266
Test name
Test status
Simulation time 65004753546 ps
CPU time 117.25 seconds
Started Jun 26 06:11:23 PM PDT 24
Finished Jun 26 06:13:22 PM PDT 24
Peak memory 199928 kb
Host smart-b21ff472-3f4f-4740-8b81-18f056c80e97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339653620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.2339653620
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.2334739427
Short name T982
Test name
Test status
Simulation time 59621052983 ps
CPU time 808.52 seconds
Started Jun 26 06:11:24 PM PDT 24
Finished Jun 26 06:24:54 PM PDT 24
Peak memory 216588 kb
Host smart-5aae041e-2f5c-4a19-8a34-b718d1819265
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334739427 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.2334739427
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1434408724
Short name T1091
Test name
Test status
Simulation time 7239808845 ps
CPU time 20.59 seconds
Started Jun 26 06:11:21 PM PDT 24
Finished Jun 26 06:11:43 PM PDT 24
Peak memory 199972 kb
Host smart-2001cc16-8aca-49aa-9ae3-3a50a3d0aff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434408724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1434408724
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.3643195100
Short name T402
Test name
Test status
Simulation time 81950997916 ps
CPU time 33.77 seconds
Started Jun 26 06:11:14 PM PDT 24
Finished Jun 26 06:11:49 PM PDT 24
Peak memory 199800 kb
Host smart-90d8e9b5-33fe-4f99-9912-2c5d13fcf955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643195100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3643195100
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1235930181
Short name T154
Test name
Test status
Simulation time 75774853763 ps
CPU time 65.25 seconds
Started Jun 26 06:14:04 PM PDT 24
Finished Jun 26 06:15:10 PM PDT 24
Peak memory 200044 kb
Host smart-461f14b4-b204-4ec6-ac7d-085aa54d4dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235930181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1235930181
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.3157416288
Short name T710
Test name
Test status
Simulation time 39236932769 ps
CPU time 26.03 seconds
Started Jun 26 06:14:08 PM PDT 24
Finished Jun 26 06:14:35 PM PDT 24
Peak memory 199916 kb
Host smart-e12728f9-d2c6-448b-8843-5b2b86d4c1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157416288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3157416288
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.3077492725
Short name T195
Test name
Test status
Simulation time 7875470766 ps
CPU time 11.75 seconds
Started Jun 26 06:14:11 PM PDT 24
Finished Jun 26 06:14:23 PM PDT 24
Peak memory 199972 kb
Host smart-5f2ca7b3-0bb9-4e7a-acd4-3e557d910ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077492725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3077492725
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.3290911442
Short name T325
Test name
Test status
Simulation time 16709659590 ps
CPU time 21.32 seconds
Started Jun 26 06:14:06 PM PDT 24
Finished Jun 26 06:14:29 PM PDT 24
Peak memory 199984 kb
Host smart-fe7918eb-d8d4-49b2-b223-4620f6f109a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290911442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3290911442
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.2136348511
Short name T370
Test name
Test status
Simulation time 9221883760 ps
CPU time 13.82 seconds
Started Jun 26 06:14:10 PM PDT 24
Finished Jun 26 06:14:25 PM PDT 24
Peak memory 200024 kb
Host smart-dec013ba-999d-4054-9928-9f62a343f603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136348511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.2136348511
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1643575250
Short name T840
Test name
Test status
Simulation time 17720187349 ps
CPU time 18.57 seconds
Started Jun 26 06:14:11 PM PDT 24
Finished Jun 26 06:14:30 PM PDT 24
Peak memory 199924 kb
Host smart-f0523b6e-a3c8-4d99-b64d-d5e56ea95cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643575250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1643575250
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.2541925294
Short name T977
Test name
Test status
Simulation time 148562243674 ps
CPU time 125.22 seconds
Started Jun 26 06:14:11 PM PDT 24
Finished Jun 26 06:16:17 PM PDT 24
Peak memory 200172 kb
Host smart-15c9300f-d38a-4af4-a4cb-1cf0c5437d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541925294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2541925294
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.1455684939
Short name T753
Test name
Test status
Simulation time 205753282979 ps
CPU time 132.77 seconds
Started Jun 26 06:14:09 PM PDT 24
Finished Jun 26 06:16:23 PM PDT 24
Peak memory 200000 kb
Host smart-8bddec03-60a5-449a-a632-845c565ae5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455684939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1455684939
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.3473211781
Short name T431
Test name
Test status
Simulation time 122612086992 ps
CPU time 94.17 seconds
Started Jun 26 06:14:07 PM PDT 24
Finished Jun 26 06:15:42 PM PDT 24
Peak memory 199800 kb
Host smart-b0577d5a-80ca-4cdd-b0f0-e5a20dd34e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473211781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.3473211781
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.959087862
Short name T954
Test name
Test status
Simulation time 72532758 ps
CPU time 0.6 seconds
Started Jun 26 06:11:24 PM PDT 24
Finished Jun 26 06:11:26 PM PDT 24
Peak memory 195272 kb
Host smart-35794647-04c2-4d17-b820-1fc5f6778f26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959087862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.959087862
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.4189517472
Short name T259
Test name
Test status
Simulation time 233878069497 ps
CPU time 273.48 seconds
Started Jun 26 06:11:22 PM PDT 24
Finished Jun 26 06:15:58 PM PDT 24
Peak memory 200020 kb
Host smart-e74eafaa-9cc8-48d6-9989-f96b8f6bd64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189517472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.4189517472
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.1616866046
Short name T658
Test name
Test status
Simulation time 44196278969 ps
CPU time 27.23 seconds
Started Jun 26 06:11:23 PM PDT 24
Finished Jun 26 06:11:52 PM PDT 24
Peak memory 199944 kb
Host smart-9d3419b1-d154-4161-bf56-4940ee9f7382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616866046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.1616866046
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.3523594797
Short name T1008
Test name
Test status
Simulation time 104567889277 ps
CPU time 49.21 seconds
Started Jun 26 06:11:24 PM PDT 24
Finished Jun 26 06:12:15 PM PDT 24
Peak memory 199872 kb
Host smart-cc42223b-618f-4aa6-9cf7-43b0e8fc0e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523594797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.3523594797
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.4171726199
Short name T434
Test name
Test status
Simulation time 65244681427 ps
CPU time 93.63 seconds
Started Jun 26 06:11:22 PM PDT 24
Finished Jun 26 06:12:57 PM PDT 24
Peak memory 199664 kb
Host smart-19a70942-3a12-45c7-a349-678ac1bfbe34
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171726199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.4171726199
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.4149130530
Short name T374
Test name
Test status
Simulation time 75069809232 ps
CPU time 435.69 seconds
Started Jun 26 06:11:21 PM PDT 24
Finished Jun 26 06:18:38 PM PDT 24
Peak memory 199980 kb
Host smart-abba5699-549a-4d2e-817f-23f891349acf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4149130530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.4149130530
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.2380532111
Short name T978
Test name
Test status
Simulation time 7720479834 ps
CPU time 13.79 seconds
Started Jun 26 06:11:21 PM PDT 24
Finished Jun 26 06:11:36 PM PDT 24
Peak memory 198764 kb
Host smart-79165487-5b7f-4785-9b57-1cc396ae3c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380532111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2380532111
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_perf.562997373
Short name T784
Test name
Test status
Simulation time 8712655764 ps
CPU time 402.77 seconds
Started Jun 26 06:11:22 PM PDT 24
Finished Jun 26 06:18:07 PM PDT 24
Peak memory 199972 kb
Host smart-bc5ebb90-3bbb-4f55-b7b6-c9521336fc3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=562997373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.562997373
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.4109652296
Short name T800
Test name
Test status
Simulation time 2747796486 ps
CPU time 18.53 seconds
Started Jun 26 06:11:22 PM PDT 24
Finished Jun 26 06:11:42 PM PDT 24
Peak memory 198044 kb
Host smart-527e9cc1-5ed5-4882-84bf-27e8fb796592
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4109652296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.4109652296
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.2734741035
Short name T767
Test name
Test status
Simulation time 26761748951 ps
CPU time 16.23 seconds
Started Jun 26 06:11:25 PM PDT 24
Finished Jun 26 06:11:43 PM PDT 24
Peak memory 199932 kb
Host smart-78333d66-35c1-40ce-8978-e3169b28c27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734741035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2734741035
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.1809549027
Short name T21
Test name
Test status
Simulation time 6621417952 ps
CPU time 10.64 seconds
Started Jun 26 06:11:27 PM PDT 24
Finished Jun 26 06:11:39 PM PDT 24
Peak memory 196644 kb
Host smart-4347a5ef-a67a-4192-abc9-6b12aa4815c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809549027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1809549027
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.1685880565
Short name T1000
Test name
Test status
Simulation time 5959765324 ps
CPU time 11.53 seconds
Started Jun 26 06:11:26 PM PDT 24
Finished Jun 26 06:11:39 PM PDT 24
Peak memory 199772 kb
Host smart-e288f82b-a264-41d5-ba98-cd1d796a2106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685880565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.1685880565
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.2829512455
Short name T546
Test name
Test status
Simulation time 97477622059 ps
CPU time 139.85 seconds
Started Jun 26 06:11:21 PM PDT 24
Finished Jun 26 06:13:42 PM PDT 24
Peak memory 199768 kb
Host smart-12989bbd-3b2a-4157-9cc1-44ab91995c75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829512455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.2829512455
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.2459757666
Short name T1018
Test name
Test status
Simulation time 6780826472 ps
CPU time 33.56 seconds
Started Jun 26 06:11:25 PM PDT 24
Finished Jun 26 06:12:01 PM PDT 24
Peak memory 199860 kb
Host smart-3fa675cd-b07c-40d7-ab3f-c62bd6b304ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459757666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2459757666
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.2995120299
Short name T237
Test name
Test status
Simulation time 72296027005 ps
CPU time 30.79 seconds
Started Jun 26 06:11:24 PM PDT 24
Finished Jun 26 06:11:57 PM PDT 24
Peak memory 199848 kb
Host smart-88817bd8-b179-467b-9714-3dae915821db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995120299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.2995120299
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.3694268680
Short name T1095
Test name
Test status
Simulation time 85896222547 ps
CPU time 16.18 seconds
Started Jun 26 06:14:10 PM PDT 24
Finished Jun 26 06:14:27 PM PDT 24
Peak memory 200000 kb
Host smart-129e3546-f37b-48ee-8c62-f78c90dc3248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694268680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3694268680
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.3828842325
Short name T1046
Test name
Test status
Simulation time 45807065675 ps
CPU time 72.44 seconds
Started Jun 26 06:14:09 PM PDT 24
Finished Jun 26 06:15:22 PM PDT 24
Peak memory 199916 kb
Host smart-e1c666b0-3474-4f1b-9caa-14924846c363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828842325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3828842325
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.2901489418
Short name T676
Test name
Test status
Simulation time 58920154286 ps
CPU time 26.2 seconds
Started Jun 26 06:14:11 PM PDT 24
Finished Jun 26 06:14:38 PM PDT 24
Peak memory 199824 kb
Host smart-26f97b61-957c-40ad-a6fc-24965752af18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901489418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2901489418
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.2879380343
Short name T855
Test name
Test status
Simulation time 11425985841 ps
CPU time 5.54 seconds
Started Jun 26 06:14:07 PM PDT 24
Finished Jun 26 06:14:14 PM PDT 24
Peak memory 199940 kb
Host smart-727f9bcc-ac48-4b01-b6c2-7c42262091f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879380343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2879380343
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.640480613
Short name T520
Test name
Test status
Simulation time 35087565507 ps
CPU time 50.6 seconds
Started Jun 26 06:14:15 PM PDT 24
Finished Jun 26 06:15:06 PM PDT 24
Peak memory 199896 kb
Host smart-ec8046b0-efb8-428f-8a17-9c5ef66b2152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640480613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.640480613
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.1018327287
Short name T102
Test name
Test status
Simulation time 83008384823 ps
CPU time 118.06 seconds
Started Jun 26 06:14:18 PM PDT 24
Finished Jun 26 06:16:17 PM PDT 24
Peak memory 199844 kb
Host smart-409182c2-0117-400a-acd0-b18ce0bf0c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018327287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1018327287
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.541937351
Short name T946
Test name
Test status
Simulation time 35602405509 ps
CPU time 47.1 seconds
Started Jun 26 06:14:16 PM PDT 24
Finished Jun 26 06:15:03 PM PDT 24
Peak memory 199808 kb
Host smart-76c2be17-49c3-4689-808d-df50725c9c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541937351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.541937351
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.185380295
Short name T172
Test name
Test status
Simulation time 34067904106 ps
CPU time 45.2 seconds
Started Jun 26 06:14:16 PM PDT 24
Finished Jun 26 06:15:02 PM PDT 24
Peak memory 200020 kb
Host smart-30db8ba4-6c7c-4297-b21b-7f19aba1f09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185380295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.185380295
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.1018308879
Short name T836
Test name
Test status
Simulation time 30502546882 ps
CPU time 98.48 seconds
Started Jun 26 06:14:18 PM PDT 24
Finished Jun 26 06:15:57 PM PDT 24
Peak memory 199952 kb
Host smart-23d5eae2-f36e-4d65-bb81-d26fc8b746d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018308879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1018308879
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.1904885049
Short name T327
Test name
Test status
Simulation time 11221262 ps
CPU time 0.56 seconds
Started Jun 26 06:11:29 PM PDT 24
Finished Jun 26 06:11:30 PM PDT 24
Peak memory 194760 kb
Host smart-40f6016d-6b07-455a-8648-280778644704
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904885049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1904885049
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.2777119173
Short name T40
Test name
Test status
Simulation time 281496242166 ps
CPU time 42.56 seconds
Started Jun 26 06:11:34 PM PDT 24
Finished Jun 26 06:12:18 PM PDT 24
Peak memory 199944 kb
Host smart-4e4f6c88-d115-4750-9c76-e791713a0ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777119173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2777119173
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.1185805292
Short name T394
Test name
Test status
Simulation time 154262271041 ps
CPU time 60.95 seconds
Started Jun 26 06:11:33 PM PDT 24
Finished Jun 26 06:12:35 PM PDT 24
Peak memory 200012 kb
Host smart-c2877f38-e24b-4955-a2a3-eb8eeb6e21c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185805292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.1185805292
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.2194316291
Short name T1056
Test name
Test status
Simulation time 16920697596 ps
CPU time 33.66 seconds
Started Jun 26 06:11:27 PM PDT 24
Finished Jun 26 06:12:02 PM PDT 24
Peak memory 199940 kb
Host smart-c87e36a7-3b84-447c-8d6b-24ae79e7752c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194316291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.2194316291
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.2645315422
Short name T107
Test name
Test status
Simulation time 60995438734 ps
CPU time 107.35 seconds
Started Jun 26 06:11:31 PM PDT 24
Finished Jun 26 06:13:19 PM PDT 24
Peak memory 199932 kb
Host smart-c721482c-e479-4f70-8cf1-84942d6d4c9c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645315422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2645315422
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.3295418964
Short name T523
Test name
Test status
Simulation time 86018673868 ps
CPU time 617.74 seconds
Started Jun 26 06:11:27 PM PDT 24
Finished Jun 26 06:21:46 PM PDT 24
Peak memory 199900 kb
Host smart-f1af1da0-b20e-4ac2-9995-3805b02f93d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3295418964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.3295418964
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.1283098396
Short name T936
Test name
Test status
Simulation time 6288331693 ps
CPU time 13.37 seconds
Started Jun 26 06:11:26 PM PDT 24
Finished Jun 26 06:11:41 PM PDT 24
Peak memory 199788 kb
Host smart-f1d8d2cb-2629-4ea9-808d-890fa904ff0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283098396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1283098396
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_perf.2594843401
Short name T642
Test name
Test status
Simulation time 8377649426 ps
CPU time 125.86 seconds
Started Jun 26 06:11:31 PM PDT 24
Finished Jun 26 06:13:38 PM PDT 24
Peak memory 199936 kb
Host smart-5b59e92d-d2c1-4271-b153-67823c453c29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2594843401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2594843401
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.1234632462
Short name T331
Test name
Test status
Simulation time 7057613580 ps
CPU time 5.49 seconds
Started Jun 26 06:11:30 PM PDT 24
Finished Jun 26 06:11:36 PM PDT 24
Peak memory 199300 kb
Host smart-b34ee3f5-db15-466a-b203-890ac9b3a1ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1234632462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1234632462
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.3547743171
Short name T479
Test name
Test status
Simulation time 7238015926 ps
CPU time 12.91 seconds
Started Jun 26 06:11:31 PM PDT 24
Finished Jun 26 06:11:45 PM PDT 24
Peak memory 199984 kb
Host smart-ae4a3b7a-e94a-401d-9cd3-81c852343c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547743171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.3547743171
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.3039364140
Short name T407
Test name
Test status
Simulation time 1525480552 ps
CPU time 1.21 seconds
Started Jun 26 06:11:34 PM PDT 24
Finished Jun 26 06:11:36 PM PDT 24
Peak memory 195576 kb
Host smart-05bb71c1-46da-4cbd-9d95-78399aea92d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039364140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3039364140
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.1345981160
Short name T350
Test name
Test status
Simulation time 111107711 ps
CPU time 1 seconds
Started Jun 26 06:11:28 PM PDT 24
Finished Jun 26 06:11:30 PM PDT 24
Peak memory 197932 kb
Host smart-b8e4dbea-c1b3-4381-a451-aabc4cbd35d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345981160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1345981160
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.3423394608
Short name T1061
Test name
Test status
Simulation time 240126538818 ps
CPU time 374.11 seconds
Started Jun 26 06:11:32 PM PDT 24
Finished Jun 26 06:17:48 PM PDT 24
Peak memory 209936 kb
Host smart-cf2c4676-3ae3-4dcf-b372-6fe2ef122f7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423394608 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.3423394608
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.3294862187
Short name T1090
Test name
Test status
Simulation time 963888944 ps
CPU time 1.88 seconds
Started Jun 26 06:11:31 PM PDT 24
Finished Jun 26 06:11:34 PM PDT 24
Peak memory 199832 kb
Host smart-5280e11f-79f4-4420-8d1d-9ae0215dbaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294862187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3294862187
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.3361145016
Short name T888
Test name
Test status
Simulation time 67073132569 ps
CPU time 27.48 seconds
Started Jun 26 06:11:28 PM PDT 24
Finished Jun 26 06:11:57 PM PDT 24
Peak memory 199908 kb
Host smart-45423834-1155-4353-8f6f-81c517d3cdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361145016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3361145016
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1290929108
Short name T680
Test name
Test status
Simulation time 211507729684 ps
CPU time 137.17 seconds
Started Jun 26 06:14:15 PM PDT 24
Finished Jun 26 06:16:32 PM PDT 24
Peak memory 199936 kb
Host smart-50e6340a-08c1-48d5-a984-d9698ff8f40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290929108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1290929108
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.656250788
Short name T741
Test name
Test status
Simulation time 40399450733 ps
CPU time 15.83 seconds
Started Jun 26 06:14:18 PM PDT 24
Finished Jun 26 06:14:35 PM PDT 24
Peak memory 199924 kb
Host smart-3d0f15ac-b6aa-4fea-814b-7a24af1ad63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656250788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.656250788
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.2608768656
Short name T185
Test name
Test status
Simulation time 86115045379 ps
CPU time 160.48 seconds
Started Jun 26 06:14:17 PM PDT 24
Finished Jun 26 06:16:58 PM PDT 24
Peak memory 199988 kb
Host smart-a3bcc9ce-9291-4c63-8a61-59bd7ce2d79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608768656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.2608768656
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.2581734407
Short name T257
Test name
Test status
Simulation time 66164311607 ps
CPU time 24.54 seconds
Started Jun 26 06:14:17 PM PDT 24
Finished Jun 26 06:14:42 PM PDT 24
Peak memory 199876 kb
Host smart-271241a0-b5e0-4fee-aae7-aa4f0aca14e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581734407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2581734407
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.4157679485
Short name T1059
Test name
Test status
Simulation time 49267652425 ps
CPU time 40.36 seconds
Started Jun 26 06:14:18 PM PDT 24
Finished Jun 26 06:14:59 PM PDT 24
Peak memory 200004 kb
Host smart-5c280132-e3e2-49b5-9d9a-35d6747e9d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157679485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.4157679485
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.3741856170
Short name T869
Test name
Test status
Simulation time 31295562968 ps
CPU time 32.44 seconds
Started Jun 26 06:14:18 PM PDT 24
Finished Jun 26 06:14:51 PM PDT 24
Peak memory 199808 kb
Host smart-8fc928f3-cee2-415b-b1ed-a8d0c60d6d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741856170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.3741856170
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.2163640175
Short name T201
Test name
Test status
Simulation time 88559658009 ps
CPU time 187.88 seconds
Started Jun 26 06:14:18 PM PDT 24
Finished Jun 26 06:17:26 PM PDT 24
Peak memory 199944 kb
Host smart-dfcd05ab-95e8-401c-8b98-d9f1c7ab1265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163640175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.2163640175
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.4065868780
Short name T104
Test name
Test status
Simulation time 18716673036 ps
CPU time 37.61 seconds
Started Jun 26 06:14:17 PM PDT 24
Finished Jun 26 06:14:56 PM PDT 24
Peak memory 199992 kb
Host smart-82721e9d-4644-4765-a7c9-771e9701a540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065868780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.4065868780
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.618239933
Short name T285
Test name
Test status
Simulation time 24936048011 ps
CPU time 37.19 seconds
Started Jun 26 06:14:18 PM PDT 24
Finished Jun 26 06:14:56 PM PDT 24
Peak memory 199976 kb
Host smart-cb8550ef-b64e-41cf-a035-99eeae9ec4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618239933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.618239933
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3686538842
Short name T212
Test name
Test status
Simulation time 108853980553 ps
CPU time 46.43 seconds
Started Jun 26 06:14:15 PM PDT 24
Finished Jun 26 06:15:03 PM PDT 24
Peak memory 200012 kb
Host smart-95298272-79d3-41a6-bacf-781ad49b5eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686538842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3686538842
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.832751154
Short name T591
Test name
Test status
Simulation time 13859805 ps
CPU time 0.57 seconds
Started Jun 26 06:10:21 PM PDT 24
Finished Jun 26 06:10:24 PM PDT 24
Peak memory 194272 kb
Host smart-b76fcffb-74b4-4b69-811f-e9f68b2dc48f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832751154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.832751154
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.845199153
Short name T278
Test name
Test status
Simulation time 187214546836 ps
CPU time 173.94 seconds
Started Jun 26 06:10:16 PM PDT 24
Finished Jun 26 06:13:13 PM PDT 24
Peak memory 199992 kb
Host smart-1d0e06ad-f6bb-420f-af43-f5da1dc9e772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845199153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.845199153
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.2802381367
Short name T652
Test name
Test status
Simulation time 222349646538 ps
CPU time 36.83 seconds
Started Jun 26 06:10:19 PM PDT 24
Finished Jun 26 06:10:58 PM PDT 24
Peak memory 199992 kb
Host smart-0caaa395-763e-4f9c-93c4-27da9499a9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802381367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2802381367
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.1737550421
Short name T914
Test name
Test status
Simulation time 58467516088 ps
CPU time 29.14 seconds
Started Jun 26 06:10:20 PM PDT 24
Finished Jun 26 06:10:52 PM PDT 24
Peak memory 200196 kb
Host smart-28af0727-611e-464b-aa0a-40e5e7c35382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737550421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1737550421
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.357914397
Short name T561
Test name
Test status
Simulation time 454747600380 ps
CPU time 339.13 seconds
Started Jun 26 06:10:13 PM PDT 24
Finished Jun 26 06:15:56 PM PDT 24
Peak memory 199024 kb
Host smart-b895dcaf-38d7-4f33-9d72-7cb4c136ec34
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357914397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.357914397
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.3484847537
Short name T636
Test name
Test status
Simulation time 72875670353 ps
CPU time 309.81 seconds
Started Jun 26 06:10:11 PM PDT 24
Finished Jun 26 06:15:24 PM PDT 24
Peak memory 199900 kb
Host smart-0fb6ac11-61fb-4283-be17-0a089dec87bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3484847537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3484847537
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.341249967
Short name T713
Test name
Test status
Simulation time 2690336018 ps
CPU time 6.05 seconds
Started Jun 26 06:10:14 PM PDT 24
Finished Jun 26 06:10:23 PM PDT 24
Peak memory 198508 kb
Host smart-02809757-9397-472b-802c-f06a8af56067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341249967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.341249967
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_perf.163629287
Short name T412
Test name
Test status
Simulation time 22970382978 ps
CPU time 1141.58 seconds
Started Jun 26 06:10:13 PM PDT 24
Finished Jun 26 06:29:18 PM PDT 24
Peak memory 200212 kb
Host smart-6096d7a5-1a39-4483-861f-0b1c3a5d01b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=163629287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.163629287
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.1700580630
Short name T373
Test name
Test status
Simulation time 5464648670 ps
CPU time 46.52 seconds
Started Jun 26 06:10:15 PM PDT 24
Finished Jun 26 06:11:05 PM PDT 24
Peak memory 199196 kb
Host smart-797b2c15-0887-4d21-8cd8-5983f8737f52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1700580630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1700580630
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.1047840123
Short name T296
Test name
Test status
Simulation time 54477360439 ps
CPU time 80.38 seconds
Started Jun 26 06:10:09 PM PDT 24
Finished Jun 26 06:11:33 PM PDT 24
Peak memory 199824 kb
Host smart-312e3cf4-9a8d-42a6-9287-2dacdcfe5139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047840123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1047840123
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.2536887623
Short name T393
Test name
Test status
Simulation time 1665808058 ps
CPU time 3.2 seconds
Started Jun 26 06:10:09 PM PDT 24
Finished Jun 26 06:10:16 PM PDT 24
Peak memory 195520 kb
Host smart-3bdbc9f7-4b06-498f-b213-b41e7d1b449b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536887623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2536887623
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.3492311854
Short name T82
Test name
Test status
Simulation time 33325854 ps
CPU time 0.77 seconds
Started Jun 26 06:10:26 PM PDT 24
Finished Jun 26 06:10:30 PM PDT 24
Peak memory 218248 kb
Host smart-1020c688-f33b-4029-9d71-78984d170c1a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492311854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3492311854
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.3873681522
Short name T348
Test name
Test status
Simulation time 5905257405 ps
CPU time 22.16 seconds
Started Jun 26 06:10:23 PM PDT 24
Finished Jun 26 06:10:49 PM PDT 24
Peak memory 199888 kb
Host smart-f1f41698-89d8-409a-885e-551f81ffc50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873681522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.3873681522
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.1286857357
Short name T438
Test name
Test status
Simulation time 649887409 ps
CPU time 1.95 seconds
Started Jun 26 06:10:13 PM PDT 24
Finished Jun 26 06:10:18 PM PDT 24
Peak memory 198496 kb
Host smart-210ccf93-21ce-4d6e-84ae-059f730269bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286857357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1286857357
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.3086410775
Short name T1057
Test name
Test status
Simulation time 46058294007 ps
CPU time 79.14 seconds
Started Jun 26 06:10:11 PM PDT 24
Finished Jun 26 06:11:34 PM PDT 24
Peak memory 199968 kb
Host smart-375a6fb7-dd4b-4610-b38b-408d52ae9977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086410775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3086410775
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.107003019
Short name T991
Test name
Test status
Simulation time 37236967 ps
CPU time 0.57 seconds
Started Jun 26 06:11:38 PM PDT 24
Finished Jun 26 06:11:40 PM PDT 24
Peak memory 194740 kb
Host smart-8336d4e8-52fc-4fa2-a07e-f55a166e9628
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107003019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.107003019
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.2558808704
Short name T136
Test name
Test status
Simulation time 177933470152 ps
CPU time 47.65 seconds
Started Jun 26 06:11:31 PM PDT 24
Finished Jun 26 06:12:19 PM PDT 24
Peak memory 199984 kb
Host smart-495dcb36-6044-4ff2-bf6a-f2002648c556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558808704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.2558808704
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.3622737024
Short name T444
Test name
Test status
Simulation time 22830359618 ps
CPU time 37.47 seconds
Started Jun 26 06:11:32 PM PDT 24
Finished Jun 26 06:12:11 PM PDT 24
Peak memory 200024 kb
Host smart-41a069e3-8681-4ce6-bf75-7707b3b3c768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622737024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3622737024
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3372074436
Short name T168
Test name
Test status
Simulation time 13796662224 ps
CPU time 25.71 seconds
Started Jun 26 06:11:31 PM PDT 24
Finished Jun 26 06:11:58 PM PDT 24
Peak memory 199864 kb
Host smart-8dd8a800-f073-4faf-913f-06b838b745ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372074436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3372074436
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.290936977
Short name T661
Test name
Test status
Simulation time 12311745447 ps
CPU time 6.27 seconds
Started Jun 26 06:11:38 PM PDT 24
Finished Jun 26 06:11:45 PM PDT 24
Peak memory 199612 kb
Host smart-3ed08b26-c734-47e3-be5c-a2c99b2b808d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290936977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.290936977
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.1066859888
Short name T1053
Test name
Test status
Simulation time 111673742824 ps
CPU time 327.66 seconds
Started Jun 26 06:11:39 PM PDT 24
Finished Jun 26 06:17:08 PM PDT 24
Peak memory 199952 kb
Host smart-ea349cdd-8a09-41ce-8d56-d6c4f5765e63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1066859888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1066859888
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1937150869
Short name T953
Test name
Test status
Simulation time 10566694535 ps
CPU time 6.86 seconds
Started Jun 26 06:11:37 PM PDT 24
Finished Jun 26 06:11:45 PM PDT 24
Peak memory 198684 kb
Host smart-e8a65800-1e20-49b8-ab0a-e2101ef985e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937150869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1937150869
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.2869711715
Short name T620
Test name
Test status
Simulation time 77754951781 ps
CPU time 34.36 seconds
Started Jun 26 06:11:41 PM PDT 24
Finished Jun 26 06:12:16 PM PDT 24
Peak memory 199780 kb
Host smart-cd38cb20-501c-4582-a4d1-4d4db41183c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869711715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2869711715
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.2158512766
Short name T305
Test name
Test status
Simulation time 12493751799 ps
CPU time 128.69 seconds
Started Jun 26 06:11:36 PM PDT 24
Finished Jun 26 06:13:46 PM PDT 24
Peak memory 199836 kb
Host smart-7e7b9da0-bc34-4d7c-852c-72988fab9a1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2158512766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2158512766
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.285417477
Short name T844
Test name
Test status
Simulation time 4284063657 ps
CPU time 30.19 seconds
Started Jun 26 06:11:30 PM PDT 24
Finished Jun 26 06:12:01 PM PDT 24
Peak memory 198712 kb
Host smart-a8296108-7486-4967-9539-a62f370f5568
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=285417477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.285417477
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.2178283197
Short name T131
Test name
Test status
Simulation time 81493496753 ps
CPU time 128.21 seconds
Started Jun 26 06:11:35 PM PDT 24
Finished Jun 26 06:13:44 PM PDT 24
Peak memory 199936 kb
Host smart-a00fc724-46e0-4162-b7c9-3ce3acbdb547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178283197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.2178283197
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.847176922
Short name T368
Test name
Test status
Simulation time 36635702818 ps
CPU time 47 seconds
Started Jun 26 06:11:37 PM PDT 24
Finished Jun 26 06:12:25 PM PDT 24
Peak memory 196436 kb
Host smart-18767f72-1d8e-45e5-aa1d-70a8f9adb218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847176922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.847176922
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.2283916487
Short name T646
Test name
Test status
Simulation time 5689104082 ps
CPU time 6.56 seconds
Started Jun 26 06:11:32 PM PDT 24
Finished Jun 26 06:11:40 PM PDT 24
Peak memory 199948 kb
Host smart-2b838fe0-caf8-4b7b-887a-1ee32ed68fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283916487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.2283916487
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.983823037
Short name T1070
Test name
Test status
Simulation time 1108866932589 ps
CPU time 228.7 seconds
Started Jun 26 06:11:39 PM PDT 24
Finished Jun 26 06:15:30 PM PDT 24
Peak memory 199976 kb
Host smart-1af4747d-19d6-4175-9d26-c09d180fbe58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983823037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.983823037
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.1744026841
Short name T91
Test name
Test status
Simulation time 59207679404 ps
CPU time 266.33 seconds
Started Jun 26 06:11:40 PM PDT 24
Finished Jun 26 06:16:08 PM PDT 24
Peak memory 208340 kb
Host smart-6c9c8ea3-9f8b-4a78-b8e1-df91e580dd45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744026841 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.1744026841
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.759191417
Short name T381
Test name
Test status
Simulation time 6744231371 ps
CPU time 12.05 seconds
Started Jun 26 06:11:36 PM PDT 24
Finished Jun 26 06:11:49 PM PDT 24
Peak memory 199416 kb
Host smart-947d2cea-8769-4b8e-92af-6d9c9fc16c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759191417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.759191417
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.2541410091
Short name T807
Test name
Test status
Simulation time 7399912520 ps
CPU time 13.21 seconds
Started Jun 26 06:11:27 PM PDT 24
Finished Jun 26 06:11:42 PM PDT 24
Peak memory 200028 kb
Host smart-af7a4920-3839-4411-9368-456b99b982cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541410091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2541410091
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1449106425
Short name T618
Test name
Test status
Simulation time 12171367 ps
CPU time 0.57 seconds
Started Jun 26 06:11:36 PM PDT 24
Finished Jun 26 06:11:37 PM PDT 24
Peak memory 195320 kb
Host smart-a5028322-0776-4800-8d6d-2737b3edc745
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449106425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1449106425
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.3814644707
Short name T84
Test name
Test status
Simulation time 32492895042 ps
CPU time 62.04 seconds
Started Jun 26 06:11:35 PM PDT 24
Finished Jun 26 06:12:37 PM PDT 24
Peak memory 199956 kb
Host smart-34f6c5b3-0eb6-4f3f-b56b-13a4b17a546a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814644707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.3814644707
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3907731572
Short name T146
Test name
Test status
Simulation time 88901920517 ps
CPU time 40.9 seconds
Started Jun 26 06:11:42 PM PDT 24
Finished Jun 26 06:12:24 PM PDT 24
Peak memory 199980 kb
Host smart-d4f991b2-9596-43e4-b199-9332d28bb860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907731572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3907731572
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.1431555837
Short name T484
Test name
Test status
Simulation time 114470692701 ps
CPU time 195.56 seconds
Started Jun 26 06:11:39 PM PDT 24
Finished Jun 26 06:14:56 PM PDT 24
Peak memory 199956 kb
Host smart-96ea690c-18f0-444d-b3a1-757b8e6a6032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431555837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1431555837
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.3171412448
Short name T410
Test name
Test status
Simulation time 31029481114 ps
CPU time 6.92 seconds
Started Jun 26 06:11:40 PM PDT 24
Finished Jun 26 06:11:48 PM PDT 24
Peak memory 198980 kb
Host smart-bfe8867b-dcc8-4da5-88ff-ec2dba8ab6bb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171412448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3171412448
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.3840635498
Short name T935
Test name
Test status
Simulation time 89628423455 ps
CPU time 548.15 seconds
Started Jun 26 06:11:36 PM PDT 24
Finished Jun 26 06:20:45 PM PDT 24
Peak memory 199900 kb
Host smart-f106b17e-aba1-4a6e-92f7-8a733c90d937
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3840635498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.3840635498
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.2041005764
Short name T630
Test name
Test status
Simulation time 4723525599 ps
CPU time 7.25 seconds
Started Jun 26 06:11:40 PM PDT 24
Finished Jun 26 06:11:49 PM PDT 24
Peak memory 198776 kb
Host smart-4c032abe-0f27-4d6a-9bbe-2355d01fad4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041005764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2041005764
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.2126571262
Short name T692
Test name
Test status
Simulation time 5411526906 ps
CPU time 8.99 seconds
Started Jun 26 06:11:40 PM PDT 24
Finished Jun 26 06:11:50 PM PDT 24
Peak memory 200060 kb
Host smart-d72e92c9-186c-4fb6-8d5d-5c78502c5e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126571262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.2126571262
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.2456004056
Short name T744
Test name
Test status
Simulation time 10175386960 ps
CPU time 615.23 seconds
Started Jun 26 06:11:39 PM PDT 24
Finished Jun 26 06:21:56 PM PDT 24
Peak memory 199904 kb
Host smart-049c581a-9c64-436b-a39d-9abda7a8c1b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2456004056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2456004056
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.2092254967
Short name T398
Test name
Test status
Simulation time 3051193631 ps
CPU time 21.78 seconds
Started Jun 26 06:11:37 PM PDT 24
Finished Jun 26 06:12:00 PM PDT 24
Peak memory 198636 kb
Host smart-1ff260d8-c6be-47e3-8245-b503641bd800
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2092254967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2092254967
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.3913887557
Short name T161
Test name
Test status
Simulation time 22750622852 ps
CPU time 40.51 seconds
Started Jun 26 06:11:39 PM PDT 24
Finished Jun 26 06:12:21 PM PDT 24
Peak memory 199912 kb
Host smart-043584a1-aecc-4926-96d7-19d0069d7903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913887557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3913887557
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.2466680671
Short name T880
Test name
Test status
Simulation time 4680380208 ps
CPU time 1.84 seconds
Started Jun 26 06:11:41 PM PDT 24
Finished Jun 26 06:11:44 PM PDT 24
Peak memory 196500 kb
Host smart-68dc3dc7-3b29-41bc-8f8f-97cbe094e669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466680671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.2466680671
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.1373491206
Short name T1042
Test name
Test status
Simulation time 466185702 ps
CPU time 2.7 seconds
Started Jun 26 06:11:39 PM PDT 24
Finished Jun 26 06:11:44 PM PDT 24
Peak memory 198724 kb
Host smart-55a1572b-0867-4b94-a21b-382958a82928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373491206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1373491206
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.2039459232
Short name T99
Test name
Test status
Simulation time 10617125464 ps
CPU time 27.62 seconds
Started Jun 26 06:11:38 PM PDT 24
Finished Jun 26 06:12:07 PM PDT 24
Peak memory 199892 kb
Host smart-14a1534b-1db2-428e-86a6-383dd708c1be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039459232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2039459232
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.3537200836
Short name T586
Test name
Test status
Simulation time 13764294525 ps
CPU time 16.31 seconds
Started Jun 26 06:11:42 PM PDT 24
Finished Jun 26 06:12:00 PM PDT 24
Peak memory 199984 kb
Host smart-1eac1020-b5af-4b23-8b93-a5618f161aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537200836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3537200836
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.3159248376
Short name T842
Test name
Test status
Simulation time 71989764527 ps
CPU time 26.34 seconds
Started Jun 26 06:11:37 PM PDT 24
Finished Jun 26 06:12:05 PM PDT 24
Peak memory 199688 kb
Host smart-72343d31-63c0-4ca2-a116-ef78f50becee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159248376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3159248376
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.26559811
Short name T24
Test name
Test status
Simulation time 13222599 ps
CPU time 0.57 seconds
Started Jun 26 06:11:48 PM PDT 24
Finished Jun 26 06:11:49 PM PDT 24
Peak memory 195256 kb
Host smart-3afaf3af-cb52-4943-a340-2da728067785
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26559811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.26559811
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.745812886
Short name T288
Test name
Test status
Simulation time 19001003708 ps
CPU time 28.01 seconds
Started Jun 26 06:11:37 PM PDT 24
Finished Jun 26 06:12:06 PM PDT 24
Peak memory 199924 kb
Host smart-a0d48027-bd7a-41a6-82bf-55875c29f5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745812886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.745812886
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.1490312029
Short name T787
Test name
Test status
Simulation time 64977109189 ps
CPU time 25.93 seconds
Started Jun 26 06:11:36 PM PDT 24
Finished Jun 26 06:12:03 PM PDT 24
Peak memory 200004 kb
Host smart-b577fd0a-e656-4c6c-98e4-acb1cbe5a6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490312029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.1490312029
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.3057311003
Short name T85
Test name
Test status
Simulation time 156634094829 ps
CPU time 173.47 seconds
Started Jun 26 06:11:36 PM PDT 24
Finished Jun 26 06:14:30 PM PDT 24
Peak memory 199956 kb
Host smart-6e4b5a1d-4bd8-4ced-882e-071b00bfddff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057311003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3057311003
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.3669853508
Short name T395
Test name
Test status
Simulation time 67047177962 ps
CPU time 102.75 seconds
Started Jun 26 06:11:38 PM PDT 24
Finished Jun 26 06:13:22 PM PDT 24
Peak memory 196876 kb
Host smart-5745ba4e-c0a7-4bbc-861f-02b5ea1c89ec
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669853508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3669853508
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.2196710218
Short name T493
Test name
Test status
Simulation time 98816562954 ps
CPU time 825.69 seconds
Started Jun 26 06:12:17 PM PDT 24
Finished Jun 26 06:26:04 PM PDT 24
Peak memory 199936 kb
Host smart-2e14cd0d-0c11-4e55-8580-1212a33e8dfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2196710218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2196710218
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.1809694111
Short name T358
Test name
Test status
Simulation time 8059474448 ps
CPU time 7 seconds
Started Jun 26 06:11:38 PM PDT 24
Finished Jun 26 06:11:46 PM PDT 24
Peak memory 199836 kb
Host smart-507e6bd2-83e5-485a-89d1-af4b0d94d49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809694111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.1809694111
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_perf.3442574008
Short name T456
Test name
Test status
Simulation time 7861511773 ps
CPU time 177.82 seconds
Started Jun 26 06:11:42 PM PDT 24
Finished Jun 26 06:14:41 PM PDT 24
Peak memory 199948 kb
Host smart-65be1b09-e4a3-4d8d-9ce0-f97307c40dd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3442574008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.3442574008
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.2720257786
Short name T728
Test name
Test status
Simulation time 4124049104 ps
CPU time 7.79 seconds
Started Jun 26 06:11:37 PM PDT 24
Finished Jun 26 06:11:46 PM PDT 24
Peak memory 198548 kb
Host smart-d5a3ca6c-1cfb-48aa-b6b0-767e9e797e7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2720257786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2720257786
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.2351978606
Short name T589
Test name
Test status
Simulation time 38080945633 ps
CPU time 61.17 seconds
Started Jun 26 06:11:39 PM PDT 24
Finished Jun 26 06:12:41 PM PDT 24
Peak memory 199840 kb
Host smart-8f65ed6b-2fb2-49a9-a7fc-309515e53fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351978606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.2351978606
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.1758774449
Short name T870
Test name
Test status
Simulation time 3746023207 ps
CPU time 3.4 seconds
Started Jun 26 06:11:38 PM PDT 24
Finished Jun 26 06:11:43 PM PDT 24
Peak memory 196432 kb
Host smart-44ab6eb0-4e99-443d-9e17-6e2a7e48413a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758774449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1758774449
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.261368511
Short name T436
Test name
Test status
Simulation time 5544464017 ps
CPU time 12.97 seconds
Started Jun 26 06:11:37 PM PDT 24
Finished Jun 26 06:11:51 PM PDT 24
Peak memory 199220 kb
Host smart-14810c19-2cef-4e08-ac47-a2984aa63516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261368511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.261368511
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.3733511035
Short name T721
Test name
Test status
Simulation time 285846488372 ps
CPU time 1776.3 seconds
Started Jun 26 06:11:39 PM PDT 24
Finished Jun 26 06:41:17 PM PDT 24
Peak memory 199944 kb
Host smart-e61394ae-2ffe-4bab-a98e-c6376dba85f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733511035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.3733511035
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1961063373
Short name T635
Test name
Test status
Simulation time 16277567324 ps
CPU time 206.93 seconds
Started Jun 26 06:11:38 PM PDT 24
Finished Jun 26 06:15:06 PM PDT 24
Peak memory 208256 kb
Host smart-3f9fa090-01c8-465b-9c29-5b0e34dc080e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961063373 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1961063373
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3246986155
Short name T876
Test name
Test status
Simulation time 766279368 ps
CPU time 2.56 seconds
Started Jun 26 06:11:39 PM PDT 24
Finished Jun 26 06:11:43 PM PDT 24
Peak memory 198408 kb
Host smart-8ba620df-31bf-4c21-bdcc-2e7cc6639e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246986155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3246986155
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.1661166352
Short name T503
Test name
Test status
Simulation time 9807137708 ps
CPU time 17.99 seconds
Started Jun 26 06:11:35 PM PDT 24
Finished Jun 26 06:11:54 PM PDT 24
Peak memory 199968 kb
Host smart-09111a71-c27f-488f-9518-9ba8d505c785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661166352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1661166352
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.3819567073
Short name T359
Test name
Test status
Simulation time 47327224 ps
CPU time 0.57 seconds
Started Jun 26 06:11:45 PM PDT 24
Finished Jun 26 06:11:46 PM PDT 24
Peak memory 195564 kb
Host smart-91d87840-372d-43ef-af25-193d984b2b2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819567073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.3819567073
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.3796999818
Short name T156
Test name
Test status
Simulation time 23882282928 ps
CPU time 29.61 seconds
Started Jun 26 06:11:48 PM PDT 24
Finished Jun 26 06:12:18 PM PDT 24
Peak memory 200172 kb
Host smart-a7733da3-46a3-4283-bcfe-89749e04cdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796999818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.3796999818
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.1239649035
Short name T737
Test name
Test status
Simulation time 232246275032 ps
CPU time 93.18 seconds
Started Jun 26 06:11:42 PM PDT 24
Finished Jun 26 06:13:17 PM PDT 24
Peak memory 199984 kb
Host smart-123d5dfc-ded9-46c5-a664-a6aee7e15467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239649035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1239649035
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.4067778130
Short name T1078
Test name
Test status
Simulation time 20011147603 ps
CPU time 32.07 seconds
Started Jun 26 06:11:49 PM PDT 24
Finished Jun 26 06:12:22 PM PDT 24
Peak memory 199904 kb
Host smart-a6da05dc-27bb-494d-9824-6fc4b5f3fdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067778130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.4067778130
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.1233720427
Short name T481
Test name
Test status
Simulation time 13401734749 ps
CPU time 18.01 seconds
Started Jun 26 06:11:50 PM PDT 24
Finished Jun 26 06:12:09 PM PDT 24
Peak memory 196932 kb
Host smart-64d81400-7790-49f0-8ba1-9c45c4ebd552
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233720427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.1233720427
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.170285738
Short name T463
Test name
Test status
Simulation time 88781542220 ps
CPU time 126.03 seconds
Started Jun 26 06:11:46 PM PDT 24
Finished Jun 26 06:13:53 PM PDT 24
Peak memory 199968 kb
Host smart-b84ae52a-6a37-4533-b5fb-300818c9d2c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=170285738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.170285738
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.4116349707
Short name T311
Test name
Test status
Simulation time 2830094498 ps
CPU time 4.04 seconds
Started Jun 26 06:11:47 PM PDT 24
Finished Jun 26 06:11:52 PM PDT 24
Peak memory 198704 kb
Host smart-547905a8-6cb7-49ac-b0fa-3218200a184b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116349707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.4116349707
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_perf.3813880650
Short name T674
Test name
Test status
Simulation time 7198923812 ps
CPU time 220.74 seconds
Started Jun 26 06:11:45 PM PDT 24
Finished Jun 26 06:15:27 PM PDT 24
Peak memory 199900 kb
Host smart-5934eb89-a448-45c5-914d-f1194ff9f149
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3813880650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3813880650
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.1630969246
Short name T896
Test name
Test status
Simulation time 3677873817 ps
CPU time 7.72 seconds
Started Jun 26 06:11:45 PM PDT 24
Finished Jun 26 06:11:54 PM PDT 24
Peak memory 199188 kb
Host smart-b7205642-9169-4785-9f60-2382b3ae0fb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1630969246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1630969246
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.517540013
Short name T777
Test name
Test status
Simulation time 110049487169 ps
CPU time 67.82 seconds
Started Jun 26 06:11:48 PM PDT 24
Finished Jun 26 06:12:56 PM PDT 24
Peak memory 199856 kb
Host smart-1805ae3e-967f-49ea-8d3d-7b8da01e132a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517540013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.517540013
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.3945616564
Short name T887
Test name
Test status
Simulation time 48362062085 ps
CPU time 16.14 seconds
Started Jun 26 06:11:44 PM PDT 24
Finished Jun 26 06:12:01 PM PDT 24
Peak memory 195776 kb
Host smart-86e449c6-d060-47ff-b591-e64dd18a187d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945616564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.3945616564
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1373390938
Short name T83
Test name
Test status
Simulation time 477172044 ps
CPU time 2.32 seconds
Started Jun 26 06:11:47 PM PDT 24
Finished Jun 26 06:11:50 PM PDT 24
Peak memory 199748 kb
Host smart-e37064dc-ced5-477c-8c63-174897d0423f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373390938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1373390938
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.569994143
Short name T1001
Test name
Test status
Simulation time 101532765831 ps
CPU time 706.03 seconds
Started Jun 26 06:11:45 PM PDT 24
Finished Jun 26 06:23:32 PM PDT 24
Peak memory 199980 kb
Host smart-830b87dd-fd28-4c3a-8c3d-81593098d3be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569994143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.569994143
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.3716647687
Short name T20
Test name
Test status
Simulation time 44460398367 ps
CPU time 271.65 seconds
Started Jun 26 06:11:45 PM PDT 24
Finished Jun 26 06:16:17 PM PDT 24
Peak memory 215752 kb
Host smart-89461375-f215-49d8-8072-51a08beb9a51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716647687 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3716647687
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.1285014141
Short name T782
Test name
Test status
Simulation time 1172208335 ps
CPU time 3.87 seconds
Started Jun 26 06:11:45 PM PDT 24
Finished Jun 26 06:11:50 PM PDT 24
Peak memory 198740 kb
Host smart-b4780c72-dd75-4783-9d0f-c169cf6a1568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285014141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1285014141
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.744370551
Short name T693
Test name
Test status
Simulation time 1502194105 ps
CPU time 2.53 seconds
Started Jun 26 06:11:42 PM PDT 24
Finished Jun 26 06:11:45 PM PDT 24
Peak memory 197472 kb
Host smart-18ffe820-5299-4840-9980-2159652e0987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744370551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.744370551
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.2761578569
Short name T809
Test name
Test status
Simulation time 19658209 ps
CPU time 0.55 seconds
Started Jun 26 06:11:46 PM PDT 24
Finished Jun 26 06:11:48 PM PDT 24
Peak memory 194728 kb
Host smart-9a748763-0b90-4300-b553-f8fdab6dd959
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761578569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2761578569
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.1612274929
Short name T133
Test name
Test status
Simulation time 116248663037 ps
CPU time 184.05 seconds
Started Jun 26 06:11:48 PM PDT 24
Finished Jun 26 06:14:53 PM PDT 24
Peak memory 199928 kb
Host smart-0106e194-120b-4953-9b52-f07fa7429f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612274929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1612274929
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.2845016105
Short name T113
Test name
Test status
Simulation time 34474338390 ps
CPU time 62.88 seconds
Started Jun 26 06:11:46 PM PDT 24
Finished Jun 26 06:12:50 PM PDT 24
Peak memory 199980 kb
Host smart-9b52d12f-ced9-4a35-8605-5daf8575e852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845016105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2845016105
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.3439862633
Short name T562
Test name
Test status
Simulation time 509836053274 ps
CPU time 43.33 seconds
Started Jun 26 06:11:49 PM PDT 24
Finished Jun 26 06:12:33 PM PDT 24
Peak memory 199908 kb
Host smart-36524597-5656-470b-9cca-afb37577ddf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439862633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3439862633
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3234725530
Short name T343
Test name
Test status
Simulation time 30444947040 ps
CPU time 12.09 seconds
Started Jun 26 06:11:48 PM PDT 24
Finished Jun 26 06:12:01 PM PDT 24
Peak memory 198340 kb
Host smart-5c1c4f93-b1b5-489e-ad3f-23685d385b69
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234725530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3234725530
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.3190475501
Short name T621
Test name
Test status
Simulation time 47547603250 ps
CPU time 436.72 seconds
Started Jun 26 06:11:44 PM PDT 24
Finished Jun 26 06:19:02 PM PDT 24
Peak memory 199916 kb
Host smart-5fe742fc-b030-4b33-8efb-b7f14e1f3cf6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3190475501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3190475501
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3289098613
Short name T579
Test name
Test status
Simulation time 5412913275 ps
CPU time 3.2 seconds
Started Jun 26 06:11:47 PM PDT 24
Finished Jun 26 06:11:51 PM PDT 24
Peak memory 199852 kb
Host smart-92800556-d93a-4228-b963-339af231fe54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289098613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3289098613
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_perf.3925207378
Short name T457
Test name
Test status
Simulation time 45935123358 ps
CPU time 407.5 seconds
Started Jun 26 06:11:44 PM PDT 24
Finished Jun 26 06:18:32 PM PDT 24
Peak memory 199900 kb
Host smart-fd0f55c6-b8fc-4cce-81e1-82cfc8177d14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3925207378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3925207378
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.2084550673
Short name T329
Test name
Test status
Simulation time 7093821432 ps
CPU time 63.5 seconds
Started Jun 26 06:11:46 PM PDT 24
Finished Jun 26 06:12:51 PM PDT 24
Peak memory 198156 kb
Host smart-5f474a27-290f-442b-99d0-a0b03b828244
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2084550673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2084550673
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.3606754174
Short name T234
Test name
Test status
Simulation time 73663376663 ps
CPU time 32.99 seconds
Started Jun 26 06:11:46 PM PDT 24
Finished Jun 26 06:12:20 PM PDT 24
Peak memory 199912 kb
Host smart-4f454062-388c-46a8-91c0-4c1108794e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606754174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.3606754174
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.2617359011
Short name T746
Test name
Test status
Simulation time 1302248921 ps
CPU time 1.68 seconds
Started Jun 26 06:11:44 PM PDT 24
Finished Jun 26 06:11:47 PM PDT 24
Peak memory 195440 kb
Host smart-173f5aec-21c9-4b4e-ae1c-91a7cae4100c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617359011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.2617359011
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3769703068
Short name T1067
Test name
Test status
Simulation time 554205750 ps
CPU time 2.6 seconds
Started Jun 26 06:11:49 PM PDT 24
Finished Jun 26 06:11:52 PM PDT 24
Peak memory 198324 kb
Host smart-c5ec328d-31b9-4d0c-8f1a-ff37e8ab9fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769703068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3769703068
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.625592762
Short name T825
Test name
Test status
Simulation time 407416784103 ps
CPU time 634.55 seconds
Started Jun 26 06:11:50 PM PDT 24
Finished Jun 26 06:22:26 PM PDT 24
Peak memory 215644 kb
Host smart-9368a664-70f0-478b-b8d0-c3da35236f2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625592762 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.625592762
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1876302168
Short name T386
Test name
Test status
Simulation time 3285310054 ps
CPU time 2.71 seconds
Started Jun 26 06:11:44 PM PDT 24
Finished Jun 26 06:11:48 PM PDT 24
Peak memory 199208 kb
Host smart-38efabe7-355d-4507-bbda-f9cfe2d84cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876302168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1876302168
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.647946782
Short name T645
Test name
Test status
Simulation time 34782829192 ps
CPU time 13.07 seconds
Started Jun 26 06:11:48 PM PDT 24
Finished Jun 26 06:12:02 PM PDT 24
Peak memory 200148 kb
Host smart-a9411304-03de-4ef0-8b4b-536481cd3a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647946782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.647946782
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.775970982
Short name T907
Test name
Test status
Simulation time 11017459 ps
CPU time 0.54 seconds
Started Jun 26 06:11:54 PM PDT 24
Finished Jun 26 06:11:56 PM PDT 24
Peak memory 194488 kb
Host smart-f8201106-a7c1-4a21-b268-b564d857a0a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775970982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.775970982
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.2424006782
Short name T757
Test name
Test status
Simulation time 36701305031 ps
CPU time 51.57 seconds
Started Jun 26 06:11:46 PM PDT 24
Finished Jun 26 06:12:39 PM PDT 24
Peak memory 200004 kb
Host smart-82665326-d9fe-4a4b-8ad8-ed5cc199dc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424006782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2424006782
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.3953690816
Short name T1047
Test name
Test status
Simulation time 41161724310 ps
CPU time 44.33 seconds
Started Jun 26 06:11:51 PM PDT 24
Finished Jun 26 06:12:37 PM PDT 24
Peak memory 199904 kb
Host smart-b2c9dd3c-6321-4579-a1e4-e0cd7a663064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953690816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3953690816
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.363607298
Short name T695
Test name
Test status
Simulation time 98581959779 ps
CPU time 60.35 seconds
Started Jun 26 06:11:57 PM PDT 24
Finished Jun 26 06:12:58 PM PDT 24
Peak memory 199904 kb
Host smart-470e5bd9-abc3-4895-9487-d9203f6c1405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363607298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.363607298
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.2385640310
Short name T837
Test name
Test status
Simulation time 14742445726 ps
CPU time 12.73 seconds
Started Jun 26 06:11:51 PM PDT 24
Finished Jun 26 06:12:05 PM PDT 24
Peak memory 199848 kb
Host smart-db95e37f-2ce0-4988-aaeb-e16a3a3e6d89
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385640310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2385640310
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_loopback.978667425
Short name T1071
Test name
Test status
Simulation time 6104431731 ps
CPU time 4.86 seconds
Started Jun 26 06:11:53 PM PDT 24
Finished Jun 26 06:11:59 PM PDT 24
Peak memory 198084 kb
Host smart-5251778f-d1b1-4339-a04e-8cfc1277b800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978667425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.978667425
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_perf.572305947
Short name T356
Test name
Test status
Simulation time 15777060896 ps
CPU time 255.15 seconds
Started Jun 26 06:11:53 PM PDT 24
Finished Jun 26 06:16:10 PM PDT 24
Peak memory 199980 kb
Host smart-5e8ca22c-3c25-4a83-897e-288cac4ee120
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=572305947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.572305947
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3951908163
Short name T338
Test name
Test status
Simulation time 5527085141 ps
CPU time 45.05 seconds
Started Jun 26 06:11:56 PM PDT 24
Finished Jun 26 06:12:42 PM PDT 24
Peak memory 199328 kb
Host smart-b7a9d195-6e9d-405d-bab2-65254ebfd40b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3951908163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3951908163
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.1780425612
Short name T778
Test name
Test status
Simulation time 155424608531 ps
CPU time 100.82 seconds
Started Jun 26 06:11:55 PM PDT 24
Finished Jun 26 06:13:37 PM PDT 24
Peak memory 199964 kb
Host smart-afeed0b5-e3a5-4f59-9617-5b1b6f64fbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780425612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1780425612
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.955993581
Short name T811
Test name
Test status
Simulation time 36122931615 ps
CPU time 13.61 seconds
Started Jun 26 06:11:53 PM PDT 24
Finished Jun 26 06:12:09 PM PDT 24
Peak memory 196164 kb
Host smart-73da0a9c-1efe-4e35-be1b-850116493c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955993581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.955993581
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2567003942
Short name T437
Test name
Test status
Simulation time 5755916126 ps
CPU time 15.42 seconds
Started Jun 26 06:11:46 PM PDT 24
Finished Jun 26 06:12:02 PM PDT 24
Peak memory 199868 kb
Host smart-85e1de72-174d-4897-8810-cd894a54e02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567003942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2567003942
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2599586120
Short name T498
Test name
Test status
Simulation time 80243775278 ps
CPU time 444.29 seconds
Started Jun 26 06:11:57 PM PDT 24
Finished Jun 26 06:19:22 PM PDT 24
Peak memory 216436 kb
Host smart-22f99413-9e19-49a3-aa64-19641033fa99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599586120 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2599586120
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.3889454482
Short name T477
Test name
Test status
Simulation time 2398104171 ps
CPU time 1.76 seconds
Started Jun 26 06:11:49 PM PDT 24
Finished Jun 26 06:11:52 PM PDT 24
Peak memory 197084 kb
Host smart-9ea1b10b-7bfe-420c-af5a-bc97f7680374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889454482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3889454482
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.1827754166
Short name T323
Test name
Test status
Simulation time 17384099889 ps
CPU time 27.23 seconds
Started Jun 26 06:11:50 PM PDT 24
Finished Jun 26 06:12:19 PM PDT 24
Peak memory 199952 kb
Host smart-eec2372f-c265-4b8d-9ffb-f08b716dfd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827754166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.1827754166
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.561759225
Short name T1019
Test name
Test status
Simulation time 37039811 ps
CPU time 0.57 seconds
Started Jun 26 06:11:50 PM PDT 24
Finished Jun 26 06:11:51 PM PDT 24
Peak memory 195232 kb
Host smart-3e041e35-d3bf-4178-9fdd-207a06d7eff0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561759225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.561759225
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2975928126
Short name T1026
Test name
Test status
Simulation time 137896844678 ps
CPU time 152.93 seconds
Started Jun 26 06:11:54 PM PDT 24
Finished Jun 26 06:14:28 PM PDT 24
Peak memory 199944 kb
Host smart-92766ff5-1598-4bb4-9eda-c6b52041ce6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975928126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2975928126
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.885593622
Short name T704
Test name
Test status
Simulation time 35969773429 ps
CPU time 16.08 seconds
Started Jun 26 06:11:51 PM PDT 24
Finished Jun 26 06:12:08 PM PDT 24
Peak memory 199844 kb
Host smart-ba53f943-c9f3-4bb5-be70-fe13751c9dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885593622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.885593622
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.3842761985
Short name T504
Test name
Test status
Simulation time 273230865962 ps
CPU time 90.68 seconds
Started Jun 26 06:11:52 PM PDT 24
Finished Jun 26 06:13:24 PM PDT 24
Peak memory 199956 kb
Host smart-e292527d-5e5e-49ac-871e-f45aa91a69ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842761985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3842761985
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.4062382269
Short name T511
Test name
Test status
Simulation time 52991120275 ps
CPU time 65.76 seconds
Started Jun 26 06:11:51 PM PDT 24
Finished Jun 26 06:12:58 PM PDT 24
Peak memory 199936 kb
Host smart-ef847965-f9d8-412f-af0d-4280bb22a5d3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062382269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.4062382269
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.1162767264
Short name T843
Test name
Test status
Simulation time 62832988820 ps
CPU time 171.4 seconds
Started Jun 26 06:11:57 PM PDT 24
Finished Jun 26 06:14:50 PM PDT 24
Peak memory 199856 kb
Host smart-1e9d00e8-a591-4ad0-94cd-8aa4045de7b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1162767264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1162767264
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.2884849026
Short name T409
Test name
Test status
Simulation time 16477765187 ps
CPU time 45.2 seconds
Started Jun 26 06:11:48 PM PDT 24
Finished Jun 26 06:12:34 PM PDT 24
Peak memory 199900 kb
Host smart-57daefbe-04b1-4078-ad37-e90f2b5db30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884849026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2884849026
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_perf.1312132755
Short name T1038
Test name
Test status
Simulation time 12960427501 ps
CPU time 720.99 seconds
Started Jun 26 06:11:53 PM PDT 24
Finished Jun 26 06:23:56 PM PDT 24
Peak memory 199968 kb
Host smart-b7e0cac7-f485-4c42-aea7-51eca649443b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1312132755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1312132755
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3108854877
Short name T411
Test name
Test status
Simulation time 1274501635 ps
CPU time 2.5 seconds
Started Jun 26 06:11:52 PM PDT 24
Finished Jun 26 06:11:56 PM PDT 24
Peak memory 198196 kb
Host smart-12f21e93-6e05-43f8-ac69-19a678848732
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3108854877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3108854877
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.962956510
Short name T302
Test name
Test status
Simulation time 98343963512 ps
CPU time 73.14 seconds
Started Jun 26 06:11:53 PM PDT 24
Finished Jun 26 06:13:07 PM PDT 24
Peak memory 199916 kb
Host smart-e3d3dcdc-31eb-4ce0-ac96-187165306221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962956510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.962956510
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.3926451404
Short name T384
Test name
Test status
Simulation time 4738770935 ps
CPU time 4.1 seconds
Started Jun 26 06:11:56 PM PDT 24
Finished Jun 26 06:12:01 PM PDT 24
Peak memory 196224 kb
Host smart-90e62a1d-e43f-47c7-9714-788d4c3d4bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926451404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3926451404
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1905808906
Short name T717
Test name
Test status
Simulation time 148313855 ps
CPU time 0.76 seconds
Started Jun 26 06:11:54 PM PDT 24
Finished Jun 26 06:11:56 PM PDT 24
Peak memory 196864 kb
Host smart-fb4c228e-ca5d-4bcb-81cc-50975cdac7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905808906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1905808906
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.2602368996
Short name T51
Test name
Test status
Simulation time 88362040499 ps
CPU time 539.99 seconds
Started Jun 26 06:11:53 PM PDT 24
Finished Jun 26 06:20:54 PM PDT 24
Peak memory 216584 kb
Host smart-e8858eb2-9bf0-416b-a5a7-1c35571f4d11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602368996 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.2602368996
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.577679342
Short name T263
Test name
Test status
Simulation time 588230554 ps
CPU time 2.42 seconds
Started Jun 26 06:11:52 PM PDT 24
Finished Jun 26 06:11:56 PM PDT 24
Peak memory 198740 kb
Host smart-f5bb5fc5-f7f4-4e11-ba9b-436d8da15496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577679342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.577679342
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.2079332034
Short name T792
Test name
Test status
Simulation time 13672409418 ps
CPU time 23.95 seconds
Started Jun 26 06:11:52 PM PDT 24
Finished Jun 26 06:12:17 PM PDT 24
Peak memory 199972 kb
Host smart-7b5d1d08-7aa6-4ab1-ad28-31b0125c798a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079332034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.2079332034
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.2334120404
Short name T610
Test name
Test status
Simulation time 17101247 ps
CPU time 0.54 seconds
Started Jun 26 06:11:59 PM PDT 24
Finished Jun 26 06:12:02 PM PDT 24
Peak memory 195300 kb
Host smart-71535038-0c7d-488d-a2ae-ec32709040b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334120404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.2334120404
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.3842276340
Short name T596
Test name
Test status
Simulation time 177638439008 ps
CPU time 93.38 seconds
Started Jun 26 06:11:51 PM PDT 24
Finished Jun 26 06:13:25 PM PDT 24
Peak memory 199992 kb
Host smart-1e009e6a-7d16-4484-ab63-59a771043043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842276340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3842276340
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.1241874102
Short name T797
Test name
Test status
Simulation time 17574473314 ps
CPU time 29.71 seconds
Started Jun 26 06:11:52 PM PDT 24
Finished Jun 26 06:12:23 PM PDT 24
Peak memory 199980 kb
Host smart-320a6ba7-da63-47b1-a074-41d1445b5271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241874102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1241874102
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.148728407
Short name T521
Test name
Test status
Simulation time 88389282879 ps
CPU time 33.02 seconds
Started Jun 26 06:11:52 PM PDT 24
Finished Jun 26 06:12:26 PM PDT 24
Peak memory 199904 kb
Host smart-8451d363-94df-41b3-9312-fcc93f71d3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148728407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.148728407
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.1753743648
Short name T18
Test name
Test status
Simulation time 42096192956 ps
CPU time 60.35 seconds
Started Jun 26 06:11:53 PM PDT 24
Finished Jun 26 06:12:56 PM PDT 24
Peak memory 199952 kb
Host smart-e41e70d0-4f1d-47d7-be4f-b23a787b8b9f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753743648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1753743648
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.84192859
Short name T426
Test name
Test status
Simulation time 103596778160 ps
CPU time 499.37 seconds
Started Jun 26 06:12:00 PM PDT 24
Finished Jun 26 06:20:21 PM PDT 24
Peak memory 199924 kb
Host smart-9db4c952-345a-4e1b-8b7e-ea3a697c4d7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=84192859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.84192859
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.3850617226
Short name T553
Test name
Test status
Simulation time 4832220507 ps
CPU time 3.09 seconds
Started Jun 26 06:11:56 PM PDT 24
Finished Jun 26 06:12:00 PM PDT 24
Peak memory 198516 kb
Host smart-d937760a-49e5-41b5-8d15-f5dcd2e7fa4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850617226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.3850617226
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_perf.194994937
Short name T88
Test name
Test status
Simulation time 19945294995 ps
CPU time 1156.95 seconds
Started Jun 26 06:11:59 PM PDT 24
Finished Jun 26 06:31:18 PM PDT 24
Peak memory 199960 kb
Host smart-198fe91a-f516-4c0e-a3f1-8c32df6ba9ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=194994937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.194994937
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.1738599600
Short name T920
Test name
Test status
Simulation time 1600841949 ps
CPU time 1.88 seconds
Started Jun 26 06:11:51 PM PDT 24
Finished Jun 26 06:11:54 PM PDT 24
Peak memory 199060 kb
Host smart-22abad6a-b44b-4df8-8931-6946d817bc62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1738599600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.1738599600
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1248007650
Short name T873
Test name
Test status
Simulation time 19956405232 ps
CPU time 13.51 seconds
Started Jun 26 06:12:01 PM PDT 24
Finished Jun 26 06:12:16 PM PDT 24
Peak memory 199944 kb
Host smart-c31ff856-4f29-4d9a-9ca6-2c5e5f206f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248007650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1248007650
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.1604308829
Short name T392
Test name
Test status
Simulation time 1940125878 ps
CPU time 2.23 seconds
Started Jun 26 06:12:03 PM PDT 24
Finished Jun 26 06:12:06 PM PDT 24
Peak memory 195340 kb
Host smart-ca228268-c261-4602-ac5c-cf123200e7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604308829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1604308829
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3719764933
Short name T464
Test name
Test status
Simulation time 293647196 ps
CPU time 1.59 seconds
Started Jun 26 06:11:53 PM PDT 24
Finished Jun 26 06:11:57 PM PDT 24
Peak memory 199252 kb
Host smart-05d9726a-4664-4cfc-a21f-34e4949339e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719764933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3719764933
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.907326145
Short name T97
Test name
Test status
Simulation time 231552056355 ps
CPU time 1038.32 seconds
Started Jun 26 06:12:00 PM PDT 24
Finished Jun 26 06:29:21 PM PDT 24
Peak memory 199900 kb
Host smart-f8f6c568-ad06-421d-b428-e8636f682b6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907326145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.907326145
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1800502036
Short name T858
Test name
Test status
Simulation time 7309497820 ps
CPU time 9.85 seconds
Started Jun 26 06:11:58 PM PDT 24
Finished Jun 26 06:12:10 PM PDT 24
Peak memory 199884 kb
Host smart-78be5d89-ec0f-44a6-87f6-f98b6daf107a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800502036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1800502036
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.1171526523
Short name T832
Test name
Test status
Simulation time 42954046392 ps
CPU time 65.84 seconds
Started Jun 26 06:11:53 PM PDT 24
Finished Jun 26 06:13:01 PM PDT 24
Peak memory 199948 kb
Host smart-e9af7b61-118c-44e3-a996-91dffb2a94aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171526523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.1171526523
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.2132707003
Short name T419
Test name
Test status
Simulation time 37028581 ps
CPU time 0.54 seconds
Started Jun 26 06:11:57 PM PDT 24
Finished Jun 26 06:11:59 PM PDT 24
Peak memory 195616 kb
Host smart-574463f0-5eb5-4eb2-a288-f17f1c291f31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132707003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2132707003
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.1665791145
Short name T528
Test name
Test status
Simulation time 149176161506 ps
CPU time 391.47 seconds
Started Jun 26 06:11:57 PM PDT 24
Finished Jun 26 06:18:30 PM PDT 24
Peak memory 199820 kb
Host smart-92de563d-cb10-4c63-b433-155b5e858c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665791145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.1665791145
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.2030328341
Short name T998
Test name
Test status
Simulation time 53776580219 ps
CPU time 77.47 seconds
Started Jun 26 06:11:59 PM PDT 24
Finished Jun 26 06:13:18 PM PDT 24
Peak memory 199984 kb
Host smart-aaded6e8-3586-44f4-a4b2-2b1798f0a513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030328341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2030328341
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3467712649
Short name T141
Test name
Test status
Simulation time 202204121326 ps
CPU time 337.03 seconds
Started Jun 26 06:11:59 PM PDT 24
Finished Jun 26 06:17:38 PM PDT 24
Peak memory 200004 kb
Host smart-2a4f0eca-94c8-4850-a658-f462eadc51ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467712649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3467712649
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3758713576
Short name T834
Test name
Test status
Simulation time 38588918348 ps
CPU time 55.15 seconds
Started Jun 26 06:12:01 PM PDT 24
Finished Jun 26 06:12:57 PM PDT 24
Peak memory 199620 kb
Host smart-9fb5b089-4aa7-4ea9-8284-7a8165a77e48
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758713576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3758713576
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.4258499936
Short name T416
Test name
Test status
Simulation time 71614211722 ps
CPU time 170.22 seconds
Started Jun 26 06:12:07 PM PDT 24
Finished Jun 26 06:14:59 PM PDT 24
Peak memory 200120 kb
Host smart-b259a614-9f0d-4cd0-b160-5542a91b43e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4258499936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.4258499936
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.3568735149
Short name T1049
Test name
Test status
Simulation time 434181025 ps
CPU time 1.54 seconds
Started Jun 26 06:12:07 PM PDT 24
Finished Jun 26 06:12:10 PM PDT 24
Peak memory 197112 kb
Host smart-237eae4f-4754-4611-9e24-aa44094f0e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568735149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3568735149
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.133789545
Short name T904
Test name
Test status
Simulation time 41004804991 ps
CPU time 13.05 seconds
Started Jun 26 06:11:57 PM PDT 24
Finished Jun 26 06:12:11 PM PDT 24
Peak memory 199948 kb
Host smart-d8cb0005-ce3a-476f-ae97-f7c66dbf2885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133789545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.133789545
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.3557998486
Short name T1097
Test name
Test status
Simulation time 23145167389 ps
CPU time 78.61 seconds
Started Jun 26 06:12:00 PM PDT 24
Finished Jun 26 06:13:20 PM PDT 24
Peak memory 199884 kb
Host smart-7512d299-ed81-4ddd-9811-b99a23f439f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3557998486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.3557998486
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.1720850796
Short name T375
Test name
Test status
Simulation time 6972932087 ps
CPU time 16.46 seconds
Started Jun 26 06:11:58 PM PDT 24
Finished Jun 26 06:12:16 PM PDT 24
Peak memory 199256 kb
Host smart-39e3ffb1-67ca-4ad1-b2a7-1e2f0396ef9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1720850796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1720850796
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2493518360
Short name T460
Test name
Test status
Simulation time 106443445824 ps
CPU time 50.52 seconds
Started Jun 26 06:12:08 PM PDT 24
Finished Jun 26 06:12:59 PM PDT 24
Peak memory 200140 kb
Host smart-588a7999-0261-4c20-a1b1-0ca59fcfbbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493518360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2493518360
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.194893561
Short name T495
Test name
Test status
Simulation time 3642854817 ps
CPU time 5.72 seconds
Started Jun 26 06:11:56 PM PDT 24
Finished Jun 26 06:12:02 PM PDT 24
Peak memory 196456 kb
Host smart-dd4e8bdf-07bf-4009-94d0-aaecae40e92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194893561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.194893561
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.4166163946
Short name T422
Test name
Test status
Simulation time 497428588 ps
CPU time 2.6 seconds
Started Jun 26 06:12:00 PM PDT 24
Finished Jun 26 06:12:04 PM PDT 24
Peak memory 199360 kb
Host smart-65558745-5647-4263-910c-2f2fdabefd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166163946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.4166163946
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.2745393794
Short name T627
Test name
Test status
Simulation time 274241454289 ps
CPU time 434.7 seconds
Started Jun 26 06:11:59 PM PDT 24
Finished Jun 26 06:19:16 PM PDT 24
Peak memory 199896 kb
Host smart-079f48f1-5952-4e2d-833c-6dfa6c7df4ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745393794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2745393794
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.4106215485
Short name T734
Test name
Test status
Simulation time 206917464422 ps
CPU time 757.36 seconds
Started Jun 26 06:12:07 PM PDT 24
Finished Jun 26 06:24:46 PM PDT 24
Peak memory 215972 kb
Host smart-e53b33d6-310e-4a30-97a3-c3a40d54cd6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106215485 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.4106215485
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.1851015768
Short name T401
Test name
Test status
Simulation time 2081028920 ps
CPU time 1.82 seconds
Started Jun 26 06:11:58 PM PDT 24
Finished Jun 26 06:12:01 PM PDT 24
Peak memory 198220 kb
Host smart-0e33a43c-dabe-4fbd-8cc6-14461313cd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851015768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1851015768
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.3864520043
Short name T608
Test name
Test status
Simulation time 108423699280 ps
CPU time 42.77 seconds
Started Jun 26 06:12:07 PM PDT 24
Finished Jun 26 06:12:51 PM PDT 24
Peak memory 200200 kb
Host smart-423bb863-8eef-48b8-9ad6-018d3b7c8f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864520043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3864520043
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.2475570503
Short name T555
Test name
Test status
Simulation time 39457984 ps
CPU time 0.57 seconds
Started Jun 26 06:12:08 PM PDT 24
Finished Jun 26 06:12:10 PM PDT 24
Peak memory 195580 kb
Host smart-5aaf0157-9cdd-4a30-bc98-2b5df6a694ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475570503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2475570503
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.324980641
Short name T376
Test name
Test status
Simulation time 59393803159 ps
CPU time 31.8 seconds
Started Jun 26 06:11:58 PM PDT 24
Finished Jun 26 06:12:31 PM PDT 24
Peak memory 199992 kb
Host smart-dd4d4144-682e-4a84-8761-3385cf64767a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324980641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.324980641
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.2218995079
Short name T747
Test name
Test status
Simulation time 112024295552 ps
CPU time 27.17 seconds
Started Jun 26 06:11:58 PM PDT 24
Finished Jun 26 06:12:27 PM PDT 24
Peak memory 199904 kb
Host smart-d65a00bd-c9b5-407b-b685-67769876c74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218995079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2218995079
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.3018330301
Short name T988
Test name
Test status
Simulation time 17560411091 ps
CPU time 34.2 seconds
Started Jun 26 06:12:04 PM PDT 24
Finished Jun 26 06:12:39 PM PDT 24
Peak memory 199992 kb
Host smart-20f3e58e-2161-4362-85eb-bddf583cfbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018330301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3018330301
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.378714231
Short name T780
Test name
Test status
Simulation time 38086967141 ps
CPU time 60.78 seconds
Started Jun 26 06:12:04 PM PDT 24
Finished Jun 26 06:13:05 PM PDT 24
Peak memory 199980 kb
Host smart-538bb532-38fb-487f-b32d-7a54334dc091
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378714231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.378714231
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.2923615099
Short name T339
Test name
Test status
Simulation time 148963482059 ps
CPU time 619.03 seconds
Started Jun 26 06:12:08 PM PDT 24
Finished Jun 26 06:22:28 PM PDT 24
Peak memory 199976 kb
Host smart-e0f16b9f-7bcc-4c8d-8a3a-7c6571a2f579
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2923615099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2923615099
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.3225636866
Short name T986
Test name
Test status
Simulation time 3271701982 ps
CPU time 5.39 seconds
Started Jun 26 06:12:07 PM PDT 24
Finished Jun 26 06:12:13 PM PDT 24
Peak memory 196168 kb
Host smart-e1ad69ef-8330-47e7-b9b7-8438b3010388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225636866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.3225636866
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_perf.1900276202
Short name T672
Test name
Test status
Simulation time 25803101564 ps
CPU time 202.37 seconds
Started Jun 26 06:12:08 PM PDT 24
Finished Jun 26 06:15:31 PM PDT 24
Peak memory 199888 kb
Host smart-3f30e58b-d810-4fcb-aecb-a65b9afa39e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1900276202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1900276202
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.2738816694
Short name T821
Test name
Test status
Simulation time 7869028200 ps
CPU time 19.48 seconds
Started Jun 26 06:12:07 PM PDT 24
Finished Jun 26 06:12:28 PM PDT 24
Peak memory 198832 kb
Host smart-2ff44be3-bf5d-4932-bcb9-f537ed759ad4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2738816694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2738816694
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.1023765086
Short name T114
Test name
Test status
Simulation time 17223278181 ps
CPU time 14.34 seconds
Started Jun 26 06:12:03 PM PDT 24
Finished Jun 26 06:12:18 PM PDT 24
Peak memory 199900 kb
Host smart-31fd708d-efa3-4010-84d5-85f4e2c951fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023765086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1023765086
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.212373061
Short name T515
Test name
Test status
Simulation time 3237075968 ps
CPU time 5.98 seconds
Started Jun 26 06:12:04 PM PDT 24
Finished Jun 26 06:12:11 PM PDT 24
Peak memory 196432 kb
Host smart-53956ea8-cd6f-4a97-968b-59c995966c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212373061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.212373061
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.3581216070
Short name T333
Test name
Test status
Simulation time 301970939 ps
CPU time 1.37 seconds
Started Jun 26 06:11:59 PM PDT 24
Finished Jun 26 06:12:02 PM PDT 24
Peak memory 198304 kb
Host smart-67d6122b-410c-4457-86dc-b116e4c399dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581216070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3581216070
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.197659589
Short name T489
Test name
Test status
Simulation time 55475166188 ps
CPU time 31.05 seconds
Started Jun 26 06:12:06 PM PDT 24
Finished Jun 26 06:12:38 PM PDT 24
Peak memory 199932 kb
Host smart-634c1219-5bfa-4921-99c6-0e98f388eb67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197659589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.197659589
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.1033955515
Short name T615
Test name
Test status
Simulation time 105914767537 ps
CPU time 1017.44 seconds
Started Jun 26 06:12:07 PM PDT 24
Finished Jun 26 06:29:06 PM PDT 24
Peak memory 226220 kb
Host smart-ea40f2c6-bc83-4d0b-a073-ce1e8e25d0b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033955515 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.1033955515
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.878463770
Short name T795
Test name
Test status
Simulation time 802251962 ps
CPU time 1.65 seconds
Started Jun 26 06:12:06 PM PDT 24
Finished Jun 26 06:12:09 PM PDT 24
Peak memory 198912 kb
Host smart-c155e793-6c78-4dd8-9d89-a3e726068c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878463770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.878463770
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.2095882652
Short name T251
Test name
Test status
Simulation time 70163815146 ps
CPU time 57.28 seconds
Started Jun 26 06:11:58 PM PDT 24
Finished Jun 26 06:12:57 PM PDT 24
Peak memory 199988 kb
Host smart-1191ab9e-6c25-4490-a426-107219d549b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095882652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2095882652
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.949770228
Short name T516
Test name
Test status
Simulation time 74185862 ps
CPU time 0.56 seconds
Started Jun 26 06:10:23 PM PDT 24
Finished Jun 26 06:10:26 PM PDT 24
Peak memory 195192 kb
Host smart-7b853dc6-b177-46de-b01f-237116f70f76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949770228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.949770228
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.267603656
Short name T679
Test name
Test status
Simulation time 68030317305 ps
CPU time 63.06 seconds
Started Jun 26 06:10:20 PM PDT 24
Finished Jun 26 06:11:26 PM PDT 24
Peak memory 199864 kb
Host smart-5ac871a2-e989-42d0-836a-cb6ca47367c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267603656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.267603656
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3449689756
Short name T1039
Test name
Test status
Simulation time 30438705121 ps
CPU time 52.6 seconds
Started Jun 26 06:10:13 PM PDT 24
Finished Jun 26 06:11:08 PM PDT 24
Peak memory 199944 kb
Host smart-cf5174d9-2337-4201-8a55-8e5c6193bb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449689756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3449689756
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.3661184238
Short name T1074
Test name
Test status
Simulation time 96578211502 ps
CPU time 174.24 seconds
Started Jun 26 06:10:10 PM PDT 24
Finished Jun 26 06:13:08 PM PDT 24
Peak memory 199980 kb
Host smart-a495279b-1655-4da8-9b0a-d1a3f8575832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661184238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3661184238
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.323862363
Short name T473
Test name
Test status
Simulation time 38755525338 ps
CPU time 84.83 seconds
Started Jun 26 06:10:20 PM PDT 24
Finished Jun 26 06:11:48 PM PDT 24
Peak memory 199848 kb
Host smart-13bb0bef-7efd-4580-8a46-2ff60d4b4ee6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323862363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.323862363
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.3044546046
Short name T934
Test name
Test status
Simulation time 103420428108 ps
CPU time 146.54 seconds
Started Jun 26 06:10:29 PM PDT 24
Finished Jun 26 06:12:58 PM PDT 24
Peak memory 199952 kb
Host smart-462db202-f3eb-443f-b314-22ac389c6c09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3044546046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3044546046
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.576355518
Short name T684
Test name
Test status
Simulation time 9815685073 ps
CPU time 25.75 seconds
Started Jun 26 06:10:15 PM PDT 24
Finished Jun 26 06:10:44 PM PDT 24
Peak memory 199720 kb
Host smart-6c467e71-65a6-49f1-a6fa-6f49bcec95e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576355518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.576355518
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_perf.268065935
Short name T688
Test name
Test status
Simulation time 11238404423 ps
CPU time 643.63 seconds
Started Jun 26 06:10:15 PM PDT 24
Finished Jun 26 06:21:02 PM PDT 24
Peak memory 199956 kb
Host smart-abc5d257-df05-4df4-8db3-c1e39ee4cdf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=268065935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.268065935
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.4163845641
Short name T330
Test name
Test status
Simulation time 8160875026 ps
CPU time 13.28 seconds
Started Jun 26 06:10:20 PM PDT 24
Finished Jun 26 06:10:36 PM PDT 24
Peak memory 199080 kb
Host smart-246b5595-90a4-4676-87a2-ee4805ef6888
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4163845641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.4163845641
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.310821952
Short name T252
Test name
Test status
Simulation time 43837176870 ps
CPU time 35.73 seconds
Started Jun 26 06:10:15 PM PDT 24
Finished Jun 26 06:10:54 PM PDT 24
Peak memory 199972 kb
Host smart-c7294b30-a1ee-4296-8478-27cbd1290842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310821952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.310821952
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.472527144
Short name T378
Test name
Test status
Simulation time 3788614091 ps
CPU time 2.26 seconds
Started Jun 26 06:10:16 PM PDT 24
Finished Jun 26 06:10:21 PM PDT 24
Peak memory 196768 kb
Host smart-abc1f7b4-d650-4017-9098-6e0da591cdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472527144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.472527144
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.3277784305
Short name T29
Test name
Test status
Simulation time 476538549 ps
CPU time 0.89 seconds
Started Jun 26 06:10:19 PM PDT 24
Finished Jun 26 06:10:23 PM PDT 24
Peak memory 218424 kb
Host smart-39171857-ba02-4659-b03f-d000b32ca99e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277784305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3277784305
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.3807470314
Short name T332
Test name
Test status
Simulation time 121948833 ps
CPU time 1.12 seconds
Started Jun 26 06:10:13 PM PDT 24
Finished Jun 26 06:10:18 PM PDT 24
Peak memory 198756 kb
Host smart-726914af-5863-423a-9f03-2a4acf8bfbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807470314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3807470314
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2160844627
Short name T142
Test name
Test status
Simulation time 225296729814 ps
CPU time 228.05 seconds
Started Jun 26 06:10:19 PM PDT 24
Finished Jun 26 06:14:10 PM PDT 24
Peak memory 199968 kb
Host smart-6b8f11bf-fee9-4e4a-8976-82ae20f66c8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160844627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2160844627
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.3847058491
Short name T32
Test name
Test status
Simulation time 4293223342 ps
CPU time 18.04 seconds
Started Jun 26 06:10:14 PM PDT 24
Finished Jun 26 06:10:35 PM PDT 24
Peak memory 216392 kb
Host smart-abedf932-392a-4873-abc2-6c34a7dac43d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847058491 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.3847058491
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.946678581
Short name T441
Test name
Test status
Simulation time 1286026579 ps
CPU time 2.53 seconds
Started Jun 26 06:10:14 PM PDT 24
Finished Jun 26 06:10:20 PM PDT 24
Peak memory 199668 kb
Host smart-b600f013-e542-40e6-a15e-e1c4ba8b3a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946678581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.946678581
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3832333337
Short name T239
Test name
Test status
Simulation time 157411805417 ps
CPU time 58.47 seconds
Started Jun 26 06:10:13 PM PDT 24
Finished Jun 26 06:11:15 PM PDT 24
Peak memory 199884 kb
Host smart-329c76b2-b6e0-4344-8423-3e10b89fc87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832333337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3832333337
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.1848394244
Short name T828
Test name
Test status
Simulation time 11880940 ps
CPU time 0.55 seconds
Started Jun 26 06:12:13 PM PDT 24
Finished Jun 26 06:12:14 PM PDT 24
Peak memory 194748 kb
Host smart-2688e6fa-a419-4131-b384-58e3c0217a2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848394244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.1848394244
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3800739017
Short name T974
Test name
Test status
Simulation time 283334304444 ps
CPU time 94.79 seconds
Started Jun 26 06:12:08 PM PDT 24
Finished Jun 26 06:13:44 PM PDT 24
Peak memory 199924 kb
Host smart-8f3a24e9-ed40-4e29-88d8-df56cdf729a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800739017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3800739017
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.3218318998
Short name T291
Test name
Test status
Simulation time 213166999159 ps
CPU time 243.37 seconds
Started Jun 26 06:12:05 PM PDT 24
Finished Jun 26 06:16:09 PM PDT 24
Peak memory 199944 kb
Host smart-69714eff-0ed3-4fb4-be0d-0c73cfb56ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218318998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.3218318998
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.3714747612
Short name T179
Test name
Test status
Simulation time 131705811540 ps
CPU time 272.28 seconds
Started Jun 26 06:12:07 PM PDT 24
Finished Jun 26 06:16:41 PM PDT 24
Peak memory 199988 kb
Host smart-3490e263-28d0-4e7c-b8e8-483247903c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714747612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3714747612
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.93934170
Short name T533
Test name
Test status
Simulation time 87726215397 ps
CPU time 65.24 seconds
Started Jun 26 06:12:13 PM PDT 24
Finished Jun 26 06:13:19 PM PDT 24
Peak memory 196064 kb
Host smart-ad5c0819-50e5-4ad2-821d-c7510f996355
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93934170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.93934170
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.686361196
Short name T648
Test name
Test status
Simulation time 286895265720 ps
CPU time 79.53 seconds
Started Jun 26 06:12:14 PM PDT 24
Finished Jun 26 06:13:35 PM PDT 24
Peak memory 199968 kb
Host smart-02489530-0f96-434f-bf6b-5ff7339b9928
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=686361196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.686361196
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2716927948
Short name T328
Test name
Test status
Simulation time 6929659639 ps
CPU time 3.93 seconds
Started Jun 26 06:12:06 PM PDT 24
Finished Jun 26 06:12:11 PM PDT 24
Peak memory 197816 kb
Host smart-6dfd1d8a-15eb-4eb3-bd00-6b4372e7dbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716927948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2716927948
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_perf.3459494016
Short name T388
Test name
Test status
Simulation time 32043090463 ps
CPU time 189.63 seconds
Started Jun 26 06:12:05 PM PDT 24
Finished Jun 26 06:15:15 PM PDT 24
Peak memory 199976 kb
Host smart-fead4dc4-a1b9-49db-871f-6a2969790be9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3459494016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.3459494016
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.3792190546
Short name T355
Test name
Test status
Simulation time 7505278466 ps
CPU time 61.58 seconds
Started Jun 26 06:12:05 PM PDT 24
Finished Jun 26 06:13:07 PM PDT 24
Peak memory 198000 kb
Host smart-d6d3d625-fe3f-4a7a-bbad-8e093a437dcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3792190546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3792190546
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.2166621316
Short name T942
Test name
Test status
Simulation time 216193369873 ps
CPU time 32.63 seconds
Started Jun 26 06:12:07 PM PDT 24
Finished Jun 26 06:12:41 PM PDT 24
Peak memory 199928 kb
Host smart-0b71573d-6157-484e-8d94-24feeeba5f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166621316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2166621316
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.754249244
Short name T297
Test name
Test status
Simulation time 3402985061 ps
CPU time 1.86 seconds
Started Jun 26 06:12:05 PM PDT 24
Finished Jun 26 06:12:08 PM PDT 24
Peak memory 195816 kb
Host smart-98e3d21e-0f77-4832-9e0a-eb75bd79fdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754249244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.754249244
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.1257921273
Short name T500
Test name
Test status
Simulation time 5387680224 ps
CPU time 6.68 seconds
Started Jun 26 06:12:07 PM PDT 24
Finished Jun 26 06:12:14 PM PDT 24
Peak memory 199820 kb
Host smart-d95c09ca-070e-48da-90e6-6167c93358e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257921273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.1257921273
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.2492436638
Short name T1073
Test name
Test status
Simulation time 1893024139 ps
CPU time 2.2 seconds
Started Jun 26 06:12:05 PM PDT 24
Finished Jun 26 06:12:08 PM PDT 24
Peak memory 198544 kb
Host smart-994968fe-106e-44a7-831b-d618b6573837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492436638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2492436638
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.807543317
Short name T766
Test name
Test status
Simulation time 174025129856 ps
CPU time 127.63 seconds
Started Jun 26 06:12:10 PM PDT 24
Finished Jun 26 06:14:19 PM PDT 24
Peak memory 199996 kb
Host smart-a36974f4-32f3-480f-9827-c310337c8805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807543317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.807543317
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.1386121341
Short name T1048
Test name
Test status
Simulation time 34544489 ps
CPU time 0.57 seconds
Started Jun 26 06:12:13 PM PDT 24
Finished Jun 26 06:12:15 PM PDT 24
Peak memory 195240 kb
Host smart-8f48fd56-6308-41a1-b098-2834a4aea488
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386121341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1386121341
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.2410202323
Short name T427
Test name
Test status
Simulation time 9591890007 ps
CPU time 17.61 seconds
Started Jun 26 06:12:15 PM PDT 24
Finished Jun 26 06:12:34 PM PDT 24
Peak memory 199968 kb
Host smart-dd0db3c8-5813-4498-aba9-7f2dbbefb2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410202323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2410202323
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.156552544
Short name T979
Test name
Test status
Simulation time 97734880457 ps
CPU time 146.42 seconds
Started Jun 26 06:12:11 PM PDT 24
Finished Jun 26 06:14:39 PM PDT 24
Peak memory 199916 kb
Host smart-d27e0531-32e2-4f71-8f03-5e071e40dea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156552544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.156552544
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.2048891902
Short name T1062
Test name
Test status
Simulation time 20344497109 ps
CPU time 36.58 seconds
Started Jun 26 06:12:14 PM PDT 24
Finished Jun 26 06:12:52 PM PDT 24
Peak memory 198612 kb
Host smart-502ef90a-1cdf-4756-87b7-eef79047fccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048891902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2048891902
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.1980405811
Short name T11
Test name
Test status
Simulation time 127803181908 ps
CPU time 59.85 seconds
Started Jun 26 06:12:12 PM PDT 24
Finished Jun 26 06:13:13 PM PDT 24
Peak memory 199992 kb
Host smart-88cb9d01-d516-45f4-96dc-05893dbf1ef3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980405811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1980405811
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.3101094123
Short name T517
Test name
Test status
Simulation time 93586449362 ps
CPU time 114.13 seconds
Started Jun 26 06:12:13 PM PDT 24
Finished Jun 26 06:14:09 PM PDT 24
Peak memory 199900 kb
Host smart-5251236a-4240-408b-a0f5-6647db5b219c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3101094123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.3101094123
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1395358841
Short name T544
Test name
Test status
Simulation time 10119466251 ps
CPU time 6.43 seconds
Started Jun 26 06:12:12 PM PDT 24
Finished Jun 26 06:12:19 PM PDT 24
Peak memory 199008 kb
Host smart-cbfe9bf9-ff21-427c-a79c-746db06b75c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395358841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1395358841
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_perf.1385203153
Short name T922
Test name
Test status
Simulation time 13589843352 ps
CPU time 705.45 seconds
Started Jun 26 06:12:11 PM PDT 24
Finished Jun 26 06:23:58 PM PDT 24
Peak memory 199924 kb
Host smart-01e8168b-9607-4fe0-9384-20c1c364e771
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1385203153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1385203153
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.2299146295
Short name T1007
Test name
Test status
Simulation time 3378345349 ps
CPU time 16.58 seconds
Started Jun 26 06:12:13 PM PDT 24
Finished Jun 26 06:12:30 PM PDT 24
Peak memory 199164 kb
Host smart-a6cb12d9-8a6f-4b39-911d-9c1ba8584c2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2299146295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2299146295
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.4039651983
Short name T985
Test name
Test status
Simulation time 166568014565 ps
CPU time 68.13 seconds
Started Jun 26 06:12:13 PM PDT 24
Finished Jun 26 06:13:22 PM PDT 24
Peak memory 199932 kb
Host smart-65599389-e255-4cf0-a0aa-cda57d50a049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039651983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.4039651983
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.2066749977
Short name T930
Test name
Test status
Simulation time 5098622732 ps
CPU time 4.45 seconds
Started Jun 26 06:12:14 PM PDT 24
Finished Jun 26 06:12:20 PM PDT 24
Peak memory 196044 kb
Host smart-5c1ac145-73c8-4ac7-90d7-838ab292e1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066749977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2066749977
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.1053214874
Short name T675
Test name
Test status
Simulation time 129128709 ps
CPU time 0.84 seconds
Started Jun 26 06:12:18 PM PDT 24
Finished Jun 26 06:12:19 PM PDT 24
Peak memory 197760 kb
Host smart-61b363c7-55b3-4b88-9a07-82a78e42ede5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053214874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.1053214874
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.3676735455
Short name T1054
Test name
Test status
Simulation time 62353693729 ps
CPU time 394.78 seconds
Started Jun 26 06:12:10 PM PDT 24
Finished Jun 26 06:18:45 PM PDT 24
Peak memory 199904 kb
Host smart-6413140d-ff60-4288-9b8b-67fb9f58bf31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676735455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3676735455
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.3215322022
Short name T96
Test name
Test status
Simulation time 159150836332 ps
CPU time 516 seconds
Started Jun 26 06:12:11 PM PDT 24
Finished Jun 26 06:20:48 PM PDT 24
Peak memory 215504 kb
Host smart-00d4d8d3-bebe-4555-82a8-6dc1717d7486
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215322022 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.3215322022
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.3265462807
Short name T313
Test name
Test status
Simulation time 1332790984 ps
CPU time 2.89 seconds
Started Jun 26 06:12:14 PM PDT 24
Finished Jun 26 06:12:18 PM PDT 24
Peak memory 198976 kb
Host smart-da110572-de7f-440f-bdfb-e8b0afcea093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265462807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3265462807
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2972587866
Short name T258
Test name
Test status
Simulation time 106413084217 ps
CPU time 14.55 seconds
Started Jun 26 06:12:14 PM PDT 24
Finished Jun 26 06:12:30 PM PDT 24
Peak memory 198452 kb
Host smart-50016d3e-7795-46c5-9b1a-691c06e3be87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972587866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2972587866
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.1029228543
Short name T582
Test name
Test status
Simulation time 24306447 ps
CPU time 0.57 seconds
Started Jun 26 06:12:22 PM PDT 24
Finished Jun 26 06:12:24 PM PDT 24
Peak memory 195520 kb
Host smart-52bb4f6a-ee35-4427-b7ef-d964a6869002
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029228543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1029228543
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.1043310752
Short name T577
Test name
Test status
Simulation time 72340150891 ps
CPU time 87.75 seconds
Started Jun 26 06:12:12 PM PDT 24
Finished Jun 26 06:13:40 PM PDT 24
Peak memory 199904 kb
Host smart-fffdd50c-ca54-41a8-a813-f3c1013f5bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043310752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1043310752
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.987830193
Short name T789
Test name
Test status
Simulation time 66602725266 ps
CPU time 57.12 seconds
Started Jun 26 06:12:13 PM PDT 24
Finished Jun 26 06:13:12 PM PDT 24
Peak memory 199904 kb
Host smart-47cb6398-1078-4df4-b969-9ba570a5dbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987830193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.987830193
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.1986504420
Short name T472
Test name
Test status
Simulation time 152114584612 ps
CPU time 161.78 seconds
Started Jun 26 06:12:21 PM PDT 24
Finished Jun 26 06:15:04 PM PDT 24
Peak memory 199980 kb
Host smart-b15c1ab9-8428-4f6a-924d-9df6d01dffac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986504420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.1986504420
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.3875828366
Short name T649
Test name
Test status
Simulation time 218932892370 ps
CPU time 125.23 seconds
Started Jun 26 06:12:24 PM PDT 24
Finished Jun 26 06:14:31 PM PDT 24
Peak memory 199840 kb
Host smart-a6febefa-6afd-4219-9319-491735acf8d4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875828366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3875828366
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.3405172936
Short name T997
Test name
Test status
Simulation time 50917414573 ps
CPU time 413.5 seconds
Started Jun 26 06:12:23 PM PDT 24
Finished Jun 26 06:19:18 PM PDT 24
Peak memory 200012 kb
Host smart-2831ea5e-cf40-4885-8804-92643c3dc082
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3405172936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3405172936
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.184928746
Short name T466
Test name
Test status
Simulation time 7124558681 ps
CPU time 5.82 seconds
Started Jun 26 06:12:22 PM PDT 24
Finished Jun 26 06:12:30 PM PDT 24
Peak memory 199368 kb
Host smart-e3fbaf0c-d48f-431b-b910-5902e3d57d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184928746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.184928746
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_perf.4135050612
Short name T612
Test name
Test status
Simulation time 24632812734 ps
CPU time 218.33 seconds
Started Jun 26 06:12:19 PM PDT 24
Finished Jun 26 06:15:58 PM PDT 24
Peak memory 199980 kb
Host smart-c47c3224-6de7-4ec4-b6c2-8993ec3b07b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4135050612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.4135050612
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.1290101524
Short name T604
Test name
Test status
Simulation time 6891742894 ps
CPU time 3.49 seconds
Started Jun 26 06:12:23 PM PDT 24
Finished Jun 26 06:12:29 PM PDT 24
Peak memory 199456 kb
Host smart-10c5f12e-6c06-479c-8068-b9d3fa05e6eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1290101524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.1290101524
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.1753164488
Short name T159
Test name
Test status
Simulation time 126272291059 ps
CPU time 199.65 seconds
Started Jun 26 06:12:21 PM PDT 24
Finished Jun 26 06:15:41 PM PDT 24
Peak memory 199924 kb
Host smart-8407276b-2a53-4b8b-b35c-a8de5f1fd825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753164488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1753164488
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.148176533
Short name T575
Test name
Test status
Simulation time 40883018371 ps
CPU time 29.07 seconds
Started Jun 26 06:12:24 PM PDT 24
Finished Jun 26 06:12:55 PM PDT 24
Peak memory 196728 kb
Host smart-d04bbe10-f7cf-4c8a-9d92-c681e03a36f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148176533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.148176533
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.2024701147
Short name T975
Test name
Test status
Simulation time 5310310167 ps
CPU time 14.66 seconds
Started Jun 26 06:12:14 PM PDT 24
Finished Jun 26 06:12:30 PM PDT 24
Peak memory 199924 kb
Host smart-0213637b-dee5-4f7f-9a89-d43c3e4b1a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024701147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2024701147
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.3024508868
Short name T941
Test name
Test status
Simulation time 87374453595 ps
CPU time 157.53 seconds
Started Jun 26 06:12:22 PM PDT 24
Finished Jun 26 06:15:01 PM PDT 24
Peak memory 199976 kb
Host smart-b527e852-e6f6-430c-a7ad-945562daaae3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024508868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.3024508868
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.4041324375
Short name T290
Test name
Test status
Simulation time 6819277749 ps
CPU time 7.35 seconds
Started Jun 26 06:12:19 PM PDT 24
Finished Jun 26 06:12:27 PM PDT 24
Peak memory 199880 kb
Host smart-5c413d7b-4a28-4794-a8dc-c78ed517b967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041324375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.4041324375
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.3491277755
Short name T885
Test name
Test status
Simulation time 53459167922 ps
CPU time 91.15 seconds
Started Jun 26 06:12:12 PM PDT 24
Finished Jun 26 06:13:44 PM PDT 24
Peak memory 199940 kb
Host smart-39beabdf-31a8-417c-bf2b-de7244f0c3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491277755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.3491277755
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1490712149
Short name T357
Test name
Test status
Simulation time 13646182 ps
CPU time 0.62 seconds
Started Jun 26 06:12:22 PM PDT 24
Finished Jun 26 06:12:24 PM PDT 24
Peak memory 195320 kb
Host smart-81cdbadd-8f45-42b4-a82f-dff362e7f856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490712149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1490712149
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.4131005076
Short name T501
Test name
Test status
Simulation time 19654609110 ps
CPU time 36.68 seconds
Started Jun 26 06:12:22 PM PDT 24
Finished Jun 26 06:13:01 PM PDT 24
Peak memory 199864 kb
Host smart-4b2c1fb8-39af-4483-9d36-f8c1697b50c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131005076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.4131005076
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3056677337
Short name T124
Test name
Test status
Simulation time 32602216569 ps
CPU time 9.6 seconds
Started Jun 26 06:12:19 PM PDT 24
Finished Jun 26 06:12:29 PM PDT 24
Peak memory 199032 kb
Host smart-35e6686a-ab2c-480a-a3d1-0140ad35ff81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056677337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3056677337
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.1072207994
Short name T524
Test name
Test status
Simulation time 14349157794 ps
CPU time 10.41 seconds
Started Jun 26 06:12:22 PM PDT 24
Finished Jun 26 06:12:34 PM PDT 24
Peak memory 198848 kb
Host smart-85b5e57a-144e-46f9-8146-aaaa363171b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072207994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.1072207994
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3971786355
Short name T899
Test name
Test status
Simulation time 51933740904 ps
CPU time 31.42 seconds
Started Jun 26 06:12:22 PM PDT 24
Finished Jun 26 06:12:55 PM PDT 24
Peak memory 200016 kb
Host smart-a25d5c5f-bc72-464c-a75e-09dbb73c7628
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971786355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3971786355
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.1965593889
Short name T387
Test name
Test status
Simulation time 99054362734 ps
CPU time 814.54 seconds
Started Jun 26 06:12:22 PM PDT 24
Finished Jun 26 06:25:58 PM PDT 24
Peak memory 199896 kb
Host smart-3bbb7305-35d1-4b6b-9457-d42f69c373b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1965593889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1965593889
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.4277977433
Short name T336
Test name
Test status
Simulation time 2276853307 ps
CPU time 2.65 seconds
Started Jun 26 06:12:21 PM PDT 24
Finished Jun 26 06:12:24 PM PDT 24
Peak memory 198480 kb
Host smart-4db38d18-23b1-4a24-9416-a262ba853542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277977433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.4277977433
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_perf.1165279118
Short name T315
Test name
Test status
Simulation time 18858154621 ps
CPU time 558.09 seconds
Started Jun 26 06:12:21 PM PDT 24
Finished Jun 26 06:21:41 PM PDT 24
Peak memory 199832 kb
Host smart-735d9808-0fdc-4390-94d7-7d77627a8576
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1165279118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1165279118
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.2414367605
Short name T969
Test name
Test status
Simulation time 3369581413 ps
CPU time 25 seconds
Started Jun 26 06:12:21 PM PDT 24
Finished Jun 26 06:12:47 PM PDT 24
Peak memory 198168 kb
Host smart-1461684b-9157-4218-9887-16a73b5b0f7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2414367605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2414367605
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.459705185
Short name T404
Test name
Test status
Simulation time 130891200020 ps
CPU time 30.46 seconds
Started Jun 26 06:12:25 PM PDT 24
Finished Jun 26 06:12:57 PM PDT 24
Peak memory 199980 kb
Host smart-2fe94d3d-4e1d-40e6-a5a2-9b32d997c140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459705185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.459705185
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.3420124885
Short name T600
Test name
Test status
Simulation time 41154241445 ps
CPU time 15.74 seconds
Started Jun 26 06:12:23 PM PDT 24
Finished Jun 26 06:12:41 PM PDT 24
Peak memory 196408 kb
Host smart-8ae0d702-8f52-4e29-9766-943deab98da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420124885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3420124885
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.3866814766
Short name T1033
Test name
Test status
Simulation time 6009179980 ps
CPU time 7.78 seconds
Started Jun 26 06:12:21 PM PDT 24
Finished Jun 26 06:12:30 PM PDT 24
Peak memory 199920 kb
Host smart-086be99c-4c91-46ec-8def-3213876e08ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866814766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.3866814766
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.2513123027
Short name T125
Test name
Test status
Simulation time 89044920762 ps
CPU time 1113.13 seconds
Started Jun 26 06:12:22 PM PDT 24
Finished Jun 26 06:30:56 PM PDT 24
Peak memory 199916 kb
Host smart-ed1455ea-7f33-4892-8e7a-3c338949720b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513123027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2513123027
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.985642760
Short name T31
Test name
Test status
Simulation time 181545695249 ps
CPU time 663.66 seconds
Started Jun 26 06:12:22 PM PDT 24
Finished Jun 26 06:23:27 PM PDT 24
Peak memory 216484 kb
Host smart-48d69ecd-92f0-4e3f-8f2b-2bf605062343
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985642760 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.985642760
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.2209632105
Short name T369
Test name
Test status
Simulation time 12645582151 ps
CPU time 5.16 seconds
Started Jun 26 06:12:20 PM PDT 24
Finished Jun 26 06:12:26 PM PDT 24
Peak memory 199548 kb
Host smart-2a336f1f-ad3a-4e6a-bc6c-408fac4fa25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209632105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.2209632105
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.2468448086
Short name T703
Test name
Test status
Simulation time 137176995081 ps
CPU time 17.59 seconds
Started Jun 26 06:12:24 PM PDT 24
Finished Jun 26 06:12:43 PM PDT 24
Peak memory 199964 kb
Host smart-8ba93217-e9d6-4f36-8b63-b5fea7c95b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468448086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.2468448086
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.331376108
Short name T510
Test name
Test status
Simulation time 45084988 ps
CPU time 0.61 seconds
Started Jun 26 06:12:32 PM PDT 24
Finished Jun 26 06:12:34 PM PDT 24
Peak memory 194952 kb
Host smart-019b54eb-b4e9-4c71-811c-d5def1ed433d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331376108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.331376108
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.2401642380
Short name T793
Test name
Test status
Simulation time 44492895205 ps
CPU time 84.1 seconds
Started Jun 26 06:12:20 PM PDT 24
Finished Jun 26 06:13:45 PM PDT 24
Peak memory 199992 kb
Host smart-626998b0-2145-48a2-9dc5-456a53f666d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401642380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.2401642380
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1513225470
Short name T130
Test name
Test status
Simulation time 91626259809 ps
CPU time 37.93 seconds
Started Jun 26 06:12:20 PM PDT 24
Finished Jun 26 06:12:59 PM PDT 24
Peak memory 199932 kb
Host smart-5ee0718e-0f1f-405b-b23c-cee294339ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513225470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1513225470
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.706957827
Short name T768
Test name
Test status
Simulation time 170402147604 ps
CPU time 27.89 seconds
Started Jun 26 06:12:24 PM PDT 24
Finished Jun 26 06:12:54 PM PDT 24
Peak memory 199924 kb
Host smart-a4d187e6-a733-4e5c-a08e-927f01291fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706957827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.706957827
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.3931032603
Short name T497
Test name
Test status
Simulation time 4080534654 ps
CPU time 11.73 seconds
Started Jun 26 06:12:24 PM PDT 24
Finished Jun 26 06:12:37 PM PDT 24
Peak memory 199928 kb
Host smart-e2993a58-e011-4cce-be30-b02c49b51a7d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931032603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3931032603
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.1893829209
Short name T564
Test name
Test status
Simulation time 146448474763 ps
CPU time 880.68 seconds
Started Jun 26 06:12:27 PM PDT 24
Finished Jun 26 06:27:09 PM PDT 24
Peak memory 199844 kb
Host smart-56fe127c-a72f-4ab0-9d82-8703e0226bc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1893829209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1893829209
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.2674844772
Short name T423
Test name
Test status
Simulation time 2837726396 ps
CPU time 4.99 seconds
Started Jun 26 06:12:29 PM PDT 24
Finished Jun 26 06:12:35 PM PDT 24
Peak memory 197536 kb
Host smart-f7f23d46-9556-4cf2-89d7-26442e032abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674844772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.2674844772
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.3258367601
Short name T912
Test name
Test status
Simulation time 18695859844 ps
CPU time 17.03 seconds
Started Jun 26 06:12:22 PM PDT 24
Finished Jun 26 06:12:41 PM PDT 24
Peak memory 197704 kb
Host smart-43ca1974-7b87-4af9-9606-a585ef70c71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258367601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.3258367601
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.3620253870
Short name T1031
Test name
Test status
Simulation time 21280595824 ps
CPU time 1064.81 seconds
Started Jun 26 06:12:29 PM PDT 24
Finished Jun 26 06:30:16 PM PDT 24
Peak memory 199916 kb
Host smart-15ae3a59-be6a-4823-a69f-58e78ece54ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3620253870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.3620253870
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2781244591
Short name T1064
Test name
Test status
Simulation time 5431326261 ps
CPU time 11.47 seconds
Started Jun 26 06:12:20 PM PDT 24
Finished Jun 26 06:12:33 PM PDT 24
Peak memory 199352 kb
Host smart-89434fad-15bc-41eb-bb81-696a1f5669ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2781244591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2781244591
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1479299172
Short name T921
Test name
Test status
Simulation time 19261433750 ps
CPU time 32.4 seconds
Started Jun 26 06:12:26 PM PDT 24
Finished Jun 26 06:13:00 PM PDT 24
Peak memory 199944 kb
Host smart-3ae8d572-0e57-477d-bad3-7ae4f7a98f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479299172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1479299172
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.3489932790
Short name T522
Test name
Test status
Simulation time 1758625849 ps
CPU time 1.33 seconds
Started Jun 26 06:12:29 PM PDT 24
Finished Jun 26 06:12:32 PM PDT 24
Peak memory 195364 kb
Host smart-a6c6dcd1-2e80-444a-9c12-2aed5bc1114a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489932790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3489932790
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.711357942
Short name T735
Test name
Test status
Simulation time 661526032 ps
CPU time 2.47 seconds
Started Jun 26 06:12:21 PM PDT 24
Finished Jun 26 06:12:24 PM PDT 24
Peak memory 199900 kb
Host smart-e01696a4-19df-4e97-8b2b-9ed2c01ac412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711357942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.711357942
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2224852003
Short name T557
Test name
Test status
Simulation time 246887708679 ps
CPU time 395.33 seconds
Started Jun 26 06:12:29 PM PDT 24
Finished Jun 26 06:19:06 PM PDT 24
Peak memory 199988 kb
Host smart-36b630fb-b004-4d2f-89bc-def1fbd28480
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224852003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2224852003
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.2876194166
Short name T848
Test name
Test status
Simulation time 2756206240 ps
CPU time 2.18 seconds
Started Jun 26 06:12:27 PM PDT 24
Finished Jun 26 06:12:30 PM PDT 24
Peak memory 199192 kb
Host smart-0b95462b-7f2d-4592-9d62-ad5b3b7188e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876194166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2876194166
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_alert_test.2460752665
Short name T539
Test name
Test status
Simulation time 11654018 ps
CPU time 0.56 seconds
Started Jun 26 06:12:30 PM PDT 24
Finished Jun 26 06:12:32 PM PDT 24
Peak memory 195232 kb
Host smart-a9472eca-84a6-458f-a2fb-7563dccd25b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460752665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2460752665
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.3364188017
Short name T554
Test name
Test status
Simulation time 102996438753 ps
CPU time 167.81 seconds
Started Jun 26 06:12:32 PM PDT 24
Finished Jun 26 06:15:21 PM PDT 24
Peak memory 199972 kb
Host smart-979172e3-412c-4adf-8967-c18598a61dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364188017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3364188017
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.157397386
Short name T262
Test name
Test status
Simulation time 49907201106 ps
CPU time 82.54 seconds
Started Jun 26 06:12:30 PM PDT 24
Finished Jun 26 06:13:54 PM PDT 24
Peak memory 199940 kb
Host smart-2e0483f9-d456-4dc3-9af1-1ce55ecfe4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157397386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.157397386
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.2776702523
Short name T1012
Test name
Test status
Simulation time 141826962467 ps
CPU time 592.79 seconds
Started Jun 26 06:12:28 PM PDT 24
Finished Jun 26 06:22:22 PM PDT 24
Peak memory 199960 kb
Host smart-ac3a4f06-bba5-41e5-871c-a7443b7e67f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776702523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2776702523
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.2962937898
Short name T274
Test name
Test status
Simulation time 207895364664 ps
CPU time 163.96 seconds
Started Jun 26 06:12:28 PM PDT 24
Finished Jun 26 06:15:12 PM PDT 24
Peak memory 199868 kb
Host smart-dd00260b-ca96-4c7a-8988-8d8e00f6c37c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962937898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.2962937898
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.871239838
Short name T1088
Test name
Test status
Simulation time 114407259038 ps
CPU time 753.9 seconds
Started Jun 26 06:12:30 PM PDT 24
Finished Jun 26 06:25:05 PM PDT 24
Peak memory 200004 kb
Host smart-e8f13a01-5768-4c84-bd9e-85bca0aa42a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=871239838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.871239838
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.668626767
Short name T341
Test name
Test status
Simulation time 8073408449 ps
CPU time 6.14 seconds
Started Jun 26 06:12:26 PM PDT 24
Finished Jun 26 06:12:34 PM PDT 24
Peak memory 199860 kb
Host smart-dca12a1d-d2ac-4bb3-9944-ebf982ef2e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668626767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.668626767
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_perf.2117022052
Short name T785
Test name
Test status
Simulation time 11522909209 ps
CPU time 719.96 seconds
Started Jun 26 06:12:26 PM PDT 24
Finished Jun 26 06:24:28 PM PDT 24
Peak memory 199888 kb
Host smart-2b0a3442-a048-41a1-badb-377ac1a374e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2117022052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2117022052
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.2621217153
Short name T414
Test name
Test status
Simulation time 6126418160 ps
CPU time 14.08 seconds
Started Jun 26 06:12:28 PM PDT 24
Finished Jun 26 06:12:44 PM PDT 24
Peak memory 197824 kb
Host smart-18d5e0d9-e224-47b9-9af8-167ab8527ecd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2621217153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2621217153
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.708565067
Short name T109
Test name
Test status
Simulation time 89852435267 ps
CPU time 151.31 seconds
Started Jun 26 06:12:29 PM PDT 24
Finished Jun 26 06:15:02 PM PDT 24
Peak memory 199964 kb
Host smart-81cc7201-2f84-4ec7-a995-ce6f098df4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708565067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.708565067
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.869204961
Short name T1086
Test name
Test status
Simulation time 2895900918 ps
CPU time 5.21 seconds
Started Jun 26 06:12:29 PM PDT 24
Finished Jun 26 06:12:35 PM PDT 24
Peak memory 196436 kb
Host smart-827c1ba0-ccca-4247-87aa-f8212efb5be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869204961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.869204961
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.608398559
Short name T685
Test name
Test status
Simulation time 249837331 ps
CPU time 1.57 seconds
Started Jun 26 06:12:30 PM PDT 24
Finished Jun 26 06:12:33 PM PDT 24
Peak memory 199060 kb
Host smart-8d154c90-2932-406f-a82e-334e8a2e7ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608398559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.608398559
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1343879768
Short name T216
Test name
Test status
Simulation time 157391190470 ps
CPU time 818.98 seconds
Started Jun 26 06:12:32 PM PDT 24
Finished Jun 26 06:26:12 PM PDT 24
Peak memory 224648 kb
Host smart-03673a09-270f-4115-b802-4290903fea25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343879768 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1343879768
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.1710664730
Short name T659
Test name
Test status
Simulation time 1504622627 ps
CPU time 2.05 seconds
Started Jun 26 06:12:26 PM PDT 24
Finished Jun 26 06:12:30 PM PDT 24
Peak memory 198924 kb
Host smart-4d1607f3-4409-480a-b6ca-c5f2c29f07da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710664730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.1710664730
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.3063511701
Short name T940
Test name
Test status
Simulation time 76988092406 ps
CPU time 32.12 seconds
Started Jun 26 06:12:32 PM PDT 24
Finished Jun 26 06:13:05 PM PDT 24
Peak memory 199816 kb
Host smart-22385045-fd57-4510-92db-547dd558b3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063511701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3063511701
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.3968699404
Short name T530
Test name
Test status
Simulation time 23070134 ps
CPU time 0.54 seconds
Started Jun 26 06:12:36 PM PDT 24
Finished Jun 26 06:12:38 PM PDT 24
Peak memory 194968 kb
Host smart-bceb85ca-8ac6-4e2b-91a7-fd691c76c2f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968699404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3968699404
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.4259483568
Short name T164
Test name
Test status
Simulation time 110789050182 ps
CPU time 46.61 seconds
Started Jun 26 06:12:29 PM PDT 24
Finished Jun 26 06:13:17 PM PDT 24
Peak memory 199904 kb
Host smart-c6a4650b-1598-4b21-87e7-d3a6d3efa834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259483568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.4259483568
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.308579208
Short name T884
Test name
Test status
Simulation time 182446321172 ps
CPU time 261.66 seconds
Started Jun 26 06:12:28 PM PDT 24
Finished Jun 26 06:16:51 PM PDT 24
Peak memory 199928 kb
Host smart-5cbad13a-955a-4120-9fff-9f779c2b611b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308579208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.308579208
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_intr.1856037284
Short name T799
Test name
Test status
Simulation time 23496997451 ps
CPU time 30.83 seconds
Started Jun 26 06:12:32 PM PDT 24
Finished Jun 26 06:13:03 PM PDT 24
Peak memory 198228 kb
Host smart-dfd4c841-13ab-486f-b21b-a06b7244fea5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856037284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.1856037284
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3300855863
Short name T950
Test name
Test status
Simulation time 142504990137 ps
CPU time 1381.82 seconds
Started Jun 26 06:12:38 PM PDT 24
Finished Jun 26 06:35:41 PM PDT 24
Peak memory 199928 kb
Host smart-4e7bfe41-2162-4d1f-aac8-e4a2b0977b88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3300855863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3300855863
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.202111686
Short name T681
Test name
Test status
Simulation time 2524257977 ps
CPU time 1.91 seconds
Started Jun 26 06:12:36 PM PDT 24
Finished Jun 26 06:12:39 PM PDT 24
Peak memory 197560 kb
Host smart-f15490e4-b36d-4b9e-b992-2e4c3996d599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202111686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.202111686
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_perf.347842324
Short name T678
Test name
Test status
Simulation time 23040637761 ps
CPU time 274.36 seconds
Started Jun 26 06:12:36 PM PDT 24
Finished Jun 26 06:17:12 PM PDT 24
Peak memory 199908 kb
Host smart-5cf6f58c-4f4e-4fe8-8e1c-27988af02c99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=347842324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.347842324
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2989239896
Short name T818
Test name
Test status
Simulation time 6344552539 ps
CPU time 53.85 seconds
Started Jun 26 06:12:31 PM PDT 24
Finished Jun 26 06:13:26 PM PDT 24
Peak memory 198220 kb
Host smart-2730ddf8-5a82-491d-8397-1ba34ec357a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2989239896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2989239896
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3967900756
Short name T761
Test name
Test status
Simulation time 800654077 ps
CPU time 1.97 seconds
Started Jun 26 06:12:31 PM PDT 24
Finished Jun 26 06:12:34 PM PDT 24
Peak memory 195416 kb
Host smart-f4da3aec-f877-43ac-9a25-8fb9c2eae06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967900756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3967900756
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.4195385842
Short name T698
Test name
Test status
Simulation time 5676132889 ps
CPU time 11.24 seconds
Started Jun 26 06:12:32 PM PDT 24
Finished Jun 26 06:12:44 PM PDT 24
Peak memory 199268 kb
Host smart-76cf8299-9dca-4d46-bbf3-a839154fa84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195385842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.4195385842
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.395004938
Short name T790
Test name
Test status
Simulation time 871419771961 ps
CPU time 630.98 seconds
Started Jun 26 06:12:36 PM PDT 24
Finished Jun 26 06:23:08 PM PDT 24
Peak memory 199980 kb
Host smart-7f4f04de-f1e5-46e3-b339-513ecf3d3597
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395004938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.395004938
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.3443999264
Short name T972
Test name
Test status
Simulation time 84838330013 ps
CPU time 680.88 seconds
Started Jun 26 06:12:37 PM PDT 24
Finished Jun 26 06:23:59 PM PDT 24
Peak memory 216440 kb
Host smart-212ce73f-8bd3-4433-8c00-125ae7bcd3e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443999264 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.3443999264
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.3817813268
Short name T448
Test name
Test status
Simulation time 1507826339 ps
CPU time 2.37 seconds
Started Jun 26 06:12:29 PM PDT 24
Finished Jun 26 06:12:33 PM PDT 24
Peak memory 199432 kb
Host smart-ff5a80fd-4d4b-445c-8042-dd75ea059b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817813268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3817813268
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1400949534
Short name T487
Test name
Test status
Simulation time 57427715011 ps
CPU time 14.84 seconds
Started Jun 26 06:12:30 PM PDT 24
Finished Jun 26 06:12:46 PM PDT 24
Peak memory 198496 kb
Host smart-cdbdb4f4-0851-4eca-a03e-68dc7b322a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400949534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1400949534
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.3754382617
Short name T396
Test name
Test status
Simulation time 20782185 ps
CPU time 0.56 seconds
Started Jun 26 06:12:40 PM PDT 24
Finished Jun 26 06:12:41 PM PDT 24
Peak memory 194496 kb
Host smart-b1719fb3-08e4-4036-a59c-80d459ef4c25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754382617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3754382617
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.2964075918
Short name T996
Test name
Test status
Simulation time 132021849344 ps
CPU time 112.12 seconds
Started Jun 26 06:12:38 PM PDT 24
Finished Jun 26 06:14:31 PM PDT 24
Peak memory 199892 kb
Host smart-60b84b13-653f-4392-af87-6c70cc807f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964075918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2964075918
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.3989316874
Short name T739
Test name
Test status
Simulation time 99960588035 ps
CPU time 160.16 seconds
Started Jun 26 06:12:35 PM PDT 24
Finished Jun 26 06:15:16 PM PDT 24
Peak memory 199640 kb
Host smart-3c0f8884-35ee-4e86-994e-52301d332b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989316874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3989316874
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.2828542341
Short name T200
Test name
Test status
Simulation time 58810861039 ps
CPU time 29.97 seconds
Started Jun 26 06:12:44 PM PDT 24
Finished Jun 26 06:13:15 PM PDT 24
Peak memory 199956 kb
Host smart-2ccff45d-c302-4997-9129-9fc2524e918e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828542341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.2828542341
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.2046974407
Short name T933
Test name
Test status
Simulation time 13648279691 ps
CPU time 7.62 seconds
Started Jun 26 06:12:44 PM PDT 24
Finished Jun 26 06:12:53 PM PDT 24
Peak memory 199660 kb
Host smart-a82e1bd8-d749-4bad-8715-fb37c5649d35
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046974407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2046974407
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.676742902
Short name T1077
Test name
Test status
Simulation time 83820249082 ps
CPU time 131.95 seconds
Started Jun 26 06:12:39 PM PDT 24
Finished Jun 26 06:14:52 PM PDT 24
Peak memory 199892 kb
Host smart-750e50a3-5fa3-4d60-9c6d-622d5b02a9e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=676742902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.676742902
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.1177690476
Short name T429
Test name
Test status
Simulation time 6082207740 ps
CPU time 11.95 seconds
Started Jun 26 06:12:34 PM PDT 24
Finished Jun 26 06:12:47 PM PDT 24
Peak memory 199644 kb
Host smart-e8dc8d7f-3c0c-4e99-8c9b-f23548b7fc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177690476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.1177690476
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_perf.3622640864
Short name T289
Test name
Test status
Simulation time 11611188989 ps
CPU time 170.61 seconds
Started Jun 26 06:12:37 PM PDT 24
Finished Jun 26 06:15:29 PM PDT 24
Peak memory 199960 kb
Host smart-ba03dcce-cfd8-47e0-8414-5d9393e06201
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3622640864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.3622640864
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.2975623595
Short name T1035
Test name
Test status
Simulation time 4022103872 ps
CPU time 30.04 seconds
Started Jun 26 06:12:36 PM PDT 24
Finished Jun 26 06:13:07 PM PDT 24
Peak memory 198068 kb
Host smart-b926410b-eaf4-4e5c-9e11-b079b4ef4b5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2975623595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2975623595
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.58856275
Short name T165
Test name
Test status
Simulation time 94442956784 ps
CPU time 35.02 seconds
Started Jun 26 06:12:38 PM PDT 24
Finished Jun 26 06:13:14 PM PDT 24
Peak memory 199836 kb
Host smart-ac7d181d-5e3c-416c-a52e-66735460ffd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58856275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.58856275
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.2327047154
Short name T268
Test name
Test status
Simulation time 41354464226 ps
CPU time 4.01 seconds
Started Jun 26 06:12:41 PM PDT 24
Finished Jun 26 06:12:46 PM PDT 24
Peak memory 196444 kb
Host smart-c9a65e70-a841-45ee-9388-5ae5f0cb9d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327047154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.2327047154
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.1506405726
Short name T924
Test name
Test status
Simulation time 5365145318 ps
CPU time 9.85 seconds
Started Jun 26 06:12:36 PM PDT 24
Finished Jun 26 06:12:48 PM PDT 24
Peak memory 199296 kb
Host smart-bb2cd72a-97f3-4831-9957-a4de959fea05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506405726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.1506405726
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.616984602
Short name T299
Test name
Test status
Simulation time 239920647682 ps
CPU time 911.09 seconds
Started Jun 26 06:12:35 PM PDT 24
Finished Jun 26 06:27:47 PM PDT 24
Peak memory 199972 kb
Host smart-80a47e40-1eae-461f-9759-689e7e12f15d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616984602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.616984602
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2027300991
Short name T958
Test name
Test status
Simulation time 7661082702 ps
CPU time 13.92 seconds
Started Jun 26 06:12:38 PM PDT 24
Finished Jun 26 06:12:53 PM PDT 24
Peak memory 199988 kb
Host smart-53585b24-a261-4f32-bb3b-1f6df065b46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027300991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2027300991
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.2568167918
Short name T867
Test name
Test status
Simulation time 196105606847 ps
CPU time 71.4 seconds
Started Jun 26 06:12:37 PM PDT 24
Finished Jun 26 06:13:50 PM PDT 24
Peak memory 199920 kb
Host smart-c6e388f0-3d35-4911-b7af-840d6affe295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568167918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2568167918
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3735369328
Short name T614
Test name
Test status
Simulation time 13892331 ps
CPU time 0.57 seconds
Started Jun 26 06:12:42 PM PDT 24
Finished Jun 26 06:12:44 PM PDT 24
Peak memory 195236 kb
Host smart-cb51d814-a175-49d6-b783-7db1ee634164
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735369328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3735369328
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2051414836
Short name T1068
Test name
Test status
Simulation time 51987159849 ps
CPU time 77.71 seconds
Started Jun 26 06:12:36 PM PDT 24
Finished Jun 26 06:13:55 PM PDT 24
Peak memory 199960 kb
Host smart-93e629df-6e65-4122-aa2b-b9e8b7725817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051414836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2051414836
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1984001114
Short name T668
Test name
Test status
Simulation time 16643155510 ps
CPU time 34.77 seconds
Started Jun 26 06:12:38 PM PDT 24
Finished Jun 26 06:13:14 PM PDT 24
Peak memory 199944 kb
Host smart-74bef4b0-3884-4452-89a1-0405e84abf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984001114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1984001114
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_intr.2649176990
Short name T788
Test name
Test status
Simulation time 6208692859 ps
CPU time 3.35 seconds
Started Jun 26 06:12:45 PM PDT 24
Finished Jun 26 06:12:49 PM PDT 24
Peak memory 199136 kb
Host smart-a85cd23e-f165-4cfd-a727-636a148a82e7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649176990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2649176990
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.3752525139
Short name T36
Test name
Test status
Simulation time 82226475104 ps
CPU time 562.71 seconds
Started Jun 26 06:12:45 PM PDT 24
Finished Jun 26 06:22:08 PM PDT 24
Peak memory 199916 kb
Host smart-1efbb11a-d839-44c4-9e7b-6a34f6dbba64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3752525139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3752525139
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.2063162143
Short name T1011
Test name
Test status
Simulation time 10704567493 ps
CPU time 22.37 seconds
Started Jun 26 06:12:36 PM PDT 24
Finished Jun 26 06:12:59 PM PDT 24
Peak memory 199948 kb
Host smart-63191d60-8600-48a7-bc09-c05656167ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063162143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.2063162143
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_perf.3733885401
Short name T1084
Test name
Test status
Simulation time 3435317678 ps
CPU time 43.42 seconds
Started Jun 26 06:12:39 PM PDT 24
Finished Jun 26 06:13:24 PM PDT 24
Peak memory 199840 kb
Host smart-f172104e-ba09-4f0a-85ab-a1fbfb657cdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3733885401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3733885401
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2328583628
Short name T966
Test name
Test status
Simulation time 7019862321 ps
CPU time 64.47 seconds
Started Jun 26 06:12:44 PM PDT 24
Finished Jun 26 06:13:50 PM PDT 24
Peak memory 198148 kb
Host smart-8ee10bf4-a1fa-46af-a0df-820a729ae065
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2328583628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2328583628
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.1849450337
Short name T157
Test name
Test status
Simulation time 27191951353 ps
CPU time 39.68 seconds
Started Jun 26 06:12:41 PM PDT 24
Finished Jun 26 06:13:22 PM PDT 24
Peak memory 199920 kb
Host smart-b45c5026-5f81-464a-9453-37cd7c4ad738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849450337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1849450337
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.2545117570
Short name T380
Test name
Test status
Simulation time 4886050943 ps
CPU time 8.31 seconds
Started Jun 26 06:12:36 PM PDT 24
Finished Jun 26 06:12:45 PM PDT 24
Peak memory 195988 kb
Host smart-59dee86a-304b-4917-b05c-a6ca3d0d39bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545117570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.2545117570
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.1484348988
Short name T453
Test name
Test status
Simulation time 734076597 ps
CPU time 2.83 seconds
Started Jun 26 06:12:38 PM PDT 24
Finished Jun 26 06:12:42 PM PDT 24
Peak memory 198332 kb
Host smart-f308b01c-f0aa-4ef8-a8c7-b0db03d1f184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484348988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.1484348988
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.3188038386
Short name T1029
Test name
Test status
Simulation time 122646948369 ps
CPU time 1531 seconds
Started Jun 26 06:12:39 PM PDT 24
Finished Jun 26 06:38:11 PM PDT 24
Peak memory 199876 kb
Host smart-628cdc7d-fb23-4d72-9944-1b79c2aa2c55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188038386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3188038386
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.3812528393
Short name T581
Test name
Test status
Simulation time 2881149436 ps
CPU time 1.62 seconds
Started Jun 26 06:12:40 PM PDT 24
Finished Jun 26 06:12:43 PM PDT 24
Peak memory 199000 kb
Host smart-629d711b-bb81-441b-87e5-bc814abbc917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812528393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3812528393
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.664429496
Short name T762
Test name
Test status
Simulation time 122325991540 ps
CPU time 244.52 seconds
Started Jun 26 06:12:35 PM PDT 24
Finished Jun 26 06:16:41 PM PDT 24
Peak memory 199912 kb
Host smart-cc8cab2a-2737-4763-9cf8-4ef5b0aeb833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664429496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.664429496
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.1803864812
Short name T983
Test name
Test status
Simulation time 15088475 ps
CPU time 0.56 seconds
Started Jun 26 06:12:54 PM PDT 24
Finished Jun 26 06:12:56 PM PDT 24
Peak memory 194104 kb
Host smart-c31ee1e0-cc84-4415-85f2-7182f4a55cc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803864812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1803864812
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.3090464126
Short name T770
Test name
Test status
Simulation time 154415897880 ps
CPU time 42.8 seconds
Started Jun 26 06:12:43 PM PDT 24
Finished Jun 26 06:13:27 PM PDT 24
Peak memory 199912 kb
Host smart-a29747ad-48a9-45c2-ae2e-ff11736c405f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090464126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3090464126
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.2388479286
Short name T432
Test name
Test status
Simulation time 64292337118 ps
CPU time 27.19 seconds
Started Jun 26 06:12:43 PM PDT 24
Finished Jun 26 06:13:11 PM PDT 24
Peak memory 200208 kb
Host smart-701e2e74-ddb7-4125-9e86-649a1dadd570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388479286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2388479286
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.3706227517
Short name T8
Test name
Test status
Simulation time 94119472655 ps
CPU time 47.4 seconds
Started Jun 26 06:12:46 PM PDT 24
Finished Jun 26 06:13:34 PM PDT 24
Peak memory 199996 kb
Host smart-fe688952-9a85-4300-bc65-0e2ab4ff141e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706227517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3706227517
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3648812409
Short name T286
Test name
Test status
Simulation time 9010891112 ps
CPU time 15.37 seconds
Started Jun 26 06:12:42 PM PDT 24
Finished Jun 26 06:12:59 PM PDT 24
Peak memory 199940 kb
Host smart-c045d2e4-6a4c-4841-b935-48c9978a3ea3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648812409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3648812409
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.1587028719
Short name T90
Test name
Test status
Simulation time 113738455635 ps
CPU time 320.22 seconds
Started Jun 26 06:12:41 PM PDT 24
Finished Jun 26 06:18:03 PM PDT 24
Peak memory 199912 kb
Host smart-a25a35e8-2f42-4f01-8150-1641236eaf63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1587028719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1587028719
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1681691593
Short name T890
Test name
Test status
Simulation time 1278672862 ps
CPU time 1.69 seconds
Started Jun 26 06:12:41 PM PDT 24
Finished Jun 26 06:12:44 PM PDT 24
Peak memory 196132 kb
Host smart-70525aa7-26da-4b25-a2c7-8459145cbeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681691593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1681691593
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_perf.2531413099
Short name T483
Test name
Test status
Simulation time 14151192780 ps
CPU time 195.52 seconds
Started Jun 26 06:12:43 PM PDT 24
Finished Jun 26 06:16:00 PM PDT 24
Peak memory 199832 kb
Host smart-43431dc6-ac89-4eae-9a32-acef03d4ed87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2531413099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.2531413099
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.4254605543
Short name T478
Test name
Test status
Simulation time 4276377486 ps
CPU time 16.73 seconds
Started Jun 26 06:12:43 PM PDT 24
Finished Jun 26 06:13:02 PM PDT 24
Peak memory 199288 kb
Host smart-ee799893-9d98-4285-a937-f33d8ef05b5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4254605543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.4254605543
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.801670849
Short name T558
Test name
Test status
Simulation time 52566270237 ps
CPU time 16.63 seconds
Started Jun 26 06:12:41 PM PDT 24
Finished Jun 26 06:12:59 PM PDT 24
Peak memory 199940 kb
Host smart-2c086eaf-2bff-41dd-842c-024e39906c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801670849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.801670849
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.1070716709
Short name T461
Test name
Test status
Simulation time 2495662962 ps
CPU time 2.52 seconds
Started Jun 26 06:12:46 PM PDT 24
Finished Jun 26 06:12:50 PM PDT 24
Peak memory 196488 kb
Host smart-d0e03879-f832-45c5-b19a-ba01f6572812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070716709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1070716709
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.3629665544
Short name T981
Test name
Test status
Simulation time 474662222 ps
CPU time 2.44 seconds
Started Jun 26 06:12:43 PM PDT 24
Finished Jun 26 06:12:46 PM PDT 24
Peak memory 199076 kb
Host smart-74c1ad48-203b-401d-9c30-2b97c80b28cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629665544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3629665544
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.1275350170
Short name T722
Test name
Test status
Simulation time 420441830804 ps
CPU time 664.36 seconds
Started Jun 26 06:12:45 PM PDT 24
Finished Jun 26 06:23:50 PM PDT 24
Peak memory 215460 kb
Host smart-97da0e4a-6da5-43b8-9a39-d0be56e13f0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275350170 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1275350170
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.1698780799
Short name T247
Test name
Test status
Simulation time 6451966153 ps
CPU time 15.85 seconds
Started Jun 26 06:12:42 PM PDT 24
Finished Jun 26 06:12:59 PM PDT 24
Peak memory 199932 kb
Host smart-670792c2-e14d-4503-9eeb-c52edfc31fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698780799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1698780799
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.828293021
Short name T509
Test name
Test status
Simulation time 30543654015 ps
CPU time 45.05 seconds
Started Jun 26 06:12:41 PM PDT 24
Finished Jun 26 06:13:28 PM PDT 24
Peak memory 199972 kb
Host smart-7eab7906-4898-48b2-8ec2-e5c695fde09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828293021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.828293021
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.636693740
Short name T25
Test name
Test status
Simulation time 17740267 ps
CPU time 0.61 seconds
Started Jun 26 06:10:22 PM PDT 24
Finished Jun 26 06:10:26 PM PDT 24
Peak memory 195312 kb
Host smart-5d18367b-89af-4da6-9be7-4e839839c854
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636693740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.636693740
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.2832347569
Short name T718
Test name
Test status
Simulation time 28350680863 ps
CPU time 41.23 seconds
Started Jun 26 06:10:21 PM PDT 24
Finished Jun 26 06:11:05 PM PDT 24
Peak memory 200004 kb
Host smart-44c86ac8-ace9-4152-bd69-3bafa9559318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832347569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.2832347569
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.3393769693
Short name T700
Test name
Test status
Simulation time 63468548405 ps
CPU time 48.42 seconds
Started Jun 26 06:10:32 PM PDT 24
Finished Jun 26 06:11:23 PM PDT 24
Peak memory 199896 kb
Host smart-d6906a83-53f3-44a0-a60d-be3e0a0d9634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393769693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.3393769693
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.2264041049
Short name T221
Test name
Test status
Simulation time 27833893191 ps
CPU time 31.68 seconds
Started Jun 26 06:10:18 PM PDT 24
Finished Jun 26 06:10:52 PM PDT 24
Peak memory 199980 kb
Host smart-a4cfa436-a65a-442a-a172-c98bbea5f8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264041049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.2264041049
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.4167923198
Short name T592
Test name
Test status
Simulation time 54840145809 ps
CPU time 32.98 seconds
Started Jun 26 06:10:23 PM PDT 24
Finished Jun 26 06:10:59 PM PDT 24
Peak memory 199916 kb
Host smart-70f66943-9a2d-4b43-a9ad-0b4083e6be13
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167923198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.4167923198
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.3781002722
Short name T276
Test name
Test status
Simulation time 167596974561 ps
CPU time 565.39 seconds
Started Jun 26 06:10:22 PM PDT 24
Finished Jun 26 06:19:50 PM PDT 24
Peak memory 200004 kb
Host smart-cc3267f2-efc9-46a0-9e55-19f21cce0cc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3781002722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.3781002722
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.1368589437
Short name T1072
Test name
Test status
Simulation time 4798249289 ps
CPU time 7.27 seconds
Started Jun 26 06:10:26 PM PDT 24
Finished Jun 26 06:10:36 PM PDT 24
Peak memory 199248 kb
Host smart-d3676b8b-0273-4d4c-b29d-81f5c82f7226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368589437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.1368589437
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_perf.652528794
Short name T467
Test name
Test status
Simulation time 8677622377 ps
CPU time 491.72 seconds
Started Jun 26 06:10:23 PM PDT 24
Finished Jun 26 06:18:38 PM PDT 24
Peak memory 200208 kb
Host smart-d1e690ab-c86a-4837-b085-0aac684c2bca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=652528794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.652528794
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.2086242898
Short name T326
Test name
Test status
Simulation time 4471932716 ps
CPU time 18.53 seconds
Started Jun 26 06:10:22 PM PDT 24
Finished Jun 26 06:10:43 PM PDT 24
Peak memory 199064 kb
Host smart-3c13c0d4-92f9-4a6c-bcd2-70a83ad7f469
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2086242898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2086242898
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.666075586
Short name T740
Test name
Test status
Simulation time 44330760350 ps
CPU time 41.15 seconds
Started Jun 26 06:10:24 PM PDT 24
Finished Jun 26 06:11:09 PM PDT 24
Peak memory 199964 kb
Host smart-f21def69-05e2-4708-9662-8ccf20c9cf95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666075586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.666075586
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.3249151478
Short name T951
Test name
Test status
Simulation time 769081495 ps
CPU time 1.84 seconds
Started Jun 26 06:10:31 PM PDT 24
Finished Jun 26 06:10:35 PM PDT 24
Peak memory 195604 kb
Host smart-8e6b38b5-1e78-496a-a71c-cd85aedc470e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249151478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3249151478
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.2335408892
Short name T536
Test name
Test status
Simulation time 5385716143 ps
CPU time 15.03 seconds
Started Jun 26 06:10:17 PM PDT 24
Finished Jun 26 06:10:35 PM PDT 24
Peak memory 199628 kb
Host smart-ba41e2bc-7c17-4f25-8903-0b3fca60649e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335408892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2335408892
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.2833073081
Short name T246
Test name
Test status
Simulation time 1570182861 ps
CPU time 1.22 seconds
Started Jun 26 06:10:37 PM PDT 24
Finished Jun 26 06:10:39 PM PDT 24
Peak memory 198596 kb
Host smart-6b4609ea-fa52-4a72-b868-b6cfc1c5a550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833073081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.2833073081
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.2621062153
Short name T882
Test name
Test status
Simulation time 51678797379 ps
CPU time 22.27 seconds
Started Jun 26 06:10:23 PM PDT 24
Finished Jun 26 06:10:48 PM PDT 24
Peak memory 199896 kb
Host smart-8a83bcdd-4087-4f32-a1f1-052b39965c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621062153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2621062153
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.249924147
Short name T931
Test name
Test status
Simulation time 52507155901 ps
CPU time 22.91 seconds
Started Jun 26 06:12:50 PM PDT 24
Finished Jun 26 06:13:14 PM PDT 24
Peak memory 199996 kb
Host smart-200502bb-8517-4074-9c45-b79fd2bf54b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249924147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.249924147
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.4206812374
Short name T776
Test name
Test status
Simulation time 66312219512 ps
CPU time 217.39 seconds
Started Jun 26 06:12:47 PM PDT 24
Finished Jun 26 06:16:26 PM PDT 24
Peak memory 216360 kb
Host smart-ffd85f3f-54e4-4d1b-9392-fc7b8d528d20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206812374 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.4206812374
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.3996997877
Short name T93
Test name
Test status
Simulation time 50967485190 ps
CPU time 224.86 seconds
Started Jun 26 06:12:49 PM PDT 24
Finished Jun 26 06:16:36 PM PDT 24
Peak memory 216040 kb
Host smart-7874c21a-c847-4ec6-bc10-e6d90f4a0b05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996997877 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.3996997877
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.1309141547
Short name T598
Test name
Test status
Simulation time 72723945901 ps
CPU time 14.15 seconds
Started Jun 26 06:12:49 PM PDT 24
Finished Jun 26 06:13:05 PM PDT 24
Peak memory 199916 kb
Host smart-594df81c-712d-4bfd-b269-5d27e5a36479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309141547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.1309141547
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.2563574091
Short name T319
Test name
Test status
Simulation time 96769255061 ps
CPU time 153.25 seconds
Started Jun 26 06:12:51 PM PDT 24
Finished Jun 26 06:15:25 PM PDT 24
Peak memory 200196 kb
Host smart-daa54bee-557e-47ec-8630-a46c40734b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563574091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.2563574091
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.1912893124
Short name T303
Test name
Test status
Simulation time 110961170099 ps
CPU time 427.51 seconds
Started Jun 26 06:12:50 PM PDT 24
Finished Jun 26 06:19:59 PM PDT 24
Peak memory 209596 kb
Host smart-153de2be-0479-40c7-acd4-a059dbc9a6fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912893124 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.1912893124
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.106544615
Short name T540
Test name
Test status
Simulation time 67376317980 ps
CPU time 112.74 seconds
Started Jun 26 06:12:49 PM PDT 24
Finished Jun 26 06:14:44 PM PDT 24
Peak memory 199932 kb
Host smart-04a1fe41-253b-4d1b-a470-77e541efd0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106544615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.106544615
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.352433114
Short name T666
Test name
Test status
Simulation time 169353909616 ps
CPU time 249.76 seconds
Started Jun 26 06:12:53 PM PDT 24
Finished Jun 26 06:17:05 PM PDT 24
Peak memory 199924 kb
Host smart-8dcecadb-80cd-4269-a317-eef4b9944a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352433114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.352433114
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.1084426193
Short name T541
Test name
Test status
Simulation time 164564808611 ps
CPU time 823.31 seconds
Started Jun 26 06:12:48 PM PDT 24
Finished Jun 26 06:26:32 PM PDT 24
Peak memory 216528 kb
Host smart-1b4250d6-750e-48f1-9557-7c779ff34588
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084426193 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.1084426193
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.3371592858
Short name T851
Test name
Test status
Simulation time 23326578648 ps
CPU time 7.17 seconds
Started Jun 26 06:12:48 PM PDT 24
Finished Jun 26 06:12:56 PM PDT 24
Peak memory 199960 kb
Host smart-01fe1306-ddec-4b66-9fd6-61486fdc9d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371592858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.3371592858
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.4000788675
Short name T917
Test name
Test status
Simulation time 17158193841 ps
CPU time 167.09 seconds
Started Jun 26 06:12:49 PM PDT 24
Finished Jun 26 06:15:38 PM PDT 24
Peak memory 208300 kb
Host smart-07563cb5-e493-4963-83bf-f152ae73cc93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000788675 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.4000788675
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.351975606
Short name T594
Test name
Test status
Simulation time 143379705967 ps
CPU time 104.54 seconds
Started Jun 26 06:12:46 PM PDT 24
Finished Jun 26 06:14:31 PM PDT 24
Peak memory 199948 kb
Host smart-8af64873-5d9b-480d-8deb-b2a8a4aeccdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351975606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.351975606
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2721339891
Short name T875
Test name
Test status
Simulation time 35851937941 ps
CPU time 241.93 seconds
Started Jun 26 06:12:54 PM PDT 24
Finished Jun 26 06:16:58 PM PDT 24
Peak memory 207876 kb
Host smart-b18fd433-adcc-40a8-9297-5be30e6ef385
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721339891 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2721339891
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1948081378
Short name T132
Test name
Test status
Simulation time 133938071444 ps
CPU time 62.43 seconds
Started Jun 26 06:12:57 PM PDT 24
Finished Jun 26 06:14:02 PM PDT 24
Peak memory 199632 kb
Host smart-7e9f72de-e4b2-458f-9f87-623dc7c0976b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948081378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1948081378
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.1612977019
Short name T304
Test name
Test status
Simulation time 159779945208 ps
CPU time 1290.78 seconds
Started Jun 26 06:12:49 PM PDT 24
Finished Jun 26 06:34:22 PM PDT 24
Peak memory 224688 kb
Host smart-f3d878b0-9988-4b17-a271-a19b9d725a9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612977019 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.1612977019
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.177395180
Short name T623
Test name
Test status
Simulation time 165888385778 ps
CPU time 59.49 seconds
Started Jun 26 06:12:53 PM PDT 24
Finished Jun 26 06:13:53 PM PDT 24
Peak memory 200000 kb
Host smart-6e262406-ee48-4a04-837b-4abf24b87949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177395180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.177395180
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.2550746966
Short name T879
Test name
Test status
Simulation time 162703637802 ps
CPU time 395.18 seconds
Started Jun 26 06:12:53 PM PDT 24
Finished Jun 26 06:19:30 PM PDT 24
Peak memory 216492 kb
Host smart-1ba108f6-4c18-469e-8b96-317584c18a14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550746966 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.2550746966
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3098089127
Short name T534
Test name
Test status
Simulation time 54980936 ps
CPU time 0.54 seconds
Started Jun 26 06:10:22 PM PDT 24
Finished Jun 26 06:10:26 PM PDT 24
Peak memory 194692 kb
Host smart-fc5cf633-7d58-4fb3-a2b8-67d991103df3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098089127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3098089127
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.999441217
Short name T859
Test name
Test status
Simulation time 19796584543 ps
CPU time 33.68 seconds
Started Jun 26 06:10:29 PM PDT 24
Finished Jun 26 06:11:05 PM PDT 24
Peak memory 199972 kb
Host smart-fbc5e952-16f2-4f4e-badd-0de484d62870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999441217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.999441217
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.1856898523
Short name T100
Test name
Test status
Simulation time 93144403396 ps
CPU time 206.54 seconds
Started Jun 26 06:10:15 PM PDT 24
Finished Jun 26 06:13:45 PM PDT 24
Peak memory 200000 kb
Host smart-89421247-ca19-4f0d-8924-b22052fc1ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856898523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.1856898523
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.3629461123
Short name T204
Test name
Test status
Simulation time 122853084713 ps
CPU time 202.24 seconds
Started Jun 26 06:10:26 PM PDT 24
Finished Jun 26 06:13:52 PM PDT 24
Peak memory 199996 kb
Host smart-e261f788-e1fa-4b97-87b0-8d10ce6372ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629461123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.3629461123
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.3662144338
Short name T454
Test name
Test status
Simulation time 17380826712 ps
CPU time 17.26 seconds
Started Jun 26 06:10:13 PM PDT 24
Finished Jun 26 06:10:33 PM PDT 24
Peak memory 197636 kb
Host smart-3c146b9a-8000-46e8-b1b9-5c81d9495109
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662144338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3662144338
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.707256908
Short name T335
Test name
Test status
Simulation time 75486560666 ps
CPU time 380.22 seconds
Started Jun 26 06:10:20 PM PDT 24
Finished Jun 26 06:16:42 PM PDT 24
Peak memory 199976 kb
Host smart-8c38fd0f-be3b-4602-88de-12646b64ca78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=707256908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.707256908
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.3747173700
Short name T707
Test name
Test status
Simulation time 2536646329 ps
CPU time 9.5 seconds
Started Jun 26 06:10:22 PM PDT 24
Finished Jun 26 06:10:35 PM PDT 24
Peak memory 198296 kb
Host smart-ca2d4d61-7107-4043-920f-07c4a88780ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747173700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.3747173700
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_perf.2089473414
Short name T702
Test name
Test status
Simulation time 10137170936 ps
CPU time 402.7 seconds
Started Jun 26 06:10:19 PM PDT 24
Finished Jun 26 06:17:04 PM PDT 24
Peak memory 199920 kb
Host smart-9c443762-cb9c-4832-b4ac-07087c7203d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2089473414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.2089473414
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.2912250199
Short name T433
Test name
Test status
Simulation time 4239990130 ps
CPU time 37.88 seconds
Started Jun 26 06:10:24 PM PDT 24
Finished Jun 26 06:11:05 PM PDT 24
Peak memory 198060 kb
Host smart-ecea3359-669b-469c-b5fd-2e7f66549bcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2912250199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.2912250199
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1829668157
Short name T424
Test name
Test status
Simulation time 41347285879 ps
CPU time 46.42 seconds
Started Jun 26 06:10:25 PM PDT 24
Finished Jun 26 06:11:14 PM PDT 24
Peak memory 199992 kb
Host smart-c6a538bc-ec3d-4628-bf2f-ba3d901e0265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829668157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1829668157
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1121075330
Short name T298
Test name
Test status
Simulation time 3864104580 ps
CPU time 3.75 seconds
Started Jun 26 06:10:30 PM PDT 24
Finished Jun 26 06:10:35 PM PDT 24
Peak memory 196784 kb
Host smart-ef8c4e7d-084b-4a72-b613-534f34c1f387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121075330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1121075330
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.1955775613
Short name T417
Test name
Test status
Simulation time 10525609104 ps
CPU time 45.74 seconds
Started Jun 26 06:10:21 PM PDT 24
Finished Jun 26 06:11:09 PM PDT 24
Peak memory 199860 kb
Host smart-43a11e65-d49d-4a4d-bfd6-694772595107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955775613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.1955775613
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.3145167035
Short name T264
Test name
Test status
Simulation time 34510200056 ps
CPU time 853.36 seconds
Started Jun 26 06:10:17 PM PDT 24
Finished Jun 26 06:24:33 PM PDT 24
Peak memory 216176 kb
Host smart-dfd40e8a-7d93-4e33-8206-75447768f53b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145167035 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.3145167035
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.1711228732
Short name T354
Test name
Test status
Simulation time 550061205 ps
CPU time 1.87 seconds
Started Jun 26 06:10:24 PM PDT 24
Finished Jun 26 06:10:29 PM PDT 24
Peak memory 198196 kb
Host smart-2e44dcd1-857a-44a2-bafa-d2a704dcdd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711228732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.1711228732
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.29494866
Short name T340
Test name
Test status
Simulation time 8910805215 ps
CPU time 13.79 seconds
Started Jun 26 06:10:22 PM PDT 24
Finished Jun 26 06:10:39 PM PDT 24
Peak memory 197596 kb
Host smart-5af560a2-955a-431a-8e3a-f2efa3789812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29494866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.29494866
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.2194762117
Short name T786
Test name
Test status
Simulation time 19946535979 ps
CPU time 15.03 seconds
Started Jun 26 06:12:53 PM PDT 24
Finished Jun 26 06:13:09 PM PDT 24
Peak memory 199996 kb
Host smart-86ff140c-1b85-4a36-bcb9-de462a27daf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194762117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.2194762117
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.3916940981
Short name T813
Test name
Test status
Simulation time 7129745383 ps
CPU time 12.95 seconds
Started Jun 26 06:12:55 PM PDT 24
Finished Jun 26 06:13:11 PM PDT 24
Peak memory 199956 kb
Host smart-749cf27e-03f0-4d64-b8cb-b8a2b4522f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916940981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.3916940981
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2767840391
Short name T188
Test name
Test status
Simulation time 48562645534 ps
CPU time 1101.12 seconds
Started Jun 26 06:12:58 PM PDT 24
Finished Jun 26 06:31:21 PM PDT 24
Peak memory 215512 kb
Host smart-d91532ae-6cfc-4d13-89ec-c7949a7d52a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767840391 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2767840391
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.1967091085
Short name T815
Test name
Test status
Simulation time 64344624849 ps
CPU time 55.25 seconds
Started Jun 26 06:12:54 PM PDT 24
Finished Jun 26 06:13:51 PM PDT 24
Peak memory 199912 kb
Host smart-b1ef22c2-1efa-4f49-82f1-31f077676736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967091085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.1967091085
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3618203022
Short name T249
Test name
Test status
Simulation time 26942316354 ps
CPU time 509 seconds
Started Jun 26 06:12:54 PM PDT 24
Finished Jun 26 06:21:26 PM PDT 24
Peak memory 215664 kb
Host smart-78772a66-d9bd-4712-8880-61f5a37a335b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618203022 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3618203022
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.638858910
Short name T595
Test name
Test status
Simulation time 30347861105 ps
CPU time 28.49 seconds
Started Jun 26 06:12:52 PM PDT 24
Finished Jun 26 06:13:22 PM PDT 24
Peak memory 200016 kb
Host smart-0af17451-61e3-4383-a694-2e571c7e54b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638858910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.638858910
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.932957805
Short name T939
Test name
Test status
Simulation time 73567204530 ps
CPU time 38.36 seconds
Started Jun 26 06:12:56 PM PDT 24
Finished Jun 26 06:13:37 PM PDT 24
Peak memory 199968 kb
Host smart-4722e237-c07f-412d-8283-285ad3044692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932957805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.932957805
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.1162978517
Short name T194
Test name
Test status
Simulation time 267965815680 ps
CPU time 28.36 seconds
Started Jun 26 06:12:52 PM PDT 24
Finished Jun 26 06:13:21 PM PDT 24
Peak memory 199964 kb
Host smart-afe86e66-f9d2-40b1-9dd4-7c9899e96167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162978517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.1162978517
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.2072269754
Short name T990
Test name
Test status
Simulation time 20214614591 ps
CPU time 431.46 seconds
Started Jun 26 06:12:55 PM PDT 24
Finished Jun 26 06:20:09 PM PDT 24
Peak memory 209224 kb
Host smart-d496c31c-84d2-45fc-8547-37ba76f3fe39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072269754 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.2072269754
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.3144464487
Short name T190
Test name
Test status
Simulation time 30537810846 ps
CPU time 29.34 seconds
Started Jun 26 06:12:57 PM PDT 24
Finished Jun 26 06:13:29 PM PDT 24
Peak memory 199616 kb
Host smart-3365a3f9-1230-4d9d-bbf0-c8d8bd045e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144464487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3144464487
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.401483129
Short name T822
Test name
Test status
Simulation time 22028005935 ps
CPU time 20.75 seconds
Started Jun 26 06:12:54 PM PDT 24
Finished Jun 26 06:13:16 PM PDT 24
Peak memory 199916 kb
Host smart-fbfbd653-a5c1-41a1-a99a-ad6410807318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401483129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.401483129
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.3719573742
Short name T186
Test name
Test status
Simulation time 35896767279 ps
CPU time 51.5 seconds
Started Jun 26 06:12:55 PM PDT 24
Finished Jun 26 06:13:49 PM PDT 24
Peak memory 199956 kb
Host smart-fa3a762c-9ed9-4946-bbdf-26858c9eff61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719573742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3719573742
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.1449384563
Short name T155
Test name
Test status
Simulation time 73372055790 ps
CPU time 28.86 seconds
Started Jun 26 06:12:56 PM PDT 24
Finished Jun 26 06:13:27 PM PDT 24
Peak memory 199496 kb
Host smart-965caa6a-b698-42d7-a42c-61b3e506dc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449384563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1449384563
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.2825365638
Short name T736
Test name
Test status
Simulation time 36498608871 ps
CPU time 184.83 seconds
Started Jun 26 06:12:56 PM PDT 24
Finished Jun 26 06:16:04 PM PDT 24
Peak memory 208264 kb
Host smart-790c2a91-2807-4f45-adff-8f583c1622a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825365638 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.2825365638
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.1353100374
Short name T26
Test name
Test status
Simulation time 28386138 ps
CPU time 0.6 seconds
Started Jun 26 06:10:25 PM PDT 24
Finished Jun 26 06:10:29 PM PDT 24
Peak memory 195512 kb
Host smart-0db62f1d-a7f4-4f4e-8a15-1bd8156466ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353100374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1353100374
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.2389483887
Short name T135
Test name
Test status
Simulation time 134215340297 ps
CPU time 261.75 seconds
Started Jun 26 06:10:20 PM PDT 24
Finished Jun 26 06:14:45 PM PDT 24
Peak memory 199924 kb
Host smart-bbde4294-0fe3-40e4-89e9-1ca55f037b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389483887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2389483887
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2346674598
Short name T571
Test name
Test status
Simulation time 41579296382 ps
CPU time 68.48 seconds
Started Jun 26 06:10:24 PM PDT 24
Finished Jun 26 06:11:35 PM PDT 24
Peak memory 199840 kb
Host smart-c6731fb5-4ce0-4256-8de8-6da650850b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346674598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2346674598
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_intr.4961943
Short name T1060
Test name
Test status
Simulation time 20810792493 ps
CPU time 21.82 seconds
Started Jun 26 06:10:29 PM PDT 24
Finished Jun 26 06:10:53 PM PDT 24
Peak memory 196872 kb
Host smart-1a79ce65-33e2-4f7c-afe8-cc4ba6f6892c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4961943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.4961943
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.439324787
Short name T471
Test name
Test status
Simulation time 53593663426 ps
CPU time 383.4 seconds
Started Jun 26 06:10:25 PM PDT 24
Finished Jun 26 06:16:52 PM PDT 24
Peak memory 199904 kb
Host smart-9b18cdfe-62e8-43ff-a57c-7b717d13e6dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=439324787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.439324787
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.626524139
Short name T346
Test name
Test status
Simulation time 13813008160 ps
CPU time 8.41 seconds
Started Jun 26 06:10:20 PM PDT 24
Finished Jun 26 06:10:31 PM PDT 24
Peak memory 199304 kb
Host smart-2ab95a25-833d-475e-bff6-6b238fc38ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626524139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.626524139
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.2935463586
Short name T820
Test name
Test status
Simulation time 29902307410 ps
CPU time 11.09 seconds
Started Jun 26 06:10:19 PM PDT 24
Finished Jun 26 06:10:33 PM PDT 24
Peak memory 199872 kb
Host smart-d60eaec3-36c5-4d5f-9181-e347f4778267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935463586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2935463586
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.2839358338
Short name T455
Test name
Test status
Simulation time 8251880436 ps
CPU time 203.87 seconds
Started Jun 26 06:10:18 PM PDT 24
Finished Jun 26 06:13:45 PM PDT 24
Peak memory 199868 kb
Host smart-d20b0253-35a1-4352-b2d6-f6aad301c46d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2839358338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2839358338
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.1879285877
Short name T980
Test name
Test status
Simulation time 5463568663 ps
CPU time 46.35 seconds
Started Jun 26 06:10:21 PM PDT 24
Finished Jun 26 06:11:10 PM PDT 24
Peak memory 199184 kb
Host smart-cb195cee-1728-4e93-9f99-c23159628ec5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1879285877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1879285877
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.943600522
Short name T959
Test name
Test status
Simulation time 25793900669 ps
CPU time 41.85 seconds
Started Jun 26 06:10:26 PM PDT 24
Finished Jun 26 06:11:11 PM PDT 24
Peak memory 200012 kb
Host smart-7c34a979-03f7-499a-be8a-66bb6e99823a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943600522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.943600522
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1878216274
Short name T344
Test name
Test status
Simulation time 35122749904 ps
CPU time 50.7 seconds
Started Jun 26 06:10:28 PM PDT 24
Finished Jun 26 06:11:21 PM PDT 24
Peak memory 195792 kb
Host smart-b11e844a-84aa-44bd-94b7-32b6c028aa5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878216274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1878216274
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.2115574898
Short name T947
Test name
Test status
Simulation time 891332764 ps
CPU time 3.54 seconds
Started Jun 26 06:10:25 PM PDT 24
Finished Jun 26 06:10:32 PM PDT 24
Peak memory 199504 kb
Host smart-f3075f1b-cc16-4ad4-b851-d5dc9c1cfdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115574898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2115574898
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.1073944291
Short name T447
Test name
Test status
Simulation time 1370293395 ps
CPU time 1.44 seconds
Started Jun 26 06:10:34 PM PDT 24
Finished Jun 26 06:10:37 PM PDT 24
Peak memory 199400 kb
Host smart-6f8663bc-f712-4bc5-bcac-f9e8f4334571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073944291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1073944291
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.3913393784
Short name T284
Test name
Test status
Simulation time 93758693841 ps
CPU time 176.41 seconds
Started Jun 26 06:10:29 PM PDT 24
Finished Jun 26 06:13:28 PM PDT 24
Peak memory 199908 kb
Host smart-38189ff2-8dfc-40eb-9b1c-894caa3e5547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913393784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.3913393784
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.813327606
Short name T640
Test name
Test status
Simulation time 67553064940 ps
CPU time 77.05 seconds
Started Jun 26 06:12:56 PM PDT 24
Finished Jun 26 06:14:17 PM PDT 24
Peak memory 199800 kb
Host smart-60a21b73-8f25-420b-a85b-5851b8ca18f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813327606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.813327606
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.2252786536
Short name T1024
Test name
Test status
Simulation time 136935826010 ps
CPU time 490.06 seconds
Started Jun 26 06:12:56 PM PDT 24
Finished Jun 26 06:21:10 PM PDT 24
Peak memory 216428 kb
Host smart-01ace278-9cb4-4c69-87aa-df282da042c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252786536 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.2252786536
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.3291749169
Short name T573
Test name
Test status
Simulation time 142837638161 ps
CPU time 121.94 seconds
Started Jun 26 06:12:54 PM PDT 24
Finished Jun 26 06:14:58 PM PDT 24
Peak memory 199976 kb
Host smart-8ad2f1fe-205e-42a8-9751-4bf585a60299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291749169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3291749169
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.2547736378
Short name T1028
Test name
Test status
Simulation time 135149043049 ps
CPU time 127.05 seconds
Started Jun 26 06:12:54 PM PDT 24
Finished Jun 26 06:15:04 PM PDT 24
Peak memory 199944 kb
Host smart-8852235b-2ff4-4a1d-900b-2c01f065e283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547736378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2547736378
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.3363676071
Short name T538
Test name
Test status
Simulation time 118801466849 ps
CPU time 430.52 seconds
Started Jun 26 06:12:56 PM PDT 24
Finished Jun 26 06:20:10 PM PDT 24
Peak memory 210080 kb
Host smart-14a65591-1455-43a3-add9-4387f357b8b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363676071 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.3363676071
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.407207497
Short name T502
Test name
Test status
Simulation time 23016235427 ps
CPU time 37.91 seconds
Started Jun 26 06:13:02 PM PDT 24
Finished Jun 26 06:13:41 PM PDT 24
Peak memory 199980 kb
Host smart-816bd07a-057e-4e4a-a529-62d34ae072cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407207497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.407207497
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.2159404141
Short name T773
Test name
Test status
Simulation time 17051791169 ps
CPU time 19.32 seconds
Started Jun 26 06:13:00 PM PDT 24
Finished Jun 26 06:13:21 PM PDT 24
Peak memory 199976 kb
Host smart-95eabfc1-101d-407d-abdf-8a2207b9d65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159404141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2159404141
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.1458271985
Short name T198
Test name
Test status
Simulation time 7699206871 ps
CPU time 13.23 seconds
Started Jun 26 06:13:04 PM PDT 24
Finished Jun 26 06:13:18 PM PDT 24
Peak memory 199440 kb
Host smart-c8190bd4-b02e-4093-bf56-bde8ccc7629a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458271985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1458271985
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3052491128
Short name T644
Test name
Test status
Simulation time 112624083182 ps
CPU time 44.47 seconds
Started Jun 26 06:13:00 PM PDT 24
Finished Jun 26 06:13:46 PM PDT 24
Peak memory 199988 kb
Host smart-12b77fc3-abe0-4426-982b-3315a315f2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052491128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3052491128
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1413972539
Short name T1021
Test name
Test status
Simulation time 32768695191 ps
CPU time 268.76 seconds
Started Jun 26 06:13:05 PM PDT 24
Finished Jun 26 06:17:35 PM PDT 24
Peak memory 215884 kb
Host smart-7e902b4a-9324-4e5d-864a-95137e994927
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413972539 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1413972539
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.3809638196
Short name T117
Test name
Test status
Simulation time 57588653908 ps
CPU time 21.69 seconds
Started Jun 26 06:13:04 PM PDT 24
Finished Jun 26 06:13:27 PM PDT 24
Peak memory 199992 kb
Host smart-ee2f47f1-962b-4b3b-922d-4a9d4ed40b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809638196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3809638196
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.3867565800
Short name T294
Test name
Test status
Simulation time 130436876584 ps
CPU time 434.07 seconds
Started Jun 26 06:13:03 PM PDT 24
Finished Jun 26 06:20:18 PM PDT 24
Peak memory 209824 kb
Host smart-c4811b9d-3cf8-4c1e-8cba-7e2a46eab1ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867565800 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.3867565800
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.188002437
Short name T798
Test name
Test status
Simulation time 41410926354 ps
CPU time 375.61 seconds
Started Jun 26 06:13:03 PM PDT 24
Finished Jun 26 06:19:20 PM PDT 24
Peak memory 216480 kb
Host smart-55fb0f15-46ff-486a-ab13-090aad136f0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188002437 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.188002437
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.4032330795
Short name T367
Test name
Test status
Simulation time 36787946 ps
CPU time 0.58 seconds
Started Jun 26 06:10:32 PM PDT 24
Finished Jun 26 06:10:35 PM PDT 24
Peak memory 195516 kb
Host smart-f33cc5d8-8acf-47d1-b0e9-a712a4a988ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032330795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.4032330795
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3087454939
Short name T938
Test name
Test status
Simulation time 21109606471 ps
CPU time 40.34 seconds
Started Jun 26 06:10:22 PM PDT 24
Finished Jun 26 06:11:05 PM PDT 24
Peak memory 199900 kb
Host smart-d20e5ae3-8b72-4de4-a710-f2e5352524b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087454939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3087454939
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1064855001
Short name T872
Test name
Test status
Simulation time 87178816720 ps
CPU time 34.23 seconds
Started Jun 26 06:10:22 PM PDT 24
Finished Jun 26 06:11:00 PM PDT 24
Peak memory 199972 kb
Host smart-7e7f5401-b094-471a-845e-79bbe7e77c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064855001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1064855001
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_intr.3465229225
Short name T265
Test name
Test status
Simulation time 30112442619 ps
CPU time 18.17 seconds
Started Jun 26 06:10:18 PM PDT 24
Finished Jun 26 06:10:38 PM PDT 24
Peak memory 200020 kb
Host smart-29c70bd5-926a-4c51-a800-c3f515b68df4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465229225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3465229225
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.763263558
Short name T993
Test name
Test status
Simulation time 115184421317 ps
CPU time 1148.36 seconds
Started Jun 26 06:10:20 PM PDT 24
Finished Jun 26 06:29:31 PM PDT 24
Peak memory 199984 kb
Host smart-fd30c4ee-d004-41e6-956a-f9896c5b3078
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=763263558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.763263558
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.2015023784
Short name T19
Test name
Test status
Simulation time 9589952575 ps
CPU time 10.4 seconds
Started Jun 26 06:10:21 PM PDT 24
Finished Jun 26 06:10:34 PM PDT 24
Peak memory 199896 kb
Host smart-613de06b-aa63-4dc7-81d9-fbf292430627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015023784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2015023784
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_perf.837240986
Short name T838
Test name
Test status
Simulation time 24585345180 ps
CPU time 627.26 seconds
Started Jun 26 06:10:27 PM PDT 24
Finished Jun 26 06:20:57 PM PDT 24
Peak memory 199932 kb
Host smart-38b68220-d7c5-448a-bf57-006a7e269362
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=837240986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.837240986
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.282817509
Short name T1041
Test name
Test status
Simulation time 4358392959 ps
CPU time 39.49 seconds
Started Jun 26 06:10:24 PM PDT 24
Finished Jun 26 06:11:07 PM PDT 24
Peak memory 199416 kb
Host smart-11538dee-dfba-409a-81a2-0e59f0771afc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=282817509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.282817509
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.4037109562
Short name T281
Test name
Test status
Simulation time 17506278065 ps
CPU time 34.71 seconds
Started Jun 26 06:10:21 PM PDT 24
Finished Jun 26 06:10:59 PM PDT 24
Peak memory 199956 kb
Host smart-d42d7191-450f-46b9-88f1-75a9062585ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037109562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.4037109562
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.2547523605
Short name T1080
Test name
Test status
Simulation time 1562541410 ps
CPU time 1.35 seconds
Started Jun 26 06:10:29 PM PDT 24
Finished Jun 26 06:10:32 PM PDT 24
Peak memory 195592 kb
Host smart-da8f636d-f698-4d7b-800a-ca4562779a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547523605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2547523605
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.3142415947
Short name T366
Test name
Test status
Simulation time 885366898 ps
CPU time 3.74 seconds
Started Jun 26 06:10:21 PM PDT 24
Finished Jun 26 06:10:27 PM PDT 24
Peak memory 199496 kb
Host smart-b6db11c9-142f-481a-9998-1b477a89d6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142415947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3142415947
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.1997005940
Short name T578
Test name
Test status
Simulation time 154762093936 ps
CPU time 446.27 seconds
Started Jun 26 06:10:29 PM PDT 24
Finished Jun 26 06:17:58 PM PDT 24
Peak memory 199908 kb
Host smart-d5cf22aa-d2a0-4e1b-be45-4e7f256753c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997005940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1997005940
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.4258488976
Short name T446
Test name
Test status
Simulation time 798742872 ps
CPU time 2.61 seconds
Started Jun 26 06:10:33 PM PDT 24
Finished Jun 26 06:10:38 PM PDT 24
Peak memory 199580 kb
Host smart-ac4b37d5-6279-4ffe-aeb8-01faf9ac5173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258488976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.4258488976
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.1769801122
Short name T720
Test name
Test status
Simulation time 37307092335 ps
CPU time 18.39 seconds
Started Jun 26 06:10:32 PM PDT 24
Finished Jun 26 06:10:53 PM PDT 24
Peak memory 199924 kb
Host smart-eff64be2-dadd-492c-bb66-33746bd7d052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769801122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.1769801122
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.4086910231
Short name T244
Test name
Test status
Simulation time 120337993196 ps
CPU time 337.11 seconds
Started Jun 26 06:13:03 PM PDT 24
Finished Jun 26 06:18:41 PM PDT 24
Peak memory 199920 kb
Host smart-5f3ecee2-5c5e-47b2-97d8-f4da1904bd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086910231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.4086910231
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2848893808
Short name T308
Test name
Test status
Simulation time 23465340856 ps
CPU time 483.9 seconds
Started Jun 26 06:13:02 PM PDT 24
Finished Jun 26 06:21:07 PM PDT 24
Peak memory 216484 kb
Host smart-5b09c128-80e8-47c2-9688-6c2d40a6e37a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848893808 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2848893808
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.1393671571
Short name T450
Test name
Test status
Simulation time 94037459001 ps
CPU time 38.22 seconds
Started Jun 26 06:13:02 PM PDT 24
Finished Jun 26 06:13:41 PM PDT 24
Peak memory 199688 kb
Host smart-c06150d6-d01d-4d02-8cc5-8b2808499d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393671571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1393671571
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.2264845793
Short name T95
Test name
Test status
Simulation time 12340740604 ps
CPU time 133.74 seconds
Started Jun 26 06:13:01 PM PDT 24
Finished Jun 26 06:15:15 PM PDT 24
Peak memory 216488 kb
Host smart-882c0ac8-df07-40ba-9371-bbb0cadbfaec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264845793 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.2264845793
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.2572237611
Short name T1017
Test name
Test status
Simulation time 74002650302 ps
CPU time 109.9 seconds
Started Jun 26 06:13:01 PM PDT 24
Finished Jun 26 06:14:52 PM PDT 24
Peak memory 199912 kb
Host smart-f04713b9-50a6-4f7d-9523-42c146935f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572237611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2572237611
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3222162070
Short name T745
Test name
Test status
Simulation time 29416845052 ps
CPU time 24.84 seconds
Started Jun 26 06:13:03 PM PDT 24
Finished Jun 26 06:13:29 PM PDT 24
Peak memory 200232 kb
Host smart-68be9a2d-e555-4591-a336-3d52845c8c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222162070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3222162070
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.1514115432
Short name T15
Test name
Test status
Simulation time 22385776412 ps
CPU time 185.5 seconds
Started Jun 26 06:13:09 PM PDT 24
Finished Jun 26 06:16:17 PM PDT 24
Peak memory 216544 kb
Host smart-40cfef62-6100-4185-bcd4-22f8c05b3c18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514115432 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.1514115432
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.2939080628
Short name T854
Test name
Test status
Simulation time 151506463830 ps
CPU time 66.97 seconds
Started Jun 26 06:13:10 PM PDT 24
Finished Jun 26 06:14:19 PM PDT 24
Peak memory 199796 kb
Host smart-f067237d-d302-45b0-903f-b88c8d3f4fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939080628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2939080628
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.1089918566
Short name T176
Test name
Test status
Simulation time 36809402009 ps
CPU time 497.14 seconds
Started Jun 26 06:13:11 PM PDT 24
Finished Jun 26 06:21:31 PM PDT 24
Peak memory 216488 kb
Host smart-13256a62-3aac-4ad1-8aab-8156d7d97783
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089918566 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.1089918566
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.2352914217
Short name T743
Test name
Test status
Simulation time 116646482938 ps
CPU time 169.03 seconds
Started Jun 26 06:13:09 PM PDT 24
Finished Jun 26 06:16:00 PM PDT 24
Peak memory 199920 kb
Host smart-d66ef144-4fd0-4162-9429-d81318150750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352914217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2352914217
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.1607816700
Short name T856
Test name
Test status
Simulation time 253087125411 ps
CPU time 901.71 seconds
Started Jun 26 06:13:08 PM PDT 24
Finished Jun 26 06:28:12 PM PDT 24
Peak memory 216520 kb
Host smart-cf2c4da4-0a00-4174-8d84-f10c3fb15b37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607816700 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.1607816700
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.2397216059
Short name T272
Test name
Test status
Simulation time 116153949095 ps
CPU time 40.89 seconds
Started Jun 26 06:13:08 PM PDT 24
Finished Jun 26 06:13:51 PM PDT 24
Peak memory 200016 kb
Host smart-c33e97c1-c268-464d-9669-886f73ba6b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397216059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2397216059
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.3114181648
Short name T839
Test name
Test status
Simulation time 18056539396 ps
CPU time 9.15 seconds
Started Jun 26 06:13:07 PM PDT 24
Finished Jun 26 06:13:19 PM PDT 24
Peak memory 199968 kb
Host smart-a4119607-7577-4e7f-912f-ab81f89401c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114181648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.3114181648
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.2857937959
Short name T861
Test name
Test status
Simulation time 27485900384 ps
CPU time 269.64 seconds
Started Jun 26 06:13:11 PM PDT 24
Finished Jun 26 06:17:43 PM PDT 24
Peak memory 216404 kb
Host smart-092ce512-daec-465e-9a1d-4ca0666c422a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857937959 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.2857937959
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.4208575504
Short name T963
Test name
Test status
Simulation time 172387044389 ps
CPU time 94.21 seconds
Started Jun 26 06:13:11 PM PDT 24
Finished Jun 26 06:14:48 PM PDT 24
Peak memory 199956 kb
Host smart-42d2a4f4-ff27-46ae-b926-3d627004cde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208575504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.4208575504
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.1829729100
Short name T505
Test name
Test status
Simulation time 43750530852 ps
CPU time 615.37 seconds
Started Jun 26 06:13:09 PM PDT 24
Finished Jun 26 06:23:27 PM PDT 24
Peak memory 216576 kb
Host smart-7636c0ce-ce29-4574-8139-a02c5598bfc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829729100 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.1829729100
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.759480197
Short name T835
Test name
Test status
Simulation time 14908802 ps
CPU time 0.56 seconds
Started Jun 26 06:10:20 PM PDT 24
Finished Jun 26 06:10:23 PM PDT 24
Peak memory 195172 kb
Host smart-286145cc-88dd-4a07-9315-5d4e9ce5f011
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759480197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.759480197
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.753052721
Short name T984
Test name
Test status
Simulation time 53725990997 ps
CPU time 96.5 seconds
Started Jun 26 06:10:21 PM PDT 24
Finished Jun 26 06:12:00 PM PDT 24
Peak memory 199856 kb
Host smart-8f2301c8-9b38-47dd-8fb5-1f8f03e09b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753052721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.753052721
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.357753059
Short name T819
Test name
Test status
Simulation time 161915537349 ps
CPU time 175.53 seconds
Started Jun 26 06:10:34 PM PDT 24
Finished Jun 26 06:13:31 PM PDT 24
Peak memory 199884 kb
Host smart-b82a2d30-f9e6-4c59-9e40-b26ddc0aed02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357753059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.357753059
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.4023121133
Short name T209
Test name
Test status
Simulation time 49190673483 ps
CPU time 52.59 seconds
Started Jun 26 06:10:32 PM PDT 24
Finished Jun 26 06:11:27 PM PDT 24
Peak memory 199976 kb
Host smart-32cfb77b-400b-40fa-a8ed-4dd3b329eef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023121133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.4023121133
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.1642813893
Short name T686
Test name
Test status
Simulation time 14276141928 ps
CPU time 36.24 seconds
Started Jun 26 06:10:31 PM PDT 24
Finished Jun 26 06:11:09 PM PDT 24
Peak memory 199600 kb
Host smart-35976d69-06df-4d25-af2c-61301b75baf3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642813893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.1642813893
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2949074771
Short name T760
Test name
Test status
Simulation time 110438360844 ps
CPU time 481.84 seconds
Started Jun 26 06:10:18 PM PDT 24
Finished Jun 26 06:18:23 PM PDT 24
Peak memory 199980 kb
Host smart-c85da26c-1329-4524-85e1-ac7ad24787ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2949074771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2949074771
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.812883377
Short name T660
Test name
Test status
Simulation time 3657740120 ps
CPU time 4.56 seconds
Started Jun 26 06:10:29 PM PDT 24
Finished Jun 26 06:10:36 PM PDT 24
Peak memory 199144 kb
Host smart-2020d7a2-1fda-44df-b1a6-4196ef74a29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812883377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.812883377
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.4080378541
Short name T944
Test name
Test status
Simulation time 6769954270 ps
CPU time 9.72 seconds
Started Jun 26 06:10:20 PM PDT 24
Finished Jun 26 06:10:33 PM PDT 24
Peak memory 200036 kb
Host smart-675de1fb-620b-404a-8357-5ca7eb24f0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080378541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.4080378541
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.3587825666
Short name T864
Test name
Test status
Simulation time 20061435345 ps
CPU time 599.3 seconds
Started Jun 26 06:10:31 PM PDT 24
Finished Jun 26 06:20:32 PM PDT 24
Peak memory 199756 kb
Host smart-7913729b-d787-40b5-9fa1-a405f76a6f50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3587825666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3587825666
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.61814571
Short name T560
Test name
Test status
Simulation time 6733338095 ps
CPU time 36.99 seconds
Started Jun 26 06:10:19 PM PDT 24
Finished Jun 26 06:10:58 PM PDT 24
Peak memory 199252 kb
Host smart-55255aab-c1b3-4952-a38e-48173c46c5b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=61814571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.61814571
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.2153398293
Short name T134
Test name
Test status
Simulation time 82513100946 ps
CPU time 137.17 seconds
Started Jun 26 06:10:24 PM PDT 24
Finished Jun 26 06:12:44 PM PDT 24
Peak memory 199988 kb
Host smart-78178418-9adf-438f-a5f6-24ecdeb8d51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153398293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2153398293
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.2953879557
Short name T624
Test name
Test status
Simulation time 36313929263 ps
CPU time 47.58 seconds
Started Jun 26 06:10:23 PM PDT 24
Finished Jun 26 06:11:13 PM PDT 24
Peak memory 195952 kb
Host smart-ab10eebb-8d65-4ecb-a179-93d7d36855e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953879557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2953879557
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.2530584277
Short name T485
Test name
Test status
Simulation time 262441262 ps
CPU time 1.4 seconds
Started Jun 26 06:10:33 PM PDT 24
Finished Jun 26 06:10:37 PM PDT 24
Peak memory 198472 kb
Host smart-c1aef33e-a8d5-443c-abe0-0924bd3a737b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530584277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.2530584277
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.800326620
Short name T751
Test name
Test status
Simulation time 53510371814 ps
CPU time 436.86 seconds
Started Jun 26 06:10:18 PM PDT 24
Finished Jun 26 06:17:37 PM PDT 24
Peak memory 216516 kb
Host smart-8ce41767-2e9c-46a7-a7bd-7d238c9658d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800326620 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.800326620
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.2253231296
Short name T607
Test name
Test status
Simulation time 6291583929 ps
CPU time 8.49 seconds
Started Jun 26 06:10:31 PM PDT 24
Finished Jun 26 06:10:42 PM PDT 24
Peak memory 199864 kb
Host smart-d98e82d8-efdd-4b82-b805-f37153b14d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253231296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2253231296
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.37714339
Short name T892
Test name
Test status
Simulation time 26292134322 ps
CPU time 48.63 seconds
Started Jun 26 06:10:31 PM PDT 24
Finished Jun 26 06:11:26 PM PDT 24
Peak memory 199936 kb
Host smart-45796dd3-beae-4e98-b4f3-91b409479ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37714339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.37714339
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.1681157438
Short name T957
Test name
Test status
Simulation time 21981635468 ps
CPU time 38.46 seconds
Started Jun 26 06:13:08 PM PDT 24
Finished Jun 26 06:13:49 PM PDT 24
Peak memory 199904 kb
Host smart-193456be-6c84-44f1-a927-91c8bc061f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681157438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1681157438
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.3105707210
Short name T949
Test name
Test status
Simulation time 47661317732 ps
CPU time 171.51 seconds
Started Jun 26 06:13:11 PM PDT 24
Finished Jun 26 06:16:05 PM PDT 24
Peak memory 216188 kb
Host smart-ff742dc6-f067-4ae4-a224-0900686d7b01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105707210 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.3105707210
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.3141042648
Short name T352
Test name
Test status
Simulation time 62839392448 ps
CPU time 93.11 seconds
Started Jun 26 06:13:11 PM PDT 24
Finished Jun 26 06:14:47 PM PDT 24
Peak memory 199644 kb
Host smart-dd8ed830-1a66-4e83-bd23-f9c213263e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141042648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3141042648
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.2908481319
Short name T103
Test name
Test status
Simulation time 21240228836 ps
CPU time 38.38 seconds
Started Jun 26 06:13:08 PM PDT 24
Finished Jun 26 06:13:48 PM PDT 24
Peak memory 199880 kb
Host smart-7eb62476-4f05-4c98-be9f-96855d32ee69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908481319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.2908481319
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.2940954274
Short name T48
Test name
Test status
Simulation time 224692727567 ps
CPU time 1216.04 seconds
Started Jun 26 06:13:11 PM PDT 24
Finished Jun 26 06:33:29 PM PDT 24
Peak memory 224736 kb
Host smart-6a4b9305-2070-40fa-be29-0ed40bd93b62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940954274 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.2940954274
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.59973501
Short name T6
Test name
Test status
Simulation time 69624284846 ps
CPU time 29.42 seconds
Started Jun 26 06:13:15 PM PDT 24
Finished Jun 26 06:13:45 PM PDT 24
Peak memory 199964 kb
Host smart-6a558d09-c65c-43f4-9c4c-474303c8cdcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59973501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.59973501
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.3416115786
Short name T643
Test name
Test status
Simulation time 44318718227 ps
CPU time 580.78 seconds
Started Jun 26 06:13:12 PM PDT 24
Finished Jun 26 06:22:55 PM PDT 24
Peak memory 216520 kb
Host smart-7cec3487-4023-4133-b097-7b8d8353ccef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416115786 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.3416115786
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.109167941
Short name T271
Test name
Test status
Simulation time 147439509671 ps
CPU time 243.89 seconds
Started Jun 26 06:13:10 PM PDT 24
Finished Jun 26 06:17:17 PM PDT 24
Peak memory 199952 kb
Host smart-487dd8cc-2a62-46cb-a5b5-b797622c9549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109167941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.109167941
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.3434243509
Short name T46
Test name
Test status
Simulation time 92302553097 ps
CPU time 650.72 seconds
Started Jun 26 06:13:09 PM PDT 24
Finished Jun 26 06:24:02 PM PDT 24
Peak memory 216404 kb
Host smart-1a97bf68-de13-444d-86b3-ae689f75c8ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434243509 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.3434243509
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3865072505
Short name T238
Test name
Test status
Simulation time 11993196798 ps
CPU time 20.57 seconds
Started Jun 26 06:13:09 PM PDT 24
Finished Jun 26 06:13:32 PM PDT 24
Peak memory 199920 kb
Host smart-91d0a2bf-414d-466a-86f7-02c8d1139b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865072505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3865072505
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.1002965876
Short name T545
Test name
Test status
Simulation time 72775297389 ps
CPU time 34.83 seconds
Started Jun 26 06:13:11 PM PDT 24
Finished Jun 26 06:13:48 PM PDT 24
Peak memory 199856 kb
Host smart-dc567aa6-50fc-40d1-abb8-a1f610c40152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002965876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1002965876
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.374446125
Short name T35
Test name
Test status
Simulation time 29701603700 ps
CPU time 181.79 seconds
Started Jun 26 06:13:10 PM PDT 24
Finished Jun 26 06:16:14 PM PDT 24
Peak memory 216560 kb
Host smart-2609cf67-3451-4126-8167-3f5f937dd897
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374446125 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.374446125
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.1089392235
Short name T812
Test name
Test status
Simulation time 35201550445 ps
CPU time 60.49 seconds
Started Jun 26 06:13:08 PM PDT 24
Finished Jun 26 06:14:10 PM PDT 24
Peak memory 199980 kb
Host smart-bd8486db-936e-423a-b6d0-05a72da5481c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089392235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.1089392235
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.3125327486
Short name T47
Test name
Test status
Simulation time 145683563844 ps
CPU time 273.39 seconds
Started Jun 26 06:13:08 PM PDT 24
Finished Jun 26 06:17:44 PM PDT 24
Peak memory 216572 kb
Host smart-f38ab9f2-9d72-44d4-a84e-b3e19577e3b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125327486 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.3125327486
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.985425467
Short name T863
Test name
Test status
Simulation time 149684303668 ps
CPU time 233.43 seconds
Started Jun 26 06:13:10 PM PDT 24
Finished Jun 26 06:17:06 PM PDT 24
Peak memory 199884 kb
Host smart-e2537e55-f6f0-4a09-a530-7e507811dc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985425467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.985425467
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.3808929575
Short name T310
Test name
Test status
Simulation time 29979277438 ps
CPU time 317.21 seconds
Started Jun 26 06:13:09 PM PDT 24
Finished Jun 26 06:18:29 PM PDT 24
Peak memory 215620 kb
Host smart-d683d9a8-0725-48d9-b020-3c55c0c32bb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808929575 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.3808929575
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.2860630886
Short name T4
Test name
Test status
Simulation time 26948186611 ps
CPU time 34.14 seconds
Started Jun 26 06:13:10 PM PDT 24
Finished Jun 26 06:13:47 PM PDT 24
Peak memory 200000 kb
Host smart-de279f86-de39-433a-bd99-327232579016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860630886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.2860630886
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.2151275932
Short name T1015
Test name
Test status
Simulation time 45004433528 ps
CPU time 534.03 seconds
Started Jun 26 06:13:09 PM PDT 24
Finished Jun 26 06:22:05 PM PDT 24
Peak memory 216572 kb
Host smart-f0bf66aa-a926-4045-b605-e3f081c8b0a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151275932 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.2151275932
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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