Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	95138	1			T1	22		T2	12		T3	2
all_values[1]	95138	1			T1	22		T2	12		T3	2
all_values[2]	95138	1			T1	22		T2	12		T3	2
all_values[3]	95138	1			T1	22		T2	12		T3	2
all_values[4]	95138	1			T1	22		T2	12		T3	2
all_values[5]	95138	1			T1	22		T2	12		T3	2
all_values[6]	95138	1			T1	22		T2	12		T3	2
all_values[7]	95138	1			T1	22		T2	12		T3	2
all_values[8]	95138	1			T1	22		T2	12		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

440097

1

T1

71

T2

64

T3

18

auto[1]

416145

1

T1

127

T2

44

T4

87

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

778497

1

T1

154

T2

97

T3

13

auto[1]

77745

1

T1

44

T2

11

T3

5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	27429	1			T2	8		T4	1		T5	798
all_values[0]	auto[0]	auto[1]	22707	1			T1	16		T2	2		T3	2
all_values[0]	auto[1]	auto[0]	28520	1			T1	5		T4	6		T5	87
all_values[0]	auto[1]	auto[1]	16482	1			T1	1		T2	2		T4	2
all_values[1]	auto[0]	auto[0]	49358	1			T1	2		T2	5		T3	2
all_values[1]	auto[0]	auto[1]	1452	1			T4	7		T5	4		T11	9
all_values[1]	auto[1]	auto[0]	43056	1			T1	15		T2	7		T4	8
all_values[1]	auto[1]	auto[1]	1272	1			T1	5		T102	18		T18	12
all_values[2]	auto[0]	auto[0]	48360	1			T1	9		T2	6		T3	1
all_values[2]	auto[0]	auto[1]	2123	1			T1	1		T2	3		T3	1
all_values[2]	auto[1]	auto[0]	42729	1			T1	5		T2	3		T4	6
all_values[2]	auto[1]	auto[1]	1926	1			T1	7		T4	2		T5	1
all_values[3]	auto[0]	auto[0]	48035	1			T1	8		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	278	1			T12	1		T13	3		T18	2
all_values[3]	auto[1]	auto[0]	46575	1			T1	14		T2	10		T4	12
all_values[3]	auto[1]	auto[1]	250	1			T13	1		T14	1		T19	2
all_values[4]	auto[0]	auto[0]	50096	1			T1	3		T2	4		T3	2
all_values[4]	auto[0]	auto[1]	424	1			T18	9		T19	3		T20	8
all_values[4]	auto[1]	auto[0]	44267	1			T1	19		T2	8		T4	11
all_values[4]	auto[1]	auto[1]	351	1			T19	3		T20	2		T22	4
all_values[5]	auto[0]	auto[0]	44187	1			T1	8		T2	5		T3	2
all_values[5]	auto[0]	auto[1]	141	1			T19	2		T20	1		T103	1
all_values[5]	auto[1]	auto[0]	50642	1			T1	14		T2	7		T4	10
all_values[5]	auto[1]	auto[1]	168	1			T19	1		T20	1		T103	2
all_values[6]	auto[0]	auto[0]	50225	1			T1	8		T2	12		T3	2
all_values[6]	auto[0]	auto[1]	132	1			T19	2		T20	1		T34	1
all_values[6]	auto[1]	auto[0]	44629	1			T1	14		T4	11		T5	285
all_values[6]	auto[1]	auto[1]	152	1			T20	4		T34	1		T99	3
all_values[7]	auto[0]	auto[0]	42815	1			T1	13		T2	7		T3	2
all_values[7]	auto[0]	auto[1]	277	1			T18	3		T20	2		T25	1
all_values[7]	auto[1]	auto[0]	51788	1			T1	9		T2	5		T4	9
all_values[7]	auto[1]	auto[1]	258	1			T19	4		T20	1		T25	1
all_values[8]	auto[0]	auto[0]	35804	1			T2	8		T5	686		T6	1
all_values[8]	auto[0]	auto[1]	16254	1			T1	3		T2	2		T3	2
all_values[8]	auto[1]	auto[0]	29982	1			T1	8		T4	7		T5	211
all_values[8]	auto[1]	auto[1]	13098	1			T1	11		T2	2		T4	3