Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1848	1			T1	1		T2	1		T4	3
auto[BaudRate115200]	1508	1			T1	2		T2	3		T4	1
auto[BaudRate230400]	1520	1			T1	1		T2	1		T3	1
auto[BaudRate128Kbps]	1557	1			T1	2		T2	3		T4	2
auto[BaudRate256Kbps]	1697	1			T1	1		T2	5		T5	2
auto[BaudRate1Mbps]	1387	1			T2	3		T3	1		T4	2
auto[BaudRate1p5Mbps]	948	1			T1	1		T5	4		T6	3

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	975	1			T114	10		T19	38		T42	8
freqs[25]	852	1			T44	10		T95	2		T34	18
freqs[48]	348	1			T260	5		T253	2		T129	10
freqs[50]	608	1			T21	20		T24	12		T13	7
freqs[100]	848	1			T5	14		T41	8		T59	8

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	178	1			T114	1		T19	1		T43	1
auto[BaudRate9600]	freqs[25]	120	1			T44	4		T34	2		T307	1
auto[BaudRate9600]	freqs[48]	63	1			T253	1		T129	2		T213	1
auto[BaudRate9600]	freqs[50]	80	1			T21	2		T24	3		T13	1
auto[BaudRate9600]	freqs[100]	136	1			T5	1		T41	1		T59	1
auto[BaudRate115200]	freqs[24]	171	1			T114	3		T19	3		T42	2
auto[BaudRate115200]	freqs[25]	103	1			T44	1		T133	2		T256	3
auto[BaudRate115200]	freqs[48]	46	1			T253	1		T129	2		T213	3
auto[BaudRate115200]	freqs[50]	78	1			T21	3		T24	3		T13	1
auto[BaudRate115200]	freqs[100]	128	1			T5	2		T59	2		T248	2
auto[BaudRate230400]	freqs[24]	137	1			T114	1		T19	4		T134	1
auto[BaudRate230400]	freqs[25]	122	1			T34	3		T133	2		T300	1
auto[BaudRate230400]	freqs[48]	47	1			T260	1		T296	2		T213	2
auto[BaudRate230400]	freqs[50]	88	1			T21	2		T13	1		T105	1
auto[BaudRate230400]	freqs[100]	102	1			T5	1		T41	2		T59	2
auto[BaudRate128Kbps]	freqs[24]	140	1			T114	1		T19	6		T42	2
auto[BaudRate128Kbps]	freqs[25]	125	1			T44	1		T95	1		T34	2
auto[BaudRate128Kbps]	freqs[48]	48	1			T129	1		T296	1		T141	1
auto[BaudRate128Kbps]	freqs[50]	102	1			T21	4		T24	3		T13	1
auto[BaudRate128Kbps]	freqs[100]	127	1			T5	2		T59	2		T271	2
auto[BaudRate256Kbps]	freqs[24]	124	1			T114	3		T19	6		T42	1
auto[BaudRate256Kbps]	freqs[25]	128	1			T44	1		T34	7		T133	4
auto[BaudRate256Kbps]	freqs[48]	56	1			T260	4		T129	2		T213	1
auto[BaudRate256Kbps]	freqs[50]	95	1			T21	3		T13	1		T180	1
auto[BaudRate256Kbps]	freqs[100]	120	1			T5	2		T41	2		T248	1
auto[BaudRate1Mbps]	freqs[24]	153	1			T19	11		T42	3		T134	2
auto[BaudRate1Mbps]	freqs[25]	166	1			T44	1		T95	1		T34	4
auto[BaudRate1Mbps]	freqs[48]	45	1			T129	2		T213	1		T310	1
auto[BaudRate1Mbps]	freqs[50]	89	1			T21	4		T13	1		T258	1
auto[BaudRate1Mbps]	freqs[100]	128	1			T5	2		T41	2		T59	1
auto[BaudRate1p5Mbps]	freqs[25]	88	1			T44	2		T133	1		T280	1
auto[BaudRate1p5Mbps]	freqs[48]	43	1			T129	1		T141	1		T215	2
auto[BaudRate1p5Mbps]	freqs[50]	76	1			T21	2		T24	3		T13	1
auto[BaudRate1p5Mbps]	freqs[100]	107	1			T5	4		T41	1		T249	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded