Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	11	119	91.54

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	11	119	91.54	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	26263547	1			T1	31		T2	115		T4	51
all_levels[1]	153729	1			T2	1		T4	2		T5	132
all_levels[2]	1721	1			T1	1		T2	1		T5	2
all_levels[3]	769	1			T5	1		T6	1		T7	1
all_levels[4]	568	1			T5	1		T6	2		T7	2
all_levels[5]	444	1			T1	2		T2	1		T5	3
all_levels[6]	300	1			T5	1		T11	1		T21	1
all_levels[7]	229	1			T1	1		T6	3		T113	2
all_levels[8]	234	1			T1	1		T6	2		T40	2
all_levels[9]	169	1			T40	1		T44	1		T92	1
all_levels[10]	171	1			T6	3		T21	1		T39	1
all_levels[11]	180	1			T11	1		T12	3		T102	2
all_levels[12]	122	1			T113	2		T114	1		T46	2
all_levels[13]	155	1			T13	1		T40	1		T113	5
all_levels[14]	121	1			T2	1		T12	2		T113	1
all_levels[15]	128	1			T21	1		T40	1		T113	1
all_levels[16]	118	1			T21	3		T39	1		T115	2
all_levels[17]	73	1			T116	1		T103	1		T104	1
all_levels[18]	85	1			T12	1		T33	2		T116	1
all_levels[19]	85	1			T117	3		T118	1		T46	1
all_levels[20]	70	1			T1	1		T115	1		T103	2
all_levels[21]	65	1			T21	1		T13	1		T115	3
all_levels[22]	45	1			T46	1		T116	1		T34	2
all_levels[23]	39	1			T119	2		T120	1		T121	1
all_levels[24]	58	1			T13	2		T113	1		T116	1
all_levels[25]	50	1			T113	1		T104	1		T122	2
all_levels[26]	59	1			T20	1		T123	1		T124	3
all_levels[27]	33	1			T18	1		T33	1		T104	1
all_levels[28]	18	1			T21	1		T103	1		T125	1
all_levels[29]	37	1			T116	2		T126	1		T123	1
all_levels[30]	32	1			T39	1		T103	1		T120	1
all_levels[31]	33	1			T103	1		T127	1		T128	2
all_levels[32]	28	1			T103	1		T129	1		T130	1
all_levels[33]	27	1			T118	1		T129	1		T99	1
all_levels[34]	29	1			T4	1		T131	1		T132	1
all_levels[35]	25	1			T116	2		T133	1		T129	1
all_levels[36]	30	1			T33	1		T103	2		T134	1
all_levels[37]	26	1			T33	1		T110	1		T135	1
all_levels[38]	16	1			T37	1		T136	1		T86	1
all_levels[39]	17	1			T137	1		T138	3		T139	2
all_levels[40]	13	1			T110	1		T138	1		T140	1
all_levels[41]	21	1			T141	1		T135	1		T142	1
all_levels[42]	7	1			T18	1		T143	1		T128	1
all_levels[43]	20	1			T117	1		T144	2		T137	1
all_levels[44]	15	1			T137	1		T99	1		T145	2
all_levels[45]	14	1			T118	4		T92	1		T143	1
all_levels[46]	13	1			T117	1		T33	1		T146	1
all_levels[47]	9	1			T4	1		T13	1		T147	1
all_levels[48]	14	1			T110	1		T128	1		T148	1
all_levels[49]	15	1			T21	3		T149	2		T150	1
all_levels[50]	16	1			T151	1		T143	1		T152	2
all_levels[51]	13	1			T25	1		T103	1		T153	1
all_levels[52]	5	1			T154	1		T155	1		T156	1
all_levels[53]	6	1			T25	1		T137	1		T157	1
all_levels[54]	8	1			T92	1		T131	1		T158	1
all_levels[55]	9	1			T159	1		T153	1		T158	1
all_levels[56]	9	1			T160	1		T161	2		T162	1
all_levels[57]	4	1			T158	1		T163	1		T155	1
all_levels[58]	5	1			T164	1		T165	3		T166	1
all_levels[59]	7	1			T150	1		T167	1		T168	3
all_levels[60]	5	1			T20	2		T37	1		T169	1
all_levels[61]	4	1			T20	1		T86	1		T162	1
all_levels[62]	5	1			T170	1		T88	1		T171	2
all_levels[63]	7	1			T121	1		T147	1		T172	1
all_levels[64]	106	1			T13	1		T14	1		T18	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26419772

1

T1

37

T2

119

T4

55

auto[1]

4263

1

T5

1

T6

9

T21

7

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	11	119	91.54	11

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[42]]	[auto[1]]	0	1	1
[all_levels[46] , all_levels[47]]	[auto[1]]	--	--	2
[all_levels[52] , all_levels[53] , all_levels[54] , all_levels[55]]	[auto[1]]	--	--	4
[all_levels[57]]	[auto[1]]	0	1	1
[all_levels[60] , all_levels[61]]	[auto[1]]	--	--	2
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	26259757	1			T1	31		T2	115		T4	51
all_levels[0]	auto[1]	3790	1			T5	1		T6	7		T21	3
all_levels[1]	auto[0]	153657	1			T2	1		T4	2		T5	132
all_levels[1]	auto[1]	72	1			T42	2		T44	1		T46	1
all_levels[2]	auto[0]	1695	1			T1	1		T2	1		T5	2
all_levels[2]	auto[1]	26	1			T21	2		T115	1		T173	1
all_levels[3]	auto[0]	749	1			T5	1		T6	1		T7	1
all_levels[3]	auto[1]	20	1			T118	1		T174	1		T175	1
all_levels[4]	auto[0]	546	1			T5	1		T6	2		T7	2
all_levels[4]	auto[1]	22	1			T14	1		T118	2		T44	1
all_levels[5]	auto[0]	431	1			T1	2		T2	1		T5	3
all_levels[5]	auto[1]	13	1			T176	2		T177	2		T178	1
all_levels[6]	auto[0]	283	1			T5	1		T11	1		T21	1
all_levels[6]	auto[1]	17	1			T132	3		T127	2		T157	1
all_levels[7]	auto[0]	218	1			T1	1		T6	3		T113	2
all_levels[7]	auto[1]	11	1			T117	2		T59	1		T179	3
all_levels[8]	auto[0]	221	1			T1	1		T6	1		T40	2
all_levels[8]	auto[1]	13	1			T6	1		T180	1		T181	2
all_levels[9]	auto[0]	164	1			T40	1		T44	1		T92	1
all_levels[9]	auto[1]	5	1			T182	1		T183	1		T184	1
all_levels[10]	auto[0]	161	1			T6	2		T21	1		T39	1
all_levels[10]	auto[1]	10	1			T6	1		T124	1		T185	2
all_levels[11]	auto[0]	167	1			T11	1		T12	2		T102	2
all_levels[11]	auto[1]	13	1			T12	1		T186	2		T187	2
all_levels[12]	auto[0]	114	1			T113	2		T114	1		T46	1
all_levels[12]	auto[1]	8	1			T46	1		T188	1		T189	1
all_levels[13]	auto[0]	143	1			T13	1		T40	1		T113	5
all_levels[13]	auto[1]	12	1			T46	1		T190	2		T181	1
all_levels[14]	auto[0]	112	1			T2	1		T12	1		T113	1
all_levels[14]	auto[1]	9	1			T12	1		T191	1		T192	1
all_levels[15]	auto[0]	111	1			T21	1		T40	1		T113	1
all_levels[15]	auto[1]	17	1			T131	2		T190	1		T145	1
all_levels[16]	auto[0]	107	1			T21	3		T39	1		T115	2
all_levels[16]	auto[1]	11	1			T193	1		T194	2		T195	1
all_levels[17]	auto[0]	70	1			T116	1		T103	1		T104	1
all_levels[17]	auto[1]	3	1			T196	1		T197	1		T198	1
all_levels[18]	auto[0]	80	1			T12	1		T33	2		T116	1
all_levels[18]	auto[1]	5	1			T183	1		T199	1		T200	2
all_levels[19]	auto[0]	69	1			T117	1		T118	1		T46	1
all_levels[19]	auto[1]	16	1			T117	2		T201	3		T202	2
all_levels[20]	auto[0]	56	1			T1	1		T115	1		T103	2
all_levels[20]	auto[1]	14	1			T190	1		T203	5		T204	1
all_levels[21]	auto[0]	55	1			T21	1		T13	1		T115	3
all_levels[21]	auto[1]	10	1			T151	2		T205	2		T192	1
all_levels[22]	auto[0]	44	1			T46	1		T116	1		T34	2
all_levels[22]	auto[1]	1	1			T202	1		-	-		-	-
all_levels[23]	auto[0]	35	1			T119	1		T120	1		T121	1
all_levels[23]	auto[1]	4	1			T119	1		T127	2		T206	1
all_levels[24]	auto[0]	47	1			T13	1		T113	1		T116	1
all_levels[24]	auto[1]	11	1			T13	1		T207	2		T193	1
all_levels[25]	auto[0]	41	1			T113	1		T104	1		T122	1
all_levels[25]	auto[1]	9	1			T122	1		T208	1		T209	2
all_levels[26]	auto[0]	48	1			T20	1		T123	1		T124	1
all_levels[26]	auto[1]	11	1			T124	2		T140	2		T210	1
all_levels[27]	auto[0]	31	1			T18	1		T33	1		T104	1
all_levels[27]	auto[1]	2	1			T211	1		T212	1		-	-
all_levels[28]	auto[0]	17	1			T21	1		T103	1		T125	1
all_levels[28]	auto[1]	1	1			T213	1		-	-		-	-
all_levels[29]	auto[0]	36	1			T116	2		T126	1		T123	1
all_levels[29]	auto[1]	1	1			T214	1		-	-		-	-
all_levels[30]	auto[0]	30	1			T39	1		T103	1		T120	1
all_levels[30]	auto[1]	2	1			T215	1		T216	1		-	-
all_levels[31]	auto[0]	28	1			T103	1		T127	1		T128	1
all_levels[31]	auto[1]	5	1			T128	1		T217	1		T218	1
all_levels[32]	auto[0]	24	1			T103	1		T129	1		T130	1
all_levels[32]	auto[1]	4	1			T219	2		T192	1		T220	1
all_levels[33]	auto[0]	20	1			T118	1		T129	1		T99	1
all_levels[33]	auto[1]	7	1			T221	1		T222	1		T223	2
all_levels[34]	auto[0]	24	1			T4	1		T131	1		T132	1
all_levels[34]	auto[1]	5	1			T224	1		T212	1		T225	3
all_levels[35]	auto[0]	21	1			T116	1		T133	1		T129	1
all_levels[35]	auto[1]	4	1			T116	1		T226	2		T227	1
all_levels[36]	auto[0]	26	1			T33	1		T103	2		T134	1
all_levels[36]	auto[1]	4	1			T228	4		-	-		-	-
all_levels[37]	auto[0]	12	1			T33	1		T110	1		T135	1
all_levels[37]	auto[1]	14	1			T229	9		T230	1		T231	4
all_levels[38]	auto[0]	14	1			T37	1		T136	1		T86	1
all_levels[38]	auto[1]	2	1			T232	1		T233	1		-	-
all_levels[39]	auto[0]	12	1			T137	1		T138	1		T139	1
all_levels[39]	auto[1]	5	1			T138	2		T139	1		T234	2
all_levels[40]	auto[0]	11	1			T110	1		T138	1		T140	1
all_levels[40]	auto[1]	2	1			T235	1		T236	1		-	-
all_levels[41]	auto[0]	18	1			T141	1		T135	1		T142	1
all_levels[41]	auto[1]	3	1			T237	1		T238	2		-	-
all_levels[42]	auto[0]	7	1			T18	1		T143	1		T128	1
all_levels[43]	auto[0]	18	1			T117	1		T144	1		T137	1
all_levels[43]	auto[1]	2	1			T144	1		T239	1		-	-
all_levels[44]	auto[0]	14	1			T137	1		T99	1		T145	1
all_levels[44]	auto[1]	1	1			T145	1		-	-		-	-
all_levels[45]	auto[0]	11	1			T118	1		T92	1		T143	1
all_levels[45]	auto[1]	3	1			T118	3		-	-		-	-
all_levels[46]	auto[0]	13	1			T117	1		T33	1		T146	1
all_levels[47]	auto[0]	9	1			T4	1		T13	1		T147	1
all_levels[48]	auto[0]	12	1			T110	1		T128	1		T148	1
all_levels[48]	auto[1]	2	1			T240	1		T231	1		-	-
all_levels[49]	auto[0]	11	1			T21	1		T149	1		T150	1
all_levels[49]	auto[1]	4	1			T21	2		T149	1		T237	1
all_levels[50]	auto[0]	8	1			T151	1		T143	1		T152	1
all_levels[50]	auto[1]	8	1			T152	1		T241	5		T212	2
all_levels[51]	auto[0]	11	1			T25	1		T103	1		T153	1
all_levels[51]	auto[1]	2	1			T154	2		-	-		-	-
all_levels[52]	auto[0]	5	1			T154	1		T155	1		T156	1
all_levels[53]	auto[0]	6	1			T25	1		T137	1		T157	1
all_levels[54]	auto[0]	8	1			T92	1		T131	1		T158	1
all_levels[55]	auto[0]	9	1			T159	1		T153	1		T158	1
all_levels[56]	auto[0]	8	1			T160	1		T161	1		T162	1
all_levels[56]	auto[1]	1	1			T161	1		-	-		-	-
all_levels[57]	auto[0]	4	1			T158	1		T163	1		T155	1
all_levels[58]	auto[0]	3	1			T164	1		T165	1		T166	1
all_levels[58]	auto[1]	2	1			T165	2		-	-		-	-
all_levels[59]	auto[0]	4	1			T150	1		T167	1		T168	1
all_levels[59]	auto[1]	3	1			T168	2		T242	1		-	-
all_levels[60]	auto[0]	5	1			T20	2		T37	1		T169	1
all_levels[61]	auto[0]	4	1			T20	1		T86	1		T162	1
all_levels[62]	auto[0]	4	1			T170	1		T88	1		T171	1
all_levels[62]	auto[1]	1	1			T171	1		-	-		-	-
all_levels[63]	auto[0]	7	1			T121	1		T147	1		T172	1
all_levels[64]	auto[0]	86	1			T13	1		T14	1		T18	1
all_levels[64]	auto[1]	20	1			T138	1		T109	2		T243	1