Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	95138	1			T1	22		T2	12		T3	2
all_pins[1]	95138	1			T1	22		T2	12		T3	2
all_pins[2]	95138	1			T1	22		T2	12		T3	2
all_pins[3]	95138	1			T1	22		T2	12		T3	2
all_pins[4]	95138	1			T1	22		T2	12		T3	2
all_pins[5]	95138	1			T1	22		T2	12		T3	2
all_pins[6]	95138	1			T1	22		T2	12		T3	2
all_pins[7]	95138	1			T1	22		T2	12		T3	2
all_pins[8]	95138	1			T1	22		T2	12		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	821611	1			T1	174		T2	104		T3	18
values[0x1]	34631	1			T1	24		T2	4		T4	7
transitions[0x0=>0x1]	27591	1			T1	24		T2	3		T4	6
transitions[0x1=>0x0]	27413	1			T1	24		T2	3		T4	5

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	78611	1			T1	21		T2	10		T3	2
all_pins[0]	values[0x1]	16527	1			T1	1		T2	2		T4	2
all_pins[0]	transitions[0x0=>0x1]	16084	1			T1	1		T2	2		T4	2
all_pins[0]	transitions[0x1=>0x0]	826	1			T1	5		T102	18		T18	12
all_pins[1]	values[0x0]	93869	1			T1	17		T2	12		T3	2
all_pins[1]	values[0x1]	1269	1			T1	5		T102	18		T18	12
all_pins[1]	transitions[0x0=>0x1]	1203	1			T1	5		T102	18		T18	12
all_pins[1]	transitions[0x1=>0x0]	1907	1			T1	7		T4	2		T5	1
all_pins[2]	values[0x0]	93165	1			T1	15		T2	12		T3	2
all_pins[2]	values[0x1]	1973	1			T1	7		T4	2		T5	1
all_pins[2]	transitions[0x0=>0x1]	1917	1			T1	7		T4	2		T5	1
all_pins[2]	transitions[0x1=>0x0]	194	1			T19	2		T44	1		T33	1
all_pins[3]	values[0x0]	94888	1			T1	22		T2	12		T3	2
all_pins[3]	values[0x1]	250	1			T13	1		T14	1		T19	2
all_pins[3]	transitions[0x0=>0x1]	219	1			T13	1		T14	1		T19	2
all_pins[3]	transitions[0x1=>0x0]	320	1			T19	3		T20	2		T22	4
all_pins[4]	values[0x0]	94787	1			T1	22		T2	12		T3	2
all_pins[4]	values[0x1]	351	1			T19	3		T20	2		T22	4
all_pins[4]	transitions[0x0=>0x1]	281	1			T19	3		T20	2		T22	4
all_pins[4]	transitions[0x1=>0x0]	144	1			T18	2		T19	1		T20	3
all_pins[5]	values[0x0]	94924	1			T1	22		T2	12		T3	2
all_pins[5]	values[0x1]	214	1			T18	2		T19	1		T20	3
all_pins[5]	transitions[0x0=>0x1]	174	1			T18	2		T19	1		T20	2
all_pins[5]	transitions[0x1=>0x0]	615	1			T11	3		T21	1		T117	1
all_pins[6]	values[0x0]	94483	1			T1	22		T2	12		T3	2
all_pins[6]	values[0x1]	655	1			T11	3		T21	1		T117	1
all_pins[6]	transitions[0x0=>0x1]	623	1			T11	3		T21	1		T117	1
all_pins[6]	transitions[0x1=>0x0]	226	1			T19	4		T20	1		T25	1
all_pins[7]	values[0x0]	94880	1			T1	22		T2	12		T3	2
all_pins[7]	values[0x1]	258	1			T19	4		T20	1		T25	1
all_pins[7]	transitions[0x0=>0x1]	159	1			T19	2		T20	1		T25	1
all_pins[7]	transitions[0x1=>0x0]	13035	1			T1	11		T2	2		T4	3
all_pins[8]	values[0x0]	82004	1			T1	11		T2	10		T3	2
all_pins[8]	values[0x1]	13134	1			T1	11		T2	2		T4	3
all_pins[8]	transitions[0x0=>0x1]	6931	1			T1	11		T2	1		T4	2
all_pins[8]	transitions[0x1=>0x0]	10146	1			T1	1		T2	1		T5	7