Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	6843862	1			T1	7		T2	22		T4	8
all_levels[1]	1719971	1			T1	4		T2	10		T4	1
all_levels[2]	333737	1			T2	34		T4	10		T5	278
all_levels[3]	313653	1			T4	2		T5	278		T6	1
all_levels[4]	412604	1			T1	3		T2	6		T5	275
all_levels[5]	207972	1			T2	2		T4	1		T5	275
all_levels[6]	269521	1			T2	4		T4	2		T5	207
all_levels[7]	205636	1			T2	1		T5	127		T7	3
all_levels[8]	185734	1			T4	2		T5	127		T6	3
all_levels[9]	189159	1			T2	1		T5	278		T6	1
all_levels[10]	190426	1			T5	176		T7	2		T11	10
all_levels[11]	413209	1			T2	2		T5	143		T6	2
all_levels[12]	184839	1			T2	21		T4	1		T5	159
all_levels[13]	244227	1			T5	279		T6	4		T7	3
all_levels[14]	184261	1			T4	3		T5	278		T6	2
all_levels[15]	225234	1			T1	12		T2	10		T4	2
all_levels[16]	336666	1			T4	1		T5	271		T7	2
all_levels[17]	175990	1			T4	2		T5	278		T7	1
all_levels[18]	191923	1			T4	2		T5	278		T6	13
all_levels[19]	241004	1			T4	2		T5	228		T7	2
all_levels[20]	206445	1			T4	2		T5	138		T11	2
all_levels[21]	420418	1			T1	4		T5	131		T7	21
all_levels[22]	187532	1			T5	222		T7	1		T102	1
all_levels[23]	173303	1			T5	224		T7	4		T21	9
all_levels[24]	648134	1			T5	134		T7	4		T11	2
all_levels[25]	297653	1			T4	1		T5	220		T7	1
all_levels[26]	275797	1			T5	278		T7	5		T11	1
all_levels[27]	173692	1			T2	2		T5	278		T11	2
all_levels[28]	217723	1			T4	2		T5	275		T11	2
all_levels[29]	172645	1			T5	277		T7	3		T11	3
all_levels[30]	382332	1			T2	2		T4	2		T5	201
all_levels[31]	431341	1			T2	3		T5	212		T7	3
all_levels[32]	9767035	1			T1	8		T4	9		T5	341212

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26419772

1

T1

37

T2

119

T4

55

auto[1]

3906

1

T1

1

T2

1

T5

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	6841496	1			T1	7		T2	22		T4	8
all_levels[0]	auto[1]	2366	1			T5	1		T6	6		T21	3
all_levels[1]	auto[0]	1719734	1			T1	4		T2	10		T4	1
all_levels[1]	auto[1]	237	1			T14	1		T115	3		T44	1
all_levels[2]	auto[0]	333702	1			T2	34		T4	10		T5	278
all_levels[2]	auto[1]	35	1			T12	1		T190	1		T270	1
all_levels[3]	auto[0]	313563	1			T4	2		T5	278		T6	1
all_levels[3]	auto[1]	90	1			T122	2		T138	2		T277	1
all_levels[4]	auto[0]	412570	1			T1	3		T2	6		T5	275
all_levels[4]	auto[1]	34	1			T13	1		T115	1		T46	1
all_levels[5]	auto[0]	207936	1			T2	2		T4	1		T5	275
all_levels[5]	auto[1]	36	1			T62	4		T144	1		T173	1
all_levels[6]	auto[0]	269489	1			T2	4		T4	2		T5	207
all_levels[6]	auto[1]	32	1			T190	1		T122	2		T211	1
all_levels[7]	auto[0]	205583	1			T2	1		T5	127		T7	3
all_levels[7]	auto[1]	53	1			T151	1		T302	3		T325	1
all_levels[8]	auto[0]	185714	1			T4	2		T5	127		T6	3
all_levels[8]	auto[1]	20	1			T117	1		T190	1		T243	1
all_levels[9]	auto[0]	189128	1			T2	1		T5	278		T6	1
all_levels[9]	auto[1]	31	1			T44	5		T92	2		T180	1
all_levels[10]	auto[0]	190397	1			T5	176		T7	2		T11	10
all_levels[10]	auto[1]	29	1			T40	1		T271	4		T124	3
all_levels[11]	auto[0]	413190	1			T2	2		T5	143		T6	2
all_levels[11]	auto[1]	19	1			T180	1		T243	1		T136	1
all_levels[12]	auto[0]	184824	1			T2	21		T4	1		T5	159
all_levels[12]	auto[1]	15	1			T14	1		T46	1		T116	1
all_levels[13]	auto[0]	244184	1			T5	279		T6	4		T7	3
all_levels[13]	auto[1]	43	1			T59	1		T291	1		T326	1
all_levels[14]	auto[0]	184238	1			T4	3		T5	278		T6	2
all_levels[14]	auto[1]	23	1			T115	1		T211	2		T327	1
all_levels[15]	auto[0]	225157	1			T1	11		T2	9		T4	2
all_levels[15]	auto[1]	77	1			T1	1		T2	1		T93	1
all_levels[16]	auto[0]	336649	1			T4	1		T5	271		T7	2
all_levels[16]	auto[1]	17	1			T151	1		T328	1		T329	1
all_levels[17]	auto[0]	175972	1			T4	2		T5	278		T7	1
all_levels[17]	auto[1]	18	1			T12	2		T190	2		T151	2
all_levels[18]	auto[0]	191905	1			T4	2		T5	278		T6	12
all_levels[18]	auto[1]	18	1			T6	1		T40	1		T134	1
all_levels[19]	auto[0]	240990	1			T4	2		T5	228		T7	2
all_levels[19]	auto[1]	14	1			T39	2		T272	1		T136	3
all_levels[20]	auto[0]	206422	1			T4	2		T5	138		T11	2
all_levels[20]	auto[1]	23	1			T113	1		T136	2		T330	2
all_levels[21]	auto[0]	420397	1			T1	4		T5	131		T7	21
all_levels[21]	auto[1]	21	1			T202	2		T154	3		T331	4
all_levels[22]	auto[0]	187522	1			T5	222		T7	1		T102	1
all_levels[22]	auto[1]	10	1			T173	1		T332	1		T177	2
all_levels[23]	auto[0]	173281	1			T5	224		T7	4		T21	7
all_levels[23]	auto[1]	22	1			T21	2		T117	1		T173	1
all_levels[24]	auto[0]	648105	1			T5	134		T7	4		T11	2
all_levels[24]	auto[1]	29	1			T119	2		T138	1		T280	4
all_levels[25]	auto[0]	297639	1			T4	1		T5	220		T7	1
all_levels[25]	auto[1]	14	1			T42	2		T146	1		T333	1
all_levels[26]	auto[0]	275779	1			T5	278		T7	5		T11	1
all_levels[26]	auto[1]	18	1			T145	2		T130	2		T140	1
all_levels[27]	auto[0]	173676	1			T2	2		T5	278		T11	2
all_levels[27]	auto[1]	16	1			T116	1		T173	1		T315	2
all_levels[28]	auto[0]	217699	1			T4	2		T5	275		T11	2
all_levels[28]	auto[1]	24	1			T185	2		T334	1		T335	1
all_levels[29]	auto[0]	172634	1			T5	277		T7	3		T11	3
all_levels[29]	auto[1]	11	1			T41	1		T33	1		T271	1
all_levels[30]	auto[0]	382315	1			T2	2		T4	2		T5	201
all_levels[30]	auto[1]	17	1			T14	1		T132	1		T336	1
all_levels[31]	auto[0]	431318	1			T2	3		T5	212		T7	3
all_levels[31]	auto[1]	23	1			T127	2		T305	1		T157	1
all_levels[32]	auto[0]	9766564	1			T1	8		T4	9		T5	341212
all_levels[32]	auto[1]	471	1			T7	1		T21	1		T12	2