Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	596	1			T19	7		T20	7		T34	4
all_values[1]	596	1			T19	7		T20	7		T34	4
all_values[2]	596	1			T19	7		T20	7		T34	4
all_values[3]	596	1			T19	7		T20	7		T34	4
all_values[4]	596	1			T19	7		T20	7		T34	4
all_values[5]	596	1			T19	7		T20	7		T34	4
all_values[6]	596	1			T19	7		T20	7		T34	4
all_values[7]	596	1			T19	7		T20	7		T34	4
all_values[8]	596	1			T19	7		T20	7		T34	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3015

1

T19

31

T20

31

T34

16

auto[1]

2349

1

T19

32

T20

32

T34

20

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1688

1

T19

19

T20

17

T34

9

auto[1]

3676

1

T19

44

T20

46

T34

27

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3134

1

T19

32

T20

31

T34

20

auto[1]

2230

1

T19

31

T20

32

T34

16

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	182	1			T19	2		T20	1		T34	2
all_values[0]	auto[0]	auto[1]	auto[1]	159	1			T20	2		T34	1		T103	3
all_values[0]	auto[1]	auto[0]	auto[1]	142	1			T19	2		T20	2		T103	2
all_values[0]	auto[1]	auto[1]	auto[1]	113	1			T19	3		T20	2		T34	1
all_values[1]	auto[0]	auto[0]	auto[0]	205	1			T19	1		T20	4		T34	1
all_values[1]	auto[0]	auto[1]	auto[0]	165	1			T19	2		T34	1		T103	4
all_values[1]	auto[1]	auto[0]	auto[1]	132	1			T20	1		T34	2		T99	2
all_values[1]	auto[1]	auto[1]	auto[1]	94	1			T19	4		T20	2		T103	1
all_values[2]	auto[0]	auto[0]	auto[0]	134	1			T19	1		T34	1		T110	1
all_values[2]	auto[0]	auto[0]	auto[1]	74	1			T19	1		T20	1		T103	1
all_values[2]	auto[0]	auto[1]	auto[0]	84	1			T19	3		T103	1		T110	2
all_values[2]	auto[0]	auto[1]	auto[1]	54	1			T20	1		T34	1		T103	1
all_values[2]	auto[1]	auto[0]	auto[1]	156	1			T19	2		T20	4		T103	2
all_values[2]	auto[1]	auto[1]	auto[1]	94	1			T20	1		T34	2		T103	2
all_values[3]	auto[0]	auto[0]	auto[0]	130	1			T19	1		T20	3		T103	2
all_values[3]	auto[0]	auto[0]	auto[1]	58	1			T19	1		T34	1		T99	2
all_values[3]	auto[0]	auto[1]	auto[0]	110	1			T19	2		T20	2		T34	1
all_values[3]	auto[0]	auto[1]	auto[1]	56	1			T35	2		T36	1		T111	1
all_values[3]	auto[1]	auto[0]	auto[1]	144	1			T19	2		T20	2		T103	2
all_values[3]	auto[1]	auto[1]	auto[1]	98	1			T19	1		T34	2		T103	1
all_values[4]	auto[0]	auto[0]	auto[0]	125	1			T19	1		T103	2		T110	3
all_values[4]	auto[0]	auto[0]	auto[1]	78	1			T19	1		T103	1		T99	1
all_values[4]	auto[0]	auto[1]	auto[0]	78	1			T20	3		T103	1		T35	4
all_values[4]	auto[0]	auto[1]	auto[1]	61	1			T19	1		T20	1		T34	1
all_values[4]	auto[1]	auto[0]	auto[1]	149	1			T19	2		T20	1		T34	2
all_values[4]	auto[1]	auto[1]	auto[1]	105	1			T19	2		T20	2		T34	1
all_values[5]	auto[0]	auto[0]	auto[0]	111	1			T34	2		T103	1		T110	1
all_values[5]	auto[0]	auto[0]	auto[1]	60	1			T19	1		T110	1		T35	1
all_values[5]	auto[0]	auto[1]	auto[0]	84	1			T19	3		T20	2		T34	1
all_values[5]	auto[0]	auto[1]	auto[1]	80	1			T20	1		T103	2		T99	2
all_values[5]	auto[1]	auto[0]	auto[1]	135	1			T19	2		T20	3		T103	2
all_values[5]	auto[1]	auto[1]	auto[1]	126	1			T19	1		T20	1		T34	1
all_values[6]	auto[0]	auto[0]	auto[0]	123	1			T19	2		T103	2		T110	1
all_values[6]	auto[0]	auto[0]	auto[1]	55	1			T19	1		T34	2		T99	1
all_values[6]	auto[0]	auto[1]	auto[0]	99	1			T19	1		T34	1		T103	1
all_values[6]	auto[0]	auto[1]	auto[1]	66	1			T20	2		T99	1		T110	1
all_values[6]	auto[1]	auto[0]	auto[1]	129	1			T19	1		T20	1		T103	3
all_values[6]	auto[1]	auto[1]	auto[1]	124	1			T19	2		T20	4		T34	1
all_values[7]	auto[0]	auto[0]	auto[0]	139	1			T19	2		T20	3		T103	2
all_values[7]	auto[0]	auto[0]	auto[1]	64	1			T20	2		T110	1		T36	2
all_values[7]	auto[0]	auto[1]	auto[0]	101	1			T34	1		T35	6		T37	2
all_values[7]	auto[0]	auto[1]	auto[1]	38	1			T34	1		T103	1		T99	1
all_values[7]	auto[1]	auto[0]	auto[1]	155	1			T19	1		T20	2		T103	3
all_values[7]	auto[1]	auto[1]	auto[1]	99	1			T19	4		T34	2		T103	1
all_values[8]	auto[0]	auto[0]	auto[1]	209	1			T19	2		T34	1		T103	3
all_values[8]	auto[0]	auto[1]	auto[1]	152	1			T19	3		T20	3		T34	1
all_values[8]	auto[1]	auto[0]	auto[1]	126	1			T19	2		T20	1		T34	2
all_values[8]	auto[1]	auto[1]	auto[1]	109	1			T20	3		T99	1		T110	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal