Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.10 97.65 100.00 98.38 100.00 99.53


Total test records in report: 1211
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T1034 /workspace/coverage/default/8.uart_rx_oversample.448091649 Jun 27 04:54:10 PM PDT 24 Jun 27 04:54:46 PM PDT 24 4088948756 ps
T1035 /workspace/coverage/default/91.uart_stress_all_with_rand_reset.2579117917 Jun 27 04:57:04 PM PDT 24 Jun 27 05:06:06 PM PDT 24 60811636169 ps
T1036 /workspace/coverage/default/25.uart_tx_ovrd.3810850392 Jun 27 04:55:06 PM PDT 24 Jun 27 04:55:12 PM PDT 24 1080282823 ps
T1037 /workspace/coverage/default/2.uart_perf.1215501365 Jun 27 04:53:38 PM PDT 24 Jun 27 04:59:24 PM PDT 24 24159660155 ps
T200 /workspace/coverage/default/200.uart_fifo_reset.4166819914 Jun 27 04:57:26 PM PDT 24 Jun 27 04:57:47 PM PDT 24 56470043437 ps
T1038 /workspace/coverage/default/41.uart_fifo_overflow.597863986 Jun 27 04:56:00 PM PDT 24 Jun 27 04:57:36 PM PDT 24 316356709108 ps
T1039 /workspace/coverage/default/46.uart_fifo_reset.2513428680 Jun 27 04:56:27 PM PDT 24 Jun 27 04:56:43 PM PDT 24 7136320582 ps
T1040 /workspace/coverage/default/25.uart_tx_rx.4067080385 Jun 27 04:55:06 PM PDT 24 Jun 27 04:55:21 PM PDT 24 24900921509 ps
T1041 /workspace/coverage/default/31.uart_tx_ovrd.3295855572 Jun 27 04:55:33 PM PDT 24 Jun 27 04:55:38 PM PDT 24 1088255211 ps
T1042 /workspace/coverage/default/34.uart_fifo_reset.2986683297 Jun 27 04:55:37 PM PDT 24 Jun 27 04:56:00 PM PDT 24 69362218193 ps
T1043 /workspace/coverage/default/215.uart_fifo_reset.2895282366 Jun 27 04:57:32 PM PDT 24 Jun 27 04:59:29 PM PDT 24 98292851410 ps
T1044 /workspace/coverage/default/99.uart_fifo_reset.3678783083 Jun 27 04:57:05 PM PDT 24 Jun 27 04:57:23 PM PDT 24 42897768621 ps
T1045 /workspace/coverage/default/41.uart_loopback.3539600055 Jun 27 04:56:06 PM PDT 24 Jun 27 04:56:13 PM PDT 24 10702114610 ps
T1046 /workspace/coverage/default/45.uart_tx_rx.4038574949 Jun 27 04:56:13 PM PDT 24 Jun 27 04:56:50 PM PDT 24 39928666587 ps
T1047 /workspace/coverage/default/34.uart_noise_filter.3362716886 Jun 27 04:55:41 PM PDT 24 Jun 27 04:56:20 PM PDT 24 95747536368 ps
T1048 /workspace/coverage/default/3.uart_smoke.3055952450 Jun 27 04:53:48 PM PDT 24 Jun 27 04:53:52 PM PDT 24 265760774 ps
T1049 /workspace/coverage/default/11.uart_smoke.322701430 Jun 27 04:54:11 PM PDT 24 Jun 27 04:54:19 PM PDT 24 927806379 ps
T1050 /workspace/coverage/default/31.uart_tx_rx.3145283784 Jun 27 04:55:32 PM PDT 24 Jun 27 04:56:05 PM PDT 24 70925912769 ps
T1051 /workspace/coverage/default/20.uart_fifo_overflow.3932290824 Jun 27 04:54:56 PM PDT 24 Jun 27 04:57:23 PM PDT 24 266931913562 ps
T1052 /workspace/coverage/default/93.uart_fifo_reset.811969257 Jun 27 04:57:03 PM PDT 24 Jun 27 04:57:30 PM PDT 24 295956326054 ps
T1053 /workspace/coverage/default/5.uart_fifo_reset.2624151254 Jun 27 04:53:53 PM PDT 24 Jun 27 04:54:21 PM PDT 24 33295179204 ps
T1054 /workspace/coverage/default/19.uart_long_xfer_wo_dly.4008229881 Jun 27 04:54:50 PM PDT 24 Jun 27 04:57:41 PM PDT 24 139103416007 ps
T1055 /workspace/coverage/default/51.uart_fifo_reset.3824763883 Jun 27 04:56:34 PM PDT 24 Jun 27 04:58:46 PM PDT 24 274459704080 ps
T1056 /workspace/coverage/default/16.uart_tx_rx.3652759150 Jun 27 04:54:35 PM PDT 24 Jun 27 04:54:57 PM PDT 24 124682246273 ps
T1057 /workspace/coverage/default/0.uart_intr.183066010 Jun 27 04:53:41 PM PDT 24 Jun 27 04:54:21 PM PDT 24 21299127582 ps
T1058 /workspace/coverage/default/22.uart_fifo_full.2570414398 Jun 27 04:54:48 PM PDT 24 Jun 27 04:55:04 PM PDT 24 27276328827 ps
T1059 /workspace/coverage/default/32.uart_tx_ovrd.1834222561 Jun 27 04:55:34 PM PDT 24 Jun 27 04:55:38 PM PDT 24 2059019544 ps
T1060 /workspace/coverage/default/13.uart_alert_test.3185318564 Jun 27 04:54:38 PM PDT 24 Jun 27 04:54:42 PM PDT 24 11548288 ps
T1061 /workspace/coverage/default/203.uart_fifo_reset.1114542132 Jun 27 04:57:26 PM PDT 24 Jun 27 04:59:55 PM PDT 24 94945295866 ps
T1062 /workspace/coverage/default/125.uart_fifo_reset.676867109 Jun 27 04:57:13 PM PDT 24 Jun 27 04:59:38 PM PDT 24 88521074671 ps
T1063 /workspace/coverage/default/5.uart_tx_ovrd.2148987335 Jun 27 04:54:08 PM PDT 24 Jun 27 04:54:33 PM PDT 24 6409404534 ps
T1064 /workspace/coverage/default/11.uart_loopback.3554209991 Jun 27 04:54:28 PM PDT 24 Jun 27 04:54:44 PM PDT 24 7554575117 ps
T1065 /workspace/coverage/default/25.uart_stress_all_with_rand_reset.3239907797 Jun 27 04:55:03 PM PDT 24 Jun 27 05:08:51 PM PDT 24 54091169396 ps
T1066 /workspace/coverage/default/36.uart_alert_test.3791559907 Jun 27 04:55:53 PM PDT 24 Jun 27 04:55:57 PM PDT 24 22171569 ps
T1067 /workspace/coverage/default/3.uart_rx_oversample.4228214710 Jun 27 04:53:54 PM PDT 24 Jun 27 04:54:00 PM PDT 24 5996204252 ps
T1068 /workspace/coverage/default/38.uart_rx_parity_err.2505638700 Jun 27 04:55:56 PM PDT 24 Jun 27 04:58:27 PM PDT 24 82361997461 ps
T1069 /workspace/coverage/default/1.uart_fifo_full.396326690 Jun 27 04:53:43 PM PDT 24 Jun 27 04:55:37 PM PDT 24 108635447522 ps
T1070 /workspace/coverage/default/276.uart_fifo_reset.2207013528 Jun 27 04:57:56 PM PDT 24 Jun 27 04:58:32 PM PDT 24 74598220160 ps
T1071 /workspace/coverage/default/32.uart_rx_start_bit_filter.405431824 Jun 27 04:55:32 PM PDT 24 Jun 27 04:55:36 PM PDT 24 3474676306 ps
T216 /workspace/coverage/default/64.uart_fifo_reset.874713920 Jun 27 04:56:56 PM PDT 24 Jun 27 04:57:24 PM PDT 24 265040661350 ps
T1072 /workspace/coverage/default/28.uart_fifo_reset.3187738768 Jun 27 04:55:08 PM PDT 24 Jun 27 04:55:47 PM PDT 24 160711540854 ps
T1073 /workspace/coverage/default/58.uart_fifo_reset.3582359247 Jun 27 04:56:55 PM PDT 24 Jun 27 04:57:13 PM PDT 24 28749053229 ps
T1074 /workspace/coverage/default/5.uart_loopback.1240889127 Jun 27 04:53:58 PM PDT 24 Jun 27 04:54:07 PM PDT 24 2785462451 ps
T231 /workspace/coverage/default/33.uart_fifo_reset.3272174244 Jun 27 04:55:37 PM PDT 24 Jun 27 04:56:32 PM PDT 24 32475916145 ps
T1075 /workspace/coverage/default/221.uart_fifo_reset.1721969975 Jun 27 04:57:22 PM PDT 24 Jun 27 04:58:05 PM PDT 24 103843748911 ps
T1076 /workspace/coverage/default/27.uart_tx_ovrd.3453024988 Jun 27 04:55:04 PM PDT 24 Jun 27 04:55:09 PM PDT 24 1295585470 ps
T1077 /workspace/coverage/cover_reg_top/5.uart_intr_test.3809466944 Jun 27 04:45:28 PM PDT 24 Jun 27 04:45:29 PM PDT 24 59755460 ps
T1078 /workspace/coverage/cover_reg_top/2.uart_intr_test.3172800751 Jun 27 04:45:05 PM PDT 24 Jun 27 04:45:12 PM PDT 24 24130394 ps
T1079 /workspace/coverage/cover_reg_top/3.uart_tl_errors.2735957123 Jun 27 04:45:03 PM PDT 24 Jun 27 04:45:09 PM PDT 24 213067525 ps
T73 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1682356579 Jun 27 04:45:43 PM PDT 24 Jun 27 04:45:47 PM PDT 24 182278843 ps
T1080 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2805107224 Jun 27 04:45:24 PM PDT 24 Jun 27 04:45:26 PM PDT 24 18561242 ps
T1081 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.199588628 Jun 27 04:45:24 PM PDT 24 Jun 27 04:45:26 PM PDT 24 32593447 ps
T50 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3760394997 Jun 27 04:45:39 PM PDT 24 Jun 27 04:45:44 PM PDT 24 23174389 ps
T1082 /workspace/coverage/cover_reg_top/39.uart_intr_test.3847035755 Jun 27 04:45:36 PM PDT 24 Jun 27 04:45:40 PM PDT 24 19066371 ps
T74 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2407000411 Jun 27 04:45:36 PM PDT 24 Jun 27 04:45:40 PM PDT 24 138973573 ps
T1083 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.277807993 Jun 27 04:45:11 PM PDT 24 Jun 27 04:45:15 PM PDT 24 14562662 ps
T63 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.572604009 Jun 27 04:45:37 PM PDT 24 Jun 27 04:45:41 PM PDT 24 34259462 ps
T1084 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2915841560 Jun 27 04:45:25 PM PDT 24 Jun 27 04:45:27 PM PDT 24 16977303 ps
T1085 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2220586591 Jun 27 04:45:32 PM PDT 24 Jun 27 04:45:36 PM PDT 24 83484042 ps
T1086 /workspace/coverage/cover_reg_top/16.uart_tl_errors.1433081624 Jun 27 04:45:40 PM PDT 24 Jun 27 04:45:45 PM PDT 24 37662493 ps
T75 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3326650127 Jun 27 04:45:30 PM PDT 24 Jun 27 04:45:34 PM PDT 24 123364574 ps
T1087 /workspace/coverage/cover_reg_top/14.uart_intr_test.849867982 Jun 27 04:45:36 PM PDT 24 Jun 27 04:45:39 PM PDT 24 14321042 ps
T1088 /workspace/coverage/cover_reg_top/30.uart_intr_test.1601105040 Jun 27 04:45:29 PM PDT 24 Jun 27 04:45:31 PM PDT 24 43678879 ps
T1089 /workspace/coverage/cover_reg_top/16.uart_csr_rw.2208581641 Jun 27 04:45:37 PM PDT 24 Jun 27 04:45:41 PM PDT 24 28676876 ps
T1090 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.4244732247 Jun 27 04:45:39 PM PDT 24 Jun 27 04:45:43 PM PDT 24 103278040 ps
T64 /workspace/coverage/cover_reg_top/4.uart_csr_rw.3470614867 Jun 27 04:45:31 PM PDT 24 Jun 27 04:45:34 PM PDT 24 14344544 ps
T1091 /workspace/coverage/cover_reg_top/15.uart_csr_rw.2201213167 Jun 27 04:45:37 PM PDT 24 Jun 27 04:45:41 PM PDT 24 36536407 ps
T1092 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.493357442 Jun 27 04:45:34 PM PDT 24 Jun 27 04:45:36 PM PDT 24 81059550 ps
T80 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2533272754 Jun 27 04:45:17 PM PDT 24 Jun 27 04:45:19 PM PDT 24 76971073 ps
T1093 /workspace/coverage/cover_reg_top/13.uart_tl_errors.1625731878 Jun 27 04:45:26 PM PDT 24 Jun 27 04:45:29 PM PDT 24 28203233 ps
T1094 /workspace/coverage/cover_reg_top/26.uart_intr_test.1496138184 Jun 27 04:45:34 PM PDT 24 Jun 27 04:45:36 PM PDT 24 14222257 ps
T65 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3433308816 Jun 27 04:45:34 PM PDT 24 Jun 27 04:45:36 PM PDT 24 60146861 ps
T1095 /workspace/coverage/cover_reg_top/9.uart_tl_errors.300994918 Jun 27 04:45:29 PM PDT 24 Jun 27 04:45:32 PM PDT 24 98724747 ps
T66 /workspace/coverage/cover_reg_top/6.uart_csr_rw.3422489403 Jun 27 04:45:23 PM PDT 24 Jun 27 04:45:25 PM PDT 24 47656905 ps
T67 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2504524811 Jun 27 04:45:37 PM PDT 24 Jun 27 04:45:41 PM PDT 24 97794356 ps
T68 /workspace/coverage/cover_reg_top/2.uart_csr_rw.1343945558 Jun 27 04:45:05 PM PDT 24 Jun 27 04:45:12 PM PDT 24 68161513 ps
T69 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.449798989 Jun 27 04:45:37 PM PDT 24 Jun 27 04:45:42 PM PDT 24 20616723 ps
T1096 /workspace/coverage/cover_reg_top/45.uart_intr_test.1399905174 Jun 27 04:45:42 PM PDT 24 Jun 27 04:45:46 PM PDT 24 22302339 ps
T70 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3602577403 Jun 27 04:45:43 PM PDT 24 Jun 27 04:45:48 PM PDT 24 36728728 ps
T1097 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.860369845 Jun 27 04:45:43 PM PDT 24 Jun 27 04:45:47 PM PDT 24 32180461 ps
T1098 /workspace/coverage/cover_reg_top/15.uart_intr_test.2434948068 Jun 27 04:45:37 PM PDT 24 Jun 27 04:45:41 PM PDT 24 11306615 ps
T1099 /workspace/coverage/cover_reg_top/37.uart_intr_test.3691614025 Jun 27 04:45:37 PM PDT 24 Jun 27 04:45:41 PM PDT 24 88590402 ps
T1100 /workspace/coverage/cover_reg_top/0.uart_csr_rw.2428787316 Jun 27 04:45:08 PM PDT 24 Jun 27 04:45:14 PM PDT 24 23995689 ps
T71 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.4261785165 Jun 27 04:45:35 PM PDT 24 Jun 27 04:45:39 PM PDT 24 29722722 ps
T1101 /workspace/coverage/cover_reg_top/0.uart_intr_test.3554156316 Jun 27 04:45:16 PM PDT 24 Jun 27 04:45:17 PM PDT 24 11565297 ps
T72 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.679762958 Jun 27 04:45:23 PM PDT 24 Jun 27 04:45:25 PM PDT 24 27094039 ps
T1102 /workspace/coverage/cover_reg_top/31.uart_intr_test.571901737 Jun 27 04:45:35 PM PDT 24 Jun 27 04:45:38 PM PDT 24 70266758 ps
T1103 /workspace/coverage/cover_reg_top/44.uart_intr_test.683603399 Jun 27 04:45:37 PM PDT 24 Jun 27 04:45:41 PM PDT 24 17800229 ps
T78 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3088482452 Jun 27 04:45:39 PM PDT 24 Jun 27 04:45:44 PM PDT 24 71517955 ps
T51 /workspace/coverage/cover_reg_top/5.uart_csr_rw.3391212566 Jun 27 04:45:26 PM PDT 24 Jun 27 04:45:28 PM PDT 24 75914601 ps
T1104 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1281841691 Jun 27 04:45:37 PM PDT 24 Jun 27 04:45:41 PM PDT 24 32004397 ps
T1105 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.727903562 Jun 27 04:45:16 PM PDT 24 Jun 27 04:45:18 PM PDT 24 316756807 ps
T1106 /workspace/coverage/cover_reg_top/6.uart_intr_test.1788435079 Jun 27 04:45:21 PM PDT 24 Jun 27 04:45:23 PM PDT 24 12826984 ps
T1107 /workspace/coverage/cover_reg_top/4.uart_intr_test.3264204504 Jun 27 04:45:24 PM PDT 24 Jun 27 04:45:25 PM PDT 24 14094634 ps
T1108 /workspace/coverage/cover_reg_top/14.uart_tl_errors.2582427711 Jun 27 04:45:34 PM PDT 24 Jun 27 04:45:37 PM PDT 24 22682507 ps
T52 /workspace/coverage/cover_reg_top/12.uart_csr_rw.2773589699 Jun 27 04:45:30 PM PDT 24 Jun 27 04:45:32 PM PDT 24 16069283 ps
T1109 /workspace/coverage/cover_reg_top/41.uart_intr_test.1184976810 Jun 27 04:45:37 PM PDT 24 Jun 27 04:45:41 PM PDT 24 23507359 ps
T1110 /workspace/coverage/cover_reg_top/7.uart_tl_errors.4122355740 Jun 27 04:45:22 PM PDT 24 Jun 27 04:45:26 PM PDT 24 658199801 ps
T1111 /workspace/coverage/cover_reg_top/34.uart_intr_test.712350981 Jun 27 04:45:40 PM PDT 24 Jun 27 04:45:44 PM PDT 24 12311549 ps
T1112 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1503009065 Jun 27 04:45:29 PM PDT 24 Jun 27 04:45:32 PM PDT 24 55823679 ps
T1113 /workspace/coverage/cover_reg_top/12.uart_tl_errors.3595049140 Jun 27 04:45:38 PM PDT 24 Jun 27 04:45:43 PM PDT 24 266638760 ps
T81 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1209211764 Jun 27 04:45:31 PM PDT 24 Jun 27 04:45:34 PM PDT 24 83861982 ps
T1114 /workspace/coverage/cover_reg_top/19.uart_tl_errors.3733506675 Jun 27 04:45:40 PM PDT 24 Jun 27 04:45:45 PM PDT 24 257645008 ps
T1115 /workspace/coverage/cover_reg_top/3.uart_csr_rw.1875492471 Jun 27 04:45:40 PM PDT 24 Jun 27 04:45:44 PM PDT 24 37722531 ps
T1116 /workspace/coverage/cover_reg_top/47.uart_intr_test.3349108443 Jun 27 04:45:34 PM PDT 24 Jun 27 04:45:37 PM PDT 24 21076602 ps
T53 /workspace/coverage/cover_reg_top/13.uart_csr_rw.3494810717 Jun 27 04:45:32 PM PDT 24 Jun 27 04:45:35 PM PDT 24 11850253 ps
T1117 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3110001186 Jun 27 04:45:40 PM PDT 24 Jun 27 04:45:44 PM PDT 24 59332717 ps
T1118 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1045153818 Jun 27 04:45:39 PM PDT 24 Jun 27 04:45:44 PM PDT 24 86958346 ps
T1119 /workspace/coverage/cover_reg_top/7.uart_csr_rw.4042681612 Jun 27 04:45:30 PM PDT 24 Jun 27 04:45:33 PM PDT 24 62477818 ps
T1120 /workspace/coverage/cover_reg_top/17.uart_tl_errors.2015038931 Jun 27 04:45:43 PM PDT 24 Jun 27 04:45:49 PM PDT 24 265388216 ps
T1121 /workspace/coverage/cover_reg_top/17.uart_intr_test.2700057633 Jun 27 04:45:35 PM PDT 24 Jun 27 04:45:38 PM PDT 24 23936522 ps
T1122 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.113768707 Jun 27 04:45:08 PM PDT 24 Jun 27 04:45:14 PM PDT 24 163874917 ps
T1123 /workspace/coverage/cover_reg_top/15.uart_tl_errors.3009366230 Jun 27 04:45:43 PM PDT 24 Jun 27 04:45:48 PM PDT 24 172251534 ps
T1124 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1295052018 Jun 27 04:45:20 PM PDT 24 Jun 27 04:45:22 PM PDT 24 89855715 ps
T1125 /workspace/coverage/cover_reg_top/7.uart_intr_test.1661672298 Jun 27 04:45:23 PM PDT 24 Jun 27 04:45:25 PM PDT 24 106065355 ps
T1126 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.4120700592 Jun 27 04:45:32 PM PDT 24 Jun 27 04:45:35 PM PDT 24 26427048 ps
T1127 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3885851659 Jun 27 04:45:16 PM PDT 24 Jun 27 04:45:18 PM PDT 24 38729472 ps
T112 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2038404535 Jun 27 04:45:25 PM PDT 24 Jun 27 04:45:28 PM PDT 24 305164906 ps
T1128 /workspace/coverage/cover_reg_top/38.uart_intr_test.2996029029 Jun 27 04:45:36 PM PDT 24 Jun 27 04:45:39 PM PDT 24 13961042 ps
T1129 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2564514488 Jun 27 04:45:03 PM PDT 24 Jun 27 04:45:10 PM PDT 24 120441452 ps
T54 /workspace/coverage/cover_reg_top/10.uart_csr_rw.317010619 Jun 27 04:45:38 PM PDT 24 Jun 27 04:45:42 PM PDT 24 36139589 ps
T1130 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1040886672 Jun 27 04:45:10 PM PDT 24 Jun 27 04:45:15 PM PDT 24 62697462 ps
T1131 /workspace/coverage/cover_reg_top/29.uart_intr_test.2782235704 Jun 27 04:45:24 PM PDT 24 Jun 27 04:45:26 PM PDT 24 15983878 ps
T55 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1956439113 Jun 27 04:45:05 PM PDT 24 Jun 27 04:45:12 PM PDT 24 18963613 ps
T1132 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2331372743 Jun 27 04:45:25 PM PDT 24 Jun 27 04:45:27 PM PDT 24 99505940 ps
T1133 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3444357555 Jun 27 04:45:25 PM PDT 24 Jun 27 04:45:27 PM PDT 24 176093275 ps
T1134 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1999861277 Jun 27 04:45:39 PM PDT 24 Jun 27 04:45:44 PM PDT 24 18102758 ps
T1135 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.934925747 Jun 27 04:45:32 PM PDT 24 Jun 27 04:45:37 PM PDT 24 114087752 ps
T1136 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2459849751 Jun 27 04:45:29 PM PDT 24 Jun 27 04:45:31 PM PDT 24 45031378 ps
T1137 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3212330620 Jun 27 04:45:08 PM PDT 24 Jun 27 04:45:15 PM PDT 24 434586905 ps
T1138 /workspace/coverage/cover_reg_top/16.uart_intr_test.1439101758 Jun 27 04:45:42 PM PDT 24 Jun 27 04:45:46 PM PDT 24 20104200 ps
T1139 /workspace/coverage/cover_reg_top/6.uart_tl_errors.3795367757 Jun 27 04:45:21 PM PDT 24 Jun 27 04:45:23 PM PDT 24 50902261 ps
T1140 /workspace/coverage/cover_reg_top/8.uart_tl_errors.724706405 Jun 27 04:45:25 PM PDT 24 Jun 27 04:45:28 PM PDT 24 521801471 ps
T1141 /workspace/coverage/cover_reg_top/42.uart_intr_test.4236176916 Jun 27 04:45:25 PM PDT 24 Jun 27 04:45:27 PM PDT 24 41846251 ps
T1142 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.903222252 Jun 27 04:45:39 PM PDT 24 Jun 27 04:45:44 PM PDT 24 20590087 ps
T1143 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.330739737 Jun 27 04:45:32 PM PDT 24 Jun 27 04:45:35 PM PDT 24 41307812 ps
T57 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2322591044 Jun 27 04:45:07 PM PDT 24 Jun 27 04:45:14 PM PDT 24 32023196 ps
T1144 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2050721634 Jun 27 04:45:03 PM PDT 24 Jun 27 04:45:10 PM PDT 24 73570638 ps
T1145 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1413964783 Jun 27 04:45:08 PM PDT 24 Jun 27 04:45:15 PM PDT 24 116095929 ps
T1146 /workspace/coverage/cover_reg_top/18.uart_csr_rw.3154350015 Jun 27 04:45:31 PM PDT 24 Jun 27 04:45:34 PM PDT 24 29264505 ps
T1147 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3741173659 Jun 27 04:45:34 PM PDT 24 Jun 27 04:45:37 PM PDT 24 52980590 ps
T1148 /workspace/coverage/cover_reg_top/25.uart_intr_test.363845282 Jun 27 04:45:34 PM PDT 24 Jun 27 04:45:37 PM PDT 24 12342799 ps
T1149 /workspace/coverage/cover_reg_top/32.uart_intr_test.1274237829 Jun 27 04:45:35 PM PDT 24 Jun 27 04:45:39 PM PDT 24 17422744 ps
T1150 /workspace/coverage/cover_reg_top/18.uart_tl_errors.3045207366 Jun 27 04:45:34 PM PDT 24 Jun 27 04:45:38 PM PDT 24 419428665 ps
T1151 /workspace/coverage/cover_reg_top/28.uart_intr_test.3237865363 Jun 27 04:45:33 PM PDT 24 Jun 27 04:45:36 PM PDT 24 13319516 ps
T76 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2473655727 Jun 27 04:45:30 PM PDT 24 Jun 27 04:45:33 PM PDT 24 714527456 ps
T1152 /workspace/coverage/cover_reg_top/13.uart_intr_test.3454808434 Jun 27 04:45:30 PM PDT 24 Jun 27 04:45:33 PM PDT 24 13541329 ps
T1153 /workspace/coverage/cover_reg_top/8.uart_intr_test.2040441376 Jun 27 04:45:28 PM PDT 24 Jun 27 04:45:29 PM PDT 24 12450361 ps
T1154 /workspace/coverage/cover_reg_top/21.uart_intr_test.1723169204 Jun 27 04:45:36 PM PDT 24 Jun 27 04:45:40 PM PDT 24 34800889 ps
T1155 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1477295209 Jun 27 04:45:31 PM PDT 24 Jun 27 04:45:35 PM PDT 24 181861347 ps
T1156 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1400492219 Jun 27 04:45:17 PM PDT 24 Jun 27 04:45:20 PM PDT 24 56032507 ps
T1157 /workspace/coverage/cover_reg_top/12.uart_intr_test.3547590376 Jun 27 04:45:27 PM PDT 24 Jun 27 04:45:29 PM PDT 24 43419995 ps
T1158 /workspace/coverage/cover_reg_top/23.uart_intr_test.805583268 Jun 27 04:45:39 PM PDT 24 Jun 27 04:45:43 PM PDT 24 30511854 ps
T1159 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2697688163 Jun 27 04:45:36 PM PDT 24 Jun 27 04:45:40 PM PDT 24 30220009 ps
T1160 /workspace/coverage/cover_reg_top/36.uart_intr_test.3489920146 Jun 27 04:45:35 PM PDT 24 Jun 27 04:45:39 PM PDT 24 40193698 ps
T1161 /workspace/coverage/cover_reg_top/2.uart_tl_errors.2873070532 Jun 27 04:45:05 PM PDT 24 Jun 27 04:45:13 PM PDT 24 27882415 ps
T1162 /workspace/coverage/cover_reg_top/19.uart_intr_test.3844694883 Jun 27 04:45:26 PM PDT 24 Jun 27 04:45:28 PM PDT 24 12598217 ps
T77 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3086576232 Jun 27 04:45:26 PM PDT 24 Jun 27 04:45:28 PM PDT 24 158568963 ps
T1163 /workspace/coverage/cover_reg_top/1.uart_intr_test.1326857370 Jun 27 04:45:30 PM PDT 24 Jun 27 04:45:33 PM PDT 24 17018475 ps
T1164 /workspace/coverage/cover_reg_top/11.uart_tl_errors.3470398044 Jun 27 04:45:31 PM PDT 24 Jun 27 04:45:35 PM PDT 24 50329673 ps
T1165 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2974761619 Jun 27 04:45:16 PM PDT 24 Jun 27 04:45:18 PM PDT 24 34172226 ps
T1166 /workspace/coverage/cover_reg_top/46.uart_intr_test.2889830926 Jun 27 04:45:43 PM PDT 24 Jun 27 04:45:46 PM PDT 24 55562201 ps
T1167 /workspace/coverage/cover_reg_top/48.uart_intr_test.2260061961 Jun 27 04:45:40 PM PDT 24 Jun 27 04:45:44 PM PDT 24 54387682 ps
T1168 /workspace/coverage/cover_reg_top/11.uart_intr_test.1587726433 Jun 27 04:45:30 PM PDT 24 Jun 27 04:45:33 PM PDT 24 25404953 ps
T1169 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3978729465 Jun 27 04:45:05 PM PDT 24 Jun 27 04:45:12 PM PDT 24 23878936 ps
T1170 /workspace/coverage/cover_reg_top/40.uart_intr_test.596233935 Jun 27 04:45:36 PM PDT 24 Jun 27 04:45:40 PM PDT 24 15403088 ps
T1171 /workspace/coverage/cover_reg_top/27.uart_intr_test.1747564328 Jun 27 04:45:24 PM PDT 24 Jun 27 04:45:26 PM PDT 24 11274836 ps
T1172 /workspace/coverage/cover_reg_top/19.uart_csr_rw.2319472938 Jun 27 04:45:35 PM PDT 24 Jun 27 04:45:38 PM PDT 24 13651118 ps
T58 /workspace/coverage/cover_reg_top/11.uart_csr_rw.95074651 Jun 27 04:45:34 PM PDT 24 Jun 27 04:45:38 PM PDT 24 55940057 ps
T1173 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1529294196 Jun 27 04:45:38 PM PDT 24 Jun 27 04:45:43 PM PDT 24 136779071 ps
T1174 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2205525172 Jun 27 04:45:29 PM PDT 24 Jun 27 04:45:32 PM PDT 24 26395213 ps
T1175 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.4085332577 Jun 27 04:45:24 PM PDT 24 Jun 27 04:45:26 PM PDT 24 32865068 ps
T1176 /workspace/coverage/cover_reg_top/9.uart_intr_test.1114568045 Jun 27 04:45:29 PM PDT 24 Jun 27 04:45:31 PM PDT 24 13203254 ps
T1177 /workspace/coverage/cover_reg_top/1.uart_tl_errors.4006484766 Jun 27 04:45:20 PM PDT 24 Jun 27 04:45:23 PM PDT 24 26435794 ps
T1178 /workspace/coverage/cover_reg_top/18.uart_intr_test.4065667804 Jun 27 04:45:29 PM PDT 24 Jun 27 04:45:31 PM PDT 24 13111540 ps
T1179 /workspace/coverage/cover_reg_top/20.uart_intr_test.2481335428 Jun 27 04:45:33 PM PDT 24 Jun 27 04:45:36 PM PDT 24 40888889 ps
T1180 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3895427433 Jun 27 04:45:29 PM PDT 24 Jun 27 04:45:31 PM PDT 24 136086163 ps
T82 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.4225065249 Jun 27 04:45:33 PM PDT 24 Jun 27 04:45:36 PM PDT 24 126426389 ps
T1181 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2801429103 Jun 27 04:45:27 PM PDT 24 Jun 27 04:45:29 PM PDT 24 166351657 ps
T56 /workspace/coverage/cover_reg_top/14.uart_csr_rw.204349979 Jun 27 04:45:40 PM PDT 24 Jun 27 04:45:44 PM PDT 24 57862335 ps
T1182 /workspace/coverage/cover_reg_top/17.uart_csr_rw.3944146493 Jun 27 04:45:35 PM PDT 24 Jun 27 04:45:38 PM PDT 24 58568631 ps
T1183 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1813402630 Jun 27 04:45:32 PM PDT 24 Jun 27 04:45:35 PM PDT 24 27405533 ps
T1184 /workspace/coverage/cover_reg_top/4.uart_tl_errors.2637888134 Jun 27 04:45:19 PM PDT 24 Jun 27 04:45:22 PM PDT 24 37664492 ps
T1185 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2440088126 Jun 27 04:45:08 PM PDT 24 Jun 27 04:45:14 PM PDT 24 27921740 ps
T1186 /workspace/coverage/cover_reg_top/10.uart_intr_test.1731995667 Jun 27 04:45:38 PM PDT 24 Jun 27 04:45:43 PM PDT 24 38701134 ps
T1187 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3581410251 Jun 27 04:45:42 PM PDT 24 Jun 27 04:45:46 PM PDT 24 167354064 ps
T1188 /workspace/coverage/cover_reg_top/49.uart_intr_test.2591026715 Jun 27 04:45:36 PM PDT 24 Jun 27 04:45:41 PM PDT 24 29475785 ps
T1189 /workspace/coverage/cover_reg_top/43.uart_intr_test.3474228396 Jun 27 04:45:42 PM PDT 24 Jun 27 04:45:46 PM PDT 24 19538719 ps
T1190 /workspace/coverage/cover_reg_top/22.uart_intr_test.2638574258 Jun 27 04:45:30 PM PDT 24 Jun 27 04:45:32 PM PDT 24 13111888 ps
T1191 /workspace/coverage/cover_reg_top/24.uart_intr_test.986076653 Jun 27 04:45:29 PM PDT 24 Jun 27 04:45:31 PM PDT 24 83625977 ps
T1192 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.596307037 Jun 27 04:45:37 PM PDT 24 Jun 27 04:45:42 PM PDT 24 812566055 ps
T1193 /workspace/coverage/cover_reg_top/5.uart_tl_errors.3185808526 Jun 27 04:45:24 PM PDT 24 Jun 27 04:45:27 PM PDT 24 40167477 ps
T1194 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.4164447878 Jun 27 04:45:31 PM PDT 24 Jun 27 04:45:33 PM PDT 24 24779329 ps
T1195 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1253592360 Jun 27 04:45:02 PM PDT 24 Jun 27 04:45:07 PM PDT 24 161274697 ps
T1196 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2752246467 Jun 27 04:45:42 PM PDT 24 Jun 27 04:45:46 PM PDT 24 97556822 ps
T1197 /workspace/coverage/cover_reg_top/10.uart_tl_errors.1030622784 Jun 27 04:45:31 PM PDT 24 Jun 27 04:45:35 PM PDT 24 1000553521 ps
T1198 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3243257783 Jun 27 04:45:21 PM PDT 24 Jun 27 04:45:23 PM PDT 24 66711766 ps
T1199 /workspace/coverage/cover_reg_top/33.uart_intr_test.2658932149 Jun 27 04:45:39 PM PDT 24 Jun 27 04:45:43 PM PDT 24 61997701 ps
T1200 /workspace/coverage/cover_reg_top/35.uart_intr_test.1690383550 Jun 27 04:45:36 PM PDT 24 Jun 27 04:45:40 PM PDT 24 42135448 ps
T1201 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.691308113 Jun 27 04:45:05 PM PDT 24 Jun 27 04:45:13 PM PDT 24 134459677 ps
T1202 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3778746406 Jun 27 04:45:43 PM PDT 24 Jun 27 04:45:47 PM PDT 24 24744796 ps
T1203 /workspace/coverage/cover_reg_top/9.uart_csr_rw.322816217 Jun 27 04:45:29 PM PDT 24 Jun 27 04:45:31 PM PDT 24 13743100 ps
T1204 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3585536653 Jun 27 04:45:41 PM PDT 24 Jun 27 04:45:45 PM PDT 24 687707404 ps
T1205 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3591730947 Jun 27 04:45:40 PM PDT 24 Jun 27 04:45:44 PM PDT 24 61992226 ps
T1206 /workspace/coverage/cover_reg_top/8.uart_csr_rw.524387978 Jun 27 04:45:28 PM PDT 24 Jun 27 04:45:29 PM PDT 24 36967310 ps
T1207 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2296575905 Jun 27 04:45:28 PM PDT 24 Jun 27 04:45:30 PM PDT 24 60461810 ps
T79 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2718198980 Jun 27 04:45:34 PM PDT 24 Jun 27 04:45:37 PM PDT 24 179878089 ps
T1208 /workspace/coverage/cover_reg_top/1.uart_csr_rw.3022318626 Jun 27 04:45:09 PM PDT 24 Jun 27 04:45:14 PM PDT 24 15595948 ps
T1209 /workspace/coverage/cover_reg_top/0.uart_tl_errors.2518802067 Jun 27 04:45:08 PM PDT 24 Jun 27 04:45:16 PM PDT 24 38844478 ps
T1210 /workspace/coverage/cover_reg_top/3.uart_intr_test.639928147 Jun 27 04:45:38 PM PDT 24 Jun 27 04:45:42 PM PDT 24 14238344 ps
T1211 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2007421838 Jun 27 04:45:32 PM PDT 24 Jun 27 04:45:35 PM PDT 24 102535042 ps

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.3460773255
Short name T5
Test name
Test status
Simulation time 20179012374 ps
CPU time 687.92 seconds
Started Jun 27 04:54:56 PM PDT 24
Finished Jun 27 05:06:25 PM PDT 24
Peak memory 216492 kb
Host smart-d265312a-0efa-48d7-9f50-fff6cb66f955
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460773255 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.3460773255
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.1261659456
Short name T19
Test name
Test status
Simulation time 226374524043 ps
CPU time 966.85 seconds
Started Jun 27 04:56:52 PM PDT 24
Finished Jun 27 05:13:02 PM PDT 24
Peak memory 210828 kb
Host smart-7fd6eb19-a6a9-4efb-9130-e3c45cf71597
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261659456 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.1261659456
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.378016569
Short name T33
Test name
Test status
Simulation time 437586551419 ps
CPU time 311.7 seconds
Started Jun 27 04:57:11 PM PDT 24
Finished Jun 27 05:02:24 PM PDT 24
Peak memory 216404 kb
Host smart-d8852072-ee61-40ea-9062-a3cb9562dc5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378016569 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.378016569
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_stress_all.3897322058
Short name T103
Test name
Test status
Simulation time 573078511758 ps
CPU time 87.75 seconds
Started Jun 27 04:56:15 PM PDT 24
Finished Jun 27 04:57:44 PM PDT 24
Peak memory 199752 kb
Host smart-957f10a2-8ea2-4ce8-92b3-365ab7274d28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897322058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.3897322058
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_tx_rx.3223982493
Short name T2
Test name
Test status
Simulation time 60057292230 ps
CPU time 21.99 seconds
Started Jun 27 04:55:36 PM PDT 24
Finished Jun 27 04:56:00 PM PDT 24
Peak memory 199928 kb
Host smart-9c94af10-10a0-49c1-8182-0d2a9dfdc633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223982493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.3223982493
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_stress_all.2707390685
Short name T18
Test name
Test status
Simulation time 274524567390 ps
CPU time 232.18 seconds
Started Jun 27 04:54:49 PM PDT 24
Finished Jun 27 04:58:44 PM PDT 24
Peak memory 199528 kb
Host smart-d8bc363e-22da-45ee-9245-08156aff78dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707390685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.2707390685
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.3397361216
Short name T247
Test name
Test status
Simulation time 85889374848 ps
CPU time 543.79 seconds
Started Jun 27 04:55:20 PM PDT 24
Finished Jun 27 05:04:25 PM PDT 24
Peak memory 199948 kb
Host smart-8d78831c-4d7f-4176-8d35-a36820cdf7ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3397361216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.3397361216
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_stress_all.3964742090
Short name T120
Test name
Test status
Simulation time 494041869291 ps
CPU time 971.53 seconds
Started Jun 27 04:55:54 PM PDT 24
Finished Jun 27 05:12:09 PM PDT 24
Peak memory 199800 kb
Host smart-d202d34a-2644-4605-aa0c-60c75a0bd69e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964742090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3964742090
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_sec_cm.3431193445
Short name T29
Test name
Test status
Simulation time 143473737 ps
CPU time 0.74 seconds
Started Jun 27 04:53:54 PM PDT 24
Finished Jun 27 04:53:57 PM PDT 24
Peak memory 218216 kb
Host smart-510276c5-0c71-4400-9c27-793d965fda08
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431193445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3431193445
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/17.uart_stress_all.3538090945
Short name T21
Test name
Test status
Simulation time 127110905584 ps
CPU time 119.78 seconds
Started Jun 27 04:54:34 PM PDT 24
Finished Jun 27 04:56:38 PM PDT 24
Peak memory 199940 kb
Host smart-d428c622-e8b3-458f-85b0-3ac1deb41a18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538090945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.3538090945
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all.4022315506
Short name T412
Test name
Test status
Simulation time 396353525814 ps
CPU time 774.49 seconds
Started Jun 27 04:54:27 PM PDT 24
Finished Jun 27 05:07:23 PM PDT 24
Peak memory 199876 kb
Host smart-52a6a314-bbc1-4702-8fec-15a4d2bd4552
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022315506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.4022315506
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.2342535956
Short name T37
Test name
Test status
Simulation time 127570808265 ps
CPU time 888.51 seconds
Started Jun 27 04:56:51 PM PDT 24
Finished Jun 27 05:11:42 PM PDT 24
Peak memory 224736 kb
Host smart-3f21b8b0-0d51-4e56-8511-41246cf1ea64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342535956 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.2342535956
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.1050305551
Short name T246
Test name
Test status
Simulation time 210868261450 ps
CPU time 51.81 seconds
Started Jun 27 04:55:08 PM PDT 24
Finished Jun 27 04:56:04 PM PDT 24
Peak memory 199800 kb
Host smart-5feda57c-a774-4036-b7a7-faf0df2c56d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050305551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1050305551
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_fifo_full.2360630494
Short name T305
Test name
Test status
Simulation time 345827458336 ps
CPU time 262.05 seconds
Started Jun 27 04:54:50 PM PDT 24
Finished Jun 27 04:59:14 PM PDT 24
Peak memory 199896 kb
Host smart-21bc3b40-035d-4de9-9123-19088e89a4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360630494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2360630494
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.3070228409
Short name T119
Test name
Test status
Simulation time 100365512891 ps
CPU time 122.74 seconds
Started Jun 27 04:57:33 PM PDT 24
Finished Jun 27 04:59:38 PM PDT 24
Peak memory 199960 kb
Host smart-3e28866b-4104-4e0b-b3e5-5f943d0637a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070228409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3070228409
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.812395859
Short name T256
Test name
Test status
Simulation time 69044965775 ps
CPU time 31.26 seconds
Started Jun 27 04:57:56 PM PDT 24
Finished Jun 27 04:58:30 PM PDT 24
Peak memory 199848 kb
Host smart-9b48f080-f5b3-45de-b341-42fd321a14cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812395859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.812395859
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.4161826216
Short name T20
Test name
Test status
Simulation time 33702011828 ps
CPU time 444.37 seconds
Started Jun 27 04:56:52 PM PDT 24
Finished Jun 27 05:04:19 PM PDT 24
Peak memory 216532 kb
Host smart-27ae11ad-e2dd-484e-9213-3578c7e84123
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161826216 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.4161826216
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.3713898
Short name T118
Test name
Test status
Simulation time 110649832629 ps
CPU time 112.61 seconds
Started Jun 27 04:57:13 PM PDT 24
Finished Jun 27 04:59:08 PM PDT 24
Peak memory 199904 kb
Host smart-4d7d3361-eaa4-4bf8-ae2b-cd8f0c46d47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.3713898
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3088482452
Short name T78
Test name
Test status
Simulation time 71517955 ps
CPU time 1.3 seconds
Started Jun 27 04:45:39 PM PDT 24
Finished Jun 27 04:45:44 PM PDT 24
Peak memory 199760 kb
Host smart-adeb2312-b47e-45d0-894d-9dfbad88bacb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088482452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3088482452
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.393999835
Short name T44
Test name
Test status
Simulation time 120445511356 ps
CPU time 71.26 seconds
Started Jun 27 04:57:12 PM PDT 24
Finished Jun 27 04:58:25 PM PDT 24
Peak memory 199904 kb
Host smart-46edd0e9-1887-4e91-9d19-853d67067092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393999835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.393999835
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.3586365684
Short name T338
Test name
Test status
Simulation time 47594326 ps
CPU time 0.56 seconds
Started Jun 27 04:55:10 PM PDT 24
Finished Jun 27 04:55:14 PM PDT 24
Peak memory 195212 kb
Host smart-7ba2d1ba-1bcd-4232-9da1-36ee59dc1c0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586365684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3586365684
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3725853802
Short name T137
Test name
Test status
Simulation time 294059767415 ps
CPU time 53.76 seconds
Started Jun 27 04:54:09 PM PDT 24
Finished Jun 27 04:55:05 PM PDT 24
Peak memory 199996 kb
Host smart-b0b2a38f-c061-4362-bc34-e9b792b66c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725853802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3725853802
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_full.97324875
Short name T4
Test name
Test status
Simulation time 211287348585 ps
CPU time 92.69 seconds
Started Jun 27 04:56:03 PM PDT 24
Finished Jun 27 04:57:40 PM PDT 24
Peak memory 199988 kb
Host smart-630f6a5a-bc9d-473a-94b4-647c0d1ee171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97324875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.97324875
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3118864136
Short name T141
Test name
Test status
Simulation time 53215977886 ps
CPU time 38.79 seconds
Started Jun 27 04:56:44 PM PDT 24
Finished Jun 27 04:57:24 PM PDT 24
Peak memory 199776 kb
Host smart-999f893f-7d02-47b1-b8d6-b56597b1d6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118864136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3118864136
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3130251650
Short name T151
Test name
Test status
Simulation time 151283606513 ps
CPU time 103.76 seconds
Started Jun 27 04:57:28 PM PDT 24
Finished Jun 27 04:59:13 PM PDT 24
Peak memory 199896 kb
Host smart-3273e97d-be3c-4508-9f34-f3534562aa60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130251650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3130251650
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.52062737
Short name T111
Test name
Test status
Simulation time 139257473334 ps
CPU time 698.78 seconds
Started Jun 27 04:54:46 PM PDT 24
Finished Jun 27 05:06:28 PM PDT 24
Peak memory 216488 kb
Host smart-7f6872ec-2e3a-4c78-ab0b-b5083214f2c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52062737 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.52062737
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.317010619
Short name T54
Test name
Test status
Simulation time 36139589 ps
CPU time 0.61 seconds
Started Jun 27 04:45:38 PM PDT 24
Finished Jun 27 04:45:42 PM PDT 24
Peak memory 195692 kb
Host smart-32fc4ab9-0e6a-4aa2-b8f3-8d351eea1a08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317010619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.317010619
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2504524811
Short name T67
Test name
Test status
Simulation time 97794356 ps
CPU time 0.8 seconds
Started Jun 27 04:45:37 PM PDT 24
Finished Jun 27 04:45:41 PM PDT 24
Peak memory 197468 kb
Host smart-af5809a8-5607-44ca-ba6b-f92b458ce8de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504524811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.2504524811
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.97986270
Short name T46
Test name
Test status
Simulation time 167863451705 ps
CPU time 164.33 seconds
Started Jun 27 04:57:58 PM PDT 24
Finished Jun 27 05:00:46 PM PDT 24
Peak memory 199916 kb
Host smart-d0c4aad5-2391-45fc-ae17-5cabf184d492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97986270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.97986270
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3581410251
Short name T1187
Test name
Test status
Simulation time 167354064 ps
CPU time 0.94 seconds
Started Jun 27 04:45:42 PM PDT 24
Finished Jun 27 04:45:46 PM PDT 24
Peak memory 199540 kb
Host smart-8a4bfd74-ce98-4585-9491-b663dbb1c91a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581410251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3581410251
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.1598133622
Short name T138
Test name
Test status
Simulation time 70908469633 ps
CPU time 104.27 seconds
Started Jun 27 04:57:12 PM PDT 24
Finished Jun 27 04:58:59 PM PDT 24
Peak memory 199928 kb
Host smart-54afb4b4-9139-4525-a229-f57fc8c08d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598133622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1598133622
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.1047557553
Short name T116
Test name
Test status
Simulation time 63276060694 ps
CPU time 122.64 seconds
Started Jun 27 04:57:14 PM PDT 24
Finished Jun 27 04:59:20 PM PDT 24
Peak memory 199824 kb
Host smart-e69c368b-34e9-4392-b60f-88b87dd3c9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047557553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.1047557553
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.2826734785
Short name T190
Test name
Test status
Simulation time 44684299779 ps
CPU time 39.09 seconds
Started Jun 27 04:57:57 PM PDT 24
Finished Jun 27 04:58:40 PM PDT 24
Peak memory 199864 kb
Host smart-ac238ffa-1312-4d10-b468-857e8f320acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826734785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.2826734785
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.2939608391
Short name T150
Test name
Test status
Simulation time 905010065873 ps
CPU time 980.19 seconds
Started Jun 27 04:54:33 PM PDT 24
Finished Jun 27 05:10:57 PM PDT 24
Peak memory 216492 kb
Host smart-bcd6ac54-9e2b-47bd-8ad2-dcf17bd95cf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939608391 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.2939608391
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.346070281
Short name T164
Test name
Test status
Simulation time 110880865589 ps
CPU time 27.14 seconds
Started Jun 27 04:57:24 PM PDT 24
Finished Jun 27 04:57:52 PM PDT 24
Peak memory 199732 kb
Host smart-d7ef4bbf-0ccd-4b62-aaa0-de5209057253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346070281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.346070281
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_perf.421595895
Short name T270
Test name
Test status
Simulation time 23496750548 ps
CPU time 691.14 seconds
Started Jun 27 04:54:32 PM PDT 24
Finished Jun 27 05:06:06 PM PDT 24
Peak memory 199912 kb
Host smart-74bfd965-fd88-4170-8f02-f416f8b7b132
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=421595895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.421595895
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1828236114
Short name T130
Test name
Test status
Simulation time 64939760041 ps
CPU time 18.17 seconds
Started Jun 27 04:57:22 PM PDT 24
Finished Jun 27 04:57:41 PM PDT 24
Peak memory 199904 kb
Host smart-dce4106b-08a5-4635-bf4c-e281181da9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828236114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1828236114
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.686211800
Short name T158
Test name
Test status
Simulation time 111954762224 ps
CPU time 633.96 seconds
Started Jun 27 04:56:51 PM PDT 24
Finished Jun 27 05:07:27 PM PDT 24
Peak memory 216492 kb
Host smart-0d7b4f07-26fb-4b30-b1ce-97976b884727
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686211800 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.686211800
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2893942339
Short name T179
Test name
Test status
Simulation time 26344783889 ps
CPU time 24.81 seconds
Started Jun 27 04:55:56 PM PDT 24
Finished Jun 27 04:56:25 PM PDT 24
Peak memory 199928 kb
Host smart-7d3774be-4dd0-4b28-bd11-f2bd19d6d509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893942339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2893942339
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.1547341715
Short name T6
Test name
Test status
Simulation time 34351128871 ps
CPU time 62.69 seconds
Started Jun 27 04:57:14 PM PDT 24
Finished Jun 27 04:58:19 PM PDT 24
Peak memory 199928 kb
Host smart-2e673b23-367f-4ce6-abf4-415007ac1517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547341715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1547341715
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.4068421930
Short name T144
Test name
Test status
Simulation time 134085126250 ps
CPU time 47.64 seconds
Started Jun 27 04:57:28 PM PDT 24
Finished Jun 27 04:58:17 PM PDT 24
Peak memory 199988 kb
Host smart-1c928cb0-f921-4c14-ac43-35d88c724ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068421930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.4068421930
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1858843916
Short name T232
Test name
Test status
Simulation time 96933561713 ps
CPU time 147.34 seconds
Started Jun 27 04:57:58 PM PDT 24
Finished Jun 27 05:00:29 PM PDT 24
Peak memory 199892 kb
Host smart-179bff82-f8de-4eb5-8bb7-f1cfe00c5062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858843916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1858843916
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1000983723
Short name T121
Test name
Test status
Simulation time 169780660849 ps
CPU time 55.44 seconds
Started Jun 27 04:55:56 PM PDT 24
Finished Jun 27 04:56:56 PM PDT 24
Peak memory 199724 kb
Host smart-e5d281e7-033c-4326-9b47-b4b92e918cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000983723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1000983723
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.3586196881
Short name T154
Test name
Test status
Simulation time 87317386504 ps
CPU time 137 seconds
Started Jun 27 04:57:03 PM PDT 24
Finished Jun 27 04:59:21 PM PDT 24
Peak memory 200112 kb
Host smart-e58817cc-01fb-43a2-833a-9408a1416310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586196881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3586196881
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.2476417807
Short name T183
Test name
Test status
Simulation time 27684067705 ps
CPU time 24.51 seconds
Started Jun 27 04:57:08 PM PDT 24
Finished Jun 27 04:57:34 PM PDT 24
Peak memory 199928 kb
Host smart-44cbe0a8-565d-49bc-86c9-8960a5aa2f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476417807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2476417807
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2902746015
Short name T208
Test name
Test status
Simulation time 73168541912 ps
CPU time 97.46 seconds
Started Jun 27 04:57:14 PM PDT 24
Finished Jun 27 04:58:54 PM PDT 24
Peak memory 199932 kb
Host smart-f47e5f6f-0594-4bd4-87ca-35d503eb0336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902746015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2902746015
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.3101875279
Short name T12
Test name
Test status
Simulation time 200983529291 ps
CPU time 27.83 seconds
Started Jun 27 04:57:27 PM PDT 24
Finished Jun 27 04:57:56 PM PDT 24
Peak memory 199820 kb
Host smart-cb88293b-8f62-4aeb-b6c0-82a1ff096083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101875279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3101875279
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2246195598
Short name T752
Test name
Test status
Simulation time 120014510038 ps
CPU time 171.88 seconds
Started Jun 27 04:57:25 PM PDT 24
Finished Jun 27 05:00:18 PM PDT 24
Peak memory 199868 kb
Host smart-925a0862-b439-442d-b3b9-c85af7fa6460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246195598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2246195598
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.1824668214
Short name T212
Test name
Test status
Simulation time 143607483436 ps
CPU time 72.34 seconds
Started Jun 27 04:57:31 PM PDT 24
Finished Jun 27 04:58:44 PM PDT 24
Peak memory 199852 kb
Host smart-16203f67-1fbc-47bd-aa81-3985ced46dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824668214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1824668214
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.2868294236
Short name T171
Test name
Test status
Simulation time 203886691730 ps
CPU time 27.99 seconds
Started Jun 27 04:58:00 PM PDT 24
Finished Jun 27 04:58:30 PM PDT 24
Peak memory 198800 kb
Host smart-ca8f9a81-cec8-4fa8-acc0-1babb005a535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868294236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2868294236
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.4073627781
Short name T201
Test name
Test status
Simulation time 124065591147 ps
CPU time 29.91 seconds
Started Jun 27 04:57:59 PM PDT 24
Finished Jun 27 04:58:32 PM PDT 24
Peak memory 199928 kb
Host smart-42c4483d-f3ae-4e7e-beaa-f11050039d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073627781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.4073627781
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.386179974
Short name T323
Test name
Test status
Simulation time 138599904261 ps
CPU time 1120.47 seconds
Started Jun 27 04:53:58 PM PDT 24
Finished Jun 27 05:12:41 PM PDT 24
Peak memory 213880 kb
Host smart-c5749099-170a-4f06-9307-0b8524f98703
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386179974 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.386179974
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.2861220854
Short name T271
Test name
Test status
Simulation time 31778823570 ps
CPU time 54.87 seconds
Started Jun 27 04:57:33 PM PDT 24
Finished Jun 27 04:58:30 PM PDT 24
Peak memory 199724 kb
Host smart-97bf6887-a446-4b13-be2a-e28c833cbcfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861220854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.2861220854
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.2471063531
Short name T934
Test name
Test status
Simulation time 171736548970 ps
CPU time 135.92 seconds
Started Jun 27 04:57:32 PM PDT 24
Finished Jun 27 04:59:50 PM PDT 24
Peak memory 199936 kb
Host smart-1f7f0ea8-fbc0-405b-8b94-0d55e7a04979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471063531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2471063531
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.1497945573
Short name T178
Test name
Test status
Simulation time 35420952431 ps
CPU time 89.47 seconds
Started Jun 27 04:57:55 PM PDT 24
Finished Jun 27 04:59:26 PM PDT 24
Peak memory 199908 kb
Host smart-c3715952-12d5-499a-99a0-ea61668c377e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497945573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.1497945573
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.3272174244
Short name T231
Test name
Test status
Simulation time 32475916145 ps
CPU time 53.21 seconds
Started Jun 27 04:55:37 PM PDT 24
Finished Jun 27 04:56:32 PM PDT 24
Peak memory 199920 kb
Host smart-281e2350-0b0c-48be-83f5-b7be279c4d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272174244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3272174244
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_stress_all.2238369327
Short name T288
Test name
Test status
Simulation time 78023803392 ps
CPU time 167.66 seconds
Started Jun 27 04:53:53 PM PDT 24
Finished Jun 27 04:56:43 PM PDT 24
Peak memory 199888 kb
Host smart-1fedfd96-a399-42fa-ae8c-41bb07f21577
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238369327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.2238369327
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.1230919424
Short name T109
Test name
Test status
Simulation time 70559258926 ps
CPU time 57.64 seconds
Started Jun 27 04:53:43 PM PDT 24
Finished Jun 27 04:54:46 PM PDT 24
Peak memory 199920 kb
Host smart-a7b15ceb-4fac-49f0-a316-9409434c20a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230919424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1230919424
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.3028074277
Short name T228
Test name
Test status
Simulation time 13998129486 ps
CPU time 16.02 seconds
Started Jun 27 04:54:12 PM PDT 24
Finished Jun 27 04:54:31 PM PDT 24
Peak memory 199716 kb
Host smart-9d6ffd84-a703-4877-bf3f-194106ac2046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028074277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3028074277
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_stress_all.3538807491
Short name T99
Test name
Test status
Simulation time 237841203673 ps
CPU time 39.87 seconds
Started Jun 27 04:54:15 PM PDT 24
Finished Jun 27 04:54:57 PM PDT 24
Peak memory 199900 kb
Host smart-66c2fd4b-d8d1-4794-85a8-b00de69894ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538807491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3538807491
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.393988199
Short name T242
Test name
Test status
Simulation time 37715082420 ps
CPU time 20.56 seconds
Started Jun 27 04:57:06 PM PDT 24
Finished Jun 27 04:57:28 PM PDT 24
Peak memory 199864 kb
Host smart-fda3bf30-a2ba-4a91-a8c4-22db45746f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393988199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.393988199
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.2807872622
Short name T236
Test name
Test status
Simulation time 64555212316 ps
CPU time 90.15 seconds
Started Jun 27 04:57:14 PM PDT 24
Finished Jun 27 04:58:47 PM PDT 24
Peak memory 199892 kb
Host smart-1c9acdfe-66c4-4f56-9e88-c382a999e04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807872622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2807872622
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.383152552
Short name T161
Test name
Test status
Simulation time 136017301726 ps
CPU time 222.72 seconds
Started Jun 27 04:57:10 PM PDT 24
Finished Jun 27 05:00:54 PM PDT 24
Peak memory 199956 kb
Host smart-45de0524-1689-4232-bcef-9405ef993039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383152552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.383152552
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.879965953
Short name T198
Test name
Test status
Simulation time 24764657844 ps
CPU time 44.32 seconds
Started Jun 27 04:57:14 PM PDT 24
Finished Jun 27 04:58:01 PM PDT 24
Peak memory 199952 kb
Host smart-01d071fe-4f41-4953-972b-f24db33c7a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879965953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.879965953
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.3192280606
Short name T220
Test name
Test status
Simulation time 28259499146 ps
CPU time 45 seconds
Started Jun 27 04:57:12 PM PDT 24
Finished Jun 27 04:58:00 PM PDT 24
Peak memory 199964 kb
Host smart-c2c9adea-87d3-4eaa-8bf0-45185beb25a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192280606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.3192280606
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.474697558
Short name T302
Test name
Test status
Simulation time 172201289458 ps
CPU time 14.53 seconds
Started Jun 27 04:57:28 PM PDT 24
Finished Jun 27 04:57:44 PM PDT 24
Peak memory 199972 kb
Host smart-6af91c0d-97f9-46c8-9021-be1e11828a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474697558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.474697558
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.3009360327
Short name T213
Test name
Test status
Simulation time 35879089639 ps
CPU time 37.14 seconds
Started Jun 27 04:57:22 PM PDT 24
Finished Jun 27 04:58:01 PM PDT 24
Peak memory 199840 kb
Host smart-ebc35222-873f-40cf-9470-52a669855586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009360327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.3009360327
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2041929755
Short name T194
Test name
Test status
Simulation time 30224674370 ps
CPU time 25.33 seconds
Started Jun 27 04:54:47 PM PDT 24
Finished Jun 27 04:55:15 PM PDT 24
Peak memory 199880 kb
Host smart-700b48be-398a-462f-a0f0-c0764bf44024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041929755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2041929755
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.40977952
Short name T165
Test name
Test status
Simulation time 17798390309 ps
CPU time 14.73 seconds
Started Jun 27 04:57:33 PM PDT 24
Finished Jun 27 04:57:50 PM PDT 24
Peak memory 199888 kb
Host smart-daeb6ad7-9f8e-47dc-9085-df7447c18e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40977952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.40977952
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.4108785758
Short name T202
Test name
Test status
Simulation time 16776984086 ps
CPU time 30.33 seconds
Started Jun 27 04:57:28 PM PDT 24
Finished Jun 27 04:58:00 PM PDT 24
Peak memory 199928 kb
Host smart-a1fd852c-9043-4403-a33f-5b2e92a7807c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108785758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.4108785758
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.3539865633
Short name T237
Test name
Test status
Simulation time 55490913777 ps
CPU time 29.48 seconds
Started Jun 27 04:57:32 PM PDT 24
Finished Jun 27 04:58:03 PM PDT 24
Peak memory 199988 kb
Host smart-df690312-5717-41e4-8a7d-9941f41b9b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539865633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3539865633
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.278621501
Short name T214
Test name
Test status
Simulation time 81624397877 ps
CPU time 38.67 seconds
Started Jun 27 04:55:21 PM PDT 24
Finished Jun 27 04:56:01 PM PDT 24
Peak memory 199820 kb
Host smart-b0438734-7951-4820-be6e-c548829113c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278621501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.278621501
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.874713920
Short name T216
Test name
Test status
Simulation time 265040661350 ps
CPU time 25.9 seconds
Started Jun 27 04:56:56 PM PDT 24
Finished Jun 27 04:57:24 PM PDT 24
Peak memory 199932 kb
Host smart-169a3001-29e4-4af4-a2c0-6c8f5046c60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874713920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.874713920
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.1957771268
Short name T145
Test name
Test status
Simulation time 33791741302 ps
CPU time 53.56 seconds
Started Jun 27 04:56:52 PM PDT 24
Finished Jun 27 04:57:49 PM PDT 24
Peak memory 200184 kb
Host smart-0c7e1f14-36f2-4836-abe4-42e7493c8b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957771268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1957771268
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3885851659
Short name T1127
Test name
Test status
Simulation time 38729472 ps
CPU time 0.7 seconds
Started Jun 27 04:45:16 PM PDT 24
Finished Jun 27 04:45:18 PM PDT 24
Peak memory 195764 kb
Host smart-b89dd62f-4b41-402d-bab4-90a65860d50d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885851659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3885851659
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2564514488
Short name T1129
Test name
Test status
Simulation time 120441452 ps
CPU time 1.48 seconds
Started Jun 27 04:45:03 PM PDT 24
Finished Jun 27 04:45:10 PM PDT 24
Peak memory 198068 kb
Host smart-ab311792-1af6-47ae-afcc-669bbc8674e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564514488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2564514488
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2322591044
Short name T57
Test name
Test status
Simulation time 32023196 ps
CPU time 0.56 seconds
Started Jun 27 04:45:07 PM PDT 24
Finished Jun 27 04:45:14 PM PDT 24
Peak memory 195684 kb
Host smart-5a891af8-b11d-4dbb-a476-04759d4f5c73
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322591044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.2322591044
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2050721634
Short name T1144
Test name
Test status
Simulation time 73570638 ps
CPU time 1.12 seconds
Started Jun 27 04:45:03 PM PDT 24
Finished Jun 27 04:45:10 PM PDT 24
Peak memory 200380 kb
Host smart-0610bfa9-e4a7-436c-9993-1ecd29e0d199
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050721634 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2050721634
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.2428787316
Short name T1100
Test name
Test status
Simulation time 23995689 ps
CPU time 0.59 seconds
Started Jun 27 04:45:08 PM PDT 24
Finished Jun 27 04:45:14 PM PDT 24
Peak memory 195784 kb
Host smart-067d7ff8-0a1f-4dfb-9f94-da1b020ae619
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428787316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.2428787316
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.3554156316
Short name T1101
Test name
Test status
Simulation time 11565297 ps
CPU time 0.61 seconds
Started Jun 27 04:45:16 PM PDT 24
Finished Jun 27 04:45:17 PM PDT 24
Peak memory 194740 kb
Host smart-11f37b6f-0077-4fc7-a71b-1c3ae3bc3fa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554156316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3554156316
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2974761619
Short name T1165
Test name
Test status
Simulation time 34172226 ps
CPU time 0.83 seconds
Started Jun 27 04:45:16 PM PDT 24
Finished Jun 27 04:45:18 PM PDT 24
Peak memory 196616 kb
Host smart-c81fc8e8-6bcc-4353-b9cf-320094382db8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974761619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.2974761619
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.2518802067
Short name T1209
Test name
Test status
Simulation time 38844478 ps
CPU time 1.9 seconds
Started Jun 27 04:45:08 PM PDT 24
Finished Jun 27 04:45:16 PM PDT 24
Peak memory 200284 kb
Host smart-dc64fa86-a639-4d46-a1e7-007de039560e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518802067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2518802067
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.727903562
Short name T1105
Test name
Test status
Simulation time 316756807 ps
CPU time 1 seconds
Started Jun 27 04:45:16 PM PDT 24
Finished Jun 27 04:45:18 PM PDT 24
Peak memory 199456 kb
Host smart-e6f03aee-0210-4c82-8220-076aa9a1ab92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727903562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.727903562
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.277807993
Short name T1083
Test name
Test status
Simulation time 14562662 ps
CPU time 0.66 seconds
Started Jun 27 04:45:11 PM PDT 24
Finished Jun 27 04:45:15 PM PDT 24
Peak memory 195064 kb
Host smart-4fb9f886-9963-4c36-8e46-38a2b3773097
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277807993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.277807993
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1400492219
Short name T1156
Test name
Test status
Simulation time 56032507 ps
CPU time 2.19 seconds
Started Jun 27 04:45:17 PM PDT 24
Finished Jun 27 04:45:20 PM PDT 24
Peak memory 197996 kb
Host smart-568af33e-7a22-4530-970f-0873fb25e897
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400492219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.1400492219
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3444357555
Short name T1133
Test name
Test status
Simulation time 176093275 ps
CPU time 0.61 seconds
Started Jun 27 04:45:25 PM PDT 24
Finished Jun 27 04:45:27 PM PDT 24
Peak memory 195684 kb
Host smart-9be6f10c-1794-43fe-9095-14b3aeb378d5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444357555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3444357555
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3212330620
Short name T1137
Test name
Test status
Simulation time 434586905 ps
CPU time 0.83 seconds
Started Jun 27 04:45:08 PM PDT 24
Finished Jun 27 04:45:15 PM PDT 24
Peak memory 200132 kb
Host smart-1096fc73-67c0-430c-b422-1164d225bff9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212330620 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.3212330620
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3022318626
Short name T1208
Test name
Test status
Simulation time 15595948 ps
CPU time 0.59 seconds
Started Jun 27 04:45:09 PM PDT 24
Finished Jun 27 04:45:14 PM PDT 24
Peak memory 195640 kb
Host smart-75c60e15-fbaf-4980-9c2f-347a890d571e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022318626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3022318626
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.1326857370
Short name T1163
Test name
Test status
Simulation time 17018475 ps
CPU time 0.61 seconds
Started Jun 27 04:45:30 PM PDT 24
Finished Jun 27 04:45:33 PM PDT 24
Peak memory 194660 kb
Host smart-62d1c84e-7cf7-4508-87d2-6f51c005ba09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326857370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1326857370
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1040886672
Short name T1130
Test name
Test status
Simulation time 62697462 ps
CPU time 0.62 seconds
Started Jun 27 04:45:10 PM PDT 24
Finished Jun 27 04:45:15 PM PDT 24
Peak memory 195696 kb
Host smart-c2888bef-3175-4220-96fa-ebc7f3c11c97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040886672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.1040886672
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.4006484766
Short name T1177
Test name
Test status
Simulation time 26435794 ps
CPU time 1.3 seconds
Started Jun 27 04:45:20 PM PDT 24
Finished Jun 27 04:45:23 PM PDT 24
Peak memory 200320 kb
Host smart-d41272f9-2287-4631-a46d-e0cd930a6e7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006484766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.4006484766
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2533272754
Short name T80
Test name
Test status
Simulation time 76971073 ps
CPU time 1.24 seconds
Started Jun 27 04:45:17 PM PDT 24
Finished Jun 27 04:45:19 PM PDT 24
Peak memory 199400 kb
Host smart-7861fdb4-e427-4cab-b665-9cb716e0b8c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533272754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2533272754
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.199588628
Short name T1081
Test name
Test status
Simulation time 32593447 ps
CPU time 0.66 seconds
Started Jun 27 04:45:24 PM PDT 24
Finished Jun 27 04:45:26 PM PDT 24
Peak memory 198364 kb
Host smart-130ebfa8-b2ff-4163-bfe2-ca66c310bed3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199588628 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.199588628
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.1731995667
Short name T1186
Test name
Test status
Simulation time 38701134 ps
CPU time 0.56 seconds
Started Jun 27 04:45:38 PM PDT 24
Finished Jun 27 04:45:43 PM PDT 24
Peak memory 194788 kb
Host smart-a5342924-be8a-4bf5-8755-d34a03fce16f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731995667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.1731995667
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3243257783
Short name T1198
Test name
Test status
Simulation time 66711766 ps
CPU time 0.62 seconds
Started Jun 27 04:45:21 PM PDT 24
Finished Jun 27 04:45:23 PM PDT 24
Peak memory 196264 kb
Host smart-4031fac2-ae70-4487-a614-22198df8c1a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243257783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.3243257783
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.1030622784
Short name T1197
Test name
Test status
Simulation time 1000553521 ps
CPU time 2.34 seconds
Started Jun 27 04:45:31 PM PDT 24
Finished Jun 27 04:45:35 PM PDT 24
Peak memory 200380 kb
Host smart-3ad9545c-377d-4df0-bf85-c5893a06a942
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030622784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1030622784
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3326650127
Short name T75
Test name
Test status
Simulation time 123364574 ps
CPU time 1.32 seconds
Started Jun 27 04:45:30 PM PDT 24
Finished Jun 27 04:45:34 PM PDT 24
Peak memory 199764 kb
Host smart-59aa7f8a-86fb-4581-bac6-4ac360a39698
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326650127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3326650127
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.4164447878
Short name T1194
Test name
Test status
Simulation time 24779329 ps
CPU time 0.72 seconds
Started Jun 27 04:45:31 PM PDT 24
Finished Jun 27 04:45:33 PM PDT 24
Peak memory 197864 kb
Host smart-a822457f-3e55-43b8-a6ba-0a3e66b5b8fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164447878 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.4164447878
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.95074651
Short name T58
Test name
Test status
Simulation time 55940057 ps
CPU time 0.59 seconds
Started Jun 27 04:45:34 PM PDT 24
Finished Jun 27 04:45:38 PM PDT 24
Peak memory 195724 kb
Host smart-b695b9b3-9830-44e4-9358-4ea3c57fe364
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95074651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.95074651
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.1587726433
Short name T1168
Test name
Test status
Simulation time 25404953 ps
CPU time 0.55 seconds
Started Jun 27 04:45:30 PM PDT 24
Finished Jun 27 04:45:33 PM PDT 24
Peak memory 194748 kb
Host smart-33395f40-b482-4cb4-a9b2-e809fb353d16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587726433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1587726433
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2801429103
Short name T1181
Test name
Test status
Simulation time 166351657 ps
CPU time 0.74 seconds
Started Jun 27 04:45:27 PM PDT 24
Finished Jun 27 04:45:29 PM PDT 24
Peak memory 195920 kb
Host smart-6058dd6c-30b2-424d-84c4-9f2a741f033c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801429103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.2801429103
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3470398044
Short name T1164
Test name
Test status
Simulation time 50329673 ps
CPU time 1.85 seconds
Started Jun 27 04:45:31 PM PDT 24
Finished Jun 27 04:45:35 PM PDT 24
Peak memory 200312 kb
Host smart-8a030803-26d8-4921-8728-ec4d6bfc564b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470398044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3470398044
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1529294196
Short name T1173
Test name
Test status
Simulation time 136779071 ps
CPU time 0.95 seconds
Started Jun 27 04:45:38 PM PDT 24
Finished Jun 27 04:45:43 PM PDT 24
Peak memory 200112 kb
Host smart-18f7418d-e6c8-45d9-bf27-cbc610657012
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529294196 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.1529294196
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2773589699
Short name T52
Test name
Test status
Simulation time 16069283 ps
CPU time 0.64 seconds
Started Jun 27 04:45:30 PM PDT 24
Finished Jun 27 04:45:32 PM PDT 24
Peak memory 195780 kb
Host smart-f1dab1c1-8541-4cf5-846c-eef927e29ea8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773589699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2773589699
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.3547590376
Short name T1157
Test name
Test status
Simulation time 43419995 ps
CPU time 0.65 seconds
Started Jun 27 04:45:27 PM PDT 24
Finished Jun 27 04:45:29 PM PDT 24
Peak memory 194636 kb
Host smart-47c3eb0a-5571-4afa-babd-d7839ff3f8f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547590376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3547590376
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.4085332577
Short name T1175
Test name
Test status
Simulation time 32865068 ps
CPU time 0.7 seconds
Started Jun 27 04:45:24 PM PDT 24
Finished Jun 27 04:45:26 PM PDT 24
Peak memory 197248 kb
Host smart-17fcb4df-0add-4b97-882f-7d73260b4865
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085332577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.4085332577
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.3595049140
Short name T1113
Test name
Test status
Simulation time 266638760 ps
CPU time 1.43 seconds
Started Jun 27 04:45:38 PM PDT 24
Finished Jun 27 04:45:43 PM PDT 24
Peak memory 200404 kb
Host smart-fc23d2f4-5cbb-4d0b-a25f-87c47035fc2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595049140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.3595049140
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.330739737
Short name T1143
Test name
Test status
Simulation time 41307812 ps
CPU time 0.98 seconds
Started Jun 27 04:45:32 PM PDT 24
Finished Jun 27 04:45:35 PM PDT 24
Peak memory 199388 kb
Host smart-313ff107-d7b7-43e7-aabe-810fe3b31239
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330739737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.330739737
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1503009065
Short name T1112
Test name
Test status
Simulation time 55823679 ps
CPU time 1.07 seconds
Started Jun 27 04:45:29 PM PDT 24
Finished Jun 27 04:45:32 PM PDT 24
Peak memory 200112 kb
Host smart-8d3ceedc-064d-44db-82a7-5313c92a8932
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503009065 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1503009065
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.3494810717
Short name T53
Test name
Test status
Simulation time 11850253 ps
CPU time 0.57 seconds
Started Jun 27 04:45:32 PM PDT 24
Finished Jun 27 04:45:35 PM PDT 24
Peak memory 195716 kb
Host smart-800c3f66-18ef-4189-82cd-d051cae9c716
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494810717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3494810717
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.3454808434
Short name T1152
Test name
Test status
Simulation time 13541329 ps
CPU time 0.55 seconds
Started Jun 27 04:45:30 PM PDT 24
Finished Jun 27 04:45:33 PM PDT 24
Peak memory 194760 kb
Host smart-f8ff9868-2b2b-4bbe-8661-61e686a2b699
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454808434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3454808434
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2205525172
Short name T1174
Test name
Test status
Simulation time 26395213 ps
CPU time 0.8 seconds
Started Jun 27 04:45:29 PM PDT 24
Finished Jun 27 04:45:32 PM PDT 24
Peak memory 197396 kb
Host smart-76ede682-315c-4a14-819d-5addebc4fdeb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205525172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.2205525172
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.1625731878
Short name T1093
Test name
Test status
Simulation time 28203233 ps
CPU time 1.3 seconds
Started Jun 27 04:45:26 PM PDT 24
Finished Jun 27 04:45:29 PM PDT 24
Peak memory 200268 kb
Host smart-0c0240d9-81a9-4fc2-8b54-58f3206a6437
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625731878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1625731878
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1045153818
Short name T1118
Test name
Test status
Simulation time 86958346 ps
CPU time 1.27 seconds
Started Jun 27 04:45:39 PM PDT 24
Finished Jun 27 04:45:44 PM PDT 24
Peak memory 199828 kb
Host smart-79356ce9-75fa-482a-b1c0-be362af32315
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045153818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1045153818
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1999861277
Short name T1134
Test name
Test status
Simulation time 18102758 ps
CPU time 0.67 seconds
Started Jun 27 04:45:39 PM PDT 24
Finished Jun 27 04:45:44 PM PDT 24
Peak memory 197940 kb
Host smart-51ceefa4-ecd3-4a62-9f17-b4dc50a9d490
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999861277 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.1999861277
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.204349979
Short name T56
Test name
Test status
Simulation time 57862335 ps
CPU time 0.61 seconds
Started Jun 27 04:45:40 PM PDT 24
Finished Jun 27 04:45:44 PM PDT 24
Peak memory 195608 kb
Host smart-56f251a5-627b-4997-9859-0a192ac67eeb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204349979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.204349979
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.849867982
Short name T1087
Test name
Test status
Simulation time 14321042 ps
CPU time 0.6 seconds
Started Jun 27 04:45:36 PM PDT 24
Finished Jun 27 04:45:39 PM PDT 24
Peak memory 194652 kb
Host smart-e9dbaa27-63eb-43a1-9c05-97a300ecf96f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849867982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.849867982
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1813402630
Short name T1183
Test name
Test status
Simulation time 27405533 ps
CPU time 0.61 seconds
Started Jun 27 04:45:32 PM PDT 24
Finished Jun 27 04:45:35 PM PDT 24
Peak memory 195780 kb
Host smart-3783a36c-c2a9-4354-b174-16f5ee44a9ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813402630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1813402630
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.2582427711
Short name T1108
Test name
Test status
Simulation time 22682507 ps
CPU time 1.04 seconds
Started Jun 27 04:45:34 PM PDT 24
Finished Jun 27 04:45:37 PM PDT 24
Peak memory 200272 kb
Host smart-32360452-9081-463c-a580-5314e6afa4db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582427711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2582427711
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3591730947
Short name T1205
Test name
Test status
Simulation time 61992226 ps
CPU time 0.97 seconds
Started Jun 27 04:45:40 PM PDT 24
Finished Jun 27 04:45:44 PM PDT 24
Peak memory 198892 kb
Host smart-3fdf0c35-1e79-425a-8069-4bb8976d1982
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591730947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3591730947
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.4244732247
Short name T1090
Test name
Test status
Simulation time 103278040 ps
CPU time 0.79 seconds
Started Jun 27 04:45:39 PM PDT 24
Finished Jun 27 04:45:43 PM PDT 24
Peak memory 200372 kb
Host smart-80e54d12-c9d2-4358-8dff-5f1bb1642419
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244732247 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.4244732247
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.2201213167
Short name T1091
Test name
Test status
Simulation time 36536407 ps
CPU time 0.6 seconds
Started Jun 27 04:45:37 PM PDT 24
Finished Jun 27 04:45:41 PM PDT 24
Peak memory 195816 kb
Host smart-26fa58a6-092c-4a1f-b177-a49ae9d8f4d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201213167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.2201213167
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2434948068
Short name T1098
Test name
Test status
Simulation time 11306615 ps
CPU time 0.57 seconds
Started Jun 27 04:45:37 PM PDT 24
Finished Jun 27 04:45:41 PM PDT 24
Peak memory 194740 kb
Host smart-e7c5706b-b22b-4859-ba7a-567d32a6cfd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434948068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2434948068
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.3009366230
Short name T1123
Test name
Test status
Simulation time 172251534 ps
CPU time 1.74 seconds
Started Jun 27 04:45:43 PM PDT 24
Finished Jun 27 04:45:48 PM PDT 24
Peak memory 200380 kb
Host smart-743defcf-2780-48b7-bdd7-4e25b60929a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009366230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3009366230
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.860369845
Short name T1097
Test name
Test status
Simulation time 32180461 ps
CPU time 0.7 seconds
Started Jun 27 04:45:43 PM PDT 24
Finished Jun 27 04:45:47 PM PDT 24
Peak memory 199168 kb
Host smart-2aaeb992-3bea-4e51-8de8-1b236534102a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860369845 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.860369845
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.2208581641
Short name T1089
Test name
Test status
Simulation time 28676876 ps
CPU time 0.58 seconds
Started Jun 27 04:45:37 PM PDT 24
Finished Jun 27 04:45:41 PM PDT 24
Peak memory 195988 kb
Host smart-c3f53c81-e848-4de5-bc3a-bcb88b0dd164
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208581641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.2208581641
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.1439101758
Short name T1138
Test name
Test status
Simulation time 20104200 ps
CPU time 0.55 seconds
Started Jun 27 04:45:42 PM PDT 24
Finished Jun 27 04:45:46 PM PDT 24
Peak memory 194756 kb
Host smart-7c4c0fd0-cd29-40b7-9704-78b9df58deab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439101758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.1439101758
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.572604009
Short name T63
Test name
Test status
Simulation time 34259462 ps
CPU time 0.69 seconds
Started Jun 27 04:45:37 PM PDT 24
Finished Jun 27 04:45:41 PM PDT 24
Peak memory 195128 kb
Host smart-346ef94d-9259-45c4-9d2d-580289052e5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572604009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr
_outstanding.572604009
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1433081624
Short name T1086
Test name
Test status
Simulation time 37662493 ps
CPU time 1.26 seconds
Started Jun 27 04:45:40 PM PDT 24
Finished Jun 27 04:45:45 PM PDT 24
Peak memory 200372 kb
Host smart-055d5a46-1b80-499f-8fdc-9651cbe46cb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433081624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1433081624
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.596307037
Short name T1192
Test name
Test status
Simulation time 812566055 ps
CPU time 1.33 seconds
Started Jun 27 04:45:37 PM PDT 24
Finished Jun 27 04:45:42 PM PDT 24
Peak memory 199972 kb
Host smart-7abb8b39-42ec-47d8-a9e6-67318078e7de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596307037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.596307037
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2296575905
Short name T1207
Test name
Test status
Simulation time 60461810 ps
CPU time 0.65 seconds
Started Jun 27 04:45:28 PM PDT 24
Finished Jun 27 04:45:30 PM PDT 24
Peak memory 198448 kb
Host smart-fbc2b21a-85ec-4898-8f78-20a0120b1250
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296575905 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.2296575905
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.3944146493
Short name T1182
Test name
Test status
Simulation time 58568631 ps
CPU time 0.62 seconds
Started Jun 27 04:45:35 PM PDT 24
Finished Jun 27 04:45:38 PM PDT 24
Peak memory 195916 kb
Host smart-daaebaf4-afcb-46a3-8cf9-8ae06ce892d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944146493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3944146493
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.2700057633
Short name T1121
Test name
Test status
Simulation time 23936522 ps
CPU time 0.56 seconds
Started Jun 27 04:45:35 PM PDT 24
Finished Jun 27 04:45:38 PM PDT 24
Peak memory 194788 kb
Host smart-2579dc46-9d98-4bca-b887-cff392472059
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700057633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2700057633
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2459849751
Short name T1136
Test name
Test status
Simulation time 45031378 ps
CPU time 0.66 seconds
Started Jun 27 04:45:29 PM PDT 24
Finished Jun 27 04:45:31 PM PDT 24
Peak memory 195100 kb
Host smart-cbf884b0-cb36-44b7-97e8-34647aa52c5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459849751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2459849751
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.2015038931
Short name T1120
Test name
Test status
Simulation time 265388216 ps
CPU time 1.84 seconds
Started Jun 27 04:45:43 PM PDT 24
Finished Jun 27 04:45:49 PM PDT 24
Peak memory 200436 kb
Host smart-a9203561-2851-4e5e-af08-d247f00ce292
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015038931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.2015038931
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1682356579
Short name T73
Test name
Test status
Simulation time 182278843 ps
CPU time 0.96 seconds
Started Jun 27 04:45:43 PM PDT 24
Finished Jun 27 04:45:47 PM PDT 24
Peak memory 199188 kb
Host smart-473a2c2b-3278-4120-ba09-73b79bfcd61c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682356579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.1682356579
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3778746406
Short name T1202
Test name
Test status
Simulation time 24744796 ps
CPU time 0.75 seconds
Started Jun 27 04:45:43 PM PDT 24
Finished Jun 27 04:45:47 PM PDT 24
Peak memory 199876 kb
Host smart-d2fbd591-d700-4325-a5ce-1f91adcfbceb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778746406 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3778746406
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3154350015
Short name T1146
Test name
Test status
Simulation time 29264505 ps
CPU time 0.63 seconds
Started Jun 27 04:45:31 PM PDT 24
Finished Jun 27 04:45:34 PM PDT 24
Peak memory 195776 kb
Host smart-3ea41989-1436-4b54-b45a-869119d18f1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154350015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3154350015
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.4065667804
Short name T1178
Test name
Test status
Simulation time 13111540 ps
CPU time 0.58 seconds
Started Jun 27 04:45:29 PM PDT 24
Finished Jun 27 04:45:31 PM PDT 24
Peak memory 194656 kb
Host smart-b4a20c4f-4580-4890-9582-c91bb1183f32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065667804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.4065667804
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3602577403
Short name T70
Test name
Test status
Simulation time 36728728 ps
CPU time 0.64 seconds
Started Jun 27 04:45:43 PM PDT 24
Finished Jun 27 04:45:48 PM PDT 24
Peak memory 196284 kb
Host smart-51d89143-6fbf-4497-82c2-7ef497b5ebe4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602577403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3602577403
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.3045207366
Short name T1150
Test name
Test status
Simulation time 419428665 ps
CPU time 1.78 seconds
Started Jun 27 04:45:34 PM PDT 24
Finished Jun 27 04:45:38 PM PDT 24
Peak memory 200344 kb
Host smart-04f258d5-8f48-45b2-ba75-208d00225d85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045207366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.3045207366
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2407000411
Short name T74
Test name
Test status
Simulation time 138973573 ps
CPU time 1.32 seconds
Started Jun 27 04:45:36 PM PDT 24
Finished Jun 27 04:45:40 PM PDT 24
Peak memory 199692 kb
Host smart-3be272f0-56f9-43aa-95f5-2350f1bed113
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407000411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.2407000411
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1281841691
Short name T1104
Test name
Test status
Simulation time 32004397 ps
CPU time 0.82 seconds
Started Jun 27 04:45:37 PM PDT 24
Finished Jun 27 04:45:41 PM PDT 24
Peak memory 200092 kb
Host smart-41cccf39-6e2d-4088-848f-cfb5d807d6e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281841691 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1281841691
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2319472938
Short name T1172
Test name
Test status
Simulation time 13651118 ps
CPU time 0.58 seconds
Started Jun 27 04:45:35 PM PDT 24
Finished Jun 27 04:45:38 PM PDT 24
Peak memory 195844 kb
Host smart-9208498a-4114-4128-853c-2ef20a690fd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319472938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2319472938
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.3844694883
Short name T1162
Test name
Test status
Simulation time 12598217 ps
CPU time 0.62 seconds
Started Jun 27 04:45:26 PM PDT 24
Finished Jun 27 04:45:28 PM PDT 24
Peak memory 194720 kb
Host smart-739fd514-ad88-4654-a731-333920031787
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844694883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3844694883
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3433308816
Short name T65
Test name
Test status
Simulation time 60146861 ps
CPU time 0.64 seconds
Started Jun 27 04:45:34 PM PDT 24
Finished Jun 27 04:45:36 PM PDT 24
Peak memory 195968 kb
Host smart-ca115c60-aa91-482a-8287-b9715e1e1031
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433308816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.3433308816
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.3733506675
Short name T1114
Test name
Test status
Simulation time 257645008 ps
CPU time 1.37 seconds
Started Jun 27 04:45:40 PM PDT 24
Finished Jun 27 04:45:45 PM PDT 24
Peak memory 200408 kb
Host smart-26495d41-98e7-491d-9e5b-38f66df81ce7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733506675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3733506675
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3585536653
Short name T1204
Test name
Test status
Simulation time 687707404 ps
CPU time 0.91 seconds
Started Jun 27 04:45:41 PM PDT 24
Finished Jun 27 04:45:45 PM PDT 24
Peak memory 199412 kb
Host smart-e32f3d14-755b-4217-9486-4aa47f98eb28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585536653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3585536653
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1956439113
Short name T55
Test name
Test status
Simulation time 18963613 ps
CPU time 0.63 seconds
Started Jun 27 04:45:05 PM PDT 24
Finished Jun 27 04:45:12 PM PDT 24
Peak memory 195280 kb
Host smart-0b70a73f-75c0-4f37-8c37-1e062adc3f45
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956439113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.1956439113
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.691308113
Short name T1201
Test name
Test status
Simulation time 134459677 ps
CPU time 1.56 seconds
Started Jun 27 04:45:05 PM PDT 24
Finished Jun 27 04:45:13 PM PDT 24
Peak memory 197980 kb
Host smart-ec7ff755-f394-4ae4-a141-69c7a439ab38
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691308113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.691308113
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3978729465
Short name T1169
Test name
Test status
Simulation time 23878936 ps
CPU time 0.55 seconds
Started Jun 27 04:45:05 PM PDT 24
Finished Jun 27 04:45:12 PM PDT 24
Peak memory 195684 kb
Host smart-ac000caf-7caf-4963-811f-d4955856ffa4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978729465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3978729465
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1413964783
Short name T1145
Test name
Test status
Simulation time 116095929 ps
CPU time 0.83 seconds
Started Jun 27 04:45:08 PM PDT 24
Finished Jun 27 04:45:15 PM PDT 24
Peak memory 200148 kb
Host smart-0cdb70bf-50c1-44bb-848f-7fde2c3b1625
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413964783 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1413964783
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.1343945558
Short name T68
Test name
Test status
Simulation time 68161513 ps
CPU time 0.61 seconds
Started Jun 27 04:45:05 PM PDT 24
Finished Jun 27 04:45:12 PM PDT 24
Peak memory 196092 kb
Host smart-4d47f276-1cfc-42f9-bbe1-5424f1d6d706
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343945558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1343945558
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3172800751
Short name T1078
Test name
Test status
Simulation time 24130394 ps
CPU time 0.56 seconds
Started Jun 27 04:45:05 PM PDT 24
Finished Jun 27 04:45:12 PM PDT 24
Peak memory 194452 kb
Host smart-a1e06739-5d1b-41cb-8638-9c486771ed30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172800751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3172800751
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2440088126
Short name T1185
Test name
Test status
Simulation time 27921740 ps
CPU time 0.77 seconds
Started Jun 27 04:45:08 PM PDT 24
Finished Jun 27 04:45:14 PM PDT 24
Peak memory 196336 kb
Host smart-8ab8945c-8855-4887-936a-1976f616602d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440088126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2440088126
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2873070532
Short name T1161
Test name
Test status
Simulation time 27882415 ps
CPU time 1.27 seconds
Started Jun 27 04:45:05 PM PDT 24
Finished Jun 27 04:45:13 PM PDT 24
Peak memory 200128 kb
Host smart-20b05b3a-852c-4eae-a51e-088d1bab2946
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873070532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2873070532
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.113768707
Short name T1122
Test name
Test status
Simulation time 163874917 ps
CPU time 0.92 seconds
Started Jun 27 04:45:08 PM PDT 24
Finished Jun 27 04:45:14 PM PDT 24
Peak memory 198980 kb
Host smart-6b76f303-db81-42e9-ab5c-2b4b0ba9eaab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113768707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.113768707
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.2481335428
Short name T1179
Test name
Test status
Simulation time 40888889 ps
CPU time 0.59 seconds
Started Jun 27 04:45:33 PM PDT 24
Finished Jun 27 04:45:36 PM PDT 24
Peak memory 194756 kb
Host smart-8e1cb2d1-327a-46ec-8ead-5a565fc07945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481335428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2481335428
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.1723169204
Short name T1154
Test name
Test status
Simulation time 34800889 ps
CPU time 0.6 seconds
Started Jun 27 04:45:36 PM PDT 24
Finished Jun 27 04:45:40 PM PDT 24
Peak memory 194744 kb
Host smart-da284201-2a6e-4033-8902-fd501fe308e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723169204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1723169204
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2638574258
Short name T1190
Test name
Test status
Simulation time 13111888 ps
CPU time 0.54 seconds
Started Jun 27 04:45:30 PM PDT 24
Finished Jun 27 04:45:32 PM PDT 24
Peak memory 194672 kb
Host smart-2fdeebdd-4f08-4c71-bbc1-b09626fef898
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638574258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2638574258
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.805583268
Short name T1158
Test name
Test status
Simulation time 30511854 ps
CPU time 0.6 seconds
Started Jun 27 04:45:39 PM PDT 24
Finished Jun 27 04:45:43 PM PDT 24
Peak memory 194744 kb
Host smart-5a4f2517-8753-410c-ba11-b286fe5c60ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805583268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.805583268
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.986076653
Short name T1191
Test name
Test status
Simulation time 83625977 ps
CPU time 0.62 seconds
Started Jun 27 04:45:29 PM PDT 24
Finished Jun 27 04:45:31 PM PDT 24
Peak memory 194680 kb
Host smart-824f8895-e1d1-44dc-a177-8052c74be07a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986076653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.986076653
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.363845282
Short name T1148
Test name
Test status
Simulation time 12342799 ps
CPU time 0.57 seconds
Started Jun 27 04:45:34 PM PDT 24
Finished Jun 27 04:45:37 PM PDT 24
Peak memory 194680 kb
Host smart-346962e7-7318-4387-a13d-f8d54b39d6f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363845282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.363845282
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.1496138184
Short name T1094
Test name
Test status
Simulation time 14222257 ps
CPU time 0.62 seconds
Started Jun 27 04:45:34 PM PDT 24
Finished Jun 27 04:45:36 PM PDT 24
Peak memory 194680 kb
Host smart-c3097e55-2a66-4d7a-a3e1-25456b82bc4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496138184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1496138184
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.1747564328
Short name T1171
Test name
Test status
Simulation time 11274836 ps
CPU time 0.54 seconds
Started Jun 27 04:45:24 PM PDT 24
Finished Jun 27 04:45:26 PM PDT 24
Peak memory 194776 kb
Host smart-454b552c-ed46-4362-9c20-b194a2657fdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747564328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1747564328
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.3237865363
Short name T1151
Test name
Test status
Simulation time 13319516 ps
CPU time 0.57 seconds
Started Jun 27 04:45:33 PM PDT 24
Finished Jun 27 04:45:36 PM PDT 24
Peak memory 194756 kb
Host smart-223d20ef-de97-464b-ab5d-865b4fc872f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237865363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3237865363
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.2782235704
Short name T1131
Test name
Test status
Simulation time 15983878 ps
CPU time 0.56 seconds
Started Jun 27 04:45:24 PM PDT 24
Finished Jun 27 04:45:26 PM PDT 24
Peak memory 194788 kb
Host smart-d931ff44-af37-4db4-805e-23792641cc8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782235704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2782235704
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2752246467
Short name T1196
Test name
Test status
Simulation time 97556822 ps
CPU time 0.69 seconds
Started Jun 27 04:45:42 PM PDT 24
Finished Jun 27 04:45:46 PM PDT 24
Peak memory 195060 kb
Host smart-d2139dcb-ed90-4b30-a552-524131a61a3c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752246467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2752246467
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1477295209
Short name T1155
Test name
Test status
Simulation time 181861347 ps
CPU time 2.31 seconds
Started Jun 27 04:45:31 PM PDT 24
Finished Jun 27 04:45:35 PM PDT 24
Peak memory 198028 kb
Host smart-6f5732b3-295f-496b-a174-c0d073a2a11c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477295209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1477295209
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.4120700592
Short name T1126
Test name
Test status
Simulation time 26427048 ps
CPU time 0.6 seconds
Started Jun 27 04:45:32 PM PDT 24
Finished Jun 27 04:45:35 PM PDT 24
Peak memory 195764 kb
Host smart-66d41e1a-a3fe-4574-b416-597c02d7c887
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120700592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.4120700592
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2697688163
Short name T1159
Test name
Test status
Simulation time 30220009 ps
CPU time 0.76 seconds
Started Jun 27 04:45:36 PM PDT 24
Finished Jun 27 04:45:40 PM PDT 24
Peak memory 199484 kb
Host smart-6cdb984a-57b6-4999-b9bd-44cd540fcc7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697688163 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.2697688163
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.1875492471
Short name T1115
Test name
Test status
Simulation time 37722531 ps
CPU time 0.58 seconds
Started Jun 27 04:45:40 PM PDT 24
Finished Jun 27 04:45:44 PM PDT 24
Peak memory 195680 kb
Host smart-a8aaed13-e962-4e69-bd49-d25822f2fd2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875492471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.1875492471
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.639928147
Short name T1210
Test name
Test status
Simulation time 14238344 ps
CPU time 0.61 seconds
Started Jun 27 04:45:38 PM PDT 24
Finished Jun 27 04:45:42 PM PDT 24
Peak memory 194664 kb
Host smart-37808adf-ac0f-4626-a331-c15f475c5dd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639928147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.639928147
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.903222252
Short name T1142
Test name
Test status
Simulation time 20590087 ps
CPU time 0.67 seconds
Started Jun 27 04:45:39 PM PDT 24
Finished Jun 27 04:45:44 PM PDT 24
Peak memory 196204 kb
Host smart-e7d34f5b-4fce-4be6-af1a-95f2cbf62c2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903222252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_
outstanding.903222252
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2735957123
Short name T1079
Test name
Test status
Simulation time 213067525 ps
CPU time 1.32 seconds
Started Jun 27 04:45:03 PM PDT 24
Finished Jun 27 04:45:09 PM PDT 24
Peak memory 200296 kb
Host smart-84e46c52-8bb2-4a44-ad6e-6595d484d713
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735957123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2735957123
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1253592360
Short name T1195
Test name
Test status
Simulation time 161274697 ps
CPU time 1.35 seconds
Started Jun 27 04:45:02 PM PDT 24
Finished Jun 27 04:45:07 PM PDT 24
Peak memory 199732 kb
Host smart-62144e40-a6db-4737-8d4e-028649e7d380
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253592360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1253592360
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.1601105040
Short name T1088
Test name
Test status
Simulation time 43678879 ps
CPU time 0.63 seconds
Started Jun 27 04:45:29 PM PDT 24
Finished Jun 27 04:45:31 PM PDT 24
Peak memory 194788 kb
Host smart-e4b374b2-55bb-4b3b-b958-5de76548b4f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601105040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1601105040
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.571901737
Short name T1102
Test name
Test status
Simulation time 70266758 ps
CPU time 0.56 seconds
Started Jun 27 04:45:35 PM PDT 24
Finished Jun 27 04:45:38 PM PDT 24
Peak memory 194652 kb
Host smart-7bb97b67-cdaa-44e9-b008-eef96343cbc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571901737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.571901737
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.1274237829
Short name T1149
Test name
Test status
Simulation time 17422744 ps
CPU time 0.57 seconds
Started Jun 27 04:45:35 PM PDT 24
Finished Jun 27 04:45:39 PM PDT 24
Peak memory 194368 kb
Host smart-21ac48cf-0a46-4544-8be2-7f161f8377c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274237829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1274237829
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.2658932149
Short name T1199
Test name
Test status
Simulation time 61997701 ps
CPU time 0.6 seconds
Started Jun 27 04:45:39 PM PDT 24
Finished Jun 27 04:45:43 PM PDT 24
Peak memory 194584 kb
Host smart-a2b09c0b-08ba-4ce9-b055-6ac6a0b40cca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658932149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.2658932149
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.712350981
Short name T1111
Test name
Test status
Simulation time 12311549 ps
CPU time 0.63 seconds
Started Jun 27 04:45:40 PM PDT 24
Finished Jun 27 04:45:44 PM PDT 24
Peak memory 194540 kb
Host smart-2c032533-2b41-48f4-9c9c-387d65c37970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712350981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.712350981
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1690383550
Short name T1200
Test name
Test status
Simulation time 42135448 ps
CPU time 0.61 seconds
Started Jun 27 04:45:36 PM PDT 24
Finished Jun 27 04:45:40 PM PDT 24
Peak memory 194652 kb
Host smart-0bfa7f36-e44c-4a44-920d-014cccb0721e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690383550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1690383550
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.3489920146
Short name T1160
Test name
Test status
Simulation time 40193698 ps
CPU time 0.57 seconds
Started Jun 27 04:45:35 PM PDT 24
Finished Jun 27 04:45:39 PM PDT 24
Peak memory 194348 kb
Host smart-fcf596f5-de9f-46dd-bc1e-e71daf80fbb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489920146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3489920146
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.3691614025
Short name T1099
Test name
Test status
Simulation time 88590402 ps
CPU time 0.55 seconds
Started Jun 27 04:45:37 PM PDT 24
Finished Jun 27 04:45:41 PM PDT 24
Peak memory 194680 kb
Host smart-7e6d29f1-3254-49d8-ab43-cc17318c4cab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691614025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.3691614025
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.2996029029
Short name T1128
Test name
Test status
Simulation time 13961042 ps
CPU time 0.57 seconds
Started Jun 27 04:45:36 PM PDT 24
Finished Jun 27 04:45:39 PM PDT 24
Peak memory 194676 kb
Host smart-8ae3dd07-a9cb-4243-b2f6-c9ac81c5b610
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996029029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2996029029
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.3847035755
Short name T1082
Test name
Test status
Simulation time 19066371 ps
CPU time 0.56 seconds
Started Jun 27 04:45:36 PM PDT 24
Finished Jun 27 04:45:40 PM PDT 24
Peak memory 194756 kb
Host smart-a54ca78a-998c-44fa-92bc-554869a21e47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847035755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3847035755
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3760394997
Short name T50
Test name
Test status
Simulation time 23174389 ps
CPU time 0.68 seconds
Started Jun 27 04:45:39 PM PDT 24
Finished Jun 27 04:45:44 PM PDT 24
Peak memory 195272 kb
Host smart-9328704b-8cad-4b2e-a3fc-b93b46a9469f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760394997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.3760394997
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.934925747
Short name T1135
Test name
Test status
Simulation time 114087752 ps
CPU time 2.23 seconds
Started Jun 27 04:45:32 PM PDT 24
Finished Jun 27 04:45:37 PM PDT 24
Peak memory 197968 kb
Host smart-1663beb6-83a1-4335-993f-0eca247c8e5f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934925747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.934925747
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.493357442
Short name T1092
Test name
Test status
Simulation time 81059550 ps
CPU time 0.55 seconds
Started Jun 27 04:45:34 PM PDT 24
Finished Jun 27 04:45:36 PM PDT 24
Peak memory 195688 kb
Host smart-97c2c56a-304f-444d-a71e-a13db554d332
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493357442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.493357442
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2220586591
Short name T1085
Test name
Test status
Simulation time 83484042 ps
CPU time 0.77 seconds
Started Jun 27 04:45:32 PM PDT 24
Finished Jun 27 04:45:36 PM PDT 24
Peak memory 199328 kb
Host smart-24b53919-e3a3-4176-bf3b-237f19a99228
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220586591 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2220586591
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.3470614867
Short name T64
Test name
Test status
Simulation time 14344544 ps
CPU time 0.58 seconds
Started Jun 27 04:45:31 PM PDT 24
Finished Jun 27 04:45:34 PM PDT 24
Peak memory 196076 kb
Host smart-dc60854f-8da5-4c9a-8722-a56d16541e1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470614867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3470614867
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.3264204504
Short name T1107
Test name
Test status
Simulation time 14094634 ps
CPU time 0.55 seconds
Started Jun 27 04:45:24 PM PDT 24
Finished Jun 27 04:45:25 PM PDT 24
Peak memory 194556 kb
Host smart-107b0898-328f-4124-a3da-0b7e71f64f06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264204504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.3264204504
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.4261785165
Short name T71
Test name
Test status
Simulation time 29722722 ps
CPU time 0.7 seconds
Started Jun 27 04:45:35 PM PDT 24
Finished Jun 27 04:45:39 PM PDT 24
Peak memory 197060 kb
Host smart-3fffdbb5-a3b8-4dad-8359-98b053e16deb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261785165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.4261785165
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.2637888134
Short name T1184
Test name
Test status
Simulation time 37664492 ps
CPU time 1.86 seconds
Started Jun 27 04:45:19 PM PDT 24
Finished Jun 27 04:45:22 PM PDT 24
Peak memory 200356 kb
Host smart-336a3f59-ab46-4883-ad19-60515e664ce1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637888134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2637888134
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2718198980
Short name T79
Test name
Test status
Simulation time 179878089 ps
CPU time 1.27 seconds
Started Jun 27 04:45:34 PM PDT 24
Finished Jun 27 04:45:37 PM PDT 24
Peak memory 199712 kb
Host smart-e0d1d8dd-8e04-4fbe-90b1-c72788c2cc8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718198980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2718198980
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.596233935
Short name T1170
Test name
Test status
Simulation time 15403088 ps
CPU time 0.57 seconds
Started Jun 27 04:45:36 PM PDT 24
Finished Jun 27 04:45:40 PM PDT 24
Peak memory 194748 kb
Host smart-2f20b334-ea00-4727-b67a-950b6c8d806b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596233935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.596233935
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.1184976810
Short name T1109
Test name
Test status
Simulation time 23507359 ps
CPU time 0.59 seconds
Started Jun 27 04:45:37 PM PDT 24
Finished Jun 27 04:45:41 PM PDT 24
Peak memory 194748 kb
Host smart-58ae43e1-3bcb-408d-b4b8-4085063478b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184976810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1184976810
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.4236176916
Short name T1141
Test name
Test status
Simulation time 41846251 ps
CPU time 0.56 seconds
Started Jun 27 04:45:25 PM PDT 24
Finished Jun 27 04:45:27 PM PDT 24
Peak memory 194716 kb
Host smart-b9f87327-b774-4b34-bce5-1957bd264bfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236176916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.4236176916
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.3474228396
Short name T1189
Test name
Test status
Simulation time 19538719 ps
CPU time 0.58 seconds
Started Jun 27 04:45:42 PM PDT 24
Finished Jun 27 04:45:46 PM PDT 24
Peak memory 194616 kb
Host smart-af516e60-d972-4a02-b4bb-ea9389693781
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474228396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3474228396
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.683603399
Short name T1103
Test name
Test status
Simulation time 17800229 ps
CPU time 0.57 seconds
Started Jun 27 04:45:37 PM PDT 24
Finished Jun 27 04:45:41 PM PDT 24
Peak memory 194968 kb
Host smart-450767c0-1928-4ca5-8ae0-3690fc4cf21f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683603399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.683603399
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.1399905174
Short name T1096
Test name
Test status
Simulation time 22302339 ps
CPU time 0.58 seconds
Started Jun 27 04:45:42 PM PDT 24
Finished Jun 27 04:45:46 PM PDT 24
Peak memory 194624 kb
Host smart-e4eb507e-e873-4e4d-a73e-8337138b9e4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399905174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1399905174
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2889830926
Short name T1166
Test name
Test status
Simulation time 55562201 ps
CPU time 0.57 seconds
Started Jun 27 04:45:43 PM PDT 24
Finished Jun 27 04:45:46 PM PDT 24
Peak memory 194736 kb
Host smart-700f6172-18ce-4d20-9bc4-992185cd5c67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889830926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2889830926
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.3349108443
Short name T1116
Test name
Test status
Simulation time 21076602 ps
CPU time 0.55 seconds
Started Jun 27 04:45:34 PM PDT 24
Finished Jun 27 04:45:37 PM PDT 24
Peak memory 194744 kb
Host smart-f0668ab1-e7ef-48d7-be76-0d9205d274ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349108443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3349108443
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2260061961
Short name T1167
Test name
Test status
Simulation time 54387682 ps
CPU time 0.57 seconds
Started Jun 27 04:45:40 PM PDT 24
Finished Jun 27 04:45:44 PM PDT 24
Peak memory 194736 kb
Host smart-884bddda-789d-4bb6-8f52-790933230183
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260061961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2260061961
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.2591026715
Short name T1188
Test name
Test status
Simulation time 29475785 ps
CPU time 0.57 seconds
Started Jun 27 04:45:36 PM PDT 24
Finished Jun 27 04:45:41 PM PDT 24
Peak memory 194976 kb
Host smart-4e37a0c1-3b4a-401d-b65f-d8e18fdb0070
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591026715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2591026715
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2805107224
Short name T1080
Test name
Test status
Simulation time 18561242 ps
CPU time 0.66 seconds
Started Jun 27 04:45:24 PM PDT 24
Finished Jun 27 04:45:26 PM PDT 24
Peak memory 197564 kb
Host smart-1b56e753-1d8f-4c50-8835-e0506fcefbb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805107224 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.2805107224
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3391212566
Short name T51
Test name
Test status
Simulation time 75914601 ps
CPU time 0.64 seconds
Started Jun 27 04:45:26 PM PDT 24
Finished Jun 27 04:45:28 PM PDT 24
Peak memory 195768 kb
Host smart-be20e7ac-3725-4a5d-baeb-97f7294967f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391212566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3391212566
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3809466944
Short name T1077
Test name
Test status
Simulation time 59755460 ps
CPU time 0.58 seconds
Started Jun 27 04:45:28 PM PDT 24
Finished Jun 27 04:45:29 PM PDT 24
Peak memory 194684 kb
Host smart-431a521c-f3de-49cd-891e-47ea3a86939e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809466944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3809466944
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.449798989
Short name T69
Test name
Test status
Simulation time 20616723 ps
CPU time 0.67 seconds
Started Jun 27 04:45:37 PM PDT 24
Finished Jun 27 04:45:42 PM PDT 24
Peak memory 196848 kb
Host smart-ec976236-e91e-477c-81c9-6818bdb5c4d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449798989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_
outstanding.449798989
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.3185808526
Short name T1193
Test name
Test status
Simulation time 40167477 ps
CPU time 1.91 seconds
Started Jun 27 04:45:24 PM PDT 24
Finished Jun 27 04:45:27 PM PDT 24
Peak memory 200392 kb
Host smart-0693d1d6-89ba-4d14-823c-a7c12e5ccecc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185808526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3185808526
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.4225065249
Short name T82
Test name
Test status
Simulation time 126426389 ps
CPU time 1.27 seconds
Started Jun 27 04:45:33 PM PDT 24
Finished Jun 27 04:45:36 PM PDT 24
Peak memory 199580 kb
Host smart-72a64281-f238-4056-9bc7-8dc0df44738b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225065249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.4225065249
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2007421838
Short name T1211
Test name
Test status
Simulation time 102535042 ps
CPU time 0.86 seconds
Started Jun 27 04:45:32 PM PDT 24
Finished Jun 27 04:45:35 PM PDT 24
Peak memory 200172 kb
Host smart-58f7871c-ca1e-4bb2-a058-64671c358288
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007421838 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2007421838
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.3422489403
Short name T66
Test name
Test status
Simulation time 47656905 ps
CPU time 0.62 seconds
Started Jun 27 04:45:23 PM PDT 24
Finished Jun 27 04:45:25 PM PDT 24
Peak memory 195924 kb
Host smart-c3fb3fc1-3e5d-4e9e-936c-f9315b28952f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422489403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3422489403
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1788435079
Short name T1106
Test name
Test status
Simulation time 12826984 ps
CPU time 0.56 seconds
Started Jun 27 04:45:21 PM PDT 24
Finished Jun 27 04:45:23 PM PDT 24
Peak memory 194700 kb
Host smart-1ef12352-1d2b-4d7e-a6e4-be46fcd0c1e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788435079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1788435079
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.679762958
Short name T72
Test name
Test status
Simulation time 27094039 ps
CPU time 0.71 seconds
Started Jun 27 04:45:23 PM PDT 24
Finished Jun 27 04:45:25 PM PDT 24
Peak memory 196204 kb
Host smart-4e7877ed-73c1-4281-b0e4-4df4cd71c315
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679762958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_
outstanding.679762958
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.3795367757
Short name T1139
Test name
Test status
Simulation time 50902261 ps
CPU time 1.08 seconds
Started Jun 27 04:45:21 PM PDT 24
Finished Jun 27 04:45:23 PM PDT 24
Peak memory 200388 kb
Host smart-9dfc568d-63dd-45f5-9101-bb06ccf1fb51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795367757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3795367757
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2038404535
Short name T112
Test name
Test status
Simulation time 305164906 ps
CPU time 1.27 seconds
Started Jun 27 04:45:25 PM PDT 24
Finished Jun 27 04:45:28 PM PDT 24
Peak memory 199796 kb
Host smart-8beefce7-0ef8-469c-a26d-a7bb028414c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038404535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.2038404535
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2331372743
Short name T1132
Test name
Test status
Simulation time 99505940 ps
CPU time 0.84 seconds
Started Jun 27 04:45:25 PM PDT 24
Finished Jun 27 04:45:27 PM PDT 24
Peak memory 200128 kb
Host smart-88f784ee-578c-4d5f-963e-35cfe8937d8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331372743 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2331372743
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.4042681612
Short name T1119
Test name
Test status
Simulation time 62477818 ps
CPU time 0.65 seconds
Started Jun 27 04:45:30 PM PDT 24
Finished Jun 27 04:45:33 PM PDT 24
Peak memory 195980 kb
Host smart-640a744a-8535-44c2-993e-1b37b251c5a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042681612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.4042681612
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1661672298
Short name T1125
Test name
Test status
Simulation time 106065355 ps
CPU time 0.54 seconds
Started Jun 27 04:45:23 PM PDT 24
Finished Jun 27 04:45:25 PM PDT 24
Peak memory 194632 kb
Host smart-b7df2396-33f0-437e-be6f-e308711073fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661672298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1661672298
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1295052018
Short name T1124
Test name
Test status
Simulation time 89855715 ps
CPU time 0.69 seconds
Started Jun 27 04:45:20 PM PDT 24
Finished Jun 27 04:45:22 PM PDT 24
Peak memory 196344 kb
Host smart-4b867fe6-a6dd-432f-b109-603e995b5551
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295052018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1295052018
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.4122355740
Short name T1110
Test name
Test status
Simulation time 658199801 ps
CPU time 2.53 seconds
Started Jun 27 04:45:22 PM PDT 24
Finished Jun 27 04:45:26 PM PDT 24
Peak memory 200376 kb
Host smart-f139dfa8-fca5-47a7-a24d-254204e5b30a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122355740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.4122355740
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3086576232
Short name T77
Test name
Test status
Simulation time 158568963 ps
CPU time 0.85 seconds
Started Jun 27 04:45:26 PM PDT 24
Finished Jun 27 04:45:28 PM PDT 24
Peak memory 199232 kb
Host smart-9b856f1f-bcc9-4b01-97c6-5f7001a72a88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086576232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3086576232
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3895427433
Short name T1180
Test name
Test status
Simulation time 136086163 ps
CPU time 0.84 seconds
Started Jun 27 04:45:29 PM PDT 24
Finished Jun 27 04:45:31 PM PDT 24
Peak memory 199804 kb
Host smart-6d043892-e1ff-47d3-a750-16a7c7ae2bde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895427433 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.3895427433
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.524387978
Short name T1206
Test name
Test status
Simulation time 36967310 ps
CPU time 0.62 seconds
Started Jun 27 04:45:28 PM PDT 24
Finished Jun 27 04:45:29 PM PDT 24
Peak memory 195708 kb
Host smart-a4d441a5-50ec-498d-adc7-c1e1f85f5211
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524387978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.524387978
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.2040441376
Short name T1153
Test name
Test status
Simulation time 12450361 ps
CPU time 0.53 seconds
Started Jun 27 04:45:28 PM PDT 24
Finished Jun 27 04:45:29 PM PDT 24
Peak memory 194676 kb
Host smart-0697f09d-2d96-4a75-a5ca-142fda82bad9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040441376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2040441376
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3741173659
Short name T1147
Test name
Test status
Simulation time 52980590 ps
CPU time 0.7 seconds
Started Jun 27 04:45:34 PM PDT 24
Finished Jun 27 04:45:37 PM PDT 24
Peak memory 197936 kb
Host smart-8cdc00d2-38f4-4f9d-8cf6-58e457a977ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741173659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.3741173659
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.724706405
Short name T1140
Test name
Test status
Simulation time 521801471 ps
CPU time 1.67 seconds
Started Jun 27 04:45:25 PM PDT 24
Finished Jun 27 04:45:28 PM PDT 24
Peak memory 200288 kb
Host smart-39d5c499-58f6-4f9e-ba0e-15dccc01fe35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724706405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.724706405
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2473655727
Short name T76
Test name
Test status
Simulation time 714527456 ps
CPU time 1.3 seconds
Started Jun 27 04:45:30 PM PDT 24
Finished Jun 27 04:45:33 PM PDT 24
Peak memory 199508 kb
Host smart-92f9dee0-eb7f-48ff-8b9d-75be1764268c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473655727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2473655727
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2915841560
Short name T1084
Test name
Test status
Simulation time 16977303 ps
CPU time 0.77 seconds
Started Jun 27 04:45:25 PM PDT 24
Finished Jun 27 04:45:27 PM PDT 24
Peak memory 199052 kb
Host smart-588271ca-67cc-4040-ae82-c906594eaaad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915841560 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.2915841560
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.322816217
Short name T1203
Test name
Test status
Simulation time 13743100 ps
CPU time 0.63 seconds
Started Jun 27 04:45:29 PM PDT 24
Finished Jun 27 04:45:31 PM PDT 24
Peak memory 195760 kb
Host smart-59e1ad78-cfc9-4cd4-81c3-21c1d2067766
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322816217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.322816217
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1114568045
Short name T1176
Test name
Test status
Simulation time 13203254 ps
CPU time 0.56 seconds
Started Jun 27 04:45:29 PM PDT 24
Finished Jun 27 04:45:31 PM PDT 24
Peak memory 194728 kb
Host smart-26627c35-8d4c-48f3-9af6-04143852e3fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114568045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1114568045
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3110001186
Short name T1117
Test name
Test status
Simulation time 59332717 ps
CPU time 0.72 seconds
Started Jun 27 04:45:40 PM PDT 24
Finished Jun 27 04:45:44 PM PDT 24
Peak memory 197260 kb
Host smart-a704edef-1874-4295-a7fb-5fd21f95f43a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110001186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.3110001186
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.300994918
Short name T1095
Test name
Test status
Simulation time 98724747 ps
CPU time 1.12 seconds
Started Jun 27 04:45:29 PM PDT 24
Finished Jun 27 04:45:32 PM PDT 24
Peak memory 200276 kb
Host smart-74d09fdb-e206-43c2-bc0c-ba8261fa5721
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300994918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.300994918
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1209211764
Short name T81
Test name
Test status
Simulation time 83861982 ps
CPU time 0.88 seconds
Started Jun 27 04:45:31 PM PDT 24
Finished Jun 27 04:45:34 PM PDT 24
Peak memory 199280 kb
Host smart-b9681071-a992-4638-b677-3acadb8b7541
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209211764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1209211764
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.199384463
Short name T1023
Test name
Test status
Simulation time 39814173 ps
CPU time 0.63 seconds
Started Jun 27 04:53:44 PM PDT 24
Finished Jun 27 04:53:49 PM PDT 24
Peak memory 194500 kb
Host smart-4bbcd87a-a4fa-4cf6-913b-63fb2fb5aab1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199384463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.199384463
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.1086144152
Short name T697
Test name
Test status
Simulation time 74834522166 ps
CPU time 189.61 seconds
Started Jun 27 04:53:44 PM PDT 24
Finished Jun 27 04:56:58 PM PDT 24
Peak memory 199908 kb
Host smart-832db5fd-3efa-4892-8c98-00af06a2d4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086144152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1086144152
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.726081207
Short name T568
Test name
Test status
Simulation time 88898349542 ps
CPU time 73.36 seconds
Started Jun 27 04:53:41 PM PDT 24
Finished Jun 27 04:55:00 PM PDT 24
Peak memory 199988 kb
Host smart-9125bb21-63f6-45c9-bb74-095f24770536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726081207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.726081207
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.4217309420
Short name T180
Test name
Test status
Simulation time 19199880773 ps
CPU time 18.96 seconds
Started Jun 27 04:53:53 PM PDT 24
Finished Jun 27 04:54:14 PM PDT 24
Peak memory 199988 kb
Host smart-ad7119eb-f458-46f5-9a26-38e13beac087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217309420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.4217309420
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.183066010
Short name T1057
Test name
Test status
Simulation time 21299127582 ps
CPU time 35.04 seconds
Started Jun 27 04:53:41 PM PDT 24
Finished Jun 27 04:54:21 PM PDT 24
Peak memory 199940 kb
Host smart-92fea2f0-ae6a-4fd9-a010-1e46a4b17083
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183066010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.183066010
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.3365993583
Short name T486
Test name
Test status
Simulation time 83789478720 ps
CPU time 475.41 seconds
Started Jun 27 04:53:43 PM PDT 24
Finished Jun 27 05:01:43 PM PDT 24
Peak memory 199892 kb
Host smart-b6b5bae1-c1da-4656-a53e-df6ef75249aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3365993583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.3365993583
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.1052832898
Short name T994
Test name
Test status
Simulation time 2370405069 ps
CPU time 4.42 seconds
Started Jun 27 04:53:42 PM PDT 24
Finished Jun 27 04:53:51 PM PDT 24
Peak memory 197224 kb
Host smart-9b6bde1a-7fef-494a-9633-bfaf2565a510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052832898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1052832898
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_perf.1485939306
Short name T966
Test name
Test status
Simulation time 14704921378 ps
CPU time 350.51 seconds
Started Jun 27 04:53:43 PM PDT 24
Finished Jun 27 04:59:38 PM PDT 24
Peak memory 199844 kb
Host smart-10b73138-ad70-4de0-99cb-ecdd7f0c81aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1485939306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1485939306
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.475358591
Short name T578
Test name
Test status
Simulation time 5125783307 ps
CPU time 21.95 seconds
Started Jun 27 04:53:46 PM PDT 24
Finished Jun 27 04:54:12 PM PDT 24
Peak memory 198124 kb
Host smart-a8842a30-5225-46a6-ab20-623e3121866e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=475358591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.475358591
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.1521999183
Short name T617
Test name
Test status
Simulation time 35302116788 ps
CPU time 21.89 seconds
Started Jun 27 04:53:40 PM PDT 24
Finished Jun 27 04:54:07 PM PDT 24
Peak memory 199868 kb
Host smart-7ab1e5b5-eaf0-4c90-9b36-56ba21ffdfff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521999183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.1521999183
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.4012422382
Short name T768
Test name
Test status
Simulation time 46947256565 ps
CPU time 19.86 seconds
Started Jun 27 04:53:43 PM PDT 24
Finished Jun 27 04:54:08 PM PDT 24
Peak memory 196008 kb
Host smart-7bac9fc2-0bd6-4c55-8bfa-1b7517e4ca56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012422382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.4012422382
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.1217491751
Short name T984
Test name
Test status
Simulation time 888211100 ps
CPU time 3.5 seconds
Started Jun 27 04:53:54 PM PDT 24
Finished Jun 27 04:54:00 PM PDT 24
Peak memory 199636 kb
Host smart-acdcef3f-c008-4403-be32-c40fe5d5bb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217491751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1217491751
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.1771925981
Short name T1016
Test name
Test status
Simulation time 803754371 ps
CPU time 2.52 seconds
Started Jun 27 04:53:53 PM PDT 24
Finished Jun 27 04:53:57 PM PDT 24
Peak memory 199804 kb
Host smart-98354b43-9a1f-4b4a-b7c8-3c0f121705f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771925981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1771925981
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.1848266062
Short name T509
Test name
Test status
Simulation time 8169820796 ps
CPU time 14.19 seconds
Started Jun 27 04:53:43 PM PDT 24
Finished Jun 27 04:54:02 PM PDT 24
Peak memory 199892 kb
Host smart-e6224dfc-8da6-4bb9-a5e4-c4d895280fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848266062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1848266062
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.2847210627
Short name T589
Test name
Test status
Simulation time 29746344 ps
CPU time 0.59 seconds
Started Jun 27 04:53:58 PM PDT 24
Finished Jun 27 04:54:01 PM PDT 24
Peak memory 195512 kb
Host smart-03a6ed0b-1aab-44f7-a534-f17cbca1bcfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847210627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.2847210627
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.396326690
Short name T1069
Test name
Test status
Simulation time 108635447522 ps
CPU time 108.6 seconds
Started Jun 27 04:53:43 PM PDT 24
Finished Jun 27 04:55:37 PM PDT 24
Peak memory 199992 kb
Host smart-c1678abc-4018-402c-bb4d-71eb81d18ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396326690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.396326690
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.1968120280
Short name T911
Test name
Test status
Simulation time 59449324496 ps
CPU time 73.74 seconds
Started Jun 27 04:53:52 PM PDT 24
Finished Jun 27 04:55:07 PM PDT 24
Peak memory 199964 kb
Host smart-60524c2e-627f-44ba-b1e6-c0ec896c226b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968120280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.1968120280
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.3623428672
Short name T489
Test name
Test status
Simulation time 15394944711 ps
CPU time 21.67 seconds
Started Jun 27 04:53:44 PM PDT 24
Finished Jun 27 04:54:10 PM PDT 24
Peak memory 196352 kb
Host smart-6335c6d9-e754-459e-b7bb-4b01956b7daa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623428672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.3623428672
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.222092863
Short name T316
Test name
Test status
Simulation time 72226796005 ps
CPU time 686.54 seconds
Started Jun 27 04:53:57 PM PDT 24
Finished Jun 27 05:05:26 PM PDT 24
Peak memory 200112 kb
Host smart-04069dcb-69fa-45cf-900c-cc0f3ecb47f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=222092863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.222092863
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.3350417696
Short name T785
Test name
Test status
Simulation time 182539048 ps
CPU time 1.99 seconds
Started Jun 27 04:53:43 PM PDT 24
Finished Jun 27 04:53:50 PM PDT 24
Peak memory 198612 kb
Host smart-7c474abd-a651-464f-a33a-37d30240646e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350417696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3350417696
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_perf.3583542692
Short name T443
Test name
Test status
Simulation time 26842469172 ps
CPU time 142.07 seconds
Started Jun 27 04:53:58 PM PDT 24
Finished Jun 27 04:56:23 PM PDT 24
Peak memory 200176 kb
Host smart-42e73869-7ba9-4939-a702-b5ec2bcb543f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3583542692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3583542692
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.3733671684
Short name T1015
Test name
Test status
Simulation time 6604235446 ps
CPU time 65.32 seconds
Started Jun 27 04:53:44 PM PDT 24
Finished Jun 27 04:54:54 PM PDT 24
Peak memory 198716 kb
Host smart-951f92d1-c39d-4f55-9b1d-1d9887523b2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3733671684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3733671684
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.4024963156
Short name T284
Test name
Test status
Simulation time 39230789330 ps
CPU time 22.25 seconds
Started Jun 27 04:53:57 PM PDT 24
Finished Jun 27 04:54:21 PM PDT 24
Peak memory 199924 kb
Host smart-583def1c-d972-43e8-928b-267b2441fcd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024963156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.4024963156
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.4049639054
Short name T809
Test name
Test status
Simulation time 65393860108 ps
CPU time 21.34 seconds
Started Jun 27 04:53:53 PM PDT 24
Finished Jun 27 04:54:16 PM PDT 24
Peak memory 196200 kb
Host smart-ee2599af-a1c1-4a93-aa5d-38aa6c3416d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049639054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.4049639054
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.493267069
Short name T83
Test name
Test status
Simulation time 55827965 ps
CPU time 0.84 seconds
Started Jun 27 04:53:43 PM PDT 24
Finished Jun 27 04:53:49 PM PDT 24
Peak memory 218260 kb
Host smart-4d48d981-cf27-498e-ae5a-bdc93ea28209
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493267069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.493267069
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.3957162733
Short name T839
Test name
Test status
Simulation time 5920999178 ps
CPU time 22.61 seconds
Started Jun 27 04:53:54 PM PDT 24
Finished Jun 27 04:54:18 PM PDT 24
Peak memory 199864 kb
Host smart-02c91d41-1975-4723-8221-ac0db2b4ed0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957162733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3957162733
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.2277661989
Short name T303
Test name
Test status
Simulation time 211063365528 ps
CPU time 109.09 seconds
Started Jun 27 04:53:44 PM PDT 24
Finished Jun 27 04:55:37 PM PDT 24
Peak memory 199784 kb
Host smart-fced5479-2c59-48f5-86cf-ad5829806917
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277661989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2277661989
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.16491858
Short name T283
Test name
Test status
Simulation time 1808121349 ps
CPU time 3.81 seconds
Started Jun 27 04:53:44 PM PDT 24
Finished Jun 27 04:53:53 PM PDT 24
Peak memory 198520 kb
Host smart-f4a06131-55ad-4bc4-bd6b-26523e280033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16491858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.16491858
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.1993554904
Short name T538
Test name
Test status
Simulation time 53011852503 ps
CPU time 82.58 seconds
Started Jun 27 04:53:53 PM PDT 24
Finished Jun 27 04:55:18 PM PDT 24
Peak memory 199972 kb
Host smart-a84f50ff-f7aa-4df1-87fe-f2c474a8dac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993554904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1993554904
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.2637032790
Short name T583
Test name
Test status
Simulation time 15537089 ps
CPU time 0.59 seconds
Started Jun 27 04:54:13 PM PDT 24
Finished Jun 27 04:54:16 PM PDT 24
Peak memory 195808 kb
Host smart-cc10e81b-55ea-418c-b267-436f4352189a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637032790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2637032790
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.2880808645
Short name T559
Test name
Test status
Simulation time 192143591101 ps
CPU time 62.49 seconds
Started Jun 27 04:54:11 PM PDT 24
Finished Jun 27 04:55:16 PM PDT 24
Peak memory 199884 kb
Host smart-c9611b2d-ca31-46de-a7a0-f064134de8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880808645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2880808645
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.31485276
Short name T987
Test name
Test status
Simulation time 72303339049 ps
CPU time 117.36 seconds
Started Jun 27 04:54:14 PM PDT 24
Finished Jun 27 04:56:14 PM PDT 24
Peak memory 199784 kb
Host smart-18ec195e-0bd4-4b57-bd4a-221afbcfcb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31485276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.31485276
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_intr.2842943337
Short name T22
Test name
Test status
Simulation time 54010194207 ps
CPU time 139.29 seconds
Started Jun 27 04:54:13 PM PDT 24
Finished Jun 27 04:56:35 PM PDT 24
Peak memory 199976 kb
Host smart-8b5fcc49-9d0d-478c-8a4e-7b25756104d8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842943337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2842943337
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.609696303
Short name T928
Test name
Test status
Simulation time 154981153654 ps
CPU time 210.22 seconds
Started Jun 27 04:54:10 PM PDT 24
Finished Jun 27 04:57:42 PM PDT 24
Peak memory 199960 kb
Host smart-c5b941cf-9bb3-4f4b-989f-18f0a9bf213a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=609696303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.609696303
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.1509009012
Short name T695
Test name
Test status
Simulation time 7348882044 ps
CPU time 13.01 seconds
Started Jun 27 04:54:15 PM PDT 24
Finished Jun 27 04:54:30 PM PDT 24
Peak memory 198624 kb
Host smart-0d659dc0-70fc-44f9-9eec-0b53d18fe890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509009012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.1509009012
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_perf.4093165475
Short name T576
Test name
Test status
Simulation time 11251951119 ps
CPU time 334.59 seconds
Started Jun 27 04:54:15 PM PDT 24
Finished Jun 27 04:59:52 PM PDT 24
Peak memory 199956 kb
Host smart-edfde80e-a1d9-4ec8-9915-4277524cba93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4093165475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.4093165475
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.2090658034
Short name T371
Test name
Test status
Simulation time 1342967592 ps
CPU time 0.71 seconds
Started Jun 27 04:54:16 PM PDT 24
Finished Jun 27 04:54:18 PM PDT 24
Peak memory 195280 kb
Host smart-ce04a60c-982b-4af1-9e42-be74d2710b12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2090658034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2090658034
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.4254722525
Short name T487
Test name
Test status
Simulation time 217256827665 ps
CPU time 190.63 seconds
Started Jun 27 04:54:15 PM PDT 24
Finished Jun 27 04:57:27 PM PDT 24
Peak memory 199928 kb
Host smart-f8b36d67-1898-448e-b587-2e17f55c78a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254722525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.4254722525
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3977668069
Short name T954
Test name
Test status
Simulation time 34805913847 ps
CPU time 14.54 seconds
Started Jun 27 04:54:12 PM PDT 24
Finished Jun 27 04:54:29 PM PDT 24
Peak memory 196056 kb
Host smart-153fe092-a589-4471-a249-803841aba157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977668069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3977668069
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.1139891296
Short name T753
Test name
Test status
Simulation time 6092346724 ps
CPU time 18.26 seconds
Started Jun 27 04:54:14 PM PDT 24
Finished Jun 27 04:54:35 PM PDT 24
Peak memory 199692 kb
Host smart-4b8f0d38-530e-42d1-a571-ff29801496fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139891296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.1139891296
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.3342496265
Short name T437
Test name
Test status
Simulation time 7159741728 ps
CPU time 9.75 seconds
Started Jun 27 04:54:10 PM PDT 24
Finished Jun 27 04:54:22 PM PDT 24
Peak memory 199216 kb
Host smart-358c0351-ebd6-41ff-b4e9-0118ff3f0ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342496265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3342496265
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.2443327656
Short name T41
Test name
Test status
Simulation time 25265171003 ps
CPU time 62.3 seconds
Started Jun 27 04:54:16 PM PDT 24
Finished Jun 27 04:55:20 PM PDT 24
Peak memory 199692 kb
Host smart-1d31522f-30c1-4345-bd70-430251420511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443327656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2443327656
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.1870806212
Short name T735
Test name
Test status
Simulation time 9372885346 ps
CPU time 5.03 seconds
Started Jun 27 04:57:14 PM PDT 24
Finished Jun 27 04:57:22 PM PDT 24
Peak memory 198988 kb
Host smart-a2fd125e-90b7-4458-85ab-60280f5ac9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870806212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1870806212
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.2422145753
Short name T884
Test name
Test status
Simulation time 28554998441 ps
CPU time 47.41 seconds
Started Jun 27 04:57:08 PM PDT 24
Finished Jun 27 04:57:57 PM PDT 24
Peak memory 199884 kb
Host smart-ad9f801f-fb9b-4fbe-bcea-0957c90e33a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422145753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2422145753
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.3156727884
Short name T728
Test name
Test status
Simulation time 47616553145 ps
CPU time 63.71 seconds
Started Jun 27 04:57:04 PM PDT 24
Finished Jun 27 04:58:09 PM PDT 24
Peak memory 199800 kb
Host smart-c4cf1127-547a-4e58-9fc6-ee413b4d32ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156727884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.3156727884
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.761389490
Short name T612
Test name
Test status
Simulation time 130817005316 ps
CPU time 429.45 seconds
Started Jun 27 04:57:13 PM PDT 24
Finished Jun 27 05:04:25 PM PDT 24
Peak memory 199988 kb
Host smart-797113b2-349a-432d-99c1-3d8b810e18b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761389490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.761389490
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.785555986
Short name T234
Test name
Test status
Simulation time 151876266986 ps
CPU time 33.06 seconds
Started Jun 27 04:57:11 PM PDT 24
Finished Jun 27 04:57:46 PM PDT 24
Peak memory 199860 kb
Host smart-8cd68655-b562-42b3-9278-77dd45d2a110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785555986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.785555986
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1833261114
Short name T176
Test name
Test status
Simulation time 58883531743 ps
CPU time 94.07 seconds
Started Jun 27 04:57:08 PM PDT 24
Finished Jun 27 04:58:43 PM PDT 24
Peak memory 199808 kb
Host smart-ec4c9866-983e-478d-8b58-b7d2761b810e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833261114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1833261114
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.265649312
Short name T916
Test name
Test status
Simulation time 101362956682 ps
CPU time 92.61 seconds
Started Jun 27 04:57:06 PM PDT 24
Finished Jun 27 04:58:40 PM PDT 24
Peak memory 199868 kb
Host smart-d5e2050d-61f7-488a-b0cc-d4bc85f17401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265649312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.265649312
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.2546457280
Short name T991
Test name
Test status
Simulation time 245733392563 ps
CPU time 105.41 seconds
Started Jun 27 04:57:13 PM PDT 24
Finished Jun 27 04:59:01 PM PDT 24
Peak memory 199928 kb
Host smart-654d9145-36f3-4756-bf5c-b44010fb6a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546457280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2546457280
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.190972997
Short name T189
Test name
Test status
Simulation time 136693144390 ps
CPU time 103.82 seconds
Started Jun 27 04:57:06 PM PDT 24
Finished Jun 27 04:58:51 PM PDT 24
Peak memory 199932 kb
Host smart-a748b3b8-d8b8-487f-a7b5-d6ee4f99a487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190972997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.190972997
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.3375507442
Short name T361
Test name
Test status
Simulation time 37900007 ps
CPU time 0.55 seconds
Started Jun 27 04:54:28 PM PDT 24
Finished Jun 27 04:54:30 PM PDT 24
Peak memory 195304 kb
Host smart-a08f377b-ab44-4d5f-bb2b-0663fdfd6601
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375507442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3375507442
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.2181292859
Short name T453
Test name
Test status
Simulation time 55520974735 ps
CPU time 80.43 seconds
Started Jun 27 04:54:12 PM PDT 24
Finished Jun 27 04:55:35 PM PDT 24
Peak memory 199952 kb
Host smart-a99bd14c-d6c4-47de-8e17-63977b5f884f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181292859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2181292859
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.3987136685
Short name T957
Test name
Test status
Simulation time 53788995618 ps
CPU time 77.54 seconds
Started Jun 27 04:54:38 PM PDT 24
Finished Jun 27 04:55:59 PM PDT 24
Peak memory 199832 kb
Host smart-802ce0a5-91ec-41f3-b08f-05e615118974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987136685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3987136685
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.1456609302
Short name T132
Test name
Test status
Simulation time 18920767748 ps
CPU time 30.5 seconds
Started Jun 27 04:54:30 PM PDT 24
Finished Jun 27 04:55:04 PM PDT 24
Peak memory 199988 kb
Host smart-855147bc-a339-4c22-ba45-14d50bf0bab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456609302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1456609302
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.147453953
Short name T530
Test name
Test status
Simulation time 25350599185 ps
CPU time 11.66 seconds
Started Jun 27 04:54:33 PM PDT 24
Finished Jun 27 04:54:48 PM PDT 24
Peak memory 199664 kb
Host smart-72b2906b-61ba-4845-b115-4e56c58f033b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147453953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.147453953
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.3760409451
Short name T628
Test name
Test status
Simulation time 353749652037 ps
CPU time 420.76 seconds
Started Jun 27 04:54:33 PM PDT 24
Finished Jun 27 05:01:37 PM PDT 24
Peak memory 199916 kb
Host smart-8cccc5ee-4da8-4c33-a4ec-6d9d92d2a9f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3760409451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3760409451
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.3554209991
Short name T1064
Test name
Test status
Simulation time 7554575117 ps
CPU time 14.78 seconds
Started Jun 27 04:54:28 PM PDT 24
Finished Jun 27 04:54:44 PM PDT 24
Peak memory 199648 kb
Host smart-dd240721-d7c2-4923-89bb-acc79c6a7be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554209991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.3554209991
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_perf.1236327175
Short name T647
Test name
Test status
Simulation time 3185489852 ps
CPU time 85.55 seconds
Started Jun 27 04:54:39 PM PDT 24
Finished Jun 27 04:56:09 PM PDT 24
Peak memory 199624 kb
Host smart-a6e63de0-6020-4539-9689-a7bcfa0a554d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1236327175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1236327175
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.687653476
Short name T557
Test name
Test status
Simulation time 6171220306 ps
CPU time 10.94 seconds
Started Jun 27 04:54:31 PM PDT 24
Finished Jun 27 04:54:44 PM PDT 24
Peak memory 199244 kb
Host smart-c141f65f-8e2e-4751-80a6-4d219d05a97e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=687653476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.687653476
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.1472712011
Short name T433
Test name
Test status
Simulation time 38883659899 ps
CPU time 15.21 seconds
Started Jun 27 04:54:29 PM PDT 24
Finished Jun 27 04:54:47 PM PDT 24
Peak memory 199728 kb
Host smart-c955892c-943c-403a-adee-e7d3e34bc6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472712011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1472712011
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.2039294599
Short name T903
Test name
Test status
Simulation time 602091921 ps
CPU time 1.5 seconds
Started Jun 27 04:54:27 PM PDT 24
Finished Jun 27 04:54:30 PM PDT 24
Peak memory 195304 kb
Host smart-7f6bdc1d-24fb-4fc7-9703-51eede6b8f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039294599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2039294599
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.322701430
Short name T1049
Test name
Test status
Simulation time 927806379 ps
CPU time 4.89 seconds
Started Jun 27 04:54:11 PM PDT 24
Finished Jun 27 04:54:19 PM PDT 24
Peak memory 198788 kb
Host smart-05e2f0fa-c5aa-4553-936b-ce4cc899b331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322701430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.322701430
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.3947577540
Short name T135
Test name
Test status
Simulation time 148178947127 ps
CPU time 229.94 seconds
Started Jun 27 04:54:29 PM PDT 24
Finished Jun 27 04:58:20 PM PDT 24
Peak memory 199876 kb
Host smart-f567565f-f1a6-49eb-b04e-6c81e5272009
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947577540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3947577540
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.1218540436
Short name T36
Test name
Test status
Simulation time 382038136383 ps
CPU time 1134.72 seconds
Started Jun 27 04:54:29 PM PDT 24
Finished Jun 27 05:13:27 PM PDT 24
Peak memory 216448 kb
Host smart-140c038b-567a-4532-bc06-bc632b6211ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218540436 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.1218540436
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.120547810
Short name T999
Test name
Test status
Simulation time 2298820519 ps
CPU time 2.05 seconds
Started Jun 27 04:54:31 PM PDT 24
Finished Jun 27 04:54:36 PM PDT 24
Peak memory 198480 kb
Host smart-10b49d86-9db3-4892-878b-0664b8fc08da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120547810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.120547810
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.3937114075
Short name T442
Test name
Test status
Simulation time 57555950040 ps
CPU time 43.92 seconds
Started Jun 27 04:54:12 PM PDT 24
Finished Jun 27 04:54:59 PM PDT 24
Peak memory 199996 kb
Host smart-4cdf5282-cf29-476f-a39a-28473634177a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937114075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3937114075
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.2963265456
Short name T191
Test name
Test status
Simulation time 7260536520 ps
CPU time 11.23 seconds
Started Jun 27 04:57:08 PM PDT 24
Finished Jun 27 04:57:20 PM PDT 24
Peak memory 199776 kb
Host smart-75a7882c-90ed-4a65-a896-7d2f727b63c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963265456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.2963265456
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.2359860392
Short name T299
Test name
Test status
Simulation time 100907111437 ps
CPU time 228.72 seconds
Started Jun 27 04:57:08 PM PDT 24
Finished Jun 27 05:00:57 PM PDT 24
Peak memory 199892 kb
Host smart-47f9c4e2-4c16-4657-aae8-584464636fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359860392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.2359860392
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.3847536527
Short name T115
Test name
Test status
Simulation time 92744874980 ps
CPU time 132.65 seconds
Started Jun 27 04:57:05 PM PDT 24
Finished Jun 27 04:59:19 PM PDT 24
Peak memory 199888 kb
Host smart-08d49c4d-d533-4305-96fb-c9347eeb5557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847536527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.3847536527
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.3743851550
Short name T148
Test name
Test status
Simulation time 102665914078 ps
CPU time 85.83 seconds
Started Jun 27 04:57:07 PM PDT 24
Finished Jun 27 04:58:34 PM PDT 24
Peak memory 199844 kb
Host smart-b224a0b8-be81-4f3f-93ab-d49623e44b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743851550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3743851550
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.1302913605
Short name T188
Test name
Test status
Simulation time 8031351722 ps
CPU time 11.84 seconds
Started Jun 27 04:57:06 PM PDT 24
Finished Jun 27 04:57:19 PM PDT 24
Peak memory 199916 kb
Host smart-0ff5ed6d-e595-478e-a607-86e204e4712a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302913605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1302913605
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.263725984
Short name T1014
Test name
Test status
Simulation time 13740349 ps
CPU time 0.56 seconds
Started Jun 27 04:54:28 PM PDT 24
Finished Jun 27 04:54:30 PM PDT 24
Peak memory 195504 kb
Host smart-02270fb0-cd4f-47c5-be7e-8af4333d4110
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263725984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.263725984
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.1252173369
Short name T457
Test name
Test status
Simulation time 133665086360 ps
CPU time 294.1 seconds
Started Jun 27 04:54:33 PM PDT 24
Finished Jun 27 04:59:30 PM PDT 24
Peak memory 199952 kb
Host smart-4ec65be8-f7a7-4bad-85a3-ace12766752f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252173369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.1252173369
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.4224198330
Short name T259
Test name
Test status
Simulation time 19468948908 ps
CPU time 32.6 seconds
Started Jun 27 04:54:34 PM PDT 24
Finished Jun 27 04:55:11 PM PDT 24
Peak memory 199936 kb
Host smart-6e043179-1f85-4123-8344-1b76c0556ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224198330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.4224198330
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.4199316230
Short name T858
Test name
Test status
Simulation time 73893005965 ps
CPU time 17.07 seconds
Started Jun 27 04:54:33 PM PDT 24
Finished Jun 27 04:54:53 PM PDT 24
Peak memory 199828 kb
Host smart-bf839f24-0a6a-48a3-8e3b-53c3a940d22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199316230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.4199316230
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.3498383903
Short name T679
Test name
Test status
Simulation time 140642027421 ps
CPU time 216.98 seconds
Started Jun 27 04:54:30 PM PDT 24
Finished Jun 27 04:58:09 PM PDT 24
Peak memory 197728 kb
Host smart-f1a144f7-fa7d-4b74-9a1d-4451fdb607f3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498383903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.3498383903
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1221285634
Short name T700
Test name
Test status
Simulation time 31367021041 ps
CPU time 227.22 seconds
Started Jun 27 04:54:27 PM PDT 24
Finished Jun 27 04:58:16 PM PDT 24
Peak memory 199916 kb
Host smart-89907ef8-e52a-4684-a4df-df11f5c66bfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1221285634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1221285634
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.115711592
Short name T23
Test name
Test status
Simulation time 5408726712 ps
CPU time 10.63 seconds
Started Jun 27 04:54:26 PM PDT 24
Finished Jun 27 04:54:38 PM PDT 24
Peak memory 199640 kb
Host smart-67b68de8-8b08-48de-8ac7-c40643d77087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115711592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.115711592
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_perf.2841677244
Short name T603
Test name
Test status
Simulation time 14886307833 ps
CPU time 191.72 seconds
Started Jun 27 04:54:35 PM PDT 24
Finished Jun 27 04:57:51 PM PDT 24
Peak memory 199808 kb
Host smart-b10cca35-98cc-441b-a188-63cfdfb9a2fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2841677244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2841677244
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.1359380264
Short name T372
Test name
Test status
Simulation time 5682446938 ps
CPU time 52.06 seconds
Started Jun 27 04:54:29 PM PDT 24
Finished Jun 27 04:55:22 PM PDT 24
Peak memory 199344 kb
Host smart-720637e5-ddce-4867-bcc7-2f2151343340
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1359380264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1359380264
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.2682165032
Short name T390
Test name
Test status
Simulation time 88276131708 ps
CPU time 131.02 seconds
Started Jun 27 04:54:34 PM PDT 24
Finished Jun 27 04:56:49 PM PDT 24
Peak memory 199944 kb
Host smart-4ad23515-5382-42aa-a636-5daab4598421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682165032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2682165032
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1869977815
Short name T786
Test name
Test status
Simulation time 2062563303 ps
CPU time 2.16 seconds
Started Jun 27 04:54:33 PM PDT 24
Finished Jun 27 04:54:39 PM PDT 24
Peak memory 195432 kb
Host smart-94715798-637b-4345-8055-b2cc478da7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869977815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1869977815
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.2660291866
Short name T854
Test name
Test status
Simulation time 846866536 ps
CPU time 3.41 seconds
Started Jun 27 04:54:31 PM PDT 24
Finished Jun 27 04:54:37 PM PDT 24
Peak memory 199660 kb
Host smart-441c6728-3c28-425c-b857-3edb27bfba8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660291866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2660291866
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3020497176
Short name T671
Test name
Test status
Simulation time 1690863487 ps
CPU time 1.69 seconds
Started Jun 27 04:54:41 PM PDT 24
Finished Jun 27 04:54:47 PM PDT 24
Peak memory 198000 kb
Host smart-ec5795f8-9a45-4d93-9988-449d2bac813e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020497176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3020497176
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.3303351067
Short name T540
Test name
Test status
Simulation time 58640915500 ps
CPU time 58.37 seconds
Started Jun 27 04:54:30 PM PDT 24
Finished Jun 27 04:55:31 PM PDT 24
Peak memory 199936 kb
Host smart-8f0452cd-3fff-43cb-acac-6528a2cae109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303351067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.3303351067
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.1777623405
Short name T149
Test name
Test status
Simulation time 84059342510 ps
CPU time 31.86 seconds
Started Jun 27 04:57:09 PM PDT 24
Finished Jun 27 04:57:41 PM PDT 24
Peak memory 199988 kb
Host smart-8a52a7f2-e5dd-42e1-9c44-bbf172b2eadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777623405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1777623405
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.1063532786
Short name T897
Test name
Test status
Simulation time 67182678019 ps
CPU time 30.49 seconds
Started Jun 27 04:57:15 PM PDT 24
Finished Jun 27 04:57:48 PM PDT 24
Peak memory 199856 kb
Host smart-99bdb2d1-005f-4e6f-be0b-e7325907c20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063532786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.1063532786
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.3433853708
Short name T613
Test name
Test status
Simulation time 53448108680 ps
CPU time 19.18 seconds
Started Jun 27 04:57:15 PM PDT 24
Finished Jun 27 04:57:37 PM PDT 24
Peak memory 199988 kb
Host smart-65ce17cd-72d2-4155-81da-28b274e8d54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433853708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3433853708
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3380562418
Short name T566
Test name
Test status
Simulation time 82630820755 ps
CPU time 29.35 seconds
Started Jun 27 04:57:14 PM PDT 24
Finished Jun 27 04:57:46 PM PDT 24
Peak memory 199964 kb
Host smart-ea4c4ffe-6212-4916-b63b-3db81886a32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380562418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3380562418
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.676867109
Short name T1062
Test name
Test status
Simulation time 88521074671 ps
CPU time 141.7 seconds
Started Jun 27 04:57:13 PM PDT 24
Finished Jun 27 04:59:38 PM PDT 24
Peak memory 199912 kb
Host smart-53313634-8222-4773-a55c-3cf45110ab73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676867109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.676867109
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.3936576929
Short name T821
Test name
Test status
Simulation time 9147224924 ps
CPU time 14.97 seconds
Started Jun 27 04:57:13 PM PDT 24
Finished Jun 27 04:57:31 PM PDT 24
Peak memory 199892 kb
Host smart-d6fc56cd-0f9c-4902-8f4f-03b4acee796b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936576929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.3936576929
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.3431446112
Short name T328
Test name
Test status
Simulation time 34106238480 ps
CPU time 48.65 seconds
Started Jun 27 04:57:13 PM PDT 24
Finished Jun 27 04:58:05 PM PDT 24
Peak memory 199832 kb
Host smart-b9607a4c-c806-4104-8806-7aff9cb4a81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431446112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.3431446112
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.3781637042
Short name T515
Test name
Test status
Simulation time 102795324284 ps
CPU time 88.26 seconds
Started Jun 27 04:57:14 PM PDT 24
Finished Jun 27 04:58:45 PM PDT 24
Peak memory 199784 kb
Host smart-ff052763-70c2-48fc-80f6-c20a6e1b9706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781637042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3781637042
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.3185318564
Short name T1060
Test name
Test status
Simulation time 11548288 ps
CPU time 0.56 seconds
Started Jun 27 04:54:38 PM PDT 24
Finished Jun 27 04:54:42 PM PDT 24
Peak memory 194124 kb
Host smart-0d48120c-8da2-48c6-9ca6-b0b26794f723
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185318564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.3185318564
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.4281268108
Short name T1027
Test name
Test status
Simulation time 83825018084 ps
CPU time 31.51 seconds
Started Jun 27 04:54:33 PM PDT 24
Finished Jun 27 04:55:08 PM PDT 24
Peak memory 199892 kb
Host smart-451c2f82-22b1-4714-a01a-97159b241884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281268108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.4281268108
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.3496356467
Short name T782
Test name
Test status
Simulation time 152985882626 ps
CPU time 62.93 seconds
Started Jun 27 04:54:31 PM PDT 24
Finished Jun 27 04:55:37 PM PDT 24
Peak memory 199892 kb
Host smart-2809c02b-fc12-4bf1-be45-c059ad61b57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496356467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.3496356467
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.529208431
Short name T167
Test name
Test status
Simulation time 159941232018 ps
CPU time 91.99 seconds
Started Jun 27 04:54:26 PM PDT 24
Finished Jun 27 04:56:00 PM PDT 24
Peak memory 199964 kb
Host smart-1a2d9398-ebb8-4bbc-b148-2d0ab1e7ecf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529208431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.529208431
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.1018795964
Short name T981
Test name
Test status
Simulation time 53105616570 ps
CPU time 14 seconds
Started Jun 27 04:54:31 PM PDT 24
Finished Jun 27 04:54:47 PM PDT 24
Peak memory 199840 kb
Host smart-61ca6b1a-1299-49ab-801e-470684b957db
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018795964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1018795964
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.4271600744
Short name T252
Test name
Test status
Simulation time 129806464526 ps
CPU time 165.96 seconds
Started Jun 27 04:54:33 PM PDT 24
Finished Jun 27 04:57:23 PM PDT 24
Peak memory 199856 kb
Host smart-ca4c251b-96ae-4a82-adc5-a8c132e032b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4271600744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.4271600744
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.3176846300
Short name T652
Test name
Test status
Simulation time 2310484636 ps
CPU time 1.67 seconds
Started Jun 27 04:54:27 PM PDT 24
Finished Jun 27 04:54:30 PM PDT 24
Peak memory 196340 kb
Host smart-8e2c6414-2a6a-4fe6-8633-535a54067805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176846300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3176846300
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.4200410901
Short name T43
Test name
Test status
Simulation time 1196767634 ps
CPU time 1.07 seconds
Started Jun 27 04:54:26 PM PDT 24
Finished Jun 27 04:54:27 PM PDT 24
Peak memory 195656 kb
Host smart-46e7f4c5-f0b6-4403-8bfe-d946d5e23bbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4200410901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.4200410901
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.228020075
Short name T425
Test name
Test status
Simulation time 71450506075 ps
CPU time 80.32 seconds
Started Jun 27 04:54:29 PM PDT 24
Finished Jun 27 04:55:52 PM PDT 24
Peak memory 200184 kb
Host smart-8f602cba-5ee0-4519-a03f-7a859d9e5297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228020075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.228020075
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.3665877955
Short name T962
Test name
Test status
Simulation time 27468737490 ps
CPU time 11.45 seconds
Started Jun 27 04:54:33 PM PDT 24
Finished Jun 27 04:54:47 PM PDT 24
Peak memory 195692 kb
Host smart-661d2b85-a122-4b99-bcd8-bf2dc38e4b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665877955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3665877955
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.3833137727
Short name T968
Test name
Test status
Simulation time 5506139395 ps
CPU time 12.77 seconds
Started Jun 27 04:54:29 PM PDT 24
Finished Jun 27 04:54:44 PM PDT 24
Peak memory 199456 kb
Host smart-359ac54e-b3ec-463c-a35a-25214fb485f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833137727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3833137727
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.2448661160
Short name T91
Test name
Test status
Simulation time 27576303295 ps
CPU time 287.64 seconds
Started Jun 27 04:54:37 PM PDT 24
Finished Jun 27 04:59:29 PM PDT 24
Peak memory 216364 kb
Host smart-2059e39b-8032-454a-a43b-5fa46fd4bbb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448661160 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.2448661160
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.509129826
Short name T614
Test name
Test status
Simulation time 1590822651 ps
CPU time 1.68 seconds
Started Jun 27 04:54:29 PM PDT 24
Finished Jun 27 04:54:33 PM PDT 24
Peak memory 198312 kb
Host smart-3e715d57-497b-4a33-92b9-be63dfa328e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509129826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.509129826
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.1126792997
Short name T7
Test name
Test status
Simulation time 50611092040 ps
CPU time 83.15 seconds
Started Jun 27 04:54:36 PM PDT 24
Finished Jun 27 04:56:03 PM PDT 24
Peak memory 199976 kb
Host smart-c22b3986-d13f-4683-b0ef-8a1e72cdf9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126792997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.1126792997
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2094731961
Short name T332
Test name
Test status
Simulation time 137389638440 ps
CPU time 81.66 seconds
Started Jun 27 04:57:12 PM PDT 24
Finished Jun 27 04:58:36 PM PDT 24
Peak memory 199860 kb
Host smart-14dc10c9-8ef8-409e-87c0-c969ac3a02ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094731961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2094731961
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.230956054
Short name T174
Test name
Test status
Simulation time 43070214223 ps
CPU time 58.72 seconds
Started Jun 27 04:57:14 PM PDT 24
Finished Jun 27 04:58:16 PM PDT 24
Peak memory 199988 kb
Host smart-fab7396b-6efc-4938-ad2e-c0fbc20b4eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230956054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.230956054
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.2210685453
Short name T168
Test name
Test status
Simulation time 25750291776 ps
CPU time 28.32 seconds
Started Jun 27 04:57:10 PM PDT 24
Finished Jun 27 04:57:40 PM PDT 24
Peak memory 199856 kb
Host smart-d7f02863-1911-42cc-bb17-c8202d25bd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210685453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2210685453
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.1572815866
Short name T1017
Test name
Test status
Simulation time 160489182149 ps
CPU time 24.01 seconds
Started Jun 27 04:57:12 PM PDT 24
Finished Jun 27 04:57:38 PM PDT 24
Peak memory 199964 kb
Host smart-595c2112-4f07-4ce3-93b1-df65412aa585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572815866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.1572815866
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.2879005840
Short name T913
Test name
Test status
Simulation time 127382732379 ps
CPU time 22.7 seconds
Started Jun 27 04:57:11 PM PDT 24
Finished Jun 27 04:57:35 PM PDT 24
Peak memory 199964 kb
Host smart-44f00da8-2139-47de-9b3a-401da618056f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879005840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.2879005840
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.1202547081
Short name T207
Test name
Test status
Simulation time 111372458611 ps
CPU time 80.46 seconds
Started Jun 27 04:57:09 PM PDT 24
Finished Jun 27 04:58:31 PM PDT 24
Peak memory 199832 kb
Host smart-b581090c-9e9e-4282-9148-4543c6569923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202547081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1202547081
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.899008385
Short name T635
Test name
Test status
Simulation time 131515094052 ps
CPU time 110.35 seconds
Started Jun 27 04:57:13 PM PDT 24
Finished Jun 27 04:59:07 PM PDT 24
Peak memory 199956 kb
Host smart-9e1a6d07-e811-4863-853a-9b802180e30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899008385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.899008385
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2159708307
Short name T850
Test name
Test status
Simulation time 36883860495 ps
CPU time 27.23 seconds
Started Jun 27 04:57:10 PM PDT 24
Finished Jun 27 04:57:39 PM PDT 24
Peak memory 199928 kb
Host smart-17a3fb6c-4c1d-48cc-b3ac-91853f7ce51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159708307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2159708307
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.2295078169
Short name T573
Test name
Test status
Simulation time 12828654 ps
CPU time 0.56 seconds
Started Jun 27 04:54:31 PM PDT 24
Finished Jun 27 04:54:35 PM PDT 24
Peak memory 195204 kb
Host smart-21ed3a82-e4d2-4255-86fd-f2b5e3639cfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295078169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.2295078169
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.2801893199
Short name T163
Test name
Test status
Simulation time 89360868785 ps
CPU time 31.26 seconds
Started Jun 27 04:54:29 PM PDT 24
Finished Jun 27 04:55:03 PM PDT 24
Peak memory 199828 kb
Host smart-45677890-f324-4475-8a04-8c4900bc0463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801893199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2801893199
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.1711147703
Short name T160
Test name
Test status
Simulation time 47822938148 ps
CPU time 28.27 seconds
Started Jun 27 04:54:30 PM PDT 24
Finished Jun 27 04:55:01 PM PDT 24
Peak memory 199820 kb
Host smart-9136d0e6-7c5c-4507-b57d-f100afdcfc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711147703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1711147703
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.311323748
Short name T887
Test name
Test status
Simulation time 65716683601 ps
CPU time 97.35 seconds
Started Jun 27 04:54:29 PM PDT 24
Finished Jun 27 04:56:09 PM PDT 24
Peak memory 199992 kb
Host smart-962cf1b7-d26b-4697-98a1-b26823f02803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311323748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.311323748
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.3660588359
Short name T907
Test name
Test status
Simulation time 14145911960 ps
CPU time 22.39 seconds
Started Jun 27 04:54:27 PM PDT 24
Finished Jun 27 04:54:51 PM PDT 24
Peak memory 196384 kb
Host smart-fbdd94cd-60f9-4287-b4eb-d7f095400a65
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660588359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3660588359
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.3888535120
Short name T847
Test name
Test status
Simulation time 345376480394 ps
CPU time 188.77 seconds
Started Jun 27 04:54:31 PM PDT 24
Finished Jun 27 04:57:43 PM PDT 24
Peak memory 199880 kb
Host smart-0b67981c-c89a-4f80-90bd-37adf9f617b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3888535120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.3888535120
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.2545114830
Short name T1021
Test name
Test status
Simulation time 3258075846 ps
CPU time 3.86 seconds
Started Jun 27 04:54:33 PM PDT 24
Finished Jun 27 04:54:40 PM PDT 24
Peak memory 199688 kb
Host smart-cb6db8b0-b4ea-46ee-aaaa-433a86c4b486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545114830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2545114830
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_perf.2799290748
Short name T651
Test name
Test status
Simulation time 22700234594 ps
CPU time 301.71 seconds
Started Jun 27 04:54:34 PM PDT 24
Finished Jun 27 04:59:40 PM PDT 24
Peak memory 199924 kb
Host smart-84266997-8600-484a-9df7-24cfd218dc7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2799290748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.2799290748
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.3826127882
Short name T394
Test name
Test status
Simulation time 6595910979 ps
CPU time 10.18 seconds
Started Jun 27 04:54:30 PM PDT 24
Finished Jun 27 04:54:43 PM PDT 24
Peak memory 198760 kb
Host smart-0a2dc288-9051-49a0-83a6-4ddb8926db91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3826127882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.3826127882
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.2141840204
Short name T250
Test name
Test status
Simulation time 92859329446 ps
CPU time 69.09 seconds
Started Jun 27 04:54:27 PM PDT 24
Finished Jun 27 04:55:37 PM PDT 24
Peak memory 199904 kb
Host smart-fc02b3b0-2941-4b8f-9b13-0cebf314a41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141840204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2141840204
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.3320355978
Short name T822
Test name
Test status
Simulation time 4269317968 ps
CPU time 6.72 seconds
Started Jun 27 04:54:32 PM PDT 24
Finished Jun 27 04:54:42 PM PDT 24
Peak memory 196292 kb
Host smart-28be2263-c3a0-4386-80a4-b60ec0b6d2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320355978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3320355978
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.1760862514
Short name T834
Test name
Test status
Simulation time 497469515 ps
CPU time 2.5 seconds
Started Jun 27 04:54:39 PM PDT 24
Finished Jun 27 04:54:45 PM PDT 24
Peak memory 198804 kb
Host smart-c6d8543e-8e98-4640-b29f-c5c129236fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760862514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1760862514
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1380179761
Short name T561
Test name
Test status
Simulation time 12065061661 ps
CPU time 29.94 seconds
Started Jun 27 04:54:31 PM PDT 24
Finished Jun 27 04:55:03 PM PDT 24
Peak memory 199724 kb
Host smart-d7eccd3a-5fbd-4c99-aa5a-aa44004506c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380179761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1380179761
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.537421404
Short name T313
Test name
Test status
Simulation time 69889760465 ps
CPU time 105.51 seconds
Started Jun 27 04:54:32 PM PDT 24
Finished Jun 27 04:56:21 PM PDT 24
Peak memory 199836 kb
Host smart-d8e07664-aee4-4183-ab13-085d4f378b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537421404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.537421404
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1220128670
Short name T1002
Test name
Test status
Simulation time 21405146897 ps
CPU time 30.51 seconds
Started Jun 27 04:57:11 PM PDT 24
Finished Jun 27 04:57:43 PM PDT 24
Peak memory 199936 kb
Host smart-108b16c5-789f-4f6b-96f4-7b85b0824814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220128670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1220128670
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.265886340
Short name T826
Test name
Test status
Simulation time 160881925721 ps
CPU time 110.66 seconds
Started Jun 27 04:57:14 PM PDT 24
Finished Jun 27 04:59:07 PM PDT 24
Peak memory 199892 kb
Host smart-f964a123-b191-471f-b9c4-8e10996d92ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265886340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.265886340
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.2586557520
Short name T226
Test name
Test status
Simulation time 25643635389 ps
CPU time 22.86 seconds
Started Jun 27 04:57:11 PM PDT 24
Finished Jun 27 04:57:35 PM PDT 24
Peak memory 199892 kb
Host smart-731b8baf-8815-45d0-95fb-3db3a94528e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586557520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2586557520
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.523302168
Short name T1031
Test name
Test status
Simulation time 170529095820 ps
CPU time 44.45 seconds
Started Jun 27 04:57:13 PM PDT 24
Finished Jun 27 04:58:00 PM PDT 24
Peak memory 199904 kb
Host smart-c136fc96-a798-4253-88c8-216e3f7e15c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523302168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.523302168
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.3921279300
Short name T722
Test name
Test status
Simulation time 34229251650 ps
CPU time 40.54 seconds
Started Jun 27 04:57:10 PM PDT 24
Finished Jun 27 04:57:52 PM PDT 24
Peak memory 199896 kb
Host smart-9cded756-67b6-4e6a-93a7-05e49d910642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921279300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3921279300
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.4157174012
Short name T531
Test name
Test status
Simulation time 70436644378 ps
CPU time 56.18 seconds
Started Jun 27 04:57:12 PM PDT 24
Finished Jun 27 04:58:11 PM PDT 24
Peak memory 199864 kb
Host smart-46ae8b03-57b0-40d2-92f8-3f4b7b08a2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157174012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.4157174012
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.3245955939
Short name T926
Test name
Test status
Simulation time 100673084441 ps
CPU time 15.7 seconds
Started Jun 27 04:57:16 PM PDT 24
Finished Jun 27 04:57:34 PM PDT 24
Peak memory 199924 kb
Host smart-8e8c435c-76e3-48e9-a7c3-71bd35b1e6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245955939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3245955939
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3595723145
Short name T577
Test name
Test status
Simulation time 34225250155 ps
CPU time 14.73 seconds
Started Jun 27 04:57:13 PM PDT 24
Finished Jun 27 04:57:31 PM PDT 24
Peak memory 199924 kb
Host smart-e3418e32-a62f-4ed2-8904-0ea111012573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595723145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3595723145
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.5706926
Short name T157
Test name
Test status
Simulation time 121555938937 ps
CPU time 145.6 seconds
Started Jun 27 04:57:17 PM PDT 24
Finished Jun 27 04:59:44 PM PDT 24
Peak memory 199996 kb
Host smart-af99a9d4-9cf6-43d6-ae39-5ae57e53a3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5706926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.5706926
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.4284624827
Short name T241
Test name
Test status
Simulation time 13084797392 ps
CPU time 20.6 seconds
Started Jun 27 04:57:13 PM PDT 24
Finished Jun 27 04:57:36 PM PDT 24
Peak memory 198676 kb
Host smart-9bae9628-dfd8-42b4-8e80-876757729fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284624827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.4284624827
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.827742370
Short name T938
Test name
Test status
Simulation time 10929895 ps
CPU time 0.55 seconds
Started Jun 27 04:54:34 PM PDT 24
Finished Jun 27 04:54:38 PM PDT 24
Peak memory 194260 kb
Host smart-a9365f0c-e069-455f-83ee-834e71972479
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827742370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.827742370
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.3350840424
Short name T909
Test name
Test status
Simulation time 15308940590 ps
CPU time 12.93 seconds
Started Jun 27 04:54:29 PM PDT 24
Finished Jun 27 04:54:44 PM PDT 24
Peak memory 199988 kb
Host smart-27094e53-0927-4fae-8ee2-e8cdaa75c25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350840424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.3350840424
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1327146827
Short name T740
Test name
Test status
Simulation time 132121066242 ps
CPU time 96.35 seconds
Started Jun 27 04:54:38 PM PDT 24
Finished Jun 27 04:56:19 PM PDT 24
Peak memory 199808 kb
Host smart-32486010-5d3a-4e47-9c7a-596f175721a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327146827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1327146827
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2431486461
Short name T416
Test name
Test status
Simulation time 24928423823 ps
CPU time 13.24 seconds
Started Jun 27 04:54:31 PM PDT 24
Finished Jun 27 04:54:47 PM PDT 24
Peak memory 199908 kb
Host smart-66b06730-0002-4cdf-913c-8b7040967984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431486461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2431486461
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.3542152573
Short name T912
Test name
Test status
Simulation time 48618668471 ps
CPU time 72.37 seconds
Started Jun 27 04:54:32 PM PDT 24
Finished Jun 27 04:55:47 PM PDT 24
Peak memory 199920 kb
Host smart-771a22e6-346a-482e-8b3c-bbaa80aad401
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542152573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3542152573
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.2565783650
Short name T525
Test name
Test status
Simulation time 86425060381 ps
CPU time 196.13 seconds
Started Jun 27 04:54:32 PM PDT 24
Finished Jun 27 04:57:52 PM PDT 24
Peak memory 199852 kb
Host smart-2cacdee7-09a1-47e2-ad6f-e19c72075733
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2565783650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2565783650
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.3051289410
Short name T812
Test name
Test status
Simulation time 1082109403 ps
CPU time 3.21 seconds
Started Jun 27 04:54:36 PM PDT 24
Finished Jun 27 04:54:43 PM PDT 24
Peak memory 198140 kb
Host smart-22af380a-6d1c-4c1c-940e-6e2271715bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051289410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3051289410
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_perf.3022982735
Short name T1007
Test name
Test status
Simulation time 20961009303 ps
CPU time 194.07 seconds
Started Jun 27 04:54:41 PM PDT 24
Finished Jun 27 04:57:59 PM PDT 24
Peak memory 199948 kb
Host smart-8011e7da-bc5c-4797-b787-29810c07ae6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3022982735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3022982735
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.192598555
Short name T899
Test name
Test status
Simulation time 6854926597 ps
CPU time 61.55 seconds
Started Jun 27 04:54:32 PM PDT 24
Finished Jun 27 04:55:37 PM PDT 24
Peak memory 198192 kb
Host smart-f90ed118-fac8-4b24-8a66-b5a2b87a78e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=192598555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.192598555
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.1615578078
Short name T777
Test name
Test status
Simulation time 97421954116 ps
CPU time 34.2 seconds
Started Jun 27 04:54:33 PM PDT 24
Finished Jun 27 04:55:10 PM PDT 24
Peak memory 199704 kb
Host smart-e9def275-c2d1-4814-9f32-050fcee0f5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615578078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1615578078
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.4068581311
Short name T392
Test name
Test status
Simulation time 42653636833 ps
CPU time 59.92 seconds
Started Jun 27 04:54:38 PM PDT 24
Finished Jun 27 04:55:41 PM PDT 24
Peak memory 195864 kb
Host smart-4fa7cd2a-9f80-4ac6-8600-77ff31d5f24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068581311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.4068581311
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.468329625
Short name T524
Test name
Test status
Simulation time 511002506 ps
CPU time 1.76 seconds
Started Jun 27 04:54:32 PM PDT 24
Finished Jun 27 04:54:37 PM PDT 24
Peak memory 199820 kb
Host smart-74893145-2100-4bb5-8596-59daa25e1ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468329625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.468329625
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.2152238229
Short name T192
Test name
Test status
Simulation time 173972610091 ps
CPU time 407.25 seconds
Started Jun 27 04:54:40 PM PDT 24
Finished Jun 27 05:01:31 PM PDT 24
Peak memory 199864 kb
Host smart-be3f9e3e-b0e7-4a73-8054-bd8ff6bd86d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152238229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2152238229
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.107862801
Short name T773
Test name
Test status
Simulation time 775841500 ps
CPU time 2.71 seconds
Started Jun 27 04:54:36 PM PDT 24
Finished Jun 27 04:54:42 PM PDT 24
Peak memory 198716 kb
Host smart-803b2a09-8877-43f9-a4a5-89b876d42e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107862801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.107862801
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.1483668117
Short name T562
Test name
Test status
Simulation time 100356619869 ps
CPU time 45.18 seconds
Started Jun 27 04:54:33 PM PDT 24
Finished Jun 27 04:55:22 PM PDT 24
Peak memory 199936 kb
Host smart-8c092ec7-39b5-409e-8e3a-b2b7ef17faac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483668117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.1483668117
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.3733399778
Short name T221
Test name
Test status
Simulation time 23456920027 ps
CPU time 57.09 seconds
Started Jun 27 04:57:12 PM PDT 24
Finished Jun 27 04:58:12 PM PDT 24
Peak memory 199920 kb
Host smart-e83ca499-966c-47b0-8c59-cd8c8eeb8894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733399778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3733399778
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.248105472
Short name T914
Test name
Test status
Simulation time 110994897737 ps
CPU time 185.45 seconds
Started Jun 27 04:57:14 PM PDT 24
Finished Jun 27 05:00:22 PM PDT 24
Peak memory 200200 kb
Host smart-4fd9293a-889d-4ad0-b91b-4b867546527b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248105472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.248105472
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.381844799
Short name T209
Test name
Test status
Simulation time 42793735344 ps
CPU time 67.71 seconds
Started Jun 27 04:57:16 PM PDT 24
Finished Jun 27 04:58:26 PM PDT 24
Peak memory 199992 kb
Host smart-03527525-a4f2-4918-b8c2-5bdd223e1d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381844799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.381844799
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.1588295268
Short name T210
Test name
Test status
Simulation time 50917941635 ps
CPU time 89.49 seconds
Started Jun 27 04:57:14 PM PDT 24
Finished Jun 27 04:58:47 PM PDT 24
Peak memory 199928 kb
Host smart-6d3f653e-2649-4bbb-a000-d9830a3b468f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588295268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1588295268
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.2754453401
Short name T946
Test name
Test status
Simulation time 29215782370 ps
CPU time 49.9 seconds
Started Jun 27 04:57:14 PM PDT 24
Finished Jun 27 04:58:07 PM PDT 24
Peak memory 199828 kb
Host smart-215fa60e-1cc5-4aec-9d0f-fd36c04b3b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754453401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.2754453401
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.997109874
Short name T291
Test name
Test status
Simulation time 69948245409 ps
CPU time 77.35 seconds
Started Jun 27 04:57:12 PM PDT 24
Finished Jun 27 04:58:32 PM PDT 24
Peak memory 199860 kb
Host smart-a3fe8793-8417-4b86-8049-c655215b2d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997109874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.997109874
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.809654779
Short name T277
Test name
Test status
Simulation time 166037514549 ps
CPU time 108.96 seconds
Started Jun 27 04:57:16 PM PDT 24
Finished Jun 27 04:59:07 PM PDT 24
Peak memory 199948 kb
Host smart-1479ebf0-2db8-42e5-a98b-31155ae6010e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809654779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.809654779
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.1791178125
Short name T691
Test name
Test status
Simulation time 55833559786 ps
CPU time 22.67 seconds
Started Jun 27 04:57:16 PM PDT 24
Finished Jun 27 04:57:41 PM PDT 24
Peak memory 199988 kb
Host smart-368fa6d7-0797-41db-8e28-6015403c6b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791178125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1791178125
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.3874018598
Short name T705
Test name
Test status
Simulation time 19067421751 ps
CPU time 9.55 seconds
Started Jun 27 04:57:15 PM PDT 24
Finished Jun 27 04:57:27 PM PDT 24
Peak memory 199828 kb
Host smart-e9b4269c-7e10-459e-9a1c-a062c0dbbcfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874018598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3874018598
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.1989432584
Short name T378
Test name
Test status
Simulation time 16334352 ps
CPU time 0.56 seconds
Started Jun 27 04:54:41 PM PDT 24
Finished Jun 27 04:54:46 PM PDT 24
Peak memory 195296 kb
Host smart-1059b0b9-cf38-490f-96c3-bfcb1c8e7c49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989432584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.1989432584
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.2771715734
Short name T456
Test name
Test status
Simulation time 53185188672 ps
CPU time 91 seconds
Started Jun 27 04:54:35 PM PDT 24
Finished Jun 27 04:56:10 PM PDT 24
Peak memory 199928 kb
Host smart-ae8b8cee-ff78-458a-b106-c460ea8997f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771715734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.2771715734
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2683786857
Short name T881
Test name
Test status
Simulation time 7919818150 ps
CPU time 17.16 seconds
Started Jun 27 04:54:41 PM PDT 24
Finished Jun 27 04:55:03 PM PDT 24
Peak memory 199864 kb
Host smart-d2abd56c-0f5b-4107-b997-23f815509aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683786857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2683786857
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.4091589977
Short name T905
Test name
Test status
Simulation time 167949661798 ps
CPU time 153.47 seconds
Started Jun 27 04:54:41 PM PDT 24
Finished Jun 27 04:57:19 PM PDT 24
Peak memory 199920 kb
Host smart-e30e9ac0-44b8-45cf-b5c1-d82cb3860c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091589977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.4091589977
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.370427837
Short name T846
Test name
Test status
Simulation time 42558911825 ps
CPU time 21.04 seconds
Started Jun 27 04:54:35 PM PDT 24
Finished Jun 27 04:55:00 PM PDT 24
Peak memory 199856 kb
Host smart-4aa8b35d-d0ba-42a2-892d-69547d677171
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370427837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.370427837
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.454666484
Short name T287
Test name
Test status
Simulation time 36765217793 ps
CPU time 259.41 seconds
Started Jun 27 04:54:35 PM PDT 24
Finished Jun 27 04:58:58 PM PDT 24
Peak memory 199908 kb
Host smart-8d713ed4-d367-4b81-b048-e1bf60953128
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=454666484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.454666484
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.1867889307
Short name T776
Test name
Test status
Simulation time 8415907263 ps
CPU time 3.48 seconds
Started Jun 27 04:54:34 PM PDT 24
Finished Jun 27 04:54:41 PM PDT 24
Peak memory 198912 kb
Host smart-ffb899ae-3a17-4cf2-a404-a57e76a56cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867889307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1867889307
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_perf.3988120346
Short name T438
Test name
Test status
Simulation time 3880666583 ps
CPU time 221.79 seconds
Started Jun 27 04:54:41 PM PDT 24
Finished Jun 27 04:58:28 PM PDT 24
Peak memory 199900 kb
Host smart-5f4869b0-a133-40a2-8ce3-c72db08acfc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3988120346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.3988120346
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.1855234932
Short name T807
Test name
Test status
Simulation time 2526685819 ps
CPU time 12.82 seconds
Started Jun 27 04:54:41 PM PDT 24
Finished Jun 27 04:54:59 PM PDT 24
Peak memory 199148 kb
Host smart-c48fc426-368b-4f00-8373-919fa5d4cb7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1855234932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1855234932
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.2180436554
Short name T258
Test name
Test status
Simulation time 13134911940 ps
CPU time 10.83 seconds
Started Jun 27 04:54:34 PM PDT 24
Finished Jun 27 04:54:48 PM PDT 24
Peak memory 199988 kb
Host smart-311b369d-44a4-4fca-96b0-b515f80195e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180436554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2180436554
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1586672517
Short name T710
Test name
Test status
Simulation time 6197234303 ps
CPU time 5.23 seconds
Started Jun 27 04:54:35 PM PDT 24
Finished Jun 27 04:54:43 PM PDT 24
Peak memory 196048 kb
Host smart-7c39aad6-8564-4787-a78f-eecddcd74c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586672517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1586672517
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.4176114249
Short name T297
Test name
Test status
Simulation time 5468518649 ps
CPU time 16.17 seconds
Started Jun 27 04:54:33 PM PDT 24
Finished Jun 27 04:54:53 PM PDT 24
Peak memory 199060 kb
Host smart-b22857cb-73ec-4c03-9233-e94c9f7034b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176114249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.4176114249
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.1140892994
Short name T804
Test name
Test status
Simulation time 2044536265 ps
CPU time 2.09 seconds
Started Jun 27 04:54:31 PM PDT 24
Finished Jun 27 04:54:36 PM PDT 24
Peak memory 198680 kb
Host smart-8f461541-52b3-4cc9-9cec-388390675844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140892994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1140892994
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.3652759150
Short name T1056
Test name
Test status
Simulation time 124682246273 ps
CPU time 18.08 seconds
Started Jun 27 04:54:35 PM PDT 24
Finished Jun 27 04:54:57 PM PDT 24
Peak memory 199960 kb
Host smart-5fe6d265-6377-4356-9d81-c7ecbc2a743f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652759150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3652759150
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.3960285636
Short name T461
Test name
Test status
Simulation time 248682048793 ps
CPU time 102.09 seconds
Started Jun 27 04:57:13 PM PDT 24
Finished Jun 27 04:58:58 PM PDT 24
Peak memory 199848 kb
Host smart-1574f8a1-889a-4fe7-9907-13a614c63cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960285636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3960285636
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2362528158
Short name T326
Test name
Test status
Simulation time 41521234075 ps
CPU time 140.39 seconds
Started Jun 27 04:57:12 PM PDT 24
Finished Jun 27 04:59:35 PM PDT 24
Peak memory 199944 kb
Host smart-cfbf2257-0eae-4133-80f8-30d41eb9398b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362528158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2362528158
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.1746288962
Short name T534
Test name
Test status
Simulation time 28131430754 ps
CPU time 41.25 seconds
Started Jun 27 04:57:13 PM PDT 24
Finished Jun 27 04:57:58 PM PDT 24
Peak memory 199880 kb
Host smart-a25638be-c3d7-4b06-a3e7-534c3baa8fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746288962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.1746288962
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.474744158
Short name T240
Test name
Test status
Simulation time 9490336705 ps
CPU time 16.56 seconds
Started Jun 27 04:57:26 PM PDT 24
Finished Jun 27 04:57:43 PM PDT 24
Peak memory 199984 kb
Host smart-3c0b16b6-df24-401b-8b42-6cbff9b6370a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474744158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.474744158
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.2743269014
Short name T279
Test name
Test status
Simulation time 33579056179 ps
CPU time 29.83 seconds
Started Jun 27 04:57:21 PM PDT 24
Finished Jun 27 04:57:52 PM PDT 24
Peak memory 199572 kb
Host smart-3f786796-df0a-420a-bd27-48844b3a1128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743269014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2743269014
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.3901118511
Short name T483
Test name
Test status
Simulation time 10251087620 ps
CPU time 18.58 seconds
Started Jun 27 04:57:22 PM PDT 24
Finished Jun 27 04:57:42 PM PDT 24
Peak memory 199940 kb
Host smart-36cf7418-ddce-45ce-a375-09404d1cb0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901118511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3901118511
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1980300881
Short name T1032
Test name
Test status
Simulation time 70203002519 ps
CPU time 113.91 seconds
Started Jun 27 04:57:25 PM PDT 24
Finished Jun 27 04:59:19 PM PDT 24
Peak memory 199948 kb
Host smart-682f0e03-beb9-44ee-9b02-730b7e7687c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980300881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1980300881
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.1997350043
Short name T997
Test name
Test status
Simulation time 344274509315 ps
CPU time 43.26 seconds
Started Jun 27 04:57:26 PM PDT 24
Finished Jun 27 04:58:11 PM PDT 24
Peak memory 199868 kb
Host smart-0a4c92f4-47ba-4d56-a318-3f87a13203ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997350043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1997350043
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.1877894248
Short name T703
Test name
Test status
Simulation time 59956635 ps
CPU time 0.59 seconds
Started Jun 27 04:54:31 PM PDT 24
Finished Jun 27 04:54:34 PM PDT 24
Peak memory 195228 kb
Host smart-b934fd79-9574-4381-8423-81dc8a691b17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877894248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1877894248
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.489332016
Short name T517
Test name
Test status
Simulation time 32952836134 ps
CPU time 48.22 seconds
Started Jun 27 04:54:42 PM PDT 24
Finished Jun 27 04:55:34 PM PDT 24
Peak memory 199948 kb
Host smart-bd4df636-38cd-4ecd-a7b7-a8ef075de496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489332016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.489332016
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.1623406752
Short name T411
Test name
Test status
Simulation time 119013586248 ps
CPU time 193.56 seconds
Started Jun 27 04:54:37 PM PDT 24
Finished Jun 27 04:57:54 PM PDT 24
Peak memory 199680 kb
Host smart-e17f14d1-e794-49e4-8ad0-fa6c5a94ff10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623406752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1623406752
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.3662404126
Short name T622
Test name
Test status
Simulation time 14057886260 ps
CPU time 16.24 seconds
Started Jun 27 04:54:39 PM PDT 24
Finished Jun 27 04:55:00 PM PDT 24
Peak memory 199584 kb
Host smart-66043709-3c8c-41dc-b071-8a7f98d0f2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662404126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.3662404126
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.1055213829
Short name T865
Test name
Test status
Simulation time 7532298821 ps
CPU time 6.22 seconds
Started Jun 27 04:54:33 PM PDT 24
Finished Jun 27 04:54:43 PM PDT 24
Peak memory 199812 kb
Host smart-b4d833d1-99a7-43bf-ba34-1e1ad2541486
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055213829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.1055213829
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.60802768
Short name T596
Test name
Test status
Simulation time 90872215093 ps
CPU time 589.42 seconds
Started Jun 27 04:54:31 PM PDT 24
Finished Jun 27 05:04:23 PM PDT 24
Peak memory 199948 kb
Host smart-41001821-d2f2-4202-8579-b6dfcdf3f987
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=60802768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.60802768
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.4226184582
Short name T861
Test name
Test status
Simulation time 2855615296 ps
CPU time 4.79 seconds
Started Jun 27 04:54:38 PM PDT 24
Finished Jun 27 04:54:46 PM PDT 24
Peak memory 198768 kb
Host smart-2b951018-2126-441b-8b7f-d6d13d5f49ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226184582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.4226184582
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_perf.3725223284
Short name T727
Test name
Test status
Simulation time 20046101659 ps
CPU time 1048.26 seconds
Started Jun 27 04:54:31 PM PDT 24
Finished Jun 27 05:12:02 PM PDT 24
Peak memory 199832 kb
Host smart-359998a4-dc28-4af4-9d22-87c3a786f72d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3725223284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.3725223284
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.2910344467
Short name T96
Test name
Test status
Simulation time 4199731527 ps
CPU time 7.69 seconds
Started Jun 27 04:54:34 PM PDT 24
Finished Jun 27 04:54:45 PM PDT 24
Peak memory 199152 kb
Host smart-f9e55d34-d451-404e-b8e7-58ee7c779db1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2910344467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2910344467
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.1897752469
Short name T678
Test name
Test status
Simulation time 31688892819 ps
CPU time 31.5 seconds
Started Jun 27 04:54:33 PM PDT 24
Finished Jun 27 04:55:07 PM PDT 24
Peak memory 199932 kb
Host smart-7b917407-9bfe-41c7-8d9e-73afeef9a869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897752469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1897752469
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.326553586
Short name T403
Test name
Test status
Simulation time 4977526827 ps
CPU time 4.79 seconds
Started Jun 27 04:54:41 PM PDT 24
Finished Jun 27 04:54:50 PM PDT 24
Peak memory 195912 kb
Host smart-7ccbbd3f-31ec-4fbf-9911-ead638deb9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326553586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.326553586
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.1503585226
Short name T468
Test name
Test status
Simulation time 915014856 ps
CPU time 1.55 seconds
Started Jun 27 04:54:41 PM PDT 24
Finished Jun 27 04:54:47 PM PDT 24
Peak memory 198688 kb
Host smart-5ca8987a-19c5-44e7-aa7f-bc2ff102caa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503585226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1503585226
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1825979019
Short name T373
Test name
Test status
Simulation time 7359236506 ps
CPU time 19.08 seconds
Started Jun 27 04:54:33 PM PDT 24
Finished Jun 27 04:54:56 PM PDT 24
Peak memory 199152 kb
Host smart-17269d89-afd0-4f45-99d8-f975ef08a5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825979019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1825979019
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.3726074956
Short name T713
Test name
Test status
Simulation time 125959179811 ps
CPU time 60.46 seconds
Started Jun 27 04:54:37 PM PDT 24
Finished Jun 27 04:55:41 PM PDT 24
Peak memory 199944 kb
Host smart-8201af6a-d14e-4c19-8fcc-7444ef88d217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726074956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3726074956
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.1898590099
Short name T737
Test name
Test status
Simulation time 266385884811 ps
CPU time 106 seconds
Started Jun 27 04:57:21 PM PDT 24
Finished Jun 27 04:59:08 PM PDT 24
Peak memory 199868 kb
Host smart-bc376d88-d2e0-49bd-92d4-aab5921e2754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898590099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1898590099
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.1339326263
Short name T993
Test name
Test status
Simulation time 42479457504 ps
CPU time 67.44 seconds
Started Jun 27 04:57:27 PM PDT 24
Finished Jun 27 04:58:36 PM PDT 24
Peak memory 199812 kb
Host smart-42229b89-d9f6-4c97-8ea6-32e431aef6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339326263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1339326263
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.3001857279
Short name T197
Test name
Test status
Simulation time 39555398385 ps
CPU time 16 seconds
Started Jun 27 04:57:21 PM PDT 24
Finished Jun 27 04:57:38 PM PDT 24
Peak memory 198648 kb
Host smart-5ce22b90-c98e-4d10-a9bb-055c82ab42d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001857279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3001857279
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.794606718
Short name T229
Test name
Test status
Simulation time 79509243239 ps
CPU time 18.63 seconds
Started Jun 27 04:57:22 PM PDT 24
Finished Jun 27 04:57:41 PM PDT 24
Peak memory 199856 kb
Host smart-40bf9d26-1196-44a6-9371-213b903416ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794606718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.794606718
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.1049503680
Short name T219
Test name
Test status
Simulation time 59953849057 ps
CPU time 6.82 seconds
Started Jun 27 04:57:26 PM PDT 24
Finished Jun 27 04:57:35 PM PDT 24
Peak memory 199500 kb
Host smart-8548f779-80b2-43e7-ae0a-e6705d1948ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049503680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1049503680
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.2073627982
Short name T888
Test name
Test status
Simulation time 99201557262 ps
CPU time 81.53 seconds
Started Jun 27 04:57:23 PM PDT 24
Finished Jun 27 04:58:46 PM PDT 24
Peak memory 199824 kb
Host smart-ec2447fb-3f4c-4133-9b68-ff276d603f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073627982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2073627982
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.3302497944
Short name T1009
Test name
Test status
Simulation time 76921509885 ps
CPU time 93.16 seconds
Started Jun 27 04:57:32 PM PDT 24
Finished Jun 27 04:59:08 PM PDT 24
Peak memory 199984 kb
Host smart-56895da0-b561-400a-8ba3-4d8bc59d66e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302497944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3302497944
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.4261683979
Short name T345
Test name
Test status
Simulation time 20320626 ps
CPU time 0.55 seconds
Started Jun 27 04:54:40 PM PDT 24
Finished Jun 27 04:54:45 PM PDT 24
Peak memory 195284 kb
Host smart-7cd231dc-2564-4c64-bb7b-72bb39bdb7c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261683979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.4261683979
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.488748267
Short name T293
Test name
Test status
Simulation time 255899310054 ps
CPU time 719.55 seconds
Started Jun 27 04:54:38 PM PDT 24
Finished Jun 27 05:06:42 PM PDT 24
Peak memory 199964 kb
Host smart-29f82971-f1ee-4552-a170-b33b9d2b0d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488748267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.488748267
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.3917308894
Short name T310
Test name
Test status
Simulation time 66889931614 ps
CPU time 47.2 seconds
Started Jun 27 04:54:33 PM PDT 24
Finished Jun 27 04:55:23 PM PDT 24
Peak memory 199748 kb
Host smart-6c7ab259-14d1-4f4a-b286-a6d9ca4ad6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917308894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3917308894
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.3623850628
Short name T720
Test name
Test status
Simulation time 85939215751 ps
CPU time 27.54 seconds
Started Jun 27 04:54:36 PM PDT 24
Finished Jun 27 04:55:08 PM PDT 24
Peak memory 199908 kb
Host smart-b3d13031-3a1d-4425-984a-54a319a74d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623850628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3623850628
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.3699988488
Short name T108
Test name
Test status
Simulation time 498687802458 ps
CPU time 151.73 seconds
Started Jun 27 04:54:36 PM PDT 24
Finished Jun 27 04:57:12 PM PDT 24
Peak memory 198260 kb
Host smart-96727996-3cb8-4420-ba78-0c7a173cd8a3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699988488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3699988488
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.1078001316
Short name T844
Test name
Test status
Simulation time 104681536792 ps
CPU time 176.43 seconds
Started Jun 27 04:54:41 PM PDT 24
Finished Jun 27 04:57:41 PM PDT 24
Peak memory 199896 kb
Host smart-5233a8eb-a03c-42e1-9b4f-2df3e211d0b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1078001316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.1078001316
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2456339876
Short name T558
Test name
Test status
Simulation time 9683352997 ps
CPU time 11.18 seconds
Started Jun 27 04:54:41 PM PDT 24
Finished Jun 27 04:54:57 PM PDT 24
Peak memory 199824 kb
Host smart-72086f75-9a96-4efe-a234-ca3f2f9d3ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456339876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2456339876
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_perf.561698881
Short name T739
Test name
Test status
Simulation time 23283520897 ps
CPU time 1313.5 seconds
Started Jun 27 04:54:35 PM PDT 24
Finished Jun 27 05:16:32 PM PDT 24
Peak memory 199896 kb
Host smart-874c8af1-e65c-4ec6-a490-deea83272c65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=561698881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.561698881
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.1327513916
Short name T744
Test name
Test status
Simulation time 5480534064 ps
CPU time 35.13 seconds
Started Jun 27 04:54:29 PM PDT 24
Finished Jun 27 04:55:06 PM PDT 24
Peak memory 198332 kb
Host smart-72ff4d92-cb47-4650-ad46-4cdde428f1dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1327513916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1327513916
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.3990029995
Short name T992
Test name
Test status
Simulation time 26760388511 ps
CPU time 24.87 seconds
Started Jun 27 04:54:38 PM PDT 24
Finished Jun 27 04:55:06 PM PDT 24
Peak memory 199828 kb
Host smart-cb4ed3f8-907e-4091-8f65-04ffd55f3656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990029995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.3990029995
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2057325929
Short name T276
Test name
Test status
Simulation time 3045471207 ps
CPU time 2.9 seconds
Started Jun 27 04:54:40 PM PDT 24
Finished Jun 27 04:54:47 PM PDT 24
Peak memory 195888 kb
Host smart-32192eac-6e44-447f-8809-e7e8b7cacdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057325929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2057325929
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2025152270
Short name T876
Test name
Test status
Simulation time 6025056286 ps
CPU time 20.69 seconds
Started Jun 27 04:54:31 PM PDT 24
Finished Jun 27 04:54:55 PM PDT 24
Peak memory 199968 kb
Host smart-75c5eecb-c63c-4dd0-a07c-57f83f2fad12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025152270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2025152270
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.4158761097
Short name T233
Test name
Test status
Simulation time 503146172265 ps
CPU time 522.07 seconds
Started Jun 27 04:54:41 PM PDT 24
Finished Jun 27 05:03:28 PM PDT 24
Peak memory 199880 kb
Host smart-e2d330c5-a77e-4add-9925-661eeab01d6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158761097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.4158761097
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.1080829152
Short name T314
Test name
Test status
Simulation time 1442629302 ps
CPU time 3.05 seconds
Started Jun 27 04:54:38 PM PDT 24
Finished Jun 27 04:54:46 PM PDT 24
Peak memory 199748 kb
Host smart-12d5ed63-1697-4046-a3be-27f7c5b9e6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080829152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1080829152
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.923910316
Short name T386
Test name
Test status
Simulation time 5491505708 ps
CPU time 8.74 seconds
Started Jun 27 04:54:32 PM PDT 24
Finished Jun 27 04:54:44 PM PDT 24
Peak memory 199860 kb
Host smart-35a5e358-d1f4-4e44-899a-ea3580a1e106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923910316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.923910316
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2092792412
Short name T248
Test name
Test status
Simulation time 104696964096 ps
CPU time 155.36 seconds
Started Jun 27 04:57:33 PM PDT 24
Finished Jun 27 05:00:11 PM PDT 24
Peak memory 199848 kb
Host smart-c48888a1-d9e0-4c0c-81b9-35811862cc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092792412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2092792412
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.2421146868
Short name T857
Test name
Test status
Simulation time 25173007477 ps
CPU time 35.84 seconds
Started Jun 27 04:57:23 PM PDT 24
Finished Jun 27 04:58:00 PM PDT 24
Peak memory 199840 kb
Host smart-531efd53-0df2-4808-bdac-51049c3ba120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421146868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2421146868
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.1917814270
Short name T500
Test name
Test status
Simulation time 134537720377 ps
CPU time 266.35 seconds
Started Jun 27 04:57:32 PM PDT 24
Finished Jun 27 05:01:59 PM PDT 24
Peak memory 199824 kb
Host smart-26b79bef-d5f9-4485-a437-76ffb3645690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917814270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1917814270
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.3657178693
Short name T203
Test name
Test status
Simulation time 96750925473 ps
CPU time 12.64 seconds
Started Jun 27 04:57:28 PM PDT 24
Finished Jun 27 04:57:42 PM PDT 24
Peak memory 199896 kb
Host smart-da8d74a9-b7f8-455c-af06-bf6775bd4868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657178693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3657178693
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.2666987186
Short name T723
Test name
Test status
Simulation time 41969619863 ps
CPU time 14.34 seconds
Started Jun 27 04:57:21 PM PDT 24
Finished Jun 27 04:57:37 PM PDT 24
Peak memory 199908 kb
Host smart-821c4d65-3666-41ef-bf94-19bad0bfa939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666987186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2666987186
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.2291939034
Short name T1001
Test name
Test status
Simulation time 23327493187 ps
CPU time 19.66 seconds
Started Jun 27 04:57:28 PM PDT 24
Finished Jun 27 04:57:50 PM PDT 24
Peak memory 199988 kb
Host smart-75ecc05c-cc23-4412-8233-eff0cb9c6f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291939034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2291939034
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.3393277996
Short name T94
Test name
Test status
Simulation time 208422092562 ps
CPU time 35.07 seconds
Started Jun 27 04:57:32 PM PDT 24
Finished Jun 27 04:58:10 PM PDT 24
Peak memory 199904 kb
Host smart-d9d0ca92-d3c2-442b-b7b3-ecff04dfdec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393277996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.3393277996
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.3140447282
Short name T869
Test name
Test status
Simulation time 42383415853 ps
CPU time 71.75 seconds
Started Jun 27 04:57:27 PM PDT 24
Finished Jun 27 04:58:41 PM PDT 24
Peak memory 199928 kb
Host smart-95bfed9f-5644-4263-b62d-4db136c60172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140447282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3140447282
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.1877032274
Short name T660
Test name
Test status
Simulation time 37038877 ps
CPU time 0.54 seconds
Started Jun 27 04:54:45 PM PDT 24
Finished Jun 27 04:54:49 PM PDT 24
Peak memory 195220 kb
Host smart-a224cc35-0102-460d-87e6-27ee05e177bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877032274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1877032274
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.2093903270
Short name T601
Test name
Test status
Simulation time 40021813543 ps
CPU time 31.43 seconds
Started Jun 27 04:54:46 PM PDT 24
Finished Jun 27 04:55:21 PM PDT 24
Peak memory 199928 kb
Host smart-8566b05e-2132-4b2f-9474-74a1feb9fcc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093903270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.2093903270
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.1092401081
Short name T268
Test name
Test status
Simulation time 88650441756 ps
CPU time 148.08 seconds
Started Jun 27 04:54:46 PM PDT 24
Finished Jun 27 04:57:18 PM PDT 24
Peak memory 199964 kb
Host smart-45c98913-ede7-4b64-8074-d7c41b75a60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092401081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.1092401081
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_intr.424776569
Short name T986
Test name
Test status
Simulation time 234824548903 ps
CPU time 153.55 seconds
Started Jun 27 04:54:53 PM PDT 24
Finished Jun 27 04:57:28 PM PDT 24
Peak memory 196848 kb
Host smart-fc5e42ba-b1d5-418f-af9b-8b7b4a1f9b1b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424776569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.424776569
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.4008229881
Short name T1054
Test name
Test status
Simulation time 139103416007 ps
CPU time 169.06 seconds
Started Jun 27 04:54:50 PM PDT 24
Finished Jun 27 04:57:41 PM PDT 24
Peak memory 199960 kb
Host smart-b9255fa9-8941-4478-aeed-520520ea26a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4008229881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.4008229881
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.829469164
Short name T956
Test name
Test status
Simulation time 8979321135 ps
CPU time 17.54 seconds
Started Jun 27 04:54:49 PM PDT 24
Finished Jun 27 04:55:09 PM PDT 24
Peak memory 199404 kb
Host smart-4b0cb736-731a-426f-9c5a-1bd1d65bbc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829469164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.829469164
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_perf.1194727986
Short name T641
Test name
Test status
Simulation time 7733663288 ps
CPU time 153.36 seconds
Started Jun 27 04:54:52 PM PDT 24
Finished Jun 27 04:57:28 PM PDT 24
Peak memory 199868 kb
Host smart-8aa0abc8-25ef-4570-8763-4edce5d4d262
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1194727986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1194727986
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.204224314
Short name T539
Test name
Test status
Simulation time 2222106834 ps
CPU time 15.15 seconds
Started Jun 27 04:54:46 PM PDT 24
Finished Jun 27 04:55:04 PM PDT 24
Peak memory 199376 kb
Host smart-28bb8a03-b910-4e52-9a45-b3ad20a611cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=204224314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.204224314
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.4086341536
Short name T1011
Test name
Test status
Simulation time 18308107491 ps
CPU time 15.26 seconds
Started Jun 27 04:54:49 PM PDT 24
Finished Jun 27 04:55:07 PM PDT 24
Peak memory 199672 kb
Host smart-f411a6d3-c000-43e9-9ced-d1ed21d9ce7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086341536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.4086341536
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.1453486178
Short name T855
Test name
Test status
Simulation time 4273072911 ps
CPU time 6.68 seconds
Started Jun 27 04:54:49 PM PDT 24
Finished Jun 27 04:54:58 PM PDT 24
Peak memory 196056 kb
Host smart-988e9d22-b57f-463c-af33-9fcb1f41c432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453486178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1453486178
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.130817436
Short name T551
Test name
Test status
Simulation time 674221990 ps
CPU time 3.09 seconds
Started Jun 27 04:54:53 PM PDT 24
Finished Jun 27 04:54:58 PM PDT 24
Peak memory 198816 kb
Host smart-956080de-9c61-4dca-b2f2-6c8a4ea50c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130817436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.130817436
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.1086439826
Short name T523
Test name
Test status
Simulation time 7668687981 ps
CPU time 10.41 seconds
Started Jun 27 04:54:49 PM PDT 24
Finished Jun 27 04:55:02 PM PDT 24
Peak memory 199640 kb
Host smart-024cf0fe-6854-42eb-bfa8-3769a207209a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086439826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1086439826
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.2072431339
Short name T965
Test name
Test status
Simulation time 73526600588 ps
CPU time 137.18 seconds
Started Jun 27 04:54:46 PM PDT 24
Finished Jun 27 04:57:06 PM PDT 24
Peak memory 199884 kb
Host smart-a730ce96-e8b5-47c0-a380-aa4fc00f1517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072431339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2072431339
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.3428845979
Short name T295
Test name
Test status
Simulation time 79715430430 ps
CPU time 204.26 seconds
Started Jun 27 04:57:27 PM PDT 24
Finished Jun 27 05:00:53 PM PDT 24
Peak memory 199928 kb
Host smart-6a29903c-330b-463b-baee-6cf6fec07cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428845979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3428845979
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.2091779640
Short name T235
Test name
Test status
Simulation time 6434302759 ps
CPU time 10.18 seconds
Started Jun 27 04:57:21 PM PDT 24
Finished Jun 27 04:57:32 PM PDT 24
Peak memory 199404 kb
Host smart-2ced5c04-847e-42fb-845b-1a5678ebeae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091779640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.2091779640
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2069767164
Short name T455
Test name
Test status
Simulation time 29671360913 ps
CPU time 21.59 seconds
Started Jun 27 04:57:28 PM PDT 24
Finished Jun 27 04:57:51 PM PDT 24
Peak memory 199976 kb
Host smart-f4196db3-e639-4917-963c-5d6b455cba29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069767164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2069767164
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.2747270856
Short name T477
Test name
Test status
Simulation time 22944463293 ps
CPU time 8.65 seconds
Started Jun 27 04:57:33 PM PDT 24
Finished Jun 27 04:57:44 PM PDT 24
Peak memory 199660 kb
Host smart-7fe68adc-f87c-4240-82f9-8afc085abb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747270856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.2747270856
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.3020843945
Short name T978
Test name
Test status
Simulation time 113911791931 ps
CPU time 47.35 seconds
Started Jun 27 04:57:23 PM PDT 24
Finished Jun 27 04:58:12 PM PDT 24
Peak memory 199784 kb
Host smart-8c647d5a-6e61-4906-a779-46bcd038caff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020843945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3020843945
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2688445193
Short name T211
Test name
Test status
Simulation time 64041882362 ps
CPU time 176.5 seconds
Started Jun 27 04:57:32 PM PDT 24
Finished Jun 27 05:00:32 PM PDT 24
Peak memory 199956 kb
Host smart-7476e92d-7c6d-4910-9532-967efe6322a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688445193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2688445193
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.179566807
Short name T662
Test name
Test status
Simulation time 109222172210 ps
CPU time 40.9 seconds
Started Jun 27 04:57:26 PM PDT 24
Finished Jun 27 04:58:09 PM PDT 24
Peak memory 199872 kb
Host smart-7edab3cd-5b63-409c-a753-73d041832ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179566807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.179566807
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.423816684
Short name T166
Test name
Test status
Simulation time 15705260262 ps
CPU time 9.59 seconds
Started Jun 27 04:57:26 PM PDT 24
Finished Jun 27 04:57:37 PM PDT 24
Peak memory 199932 kb
Host smart-6cf601eb-1553-4f04-9207-fcf780eaf4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423816684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.423816684
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.424445788
Short name T751
Test name
Test status
Simulation time 26868040 ps
CPU time 0.52 seconds
Started Jun 27 04:53:54 PM PDT 24
Finished Jun 27 04:53:58 PM PDT 24
Peak memory 194756 kb
Host smart-eca2e0b7-f5d7-4ebe-8c13-75e2715c982d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424445788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.424445788
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.4021653030
Short name T432
Test name
Test status
Simulation time 219202509284 ps
CPU time 194.75 seconds
Started Jun 27 04:53:58 PM PDT 24
Finished Jun 27 04:57:15 PM PDT 24
Peak memory 200088 kb
Host smart-7023993b-9c1b-4161-8e6d-a7fb57f44514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021653030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.4021653030
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.1158707688
Short name T172
Test name
Test status
Simulation time 192509158062 ps
CPU time 156.49 seconds
Started Jun 27 04:53:57 PM PDT 24
Finished Jun 27 04:56:36 PM PDT 24
Peak memory 199872 kb
Host smart-c7379a67-9715-4c29-8992-118972befbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158707688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1158707688
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.145781994
Short name T756
Test name
Test status
Simulation time 90845504057 ps
CPU time 143.62 seconds
Started Jun 27 04:53:39 PM PDT 24
Finished Jun 27 04:56:08 PM PDT 24
Peak memory 199992 kb
Host smart-6d5d2371-5838-4cac-a32a-7cf185786769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145781994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.145781994
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.1746982315
Short name T296
Test name
Test status
Simulation time 41111880508 ps
CPU time 38.11 seconds
Started Jun 27 04:53:38 PM PDT 24
Finished Jun 27 04:54:21 PM PDT 24
Peak memory 199976 kb
Host smart-9231a193-b12d-4b45-96a1-4f1acb3f5192
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746982315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1746982315
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.3133207951
Short name T741
Test name
Test status
Simulation time 169776717658 ps
CPU time 1077.95 seconds
Started Jun 27 04:53:38 PM PDT 24
Finished Jun 27 05:11:41 PM PDT 24
Peak memory 199796 kb
Host smart-9c4893a4-b2ed-4a0a-94fc-9e83fea39e5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3133207951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.3133207951
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.1323941493
Short name T889
Test name
Test status
Simulation time 6863833213 ps
CPU time 11.91 seconds
Started Jun 27 04:53:53 PM PDT 24
Finished Jun 27 04:54:06 PM PDT 24
Peak memory 199092 kb
Host smart-ba409f0f-f971-4bf7-a523-2202d5247fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323941493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1323941493
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_perf.1215501365
Short name T1037
Test name
Test status
Simulation time 24159660155 ps
CPU time 341.07 seconds
Started Jun 27 04:53:38 PM PDT 24
Finished Jun 27 04:59:24 PM PDT 24
Peak memory 199800 kb
Host smart-46f9028c-384b-4c80-8956-8405ce842a41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1215501365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.1215501365
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.4271940578
Short name T98
Test name
Test status
Simulation time 6046027440 ps
CPU time 9.24 seconds
Started Jun 27 04:53:54 PM PDT 24
Finished Jun 27 04:54:06 PM PDT 24
Peak memory 198104 kb
Host smart-459d4882-a084-4a0f-a46f-8fc6d5c4d85e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4271940578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.4271940578
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.3877834680
Short name T874
Test name
Test status
Simulation time 92749384833 ps
CPU time 169.7 seconds
Started Jun 27 04:53:37 PM PDT 24
Finished Jun 27 04:56:31 PM PDT 24
Peak memory 199876 kb
Host smart-798b4ffe-f43a-411a-a6f8-b39b25d3fc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877834680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3877834680
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.3902622692
Short name T941
Test name
Test status
Simulation time 5066640100 ps
CPU time 2.84 seconds
Started Jun 27 04:53:37 PM PDT 24
Finished Jun 27 04:53:44 PM PDT 24
Peak memory 196308 kb
Host smart-bb1c44d7-5716-4e12-85ea-c7d49072db48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902622692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3902622692
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.2748263025
Short name T30
Test name
Test status
Simulation time 40423305 ps
CPU time 0.78 seconds
Started Jun 27 04:53:38 PM PDT 24
Finished Jun 27 04:53:44 PM PDT 24
Peak memory 218284 kb
Host smart-7ac84b60-1be9-4b1d-9418-233f526be2ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748263025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2748263025
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.3479735836
Short name T964
Test name
Test status
Simulation time 504077333 ps
CPU time 1.94 seconds
Started Jun 27 04:53:57 PM PDT 24
Finished Jun 27 04:54:02 PM PDT 24
Peak memory 198476 kb
Host smart-f899efd7-79b0-4419-987d-847c63d273eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479735836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.3479735836
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.3669011639
Short name T275
Test name
Test status
Simulation time 60862167617 ps
CPU time 102.07 seconds
Started Jun 27 04:53:39 PM PDT 24
Finished Jun 27 04:55:27 PM PDT 24
Peak memory 199972 kb
Host smart-38fd1d11-eb4d-4c49-a012-0bf4ed8197a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669011639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3669011639
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1975664096
Short name T814
Test name
Test status
Simulation time 783092377 ps
CPU time 1.86 seconds
Started Jun 27 04:53:43 PM PDT 24
Finished Jun 27 04:53:50 PM PDT 24
Peak memory 198152 kb
Host smart-2af4faba-0997-4f2b-9024-8412ded0a008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975664096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1975664096
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.4277869003
Short name T885
Test name
Test status
Simulation time 16109394357 ps
CPU time 6.58 seconds
Started Jun 27 04:53:58 PM PDT 24
Finished Jun 27 04:54:07 PM PDT 24
Peak memory 197572 kb
Host smart-ac3eb108-7029-45db-a04e-d028f0cfc787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277869003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.4277869003
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.154853524
Short name T901
Test name
Test status
Simulation time 19596890 ps
CPU time 0.53 seconds
Started Jun 27 04:54:49 PM PDT 24
Finished Jun 27 04:54:52 PM PDT 24
Peak memory 194280 kb
Host smart-40d9fc26-49d5-47ca-8d51-8f2bbcbb124b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154853524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.154853524
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.4085435261
Short name T555
Test name
Test status
Simulation time 91249549307 ps
CPU time 86.45 seconds
Started Jun 27 04:54:44 PM PDT 24
Finished Jun 27 04:56:15 PM PDT 24
Peak memory 199908 kb
Host smart-1a319a65-52ae-467e-9fb3-da5fbf45c51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085435261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.4085435261
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.3932290824
Short name T1051
Test name
Test status
Simulation time 266931913562 ps
CPU time 145.19 seconds
Started Jun 27 04:54:56 PM PDT 24
Finished Jun 27 04:57:23 PM PDT 24
Peak memory 199680 kb
Host smart-da9daec4-a1be-4b7b-be98-157fb7fbf78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932290824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3932290824
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.60873614
Short name T674
Test name
Test status
Simulation time 92687058315 ps
CPU time 159.89 seconds
Started Jun 27 04:54:48 PM PDT 24
Finished Jun 27 04:57:31 PM PDT 24
Peak memory 199948 kb
Host smart-973ea484-babf-43ee-8cca-ae07ab535f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60873614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.60873614
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.455788902
Short name T873
Test name
Test status
Simulation time 319109799123 ps
CPU time 545.21 seconds
Started Jun 27 04:54:50 PM PDT 24
Finished Jun 27 05:03:58 PM PDT 24
Peak memory 199196 kb
Host smart-7035dfde-1145-483f-b17f-96c2426c0022
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455788902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.455788902
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.1260091306
Short name T514
Test name
Test status
Simulation time 106580417277 ps
CPU time 368.75 seconds
Started Jun 27 04:54:48 PM PDT 24
Finished Jun 27 05:01:00 PM PDT 24
Peak memory 199876 kb
Host smart-2ca1edd6-c02a-4115-be20-abd78775ea8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1260091306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1260091306
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.3266865579
Short name T521
Test name
Test status
Simulation time 2337713769 ps
CPU time 5.32 seconds
Started Jun 27 04:54:53 PM PDT 24
Finished Jun 27 04:55:00 PM PDT 24
Peak memory 199140 kb
Host smart-7678007e-aafe-4aa4-a07b-2c12b96e5d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266865579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.3266865579
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_perf.111693058
Short name T482
Test name
Test status
Simulation time 4921934045 ps
CPU time 132.09 seconds
Started Jun 27 04:54:53 PM PDT 24
Finished Jun 27 04:57:07 PM PDT 24
Peak memory 199776 kb
Host smart-a48ce164-3d35-4996-96f3-a053d2268088
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=111693058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.111693058
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.3471695903
Short name T458
Test name
Test status
Simulation time 4541458792 ps
CPU time 36.13 seconds
Started Jun 27 04:54:45 PM PDT 24
Finished Jun 27 04:55:24 PM PDT 24
Peak memory 199296 kb
Host smart-566454d5-ab2c-4032-8692-493661c02539
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3471695903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.3471695903
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.3311996006
Short name T249
Test name
Test status
Simulation time 24223128729 ps
CPU time 43.27 seconds
Started Jun 27 04:54:48 PM PDT 24
Finished Jun 27 04:55:34 PM PDT 24
Peak memory 199888 kb
Host smart-72a61365-328c-4398-9aab-00f86c571610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311996006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.3311996006
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.531147603
Short name T384
Test name
Test status
Simulation time 33020312127 ps
CPU time 49.29 seconds
Started Jun 27 04:54:53 PM PDT 24
Finished Jun 27 04:55:44 PM PDT 24
Peak memory 195932 kb
Host smart-1e43b901-f1ca-4376-b72e-913ac0ae173d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531147603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.531147603
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.1063154627
Short name T536
Test name
Test status
Simulation time 287657044 ps
CPU time 1.49 seconds
Started Jun 27 04:54:47 PM PDT 24
Finished Jun 27 04:54:52 PM PDT 24
Peak memory 198288 kb
Host smart-dc584de1-b3b0-44cb-8e98-3fbee6b8ace4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063154627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1063154627
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.1893568906
Short name T3
Test name
Test status
Simulation time 1287639445 ps
CPU time 1.61 seconds
Started Jun 27 04:54:48 PM PDT 24
Finished Jun 27 04:54:53 PM PDT 24
Peak memory 200028 kb
Host smart-b609384a-d237-46b9-b56f-2615c2283469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893568906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1893568906
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.4054177084
Short name T602
Test name
Test status
Simulation time 19144245740 ps
CPU time 14.73 seconds
Started Jun 27 04:54:49 PM PDT 24
Finished Jun 27 04:55:07 PM PDT 24
Peak memory 197600 kb
Host smart-2a9fe3de-6421-49c5-86da-50ffb288d835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054177084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.4054177084
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.4166819914
Short name T200
Test name
Test status
Simulation time 56470043437 ps
CPU time 20.1 seconds
Started Jun 27 04:57:26 PM PDT 24
Finished Jun 27 04:57:47 PM PDT 24
Peak memory 199952 kb
Host smart-e4a9a253-a3c5-419e-96b8-7d3e903f5261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166819914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.4166819914
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.2603095751
Short name T440
Test name
Test status
Simulation time 85894519485 ps
CPU time 17.76 seconds
Started Jun 27 04:57:22 PM PDT 24
Finished Jun 27 04:57:41 PM PDT 24
Peak memory 199912 kb
Host smart-850bf78e-bf5b-43df-b774-4d847afb0e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603095751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.2603095751
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.2515645924
Short name T175
Test name
Test status
Simulation time 2944737359 ps
CPU time 5.69 seconds
Started Jun 27 04:57:23 PM PDT 24
Finished Jun 27 04:57:30 PM PDT 24
Peak memory 198764 kb
Host smart-cc0cd575-87cc-4440-9c91-00450d01c0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515645924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2515645924
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.1114542132
Short name T1061
Test name
Test status
Simulation time 94945295866 ps
CPU time 147.1 seconds
Started Jun 27 04:57:26 PM PDT 24
Finished Jun 27 04:59:55 PM PDT 24
Peak memory 199932 kb
Host smart-c327fe51-4a3a-4258-a22b-d1451fcd6f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114542132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.1114542132
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.446399600
Short name T904
Test name
Test status
Simulation time 49874572208 ps
CPU time 19.8 seconds
Started Jun 27 04:57:32 PM PDT 24
Finished Jun 27 04:57:55 PM PDT 24
Peak memory 200008 kb
Host smart-0e373d13-e5eb-4077-a0d6-f980726ee71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446399600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.446399600
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.656892595
Short name T585
Test name
Test status
Simulation time 34883346625 ps
CPU time 99.5 seconds
Started Jun 27 04:57:32 PM PDT 24
Finished Jun 27 04:59:15 PM PDT 24
Peak memory 199752 kb
Host smart-084162df-b845-48ff-941d-b40616396648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656892595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.656892595
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.2836513413
Short name T919
Test name
Test status
Simulation time 82436185348 ps
CPU time 82.77 seconds
Started Jun 27 04:57:26 PM PDT 24
Finished Jun 27 04:58:50 PM PDT 24
Peak memory 199900 kb
Host smart-3b5d3d98-79f4-4b75-91f2-2f808d1b1658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836513413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.2836513413
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.781708942
Short name T951
Test name
Test status
Simulation time 37426650762 ps
CPU time 26.96 seconds
Started Jun 27 04:57:27 PM PDT 24
Finished Jun 27 04:57:55 PM PDT 24
Peak memory 199952 kb
Host smart-a7d915ab-bfa5-456e-b13b-b8fd5b3461f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781708942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.781708942
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.2201901522
Short name T127
Test name
Test status
Simulation time 68739701043 ps
CPU time 65.53 seconds
Started Jun 27 04:57:33 PM PDT 24
Finished Jun 27 04:58:41 PM PDT 24
Peak memory 199764 kb
Host smart-e90dfbd1-43c0-4d89-9c3e-2de3e947c80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201901522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2201901522
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.3290450877
Short name T513
Test name
Test status
Simulation time 128561779515 ps
CPU time 31.45 seconds
Started Jun 27 04:57:26 PM PDT 24
Finished Jun 27 04:57:59 PM PDT 24
Peak memory 199948 kb
Host smart-a74ee35b-bd40-4ffb-ac8c-cc54646b3f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290450877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3290450877
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.2439712318
Short name T454
Test name
Test status
Simulation time 22536894 ps
CPU time 0.52 seconds
Started Jun 27 04:54:54 PM PDT 24
Finished Jun 27 04:54:56 PM PDT 24
Peak memory 193816 kb
Host smart-00d5569d-75de-49a5-b1b2-cb9120e30ed5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439712318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2439712318
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.1816523179
Short name T474
Test name
Test status
Simulation time 109518513800 ps
CPU time 117 seconds
Started Jun 27 04:54:53 PM PDT 24
Finished Jun 27 04:56:52 PM PDT 24
Peak memory 199892 kb
Host smart-067f81fe-1ffa-4c9e-ae20-edfaca444fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816523179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.1816523179
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.1254206896
Short name T1010
Test name
Test status
Simulation time 126774662546 ps
CPU time 464.92 seconds
Started Jun 27 04:54:48 PM PDT 24
Finished Jun 27 05:02:36 PM PDT 24
Peak memory 199956 kb
Host smart-15169506-e204-4fe2-afe6-307290e8da65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254206896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1254206896
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.433636227
Short name T648
Test name
Test status
Simulation time 156155392658 ps
CPU time 100.78 seconds
Started Jun 27 04:54:54 PM PDT 24
Finished Jun 27 04:56:37 PM PDT 24
Peak memory 199912 kb
Host smart-dc415192-dce1-4cd1-aba3-61f1d2912288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433636227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.433636227
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.3576725020
Short name T758
Test name
Test status
Simulation time 13845788519 ps
CPU time 20.66 seconds
Started Jun 27 04:54:49 PM PDT 24
Finished Jun 27 04:55:12 PM PDT 24
Peak memory 196344 kb
Host smart-0fd454e2-5595-43cd-b62e-eec98d78e8da
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576725020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.3576725020
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.3233521765
Short name T672
Test name
Test status
Simulation time 137994697203 ps
CPU time 119.86 seconds
Started Jun 27 04:54:49 PM PDT 24
Finished Jun 27 04:56:52 PM PDT 24
Peak memory 199900 kb
Host smart-f19557be-1012-4a3d-90fd-eb2f9549ef8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3233521765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3233521765
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.1801493577
Short name T835
Test name
Test status
Simulation time 4134231530 ps
CPU time 3.8 seconds
Started Jun 27 04:54:49 PM PDT 24
Finished Jun 27 04:54:56 PM PDT 24
Peak memory 196736 kb
Host smart-41498472-b0d7-48dc-86f6-6870f87faa9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801493577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1801493577
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_perf.1086550557
Short name T798
Test name
Test status
Simulation time 15115729277 ps
CPU time 858.58 seconds
Started Jun 27 04:54:51 PM PDT 24
Finished Jun 27 05:09:12 PM PDT 24
Peak memory 199908 kb
Host smart-4044a526-28ed-4908-850f-17d3fac7e0f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1086550557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1086550557
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.1445202616
Short name T808
Test name
Test status
Simulation time 3685089287 ps
CPU time 6.52 seconds
Started Jun 27 04:54:49 PM PDT 24
Finished Jun 27 04:54:58 PM PDT 24
Peak memory 198928 kb
Host smart-f8f72251-523e-4522-9ccd-9a08a20c307f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1445202616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1445202616
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.848256161
Short name T769
Test name
Test status
Simulation time 4211820191 ps
CPU time 5.78 seconds
Started Jun 27 04:54:47 PM PDT 24
Finished Jun 27 04:54:56 PM PDT 24
Peak memory 199940 kb
Host smart-eda3f91d-0e81-41ad-9ee6-c8a23e7fd5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848256161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.848256161
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.3719985168
Short name T639
Test name
Test status
Simulation time 73007337511 ps
CPU time 116.31 seconds
Started Jun 27 04:54:46 PM PDT 24
Finished Jun 27 04:56:46 PM PDT 24
Peak memory 195988 kb
Host smart-e73ee6e5-ddf4-4eba-a654-b4addec41300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719985168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.3719985168
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.3031260154
Short name T771
Test name
Test status
Simulation time 894491443 ps
CPU time 2.75 seconds
Started Jun 27 04:54:48 PM PDT 24
Finished Jun 27 04:54:54 PM PDT 24
Peak memory 199504 kb
Host smart-66e92eb8-ddfd-4c95-8774-94fc283901d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031260154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3031260154
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.2160300296
Short name T196
Test name
Test status
Simulation time 87874728916 ps
CPU time 180.88 seconds
Started Jun 27 04:54:46 PM PDT 24
Finished Jun 27 04:57:50 PM PDT 24
Peak memory 199960 kb
Host smart-1d5f724f-699c-448a-b06f-5092bb011387
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160300296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2160300296
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.4000302079
Short name T471
Test name
Test status
Simulation time 570589469 ps
CPU time 1.69 seconds
Started Jun 27 04:55:00 PM PDT 24
Finished Jun 27 04:55:02 PM PDT 24
Peak memory 198628 kb
Host smart-6572de77-653e-42d0-a17f-eb7cf4c1cb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000302079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.4000302079
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.1687337681
Short name T605
Test name
Test status
Simulation time 40959358107 ps
CPU time 8.77 seconds
Started Jun 27 04:54:54 PM PDT 24
Finished Jun 27 04:55:05 PM PDT 24
Peak memory 199840 kb
Host smart-5a741d4c-53e0-453a-9228-a387dd6146a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687337681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1687337681
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.2473983096
Short name T977
Test name
Test status
Simulation time 8544755290 ps
CPU time 36.68 seconds
Started Jun 27 04:57:32 PM PDT 24
Finished Jun 27 04:58:12 PM PDT 24
Peak memory 199924 kb
Host smart-4b482771-d18f-4239-9ed8-640e52d7d7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473983096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.2473983096
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.1634129210
Short name T619
Test name
Test status
Simulation time 94740481470 ps
CPU time 44.29 seconds
Started Jun 27 04:57:28 PM PDT 24
Finished Jun 27 04:58:14 PM PDT 24
Peak memory 199904 kb
Host smart-f53810c2-46e0-4208-87ac-c4347cc4e6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634129210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.1634129210
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2476149517
Short name T910
Test name
Test status
Simulation time 76391726773 ps
CPU time 65.4 seconds
Started Jun 27 04:57:32 PM PDT 24
Finished Jun 27 04:58:40 PM PDT 24
Peak memory 199984 kb
Host smart-3eb165d8-eeec-46ad-bfda-f4c3a2b2a735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476149517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2476149517
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.467587423
Short name T484
Test name
Test status
Simulation time 4496002509 ps
CPU time 6.99 seconds
Started Jun 27 04:57:31 PM PDT 24
Finished Jun 27 04:57:39 PM PDT 24
Peak memory 199952 kb
Host smart-db50ee4c-1005-41e7-8fcd-b7ed3c615948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467587423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.467587423
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2895282366
Short name T1043
Test name
Test status
Simulation time 98292851410 ps
CPU time 115.52 seconds
Started Jun 27 04:57:32 PM PDT 24
Finished Jun 27 04:59:29 PM PDT 24
Peak memory 199960 kb
Host smart-f938930d-b8db-4a09-af8f-5f57d266cff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895282366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2895282366
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.234023753
Short name T866
Test name
Test status
Simulation time 30007461656 ps
CPU time 83.78 seconds
Started Jun 27 04:57:27 PM PDT 24
Finished Jun 27 04:58:53 PM PDT 24
Peak memory 200032 kb
Host smart-faa0aa3b-7387-40f0-86ea-380b1c3bffc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234023753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.234023753
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.44315052
Short name T280
Test name
Test status
Simulation time 83946117825 ps
CPU time 41.01 seconds
Started Jun 27 04:57:32 PM PDT 24
Finished Jun 27 04:58:16 PM PDT 24
Peak memory 199792 kb
Host smart-e6b1c538-1487-43f9-a0b1-4d45716c8a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44315052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.44315052
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.977757774
Short name T473
Test name
Test status
Simulation time 95468931628 ps
CPU time 159.19 seconds
Started Jun 27 04:57:28 PM PDT 24
Finished Jun 27 05:00:09 PM PDT 24
Peak memory 199988 kb
Host smart-c74f9303-ddbc-4b25-b59d-a35351617ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977757774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.977757774
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.1318109079
Short name T370
Test name
Test status
Simulation time 24064414 ps
CPU time 0.61 seconds
Started Jun 27 04:55:00 PM PDT 24
Finished Jun 27 04:55:02 PM PDT 24
Peak memory 195304 kb
Host smart-90c23d76-7607-4891-9380-3e5c1e44fef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318109079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.1318109079
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2570414398
Short name T1058
Test name
Test status
Simulation time 27276328827 ps
CPU time 13.01 seconds
Started Jun 27 04:54:48 PM PDT 24
Finished Jun 27 04:55:04 PM PDT 24
Peak memory 199992 kb
Host smart-f6850a65-0396-4384-b831-11998d0f3503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570414398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2570414398
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.1339202291
Short name T169
Test name
Test status
Simulation time 13743701424 ps
CPU time 21.68 seconds
Started Jun 27 04:54:49 PM PDT 24
Finished Jun 27 04:55:18 PM PDT 24
Peak memory 200000 kb
Host smart-12cd2048-6deb-4e49-90b2-31c1276f92f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339202291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.1339202291
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.2451227236
Short name T832
Test name
Test status
Simulation time 36445372685 ps
CPU time 11.83 seconds
Started Jun 27 04:54:52 PM PDT 24
Finished Jun 27 04:55:06 PM PDT 24
Peak memory 199908 kb
Host smart-4a80c0ad-5af9-4f58-98ab-c94f68e60b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451227236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2451227236
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.3832995836
Short name T105
Test name
Test status
Simulation time 31720565073 ps
CPU time 26.1 seconds
Started Jun 27 04:54:54 PM PDT 24
Finished Jun 27 04:55:21 PM PDT 24
Peak memory 198564 kb
Host smart-f137dd52-08b3-471d-939c-b8e860cc8d9f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832995836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3832995836
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.1988882374
Short name T375
Test name
Test status
Simulation time 138149772597 ps
CPU time 267.96 seconds
Started Jun 27 04:54:53 PM PDT 24
Finished Jun 27 04:59:23 PM PDT 24
Peak memory 199920 kb
Host smart-86ed3761-4170-4fba-8f8b-09f0a260e455
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1988882374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1988882374
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.137294190
Short name T878
Test name
Test status
Simulation time 1352372134 ps
CPU time 1.93 seconds
Started Jun 27 04:55:07 PM PDT 24
Finished Jun 27 04:55:13 PM PDT 24
Peak memory 196684 kb
Host smart-18bba652-b086-430e-949c-1a2334777576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137294190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.137294190
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_perf.3673066332
Short name T369
Test name
Test status
Simulation time 7247474480 ps
CPU time 417.67 seconds
Started Jun 27 04:54:46 PM PDT 24
Finished Jun 27 05:01:47 PM PDT 24
Peak memory 199944 kb
Host smart-657d9adf-656b-405f-9a49-73b43f2f806f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3673066332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3673066332
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.1843198302
Short name T16
Test name
Test status
Simulation time 5663292840 ps
CPU time 56.05 seconds
Started Jun 27 04:54:49 PM PDT 24
Finished Jun 27 04:55:48 PM PDT 24
Peak memory 199532 kb
Host smart-91e9b8c0-9568-4ed1-8976-025d647a54f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1843198302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1843198302
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1539733807
Short name T597
Test name
Test status
Simulation time 122675166994 ps
CPU time 48.15 seconds
Started Jun 27 04:55:00 PM PDT 24
Finished Jun 27 04:55:49 PM PDT 24
Peak memory 199836 kb
Host smart-9859bd21-02ed-47da-b52a-4565595f81b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539733807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1539733807
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.3012673747
Short name T921
Test name
Test status
Simulation time 5489043880 ps
CPU time 2.67 seconds
Started Jun 27 04:54:51 PM PDT 24
Finished Jun 27 04:54:56 PM PDT 24
Peak memory 196244 kb
Host smart-4ae1e9bd-60bf-45be-9c44-1f6453e9b035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012673747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.3012673747
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.3334968983
Short name T824
Test name
Test status
Simulation time 673253826 ps
CPU time 4.97 seconds
Started Jun 27 04:54:46 PM PDT 24
Finished Jun 27 04:54:54 PM PDT 24
Peak memory 198836 kb
Host smart-bf349950-3988-42dc-8d4f-7ed83eefa705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334968983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3334968983
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.1647501621
Short name T428
Test name
Test status
Simulation time 123704833971 ps
CPU time 187.75 seconds
Started Jun 27 04:54:55 PM PDT 24
Finished Jun 27 04:58:05 PM PDT 24
Peak memory 199876 kb
Host smart-a388b8f1-c365-4c7f-944e-48e1ceeab4f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647501621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1647501621
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.4206658830
Short name T650
Test name
Test status
Simulation time 783474987 ps
CPU time 2.7 seconds
Started Jun 27 04:54:49 PM PDT 24
Finished Jun 27 04:54:54 PM PDT 24
Peak memory 199040 kb
Host smart-56e71232-57ab-47a1-9514-8a3c13f10099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206658830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.4206658830
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3253515695
Short name T556
Test name
Test status
Simulation time 62412239472 ps
CPU time 13.94 seconds
Started Jun 27 04:54:51 PM PDT 24
Finished Jun 27 04:55:07 PM PDT 24
Peak memory 199996 kb
Host smart-50a4c13e-93b5-4284-bd2f-912c2f8259a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253515695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3253515695
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1146598758
Short name T131
Test name
Test status
Simulation time 172740940857 ps
CPU time 20.7 seconds
Started Jun 27 04:57:32 PM PDT 24
Finished Jun 27 04:57:56 PM PDT 24
Peak memory 199980 kb
Host smart-2ff61d74-0fae-45e0-82d9-0b3fd2ef50a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146598758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1146598758
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.1721969975
Short name T1075
Test name
Test status
Simulation time 103843748911 ps
CPU time 41.8 seconds
Started Jun 27 04:57:22 PM PDT 24
Finished Jun 27 04:58:05 PM PDT 24
Peak memory 199924 kb
Host smart-8d0d733a-8d3f-49cf-8f2a-f8004e53eb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721969975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1721969975
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.935822985
Short name T823
Test name
Test status
Simulation time 49793685813 ps
CPU time 11.7 seconds
Started Jun 27 04:57:32 PM PDT 24
Finished Jun 27 04:57:46 PM PDT 24
Peak memory 199924 kb
Host smart-0200ae23-2fc8-4349-afd1-ab269efb2254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935822985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.935822985
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1330853574
Short name T193
Test name
Test status
Simulation time 21316518811 ps
CPU time 37.18 seconds
Started Jun 27 04:57:28 PM PDT 24
Finished Jun 27 04:58:07 PM PDT 24
Peak memory 199932 kb
Host smart-ff2b6138-c4a7-4338-a6a2-4619f69b79bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330853574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1330853574
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.1285345733
Short name T507
Test name
Test status
Simulation time 17353705855 ps
CPU time 28.68 seconds
Started Jun 27 04:57:27 PM PDT 24
Finished Jun 27 04:57:58 PM PDT 24
Peak memory 199888 kb
Host smart-25d8a3c9-d962-411c-b969-9ccb1fac17f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285345733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1285345733
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2467994170
Short name T532
Test name
Test status
Simulation time 39437931772 ps
CPU time 18.79 seconds
Started Jun 27 04:57:28 PM PDT 24
Finished Jun 27 04:57:49 PM PDT 24
Peak memory 199868 kb
Host smart-d7c4d8a0-5d13-4b93-952a-6a8977270f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467994170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2467994170
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1726557548
Short name T745
Test name
Test status
Simulation time 57025027742 ps
CPU time 52.27 seconds
Started Jun 27 04:57:32 PM PDT 24
Finished Jun 27 04:58:26 PM PDT 24
Peak memory 199972 kb
Host smart-40e1baf9-a77a-4a44-b017-77fe8277ddae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726557548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1726557548
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.2559149019
Short name T527
Test name
Test status
Simulation time 11108285 ps
CPU time 0.51 seconds
Started Jun 27 04:54:55 PM PDT 24
Finished Jun 27 04:54:58 PM PDT 24
Peak memory 194256 kb
Host smart-ff7bfa88-8311-4112-891f-0525ee136b53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559149019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.2559149019
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.316324852
Short name T335
Test name
Test status
Simulation time 62766039385 ps
CPU time 24.91 seconds
Started Jun 27 04:55:00 PM PDT 24
Finished Jun 27 04:55:26 PM PDT 24
Peak memory 199840 kb
Host smart-71317b1a-fad0-49c9-8216-44224b46dfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316324852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.316324852
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.986212734
Short name T620
Test name
Test status
Simulation time 100244182870 ps
CPU time 120.07 seconds
Started Jun 27 04:55:02 PM PDT 24
Finished Jun 27 04:57:04 PM PDT 24
Peak memory 199860 kb
Host smart-c8243d5f-1fe0-4af3-8316-3434f12ff039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986212734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.986212734
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.953809048
Short name T582
Test name
Test status
Simulation time 60334525095 ps
CPU time 63.88 seconds
Started Jun 27 04:54:53 PM PDT 24
Finished Jun 27 04:55:59 PM PDT 24
Peak memory 199972 kb
Host smart-580fd215-adf6-40c0-8166-521023001fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953809048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.953809048
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.2570016323
Short name T363
Test name
Test status
Simulation time 144412968558 ps
CPU time 54.82 seconds
Started Jun 27 04:55:09 PM PDT 24
Finished Jun 27 04:56:08 PM PDT 24
Peak memory 196196 kb
Host smart-af53ab99-ddbe-4e0a-bb7c-a024682b0f95
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570016323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2570016323
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.250111267
Short name T446
Test name
Test status
Simulation time 273853069696 ps
CPU time 417.37 seconds
Started Jun 27 04:54:56 PM PDT 24
Finished Jun 27 05:01:55 PM PDT 24
Peak memory 199884 kb
Host smart-d1399d5f-d00c-4013-b2f1-9ddc13c40236
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=250111267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.250111267
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.6866385
Short name T588
Test name
Test status
Simulation time 5414340712 ps
CPU time 3.38 seconds
Started Jun 27 04:54:56 PM PDT 24
Finished Jun 27 04:55:01 PM PDT 24
Peak memory 199712 kb
Host smart-3b118466-6c72-4a03-ba72-cc4891280a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6866385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.6866385
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_perf.3935648422
Short name T254
Test name
Test status
Simulation time 13313015255 ps
CPU time 227.95 seconds
Started Jun 27 04:54:55 PM PDT 24
Finished Jun 27 04:58:45 PM PDT 24
Peak memory 199968 kb
Host smart-a1119469-1f87-42a8-9e85-ceca3e96f2ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3935648422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3935648422
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.822745959
Short name T810
Test name
Test status
Simulation time 4717436746 ps
CPU time 3.14 seconds
Started Jun 27 04:54:49 PM PDT 24
Finished Jun 27 04:54:55 PM PDT 24
Peak memory 198044 kb
Host smart-a7208ea2-44db-4781-a5c5-695dd57fcfbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=822745959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.822745959
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.3259032577
Short name T379
Test name
Test status
Simulation time 33027050256 ps
CPU time 36.66 seconds
Started Jun 27 04:55:08 PM PDT 24
Finished Jun 27 04:55:49 PM PDT 24
Peak memory 199988 kb
Host smart-93d8cec6-7643-45af-95e7-eb84353c616d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259032577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3259032577
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.2779408343
Short name T627
Test name
Test status
Simulation time 42866401739 ps
CPU time 68.98 seconds
Started Jun 27 04:54:55 PM PDT 24
Finished Jun 27 04:56:06 PM PDT 24
Peak memory 195748 kb
Host smart-703d0a81-7d96-4e7f-8c7a-f961b7c0207a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779408343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.2779408343
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.661364844
Short name T629
Test name
Test status
Simulation time 5840408025 ps
CPU time 22.88 seconds
Started Jun 27 04:54:55 PM PDT 24
Finished Jun 27 04:55:20 PM PDT 24
Peak memory 199792 kb
Host smart-7aee40fb-8bb0-44ce-8701-8b2289691153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661364844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.661364844
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.3942775704
Short name T336
Test name
Test status
Simulation time 337413635645 ps
CPU time 355.8 seconds
Started Jun 27 04:54:47 PM PDT 24
Finished Jun 27 05:00:46 PM PDT 24
Peak memory 199860 kb
Host smart-8875ddee-1ca8-48d4-b19b-93861e6faa04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942775704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.3942775704
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.1025989417
Short name T391
Test name
Test status
Simulation time 550061000 ps
CPU time 1.52 seconds
Started Jun 27 04:54:55 PM PDT 24
Finished Jun 27 04:54:59 PM PDT 24
Peak memory 198300 kb
Host smart-0b72a7c8-7b9b-4ec4-af52-608a3d4286e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025989417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1025989417
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1920887437
Short name T860
Test name
Test status
Simulation time 125190061284 ps
CPU time 43.18 seconds
Started Jun 27 04:55:02 PM PDT 24
Finished Jun 27 04:55:47 PM PDT 24
Peak memory 199808 kb
Host smart-f938d743-35e3-400a-9cdf-f7642eade678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920887437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1920887437
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.210235582
Short name T670
Test name
Test status
Simulation time 26112028819 ps
CPU time 23.39 seconds
Started Jun 27 04:57:28 PM PDT 24
Finished Jun 27 04:57:53 PM PDT 24
Peak memory 199836 kb
Host smart-86100017-05f4-467e-93fe-cf830ec30d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210235582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.210235582
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.2605151712
Short name T761
Test name
Test status
Simulation time 96687630295 ps
CPU time 173.38 seconds
Started Jun 27 04:57:32 PM PDT 24
Finished Jun 27 05:00:28 PM PDT 24
Peak memory 199908 kb
Host smart-1e23af9b-9535-429e-89f7-fa891beded2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605151712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2605151712
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.4175771065
Short name T479
Test name
Test status
Simulation time 125549645709 ps
CPU time 56.38 seconds
Started Jun 27 04:57:22 PM PDT 24
Finished Jun 27 04:58:19 PM PDT 24
Peak memory 199924 kb
Host smart-ebe63c8d-2ccc-4234-8052-4d9a0590e065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175771065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.4175771065
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.432451244
Short name T469
Test name
Test status
Simulation time 22455233191 ps
CPU time 30.42 seconds
Started Jun 27 04:57:33 PM PDT 24
Finished Jun 27 04:58:06 PM PDT 24
Peak memory 199664 kb
Host smart-67967ec9-2ba7-45d7-b2e6-3b4b42fad26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432451244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.432451244
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.2940122203
Short name T329
Test name
Test status
Simulation time 65645639001 ps
CPU time 95.16 seconds
Started Jun 27 04:57:33 PM PDT 24
Finished Jun 27 04:59:11 PM PDT 24
Peak memory 199908 kb
Host smart-992365d2-9119-4da5-a92e-9795ec331706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940122203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.2940122203
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.3409216164
Short name T223
Test name
Test status
Simulation time 17382135330 ps
CPU time 37.2 seconds
Started Jun 27 04:57:32 PM PDT 24
Finished Jun 27 04:58:12 PM PDT 24
Peak memory 199928 kb
Host smart-f6af2848-68d0-49e0-a7f5-4eb1dfbcde57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409216164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.3409216164
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3467658329
Short name T450
Test name
Test status
Simulation time 18071344246 ps
CPU time 25.57 seconds
Started Jun 27 04:57:31 PM PDT 24
Finished Jun 27 04:57:58 PM PDT 24
Peak memory 198320 kb
Host smart-5f20cf7a-3066-4427-8bd1-b6be20b89cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467658329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3467658329
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.1841622876
Short name T673
Test name
Test status
Simulation time 64194450589 ps
CPU time 28.37 seconds
Started Jun 27 04:57:32 PM PDT 24
Finished Jun 27 04:58:03 PM PDT 24
Peak memory 199876 kb
Host smart-55185e7f-145b-4146-b5e8-e03fb5f68904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841622876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.1841622876
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.953230227
Short name T787
Test name
Test status
Simulation time 61055488941 ps
CPU time 91.59 seconds
Started Jun 27 04:57:32 PM PDT 24
Finished Jun 27 04:59:07 PM PDT 24
Peak memory 199916 kb
Host smart-55f600ca-0a5c-4d97-b52f-37d7be1e3f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953230227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.953230227
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.4234289123
Short name T510
Test name
Test status
Simulation time 40183249 ps
CPU time 0.52 seconds
Started Jun 27 04:54:49 PM PDT 24
Finished Jun 27 04:54:53 PM PDT 24
Peak memory 195564 kb
Host smart-b08f5e72-a54b-4b1b-98b3-e7ac751124ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234289123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.4234289123
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.2511805185
Short name T675
Test name
Test status
Simulation time 45715214463 ps
CPU time 72.92 seconds
Started Jun 27 04:54:56 PM PDT 24
Finished Jun 27 04:56:11 PM PDT 24
Peak memory 199904 kb
Host smart-7c02d553-8420-4077-b3dc-05056ef69f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511805185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2511805185
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.104630449
Short name T843
Test name
Test status
Simulation time 198027384512 ps
CPU time 370.13 seconds
Started Jun 27 04:54:56 PM PDT 24
Finished Jun 27 05:01:08 PM PDT 24
Peak memory 199600 kb
Host smart-ac06d535-7b08-49d1-9d98-0175a2aa042c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104630449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.104630449
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.3691207910
Short name T222
Test name
Test status
Simulation time 65853980193 ps
CPU time 153.91 seconds
Started Jun 27 04:54:53 PM PDT 24
Finished Jun 27 04:57:29 PM PDT 24
Peak memory 199808 kb
Host smart-6795c0d3-5d57-4ee6-9ab0-083aa84ee085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691207910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3691207910
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.1321814344
Short name T952
Test name
Test status
Simulation time 284514680188 ps
CPU time 119.81 seconds
Started Jun 27 04:55:06 PM PDT 24
Finished Jun 27 04:57:09 PM PDT 24
Peak memory 198176 kb
Host smart-c6dab591-99cd-4f88-af9a-425cdfd2ee89
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321814344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.1321814344
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.2987501094
Short name T759
Test name
Test status
Simulation time 69135175764 ps
CPU time 625.44 seconds
Started Jun 27 04:54:49 PM PDT 24
Finished Jun 27 05:05:18 PM PDT 24
Peak memory 199856 kb
Host smart-d10cdc30-a8da-4d4b-8f1c-a8adcea7f70e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2987501094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.2987501094
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3931201523
Short name T684
Test name
Test status
Simulation time 6736448062 ps
CPU time 10.03 seconds
Started Jun 27 04:54:54 PM PDT 24
Finished Jun 27 04:55:06 PM PDT 24
Peak memory 198360 kb
Host smart-6843cf23-e154-4255-9aee-d5195aac0b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931201523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3931201523
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.322543183
Short name T894
Test name
Test status
Simulation time 12497535362 ps
CPU time 9.36 seconds
Started Jun 27 04:54:49 PM PDT 24
Finished Jun 27 04:55:01 PM PDT 24
Peak memory 199624 kb
Host smart-747bafdc-3f37-4c0e-8ed2-f439f56821b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322543183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.322543183
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.1930232492
Short name T851
Test name
Test status
Simulation time 16016352538 ps
CPU time 935.6 seconds
Started Jun 27 04:55:00 PM PDT 24
Finished Jun 27 05:10:37 PM PDT 24
Peak memory 199840 kb
Host smart-9d38161a-d9d6-4e53-8acf-c91e73f72071
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1930232492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.1930232492
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.3273989793
Short name T949
Test name
Test status
Simulation time 3804202681 ps
CPU time 26.62 seconds
Started Jun 27 04:55:06 PM PDT 24
Finished Jun 27 04:55:35 PM PDT 24
Peak memory 199136 kb
Host smart-0b43ec3f-50a7-4627-946d-41a73346aa2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3273989793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3273989793
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.540746424
Short name T749
Test name
Test status
Simulation time 72286321322 ps
CPU time 119.92 seconds
Started Jun 27 04:54:56 PM PDT 24
Finished Jun 27 04:56:58 PM PDT 24
Peak memory 199584 kb
Host smart-039f15ba-bc45-4a02-aaf7-b4689cec57ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540746424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.540746424
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1994372049
Short name T300
Test name
Test status
Simulation time 3950678923 ps
CPU time 2.14 seconds
Started Jun 27 04:54:57 PM PDT 24
Finished Jun 27 04:55:00 PM PDT 24
Peak memory 196048 kb
Host smart-e564d6c8-1f6a-4bd5-979a-892ab8752385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994372049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1994372049
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.2546627852
Short name T350
Test name
Test status
Simulation time 88966009 ps
CPU time 0.86 seconds
Started Jun 27 04:55:06 PM PDT 24
Finished Jun 27 04:55:10 PM PDT 24
Peak memory 196896 kb
Host smart-61b0917c-ad89-4a43-8c95-268ad82b5388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546627852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2546627852
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.622722503
Short name T225
Test name
Test status
Simulation time 66013270321 ps
CPU time 122.85 seconds
Started Jun 27 04:54:54 PM PDT 24
Finished Jun 27 04:56:59 PM PDT 24
Peak memory 199936 kb
Host smart-792be64f-749a-47ed-87b8-7e7ee1ace5f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622722503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.622722503
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.3363256550
Short name T439
Test name
Test status
Simulation time 55083997299 ps
CPU time 220.8 seconds
Started Jun 27 04:54:49 PM PDT 24
Finished Jun 27 04:58:33 PM PDT 24
Peak memory 216416 kb
Host smart-f4c3e2f4-c0b7-4417-ac28-addcae31a7f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363256550 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.3363256550
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.1604510366
Short name T476
Test name
Test status
Simulation time 1270948432 ps
CPU time 1.83 seconds
Started Jun 27 04:54:49 PM PDT 24
Finished Jun 27 04:54:54 PM PDT 24
Peak memory 199832 kb
Host smart-4e55676b-99ac-4420-b869-315cba9ff828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604510366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1604510366
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.3133826146
Short name T1008
Test name
Test status
Simulation time 83348542563 ps
CPU time 29.43 seconds
Started Jun 27 04:54:49 PM PDT 24
Finished Jun 27 04:55:21 PM PDT 24
Peak memory 199904 kb
Host smart-e528e240-e1c5-45d0-847f-80580d3e9750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133826146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3133826146
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.3760454454
Short name T59
Test name
Test status
Simulation time 32841501904 ps
CPU time 66.32 seconds
Started Jun 27 04:57:32 PM PDT 24
Finished Jun 27 04:58:40 PM PDT 24
Peak memory 199992 kb
Host smart-4a263dee-4769-4c5d-b3cb-638832772bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760454454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3760454454
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.2538717111
Short name T494
Test name
Test status
Simulation time 33331577377 ps
CPU time 24.87 seconds
Started Jun 27 04:57:32 PM PDT 24
Finished Jun 27 04:58:00 PM PDT 24
Peak memory 199928 kb
Host smart-04b68036-4bc7-4f82-a945-013fb885ae0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538717111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2538717111
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.4147618797
Short name T142
Test name
Test status
Simulation time 179473326428 ps
CPU time 166.61 seconds
Started Jun 27 04:57:32 PM PDT 24
Finished Jun 27 05:00:21 PM PDT 24
Peak memory 199924 kb
Host smart-4a2d554b-900d-4989-a5f6-cab8f2cffb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147618797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.4147618797
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.1633061057
Short name T399
Test name
Test status
Simulation time 25185951903 ps
CPU time 33.53 seconds
Started Jun 27 04:57:24 PM PDT 24
Finished Jun 27 04:57:58 PM PDT 24
Peak memory 199852 kb
Host smart-a7a67d53-e671-4bdf-b8d8-8fea5e8d9e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633061057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.1633061057
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2973612541
Short name T230
Test name
Test status
Simulation time 63347488556 ps
CPU time 27.23 seconds
Started Jun 27 04:57:30 PM PDT 24
Finished Jun 27 04:57:58 PM PDT 24
Peak memory 199924 kb
Host smart-4a75f900-ef37-4ccd-a3fd-d9043ee8489e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973612541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2973612541
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.3728973371
Short name T746
Test name
Test status
Simulation time 129459449338 ps
CPU time 51.47 seconds
Started Jun 27 04:57:53 PM PDT 24
Finished Jun 27 04:58:46 PM PDT 24
Peak memory 199900 kb
Host smart-0a9cf087-942c-4c0a-bca4-320e715dea10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728973371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.3728973371
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.3019807880
Short name T867
Test name
Test status
Simulation time 11876977451 ps
CPU time 19.47 seconds
Started Jun 27 04:57:53 PM PDT 24
Finished Jun 27 04:58:14 PM PDT 24
Peak memory 199980 kb
Host smart-5b648ec0-f977-4fa7-bc13-e5ab6e351ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019807880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3019807880
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2871912623
Short name T565
Test name
Test status
Simulation time 130152491873 ps
CPU time 118 seconds
Started Jun 27 04:57:56 PM PDT 24
Finished Jun 27 04:59:57 PM PDT 24
Peak memory 199876 kb
Host smart-9bcd02b7-f9bb-4fc6-9754-30cbf056dd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871912623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2871912623
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.159208903
Short name T113
Test name
Test status
Simulation time 39628578691 ps
CPU time 62.34 seconds
Started Jun 27 04:57:56 PM PDT 24
Finished Jun 27 04:59:01 PM PDT 24
Peak memory 199928 kb
Host smart-1fec724b-c012-437c-add4-a4946e318448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159208903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.159208903
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.2267107101
Short name T348
Test name
Test status
Simulation time 12044911 ps
CPU time 0.6 seconds
Started Jun 27 04:55:08 PM PDT 24
Finished Jun 27 04:55:13 PM PDT 24
Peak memory 195524 kb
Host smart-3cd7eb52-02b7-4337-87f1-6d82f674868e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267107101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2267107101
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2504220378
Short name T699
Test name
Test status
Simulation time 87259174785 ps
CPU time 392.61 seconds
Started Jun 27 04:54:54 PM PDT 24
Finished Jun 27 05:01:29 PM PDT 24
Peak memory 199388 kb
Host smart-8f21ffc2-9bcd-4942-8a1a-75ee8e0fdb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504220378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2504220378
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.3894431381
Short name T97
Test name
Test status
Simulation time 37341000969 ps
CPU time 21.89 seconds
Started Jun 27 04:55:00 PM PDT 24
Finished Jun 27 04:55:23 PM PDT 24
Peak memory 199732 kb
Host smart-cd04b965-fea3-4248-a303-bd9ad81f6b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894431381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3894431381
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.156045219
Short name T770
Test name
Test status
Simulation time 3839698600 ps
CPU time 15.06 seconds
Started Jun 27 04:55:00 PM PDT 24
Finished Jun 27 04:55:16 PM PDT 24
Peak memory 199816 kb
Host smart-f059d524-86d1-48ef-80fa-94492f4ea871
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156045219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.156045219
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.3000324869
Short name T764
Test name
Test status
Simulation time 89925400302 ps
CPU time 180.61 seconds
Started Jun 27 04:55:06 PM PDT 24
Finished Jun 27 04:58:10 PM PDT 24
Peak memory 200176 kb
Host smart-1c9d3094-def5-4a1f-a41b-993b7e0269aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3000324869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.3000324869
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.1453752819
Short name T732
Test name
Test status
Simulation time 2446818993 ps
CPU time 1.76 seconds
Started Jun 27 04:54:53 PM PDT 24
Finished Jun 27 04:54:57 PM PDT 24
Peak memory 197076 kb
Host smart-be9d6fcb-3d0e-4427-a859-2aa58eb8f7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453752819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1453752819
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_perf.2432029999
Short name T939
Test name
Test status
Simulation time 8889431284 ps
CPU time 483.71 seconds
Started Jun 27 04:55:06 PM PDT 24
Finished Jun 27 05:03:13 PM PDT 24
Peak memory 199824 kb
Host smart-d72f855b-a643-498b-92c0-9abb37274d9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2432029999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2432029999
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.3684949540
Short name T853
Test name
Test status
Simulation time 6883619231 ps
CPU time 63.69 seconds
Started Jun 27 04:55:00 PM PDT 24
Finished Jun 27 04:56:05 PM PDT 24
Peak memory 198072 kb
Host smart-e427a85b-f815-4f5c-8b0d-8af0a33f6e43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3684949540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.3684949540
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1924210139
Short name T466
Test name
Test status
Simulation time 19494677479 ps
CPU time 33.97 seconds
Started Jun 27 04:54:52 PM PDT 24
Finished Jun 27 04:55:28 PM PDT 24
Peak memory 199892 kb
Host smart-3d8144a5-c3e4-43d4-b925-20b3c30fb58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924210139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1924210139
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.1780275104
Short name T581
Test name
Test status
Simulation time 2428314531 ps
CPU time 1.49 seconds
Started Jun 27 04:55:02 PM PDT 24
Finished Jun 27 04:55:05 PM PDT 24
Peak memory 196288 kb
Host smart-b0590aca-39ba-4698-956d-fd755fb7fa12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780275104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.1780275104
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.780420733
Short name T937
Test name
Test status
Simulation time 6252476722 ps
CPU time 10.38 seconds
Started Jun 27 04:55:09 PM PDT 24
Finished Jun 27 04:55:24 PM PDT 24
Peak memory 199912 kb
Host smart-ccb1b6ec-9407-499f-b9ec-d666bdfe79db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780420733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.780420733
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.900956687
Short name T898
Test name
Test status
Simulation time 32990534426 ps
CPU time 307.56 seconds
Started Jun 27 04:55:10 PM PDT 24
Finished Jun 27 05:00:22 PM PDT 24
Peak memory 199900 kb
Host smart-d2faa3f6-72c2-4abc-a6d6-b46d54538d7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900956687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.900956687
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.3239907797
Short name T1065
Test name
Test status
Simulation time 54091169396 ps
CPU time 825.61 seconds
Started Jun 27 04:55:03 PM PDT 24
Finished Jun 27 05:08:51 PM PDT 24
Peak memory 216496 kb
Host smart-7d0a3ba9-ba4c-46d7-8779-5f6d330ac0bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239907797 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.3239907797
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.3810850392
Short name T1036
Test name
Test status
Simulation time 1080282823 ps
CPU time 3.51 seconds
Started Jun 27 04:55:06 PM PDT 24
Finished Jun 27 04:55:12 PM PDT 24
Peak memory 198864 kb
Host smart-5e52a62c-b476-479b-8816-d830b6e32efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810850392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3810850392
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.4067080385
Short name T1040
Test name
Test status
Simulation time 24900921509 ps
CPU time 12.01 seconds
Started Jun 27 04:55:06 PM PDT 24
Finished Jun 27 04:55:21 PM PDT 24
Peak memory 199924 kb
Host smart-b5e3b844-014f-4495-bac3-1896cdbc53e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067080385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.4067080385
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.4189765689
Short name T930
Test name
Test status
Simulation time 98261251027 ps
CPU time 72.31 seconds
Started Jun 27 04:57:57 PM PDT 24
Finished Jun 27 04:59:12 PM PDT 24
Peak memory 199904 kb
Host smart-36a2080f-3d31-4f7b-99c5-65be649c99a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189765689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.4189765689
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.509844447
Short name T315
Test name
Test status
Simulation time 121121812680 ps
CPU time 80 seconds
Started Jun 27 04:57:54 PM PDT 24
Finished Jun 27 04:59:16 PM PDT 24
Peak memory 199872 kb
Host smart-816eeae0-7dab-4ec4-b477-9b904db18c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509844447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.509844447
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.3331488824
Short name T757
Test name
Test status
Simulation time 136375141751 ps
CPU time 46.26 seconds
Started Jun 27 04:57:55 PM PDT 24
Finished Jun 27 04:58:44 PM PDT 24
Peak memory 200168 kb
Host smart-ddd7f5b2-c3f9-4dcb-ad8f-7cf3ef33f6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331488824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3331488824
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.3386579162
Short name T871
Test name
Test status
Simulation time 22503357027 ps
CPU time 17.66 seconds
Started Jun 27 04:57:56 PM PDT 24
Finished Jun 27 04:58:17 PM PDT 24
Peak memory 199956 kb
Host smart-0c6d1492-c23b-421e-8ca0-afec09d59b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386579162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.3386579162
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.3864276854
Short name T980
Test name
Test status
Simulation time 42231521895 ps
CPU time 33.41 seconds
Started Jun 27 04:57:55 PM PDT 24
Finished Jun 27 04:58:30 PM PDT 24
Peak memory 199904 kb
Host smart-a05f4ef3-d08a-4aaf-8774-a03d903cd7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864276854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.3864276854
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1797064658
Short name T195
Test name
Test status
Simulation time 21153325066 ps
CPU time 9.86 seconds
Started Jun 27 04:57:54 PM PDT 24
Finished Jun 27 04:58:06 PM PDT 24
Peak memory 199820 kb
Host smart-cf6d2e3f-9684-4cbc-a16a-a80274c08885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797064658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1797064658
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.4168891494
Short name T570
Test name
Test status
Simulation time 125278513719 ps
CPU time 183.48 seconds
Started Jun 27 04:57:58 PM PDT 24
Finished Jun 27 05:01:04 PM PDT 24
Peak memory 199868 kb
Host smart-61ec12c5-33e6-4f4e-91cb-d48df9317f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168891494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.4168891494
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.98701443
Short name T663
Test name
Test status
Simulation time 31204172582 ps
CPU time 21.77 seconds
Started Jun 27 04:57:55 PM PDT 24
Finished Jun 27 04:58:19 PM PDT 24
Peak memory 199820 kb
Host smart-198494da-49ad-409e-b886-c1e981d79a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98701443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.98701443
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.2580137310
Short name T656
Test name
Test status
Simulation time 21619315 ps
CPU time 0.55 seconds
Started Jun 27 04:55:16 PM PDT 24
Finished Jun 27 04:55:17 PM PDT 24
Peak memory 195156 kb
Host smart-53feeb1e-c0bf-466e-86c2-2dfe4f14be48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580137310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.2580137310
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1680168012
Short name T126
Test name
Test status
Simulation time 47564306736 ps
CPU time 33.77 seconds
Started Jun 27 04:55:07 PM PDT 24
Finished Jun 27 04:55:45 PM PDT 24
Peak memory 199828 kb
Host smart-49ff61c4-e402-4a46-84e8-2a018638a28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680168012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1680168012
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1061177615
Short name T327
Test name
Test status
Simulation time 128852617548 ps
CPU time 203.95 seconds
Started Jun 27 04:55:04 PM PDT 24
Finished Jun 27 04:58:30 PM PDT 24
Peak memory 199892 kb
Host smart-8eeabfe0-34cb-47e9-8ec6-242544779d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061177615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1061177615
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3035342962
Short name T863
Test name
Test status
Simulation time 242668033694 ps
CPU time 31.65 seconds
Started Jun 27 04:55:16 PM PDT 24
Finished Jun 27 04:55:49 PM PDT 24
Peak memory 199776 kb
Host smart-c7aed533-207a-46d7-885e-cf7ad095b63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035342962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3035342962
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.3283088696
Short name T1000
Test name
Test status
Simulation time 267940566297 ps
CPU time 117.62 seconds
Started Jun 27 04:55:09 PM PDT 24
Finished Jun 27 04:57:11 PM PDT 24
Peak memory 200140 kb
Host smart-81187c68-1ca3-454f-b178-59288eef0769
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283088696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3283088696
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.3083364471
Short name T598
Test name
Test status
Simulation time 152167681534 ps
CPU time 350 seconds
Started Jun 27 04:55:08 PM PDT 24
Finished Jun 27 05:01:02 PM PDT 24
Peak memory 199864 kb
Host smart-80930276-6738-4d5e-9520-bfa850140bbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3083364471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.3083364471
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.3357778888
Short name T906
Test name
Test status
Simulation time 8920591504 ps
CPU time 22.68 seconds
Started Jun 27 04:55:08 PM PDT 24
Finished Jun 27 04:55:35 PM PDT 24
Peak memory 199464 kb
Host smart-cbbb72a0-ffb2-4e4b-86e3-36c7deb6234a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357778888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3357778888
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.2219642881
Short name T367
Test name
Test status
Simulation time 26744755819 ps
CPU time 22.01 seconds
Started Jun 27 04:55:06 PM PDT 24
Finished Jun 27 04:55:32 PM PDT 24
Peak memory 199780 kb
Host smart-03550f6e-8082-4221-93ff-e08335322fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219642881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.2219642881
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.1178270006
Short name T655
Test name
Test status
Simulation time 1498620513 ps
CPU time 73.87 seconds
Started Jun 27 04:55:05 PM PDT 24
Finished Jun 27 04:56:22 PM PDT 24
Peak memory 199776 kb
Host smart-f6ed71c6-f2ad-4f92-8627-466a09014833
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1178270006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.1178270006
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.2025941529
Short name T845
Test name
Test status
Simulation time 1926912878 ps
CPU time 3.1 seconds
Started Jun 27 04:55:07 PM PDT 24
Finished Jun 27 04:55:13 PM PDT 24
Peak memory 199060 kb
Host smart-49133ea2-0387-4bc4-9db3-c9478ae8b4c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2025941529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.2025941529
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.2865739965
Short name T413
Test name
Test status
Simulation time 31397345457 ps
CPU time 11.8 seconds
Started Jun 27 04:55:10 PM PDT 24
Finished Jun 27 04:55:26 PM PDT 24
Peak memory 195804 kb
Host smart-d088a0c9-f8b7-4c35-91d8-40c1a9be2b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865739965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.2865739965
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.484575371
Short name T569
Test name
Test status
Simulation time 495351350 ps
CPU time 2.11 seconds
Started Jun 27 04:55:21 PM PDT 24
Finished Jun 27 04:55:24 PM PDT 24
Peak memory 198748 kb
Host smart-9cadcd8f-426b-4b9d-b81f-87bcf047de02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484575371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.484575371
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.2493174168
Short name T320
Test name
Test status
Simulation time 28186338729 ps
CPU time 264.29 seconds
Started Jun 27 04:55:09 PM PDT 24
Finished Jun 27 04:59:38 PM PDT 24
Peak memory 208344 kb
Host smart-c4657f19-c554-4dd5-a639-9e8eaef3cf2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493174168 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.2493174168
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.4006975807
Short name T424
Test name
Test status
Simulation time 7212007062 ps
CPU time 13.46 seconds
Started Jun 27 04:55:09 PM PDT 24
Finished Jun 27 04:55:27 PM PDT 24
Peak memory 199828 kb
Host smart-4e74c674-c29b-47d4-8435-49ee32a91aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006975807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.4006975807
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2896083709
Short name T579
Test name
Test status
Simulation time 54095398077 ps
CPU time 32.52 seconds
Started Jun 27 04:55:10 PM PDT 24
Finished Jun 27 04:55:47 PM PDT 24
Peak memory 199976 kb
Host smart-5b874133-a623-4908-ad58-5b5447ea4207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896083709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2896083709
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.1001833999
Short name T841
Test name
Test status
Simulation time 16296358281 ps
CPU time 17.32 seconds
Started Jun 27 04:57:56 PM PDT 24
Finished Jun 27 04:58:15 PM PDT 24
Peak memory 199692 kb
Host smart-c455e87f-ef9b-4839-a90e-70e1ded5ebac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001833999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1001833999
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.399740903
Short name T606
Test name
Test status
Simulation time 108723346000 ps
CPU time 27.09 seconds
Started Jun 27 04:57:54 PM PDT 24
Finished Jun 27 04:58:23 PM PDT 24
Peak memory 199908 kb
Host smart-1228130f-bb96-410c-8411-9f9a37769b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399740903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.399740903
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.2900117173
Short name T152
Test name
Test status
Simulation time 91459841126 ps
CPU time 30.82 seconds
Started Jun 27 04:57:57 PM PDT 24
Finished Jun 27 04:58:30 PM PDT 24
Peak memory 199820 kb
Host smart-644a695b-fd47-4422-828c-755fe6704b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900117173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2900117173
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.1628935457
Short name T882
Test name
Test status
Simulation time 169458255865 ps
CPU time 43.83 seconds
Started Jun 27 04:57:54 PM PDT 24
Finished Jun 27 04:58:39 PM PDT 24
Peak memory 200032 kb
Host smart-c668eb7c-cd52-453e-899e-b5590106bd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628935457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.1628935457
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.4215027238
Short name T657
Test name
Test status
Simulation time 59142977478 ps
CPU time 39.85 seconds
Started Jun 27 04:57:57 PM PDT 24
Finished Jun 27 04:58:40 PM PDT 24
Peak memory 199912 kb
Host smart-c2ebd3b6-06fd-44a6-9554-88af26df7288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215027238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.4215027238
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.1160098787
Short name T255
Test name
Test status
Simulation time 51651841804 ps
CPU time 23.27 seconds
Started Jun 27 04:57:56 PM PDT 24
Finished Jun 27 04:58:22 PM PDT 24
Peak memory 199804 kb
Host smart-10eb727b-b747-4808-ad2c-0bccf9d2a77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160098787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.1160098787
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.2480363563
Short name T714
Test name
Test status
Simulation time 64991410781 ps
CPU time 90.22 seconds
Started Jun 27 04:57:55 PM PDT 24
Finished Jun 27 04:59:27 PM PDT 24
Peak memory 199984 kb
Host smart-d7be885a-dcad-45a0-b1b5-a084390e3c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480363563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2480363563
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.1032608016
Short name T170
Test name
Test status
Simulation time 66266933800 ps
CPU time 28.52 seconds
Started Jun 27 04:57:54 PM PDT 24
Finished Jun 27 04:58:23 PM PDT 24
Peak memory 199888 kb
Host smart-6fa29d83-c5c0-4819-b239-6a5efa821583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032608016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.1032608016
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2742996217
Short name T550
Test name
Test status
Simulation time 43479835899 ps
CPU time 154.78 seconds
Started Jun 27 04:57:58 PM PDT 24
Finished Jun 27 05:00:36 PM PDT 24
Peak memory 199876 kb
Host smart-e094788d-d603-4788-a359-1d21daa41c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742996217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2742996217
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.1873681424
Short name T632
Test name
Test status
Simulation time 11717726 ps
CPU time 0.56 seconds
Started Jun 27 04:55:10 PM PDT 24
Finished Jun 27 04:55:14 PM PDT 24
Peak memory 195548 kb
Host smart-9618f3b5-e932-4983-86a2-aa78b356418f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873681424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.1873681424
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.4251126624
Short name T294
Test name
Test status
Simulation time 113815776647 ps
CPU time 325.96 seconds
Started Jun 27 04:55:09 PM PDT 24
Finished Jun 27 05:00:39 PM PDT 24
Peak memory 199912 kb
Host smart-8d765057-194d-47f8-9fd8-8bd5e701c125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251126624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.4251126624
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.3664320075
Short name T156
Test name
Test status
Simulation time 65835345299 ps
CPU time 17.75 seconds
Started Jun 27 04:55:10 PM PDT 24
Finished Jun 27 04:55:32 PM PDT 24
Peak memory 200012 kb
Host smart-f8998822-bb6c-45bb-a7ff-83d03663416f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664320075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.3664320075
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.2045618006
Short name T406
Test name
Test status
Simulation time 41842086017 ps
CPU time 32.99 seconds
Started Jun 27 04:55:22 PM PDT 24
Finished Jun 27 04:55:57 PM PDT 24
Peak memory 199024 kb
Host smart-e19de931-8bfd-4f33-914a-1d16f3680c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045618006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.2045618006
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.150772109
Short name T475
Test name
Test status
Simulation time 37103026398 ps
CPU time 48.57 seconds
Started Jun 27 04:55:09 PM PDT 24
Finished Jun 27 04:56:01 PM PDT 24
Peak memory 199716 kb
Host smart-725e7c5e-45a3-4bef-ad7c-9c708cb9d5ab
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150772109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.150772109
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.991353006
Short name T481
Test name
Test status
Simulation time 98637950389 ps
CPU time 430.72 seconds
Started Jun 27 04:55:10 PM PDT 24
Finished Jun 27 05:02:25 PM PDT 24
Peak memory 199868 kb
Host smart-7b3d33f6-77f0-42bd-8642-42a6c4d16f3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=991353006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.991353006
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.125571782
Short name T24
Test name
Test status
Simulation time 3162831297 ps
CPU time 4.02 seconds
Started Jun 27 04:55:04 PM PDT 24
Finished Jun 27 04:55:10 PM PDT 24
Peak memory 198700 kb
Host smart-b6f1ce26-e3f6-4589-94df-ca4eef74ad48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125571782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.125571782
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_perf.1247425515
Short name T715
Test name
Test status
Simulation time 24552152515 ps
CPU time 1246.69 seconds
Started Jun 27 04:55:09 PM PDT 24
Finished Jun 27 05:16:00 PM PDT 24
Peak memory 199960 kb
Host smart-32e0a1e0-7bb0-4fcf-b0a4-f327e10fcb7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1247425515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1247425515
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.4000144068
Short name T360
Test name
Test status
Simulation time 4348437955 ps
CPU time 9.32 seconds
Started Jun 27 04:55:22 PM PDT 24
Finished Jun 27 04:55:33 PM PDT 24
Peak memory 198780 kb
Host smart-61f07188-b3d8-4652-a674-3a4e1f6871b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4000144068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.4000144068
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.131586083
Short name T260
Test name
Test status
Simulation time 19899072467 ps
CPU time 25.87 seconds
Started Jun 27 04:55:05 PM PDT 24
Finished Jun 27 04:55:33 PM PDT 24
Peak memory 199900 kb
Host smart-49765769-745e-414b-9822-7e3f8f0f18fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131586083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.131586083
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.2956558360
Short name T26
Test name
Test status
Simulation time 40249654282 ps
CPU time 14.96 seconds
Started Jun 27 04:55:15 PM PDT 24
Finished Jun 27 04:55:31 PM PDT 24
Peak memory 196724 kb
Host smart-75e3ea2f-3749-4db3-aa55-cccc7f1d9011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956558360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.2956558360
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.3795591460
Short name T755
Test name
Test status
Simulation time 266240650 ps
CPU time 1.88 seconds
Started Jun 27 04:55:05 PM PDT 24
Finished Jun 27 04:55:10 PM PDT 24
Peak memory 198512 kb
Host smart-e8c6a9f9-817d-4567-96b6-322a61e2b17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795591460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.3795591460
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.3258288656
Short name T945
Test name
Test status
Simulation time 96731759480 ps
CPU time 79.61 seconds
Started Jun 27 04:55:10 PM PDT 24
Finished Jun 27 04:56:34 PM PDT 24
Peak memory 199900 kb
Host smart-caa9c022-82b2-4938-8da0-b6b140f9e1f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258288656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3258288656
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.1023083335
Short name T322
Test name
Test status
Simulation time 183624032476 ps
CPU time 664.59 seconds
Started Jun 27 04:55:16 PM PDT 24
Finished Jun 27 05:06:21 PM PDT 24
Peak memory 216368 kb
Host smart-14fc58ab-ae06-43c6-8b0d-8d9e4cd975c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023083335 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.1023083335
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.3453024988
Short name T1076
Test name
Test status
Simulation time 1295585470 ps
CPU time 2.9 seconds
Started Jun 27 04:55:04 PM PDT 24
Finished Jun 27 04:55:09 PM PDT 24
Peak memory 198620 kb
Host smart-07110e7f-1540-47f3-b2a1-9609e44433d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453024988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.3453024988
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.167621671
Short name T917
Test name
Test status
Simulation time 103241192026 ps
CPU time 55.82 seconds
Started Jun 27 04:55:08 PM PDT 24
Finished Jun 27 04:56:08 PM PDT 24
Peak memory 199992 kb
Host smart-9bbe38a7-9e82-425f-b877-97d591bee5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167621671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.167621671
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.311661217
Short name T441
Test name
Test status
Simulation time 33364508519 ps
CPU time 14.56 seconds
Started Jun 27 04:57:55 PM PDT 24
Finished Jun 27 04:58:11 PM PDT 24
Peak memory 200108 kb
Host smart-1e927b48-ee76-4809-a55e-4e8d26f872be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311661217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.311661217
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.873391036
Short name T518
Test name
Test status
Simulation time 254874702940 ps
CPU time 114.91 seconds
Started Jun 27 04:57:58 PM PDT 24
Finished Jun 27 04:59:56 PM PDT 24
Peak memory 199908 kb
Host smart-cb865eef-d4ad-497e-a351-1b6cfd28146a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873391036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.873391036
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.1402265345
Short name T136
Test name
Test status
Simulation time 49559311541 ps
CPU time 22.88 seconds
Started Jun 27 04:57:57 PM PDT 24
Finished Jun 27 04:58:24 PM PDT 24
Peak memory 199916 kb
Host smart-007a0d53-3d69-4833-9c15-7d5865c86acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402265345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1402265345
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.67960641
Short name T959
Test name
Test status
Simulation time 14420752441 ps
CPU time 21.73 seconds
Started Jun 27 04:57:56 PM PDT 24
Finished Jun 27 04:58:20 PM PDT 24
Peak memory 199984 kb
Host smart-9da21c3e-38a2-4b55-8170-11f1b637547a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67960641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.67960641
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.3852730968
Short name T184
Test name
Test status
Simulation time 112339759338 ps
CPU time 179.65 seconds
Started Jun 27 04:57:56 PM PDT 24
Finished Jun 27 05:00:58 PM PDT 24
Peak memory 200128 kb
Host smart-f32a54a3-de52-4578-95ea-25cb75a39658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852730968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.3852730968
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.98981809
Short name T988
Test name
Test status
Simulation time 7827300279 ps
CPU time 11.36 seconds
Started Jun 27 04:57:56 PM PDT 24
Finished Jun 27 04:58:09 PM PDT 24
Peak memory 199960 kb
Host smart-76ebc232-676c-436d-bba2-015462274f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98981809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.98981809
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.2207013528
Short name T1070
Test name
Test status
Simulation time 74598220160 ps
CPU time 34.43 seconds
Started Jun 27 04:57:56 PM PDT 24
Finished Jun 27 04:58:32 PM PDT 24
Peak memory 199928 kb
Host smart-22ab189e-0fd6-479c-bc34-faac38c9d795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207013528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2207013528
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.3483418121
Short name T239
Test name
Test status
Simulation time 32900917292 ps
CPU time 24.93 seconds
Started Jun 27 04:58:00 PM PDT 24
Finished Jun 27 04:58:28 PM PDT 24
Peak memory 199984 kb
Host smart-15656bd5-ed9e-4c9b-8093-e8bfc78d34f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483418121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3483418121
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.1061640837
Short name T806
Test name
Test status
Simulation time 96195615774 ps
CPU time 319.42 seconds
Started Jun 27 04:57:55 PM PDT 24
Finished Jun 27 05:03:17 PM PDT 24
Peak memory 199928 kb
Host smart-7366105b-9206-444e-9a48-a05fd96befc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061640837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1061640837
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3093337836
Short name T564
Test name
Test status
Simulation time 38301451 ps
CPU time 0.53 seconds
Started Jun 27 04:55:21 PM PDT 24
Finished Jun 27 04:55:23 PM PDT 24
Peak memory 195140 kb
Host smart-4630ccd1-dc11-4101-aeb1-734b263b15a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093337836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3093337836
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.849132593
Short name T721
Test name
Test status
Simulation time 46479771755 ps
CPU time 13.8 seconds
Started Jun 27 04:55:11 PM PDT 24
Finished Jun 27 04:55:28 PM PDT 24
Peak memory 199932 kb
Host smart-00dcfc3e-c02f-469e-9da1-6b4c6f168ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849132593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.849132593
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.2735013037
Short name T760
Test name
Test status
Simulation time 37193183765 ps
CPU time 29.2 seconds
Started Jun 27 04:55:08 PM PDT 24
Finished Jun 27 04:55:41 PM PDT 24
Peak memory 199928 kb
Host smart-867720cc-a797-4217-b99a-c43bc78c736c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735013037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2735013037
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.3187738768
Short name T1072
Test name
Test status
Simulation time 160711540854 ps
CPU time 34.6 seconds
Started Jun 27 04:55:08 PM PDT 24
Finished Jun 27 04:55:47 PM PDT 24
Peak memory 199740 kb
Host smart-c445bb59-8058-47e6-9d41-bdb1f916ae1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187738768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.3187738768
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.2450104710
Short name T389
Test name
Test status
Simulation time 12985110764 ps
CPU time 19.68 seconds
Started Jun 27 04:55:11 PM PDT 24
Finished Jun 27 04:55:34 PM PDT 24
Peak memory 196824 kb
Host smart-4c38da4c-bbf6-4551-bb70-b130ef10d503
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450104710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.2450104710
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2613438495
Short name T460
Test name
Test status
Simulation time 40438652537 ps
CPU time 60.06 seconds
Started Jun 27 04:55:05 PM PDT 24
Finished Jun 27 04:56:08 PM PDT 24
Peak memory 199872 kb
Host smart-125e6e9a-68e4-432f-9dc4-7e86d9f44dd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2613438495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2613438495
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.416599466
Short name T472
Test name
Test status
Simulation time 1080358407 ps
CPU time 1.05 seconds
Started Jun 27 04:55:07 PM PDT 24
Finished Jun 27 04:55:12 PM PDT 24
Peak memory 195892 kb
Host smart-af3a15a6-7b6a-43e5-8b45-37ca2af1ce38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416599466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.416599466
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_perf.281133898
Short name T508
Test name
Test status
Simulation time 8093540185 ps
CPU time 425.69 seconds
Started Jun 27 04:55:07 PM PDT 24
Finished Jun 27 05:02:17 PM PDT 24
Peak memory 199888 kb
Host smart-c1b9ddb2-dfd3-48a0-b50d-e8074be0d356
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=281133898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.281133898
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.837012181
Short name T922
Test name
Test status
Simulation time 6617603274 ps
CPU time 9.99 seconds
Started Jun 27 04:55:08 PM PDT 24
Finished Jun 27 04:55:22 PM PDT 24
Peak memory 199204 kb
Host smart-c4325553-5975-47f2-8582-c8c14c82086e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=837012181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.837012181
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.4211499768
Short name T25
Test name
Test status
Simulation time 38979521224 ps
CPU time 31.96 seconds
Started Jun 27 04:55:11 PM PDT 24
Finished Jun 27 04:55:47 PM PDT 24
Peak memory 199688 kb
Host smart-af461f98-c323-4d1b-bdca-189e16ab54e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211499768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.4211499768
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.2176682385
Short name T779
Test name
Test status
Simulation time 45600927873 ps
CPU time 37.52 seconds
Started Jun 27 04:55:06 PM PDT 24
Finished Jun 27 04:55:47 PM PDT 24
Peak memory 195764 kb
Host smart-12af8f34-b018-4306-b678-d42897955a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176682385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2176682385
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.1520928735
Short name T738
Test name
Test status
Simulation time 661518156 ps
CPU time 1.81 seconds
Started Jun 27 04:55:04 PM PDT 24
Finished Jun 27 04:55:07 PM PDT 24
Peak memory 198772 kb
Host smart-4d712390-2d27-4dea-92e0-c130334d60a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520928735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.1520928735
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.4179078243
Short name T492
Test name
Test status
Simulation time 294919373084 ps
CPU time 644.43 seconds
Started Jun 27 04:55:16 PM PDT 24
Finished Jun 27 05:06:01 PM PDT 24
Peak memory 199776 kb
Host smart-72d0b241-5525-4cef-9c8f-7ea713fd0789
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179078243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.4179078243
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1719740627
Short name T560
Test name
Test status
Simulation time 6115194695 ps
CPU time 15.18 seconds
Started Jun 27 04:55:10 PM PDT 24
Finished Jun 27 04:55:29 PM PDT 24
Peak memory 199820 kb
Host smart-b139e2fd-c887-4473-9332-61fe46bcc86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719740627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1719740627
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.1605070542
Short name T800
Test name
Test status
Simulation time 83284903992 ps
CPU time 119.74 seconds
Started Jun 27 04:55:09 PM PDT 24
Finished Jun 27 04:57:13 PM PDT 24
Peak memory 199876 kb
Host smart-e28c4e16-293f-4f5f-884d-bdfdf1847b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605070542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1605070542
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.4210257225
Short name T182
Test name
Test status
Simulation time 101414775272 ps
CPU time 42.5 seconds
Started Jun 27 04:57:57 PM PDT 24
Finished Jun 27 04:58:43 PM PDT 24
Peak memory 199852 kb
Host smart-d11a6059-de9e-4f16-abae-5d3ee8761a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210257225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.4210257225
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.194298660
Short name T325
Test name
Test status
Simulation time 38120657501 ps
CPU time 15.76 seconds
Started Jun 27 04:58:00 PM PDT 24
Finished Jun 27 04:58:18 PM PDT 24
Peak memory 199912 kb
Host smart-5d894531-27ee-4d0f-90cc-fcc7cb0047ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194298660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.194298660
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.2537960956
Short name T925
Test name
Test status
Simulation time 17861050897 ps
CPU time 29.14 seconds
Started Jun 27 04:57:57 PM PDT 24
Finished Jun 27 04:58:29 PM PDT 24
Peak memory 199912 kb
Host smart-df672910-f301-4b58-af46-bade792576a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537960956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2537960956
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.644109406
Short name T39
Test name
Test status
Simulation time 146810681690 ps
CPU time 29.7 seconds
Started Jun 27 04:57:55 PM PDT 24
Finished Jun 27 04:58:27 PM PDT 24
Peak memory 199932 kb
Host smart-91b014b9-6996-445b-8531-92580f51d43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644109406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.644109406
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2248458574
Short name T199
Test name
Test status
Simulation time 21515339918 ps
CPU time 38.99 seconds
Started Jun 27 04:57:57 PM PDT 24
Finished Jun 27 04:58:39 PM PDT 24
Peak memory 199912 kb
Host smart-aa63bd3e-8a11-42b2-863f-a71a17ff5b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248458574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2248458574
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.1491720706
Short name T217
Test name
Test status
Simulation time 90661331568 ps
CPU time 78.91 seconds
Started Jun 27 04:57:57 PM PDT 24
Finished Jun 27 04:59:19 PM PDT 24
Peak memory 199896 kb
Host smart-8fe5d7a0-9c03-4707-baf0-8319b021c8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491720706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1491720706
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.982656392
Short name T747
Test name
Test status
Simulation time 167180940816 ps
CPU time 19.93 seconds
Started Jun 27 04:57:58 PM PDT 24
Finished Jun 27 04:58:21 PM PDT 24
Peak memory 199880 kb
Host smart-ac049101-cad0-49dd-8505-0ea562fda179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982656392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.982656392
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1843189129
Short name T667
Test name
Test status
Simulation time 146924774693 ps
CPU time 129.75 seconds
Started Jun 27 04:58:01 PM PDT 24
Finished Jun 27 05:00:13 PM PDT 24
Peak memory 199888 kb
Host smart-a1dcf5e8-7605-4926-8611-0da383b3892b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843189129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1843189129
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.3549485170
Short name T333
Test name
Test status
Simulation time 56698818376 ps
CPU time 83.1 seconds
Started Jun 27 04:57:57 PM PDT 24
Finished Jun 27 04:59:23 PM PDT 24
Peak memory 199844 kb
Host smart-4972b215-50cb-44fe-ace7-40f4d4b093b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549485170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3549485170
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3991424606
Short name T435
Test name
Test status
Simulation time 29339926386 ps
CPU time 49.26 seconds
Started Jun 27 04:55:09 PM PDT 24
Finished Jun 27 04:56:02 PM PDT 24
Peak memory 199816 kb
Host smart-94b36883-4231-44bc-99eb-8b7730e1fb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991424606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3991424606
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.2046092729
Short name T143
Test name
Test status
Simulation time 177743089564 ps
CPU time 29.83 seconds
Started Jun 27 04:55:22 PM PDT 24
Finished Jun 27 04:55:53 PM PDT 24
Peak memory 199332 kb
Host smart-f07a5e2c-e79c-46e3-bb42-778a77481006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046092729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2046092729
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_intr.30551050
Short name T940
Test name
Test status
Simulation time 42807190699 ps
CPU time 63.5 seconds
Started Jun 27 04:55:22 PM PDT 24
Finished Jun 27 04:56:27 PM PDT 24
Peak memory 199652 kb
Host smart-9d516933-3407-4eab-b0ac-42c1c243eb06
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30551050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.30551050
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_loopback.512659197
Short name T818
Test name
Test status
Simulation time 4573137065 ps
CPU time 9.98 seconds
Started Jun 27 04:55:06 PM PDT 24
Finished Jun 27 04:55:19 PM PDT 24
Peak memory 199436 kb
Host smart-d32808d7-bd16-4c42-bc60-1e097249dca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512659197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.512659197
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_perf.302213136
Short name T716
Test name
Test status
Simulation time 14903087760 ps
CPU time 856.04 seconds
Started Jun 27 04:55:10 PM PDT 24
Finished Jun 27 05:09:30 PM PDT 24
Peak memory 199932 kb
Host smart-b546cb6c-786d-405f-9b44-81cdd0a59828
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=302213136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.302213136
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2214460734
Short name T572
Test name
Test status
Simulation time 2098339358 ps
CPU time 7.26 seconds
Started Jun 27 04:55:09 PM PDT 24
Finished Jun 27 04:55:20 PM PDT 24
Peak memory 197972 kb
Host smart-8b56b607-d237-435a-a0e5-81c9470bd65e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2214460734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2214460734
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.458960014
Short name T708
Test name
Test status
Simulation time 42043088262 ps
CPU time 18 seconds
Started Jun 27 04:55:21 PM PDT 24
Finished Jun 27 04:55:40 PM PDT 24
Peak memory 199916 kb
Host smart-b071a3de-d31e-4a1e-b900-8c801557f74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458960014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.458960014
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.3734379557
Short name T285
Test name
Test status
Simulation time 49857347104 ps
CPU time 19.49 seconds
Started Jun 27 04:55:09 PM PDT 24
Finished Jun 27 04:55:33 PM PDT 24
Peak memory 195956 kb
Host smart-2a757606-2178-4445-9836-82235f48085b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734379557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3734379557
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.1160528869
Short name T95
Test name
Test status
Simulation time 483844949 ps
CPU time 1.31 seconds
Started Jun 27 04:55:22 PM PDT 24
Finished Jun 27 04:55:24 PM PDT 24
Peak memory 198612 kb
Host smart-4b35b00e-81d0-44aa-9548-54abd0a8cd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160528869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1160528869
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.1926265286
Short name T535
Test name
Test status
Simulation time 192770495403 ps
CPU time 341.4 seconds
Started Jun 27 04:55:11 PM PDT 24
Finished Jun 27 05:00:56 PM PDT 24
Peak memory 199876 kb
Host smart-35b5f09b-2bd4-4a4d-a43c-4f3f7d65c55e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926265286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.1926265286
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.770554644
Short name T87
Test name
Test status
Simulation time 15297786048 ps
CPU time 170.49 seconds
Started Jun 27 04:55:21 PM PDT 24
Finished Jun 27 04:58:13 PM PDT 24
Peak memory 208204 kb
Host smart-1207d686-1838-45d3-a57f-4a39d2f1f84f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770554644 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.770554644
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.253103316
Short name T586
Test name
Test status
Simulation time 1352747228 ps
CPU time 2.48 seconds
Started Jun 27 04:55:09 PM PDT 24
Finished Jun 27 04:55:15 PM PDT 24
Peak memory 198212 kb
Host smart-3c8c7315-02af-43a5-8e28-64c659db9017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253103316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.253103316
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.18554481
Short name T496
Test name
Test status
Simulation time 99912753310 ps
CPU time 79.66 seconds
Started Jun 27 04:55:09 PM PDT 24
Finished Jun 27 04:56:33 PM PDT 24
Peak memory 199976 kb
Host smart-164e2ee3-7125-4664-8165-df1fe9de95e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18554481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.18554481
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1089058301
Short name T139
Test name
Test status
Simulation time 82562350443 ps
CPU time 46.15 seconds
Started Jun 27 04:57:56 PM PDT 24
Finished Jun 27 04:58:45 PM PDT 24
Peak memory 199856 kb
Host smart-94dab800-93c6-4bac-b5dc-946ae5a2e4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089058301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1089058301
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.29597402
Short name T677
Test name
Test status
Simulation time 92346529243 ps
CPU time 17.12 seconds
Started Jun 27 04:57:55 PM PDT 24
Finished Jun 27 04:58:15 PM PDT 24
Peak memory 198248 kb
Host smart-df911e76-f3a5-45cc-b985-7810e295bf89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29597402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.29597402
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.1031704173
Short name T187
Test name
Test status
Simulation time 23436469053 ps
CPU time 40.76 seconds
Started Jun 27 04:57:57 PM PDT 24
Finished Jun 27 04:58:42 PM PDT 24
Peak memory 199900 kb
Host smart-438eca63-457d-4765-b0de-2156d0d012b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031704173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1031704173
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.1445420914
Short name T40
Test name
Test status
Simulation time 17509127456 ps
CPU time 27.46 seconds
Started Jun 27 04:57:57 PM PDT 24
Finished Jun 27 04:58:28 PM PDT 24
Peak memory 199904 kb
Host smart-810e9ecf-aa38-44c0-accc-8d9db144e10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445420914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.1445420914
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2637230776
Short name T817
Test name
Test status
Simulation time 116683149609 ps
CPU time 31.63 seconds
Started Jun 27 04:57:59 PM PDT 24
Finished Jun 27 04:58:33 PM PDT 24
Peak memory 199928 kb
Host smart-c5308c99-14c6-4582-b97f-7109d8b93aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637230776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2637230776
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.2372765509
Short name T780
Test name
Test status
Simulation time 55827901070 ps
CPU time 79.65 seconds
Started Jun 27 04:57:57 PM PDT 24
Finished Jun 27 04:59:19 PM PDT 24
Peak memory 199916 kb
Host smart-7d4c6685-89fb-4bd3-9966-f3c37ef26b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372765509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.2372765509
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.3955244177
Short name T942
Test name
Test status
Simulation time 26614248480 ps
CPU time 17.19 seconds
Started Jun 27 04:57:58 PM PDT 24
Finished Jun 27 04:58:19 PM PDT 24
Peak memory 199652 kb
Host smart-2b5c44c4-d987-49fc-90d5-b3787f1adef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955244177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3955244177
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.4210982364
Short name T528
Test name
Test status
Simulation time 290135041190 ps
CPU time 452.13 seconds
Started Jun 27 04:57:58 PM PDT 24
Finished Jun 27 05:05:34 PM PDT 24
Peak memory 199896 kb
Host smart-0341e7d2-136f-44ef-bbf5-9aac607db4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210982364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.4210982364
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.3193786232
Short name T594
Test name
Test status
Simulation time 40026287 ps
CPU time 0.54 seconds
Started Jun 27 04:53:59 PM PDT 24
Finished Jun 27 04:54:02 PM PDT 24
Peak memory 194348 kb
Host smart-3125c7ab-872a-4e61-aec4-ad6e4ed753fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193786232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3193786232
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.3948790030
Short name T1
Test name
Test status
Simulation time 25062251551 ps
CPU time 41.29 seconds
Started Jun 27 04:53:44 PM PDT 24
Finished Jun 27 04:54:30 PM PDT 24
Peak memory 199764 kb
Host smart-0c936c76-e52c-46f9-8d8c-e33bccd9df8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948790030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.3948790030
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.2908655646
Short name T267
Test name
Test status
Simulation time 36210128273 ps
CPU time 52.26 seconds
Started Jun 27 04:53:47 PM PDT 24
Finished Jun 27 04:54:43 PM PDT 24
Peak memory 199988 kb
Host smart-9b91cdf1-49ab-4c66-9896-25e0c83f2b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908655646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2908655646
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.3290230720
Short name T669
Test name
Test status
Simulation time 40346807314 ps
CPU time 10.01 seconds
Started Jun 27 04:53:48 PM PDT 24
Finished Jun 27 04:54:01 PM PDT 24
Peak memory 199940 kb
Host smart-d98db628-228e-417f-90ce-aa694558a637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290230720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.3290230720
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.2619768115
Short name T376
Test name
Test status
Simulation time 231877940625 ps
CPU time 364.65 seconds
Started Jun 27 04:53:45 PM PDT 24
Finished Jun 27 04:59:54 PM PDT 24
Peak memory 198540 kb
Host smart-a8db1a25-9f8a-4192-937d-1384c042ac5b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619768115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2619768115
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.2904781252
Short name T983
Test name
Test status
Simulation time 133875748687 ps
CPU time 1055.56 seconds
Started Jun 27 04:53:44 PM PDT 24
Finished Jun 27 05:11:24 PM PDT 24
Peak memory 199880 kb
Host smart-cb5208fe-0b51-4df7-91e3-10ebc69c2bb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2904781252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.2904781252
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.2943832906
Short name T789
Test name
Test status
Simulation time 9381390528 ps
CPU time 10.73 seconds
Started Jun 27 04:53:44 PM PDT 24
Finished Jun 27 04:53:59 PM PDT 24
Peak memory 199812 kb
Host smart-843ffbec-fd7a-4cca-8f2e-e711ad54c0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943832906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2943832906
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_perf.2570338
Short name T245
Test name
Test status
Simulation time 11606784354 ps
CPU time 617.25 seconds
Started Jun 27 04:53:37 PM PDT 24
Finished Jun 27 05:03:59 PM PDT 24
Peak memory 199820 kb
Host smart-c3fe987c-a1b0-499a-b732-d37157029f19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2570338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2570338
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.4228214710
Short name T1067
Test name
Test status
Simulation time 5996204252 ps
CPU time 2.87 seconds
Started Jun 27 04:53:54 PM PDT 24
Finished Jun 27 04:54:00 PM PDT 24
Peak memory 199316 kb
Host smart-5cd3a02e-1e8d-44f1-b214-a375cb99a25d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4228214710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.4228214710
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.2859897483
Short name T828
Test name
Test status
Simulation time 86281116648 ps
CPU time 132.29 seconds
Started Jun 27 04:53:40 PM PDT 24
Finished Jun 27 04:55:57 PM PDT 24
Peak memory 199988 kb
Host smart-1260fc6e-8c0b-413b-b244-71a2b19706bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859897483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.2859897483
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.1733006025
Short name T862
Test name
Test status
Simulation time 34091112786 ps
CPU time 14.12 seconds
Started Jun 27 04:53:42 PM PDT 24
Finished Jun 27 04:54:01 PM PDT 24
Peak memory 195936 kb
Host smart-b1bd0ce4-97db-49e5-b0bf-4c8006855bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733006025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1733006025
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.3113769666
Short name T31
Test name
Test status
Simulation time 58541459 ps
CPU time 0.83 seconds
Started Jun 27 04:53:52 PM PDT 24
Finished Jun 27 04:53:53 PM PDT 24
Peak memory 218216 kb
Host smart-6fad6efc-d02b-40d5-9361-34a13275593e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113769666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3113769666
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.3055952450
Short name T1048
Test name
Test status
Simulation time 265760774 ps
CPU time 1.37 seconds
Started Jun 27 04:53:48 PM PDT 24
Finished Jun 27 04:53:52 PM PDT 24
Peak memory 199880 kb
Host smart-7d174fb6-8712-46fa-b36b-74fffd864984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055952450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.3055952450
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.1312401785
Short name T101
Test name
Test status
Simulation time 42668953362 ps
CPU time 61.31 seconds
Started Jun 27 04:53:54 PM PDT 24
Finished Jun 27 04:54:58 PM PDT 24
Peak memory 200108 kb
Host smart-48b92e8d-92b6-40df-b69a-bd2b1b7ce2c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312401785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.1312401785
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.256505307
Short name T89
Test name
Test status
Simulation time 19599174725 ps
CPU time 194.58 seconds
Started Jun 27 04:53:35 PM PDT 24
Finished Jun 27 04:56:54 PM PDT 24
Peak memory 215576 kb
Host smart-f2173848-cbf7-4aa4-abbf-533381fc6007
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256505307 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.256505307
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2072352830
Short name T931
Test name
Test status
Simulation time 2291365057 ps
CPU time 2.66 seconds
Started Jun 27 04:53:54 PM PDT 24
Finished Jun 27 04:53:58 PM PDT 24
Peak memory 199660 kb
Host smart-1b524c80-f059-4278-a523-d372cfd0807c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072352830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2072352830
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.4288897063
Short name T687
Test name
Test status
Simulation time 25964979744 ps
CPU time 10.04 seconds
Started Jun 27 04:53:53 PM PDT 24
Finished Jun 27 04:54:05 PM PDT 24
Peak memory 199728 kb
Host smart-386e96d4-b508-4cf5-bfe7-1f96d9def6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288897063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.4288897063
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.2453105017
Short name T920
Test name
Test status
Simulation time 28201792 ps
CPU time 0.56 seconds
Started Jun 27 04:55:30 PM PDT 24
Finished Jun 27 04:55:31 PM PDT 24
Peak memory 195232 kb
Host smart-a57fb8c0-aa66-4e4f-b09d-4fff615bd9f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453105017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.2453105017
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.1995416945
Short name T546
Test name
Test status
Simulation time 122903291842 ps
CPU time 186.24 seconds
Started Jun 27 04:55:07 PM PDT 24
Finished Jun 27 04:58:17 PM PDT 24
Peak memory 199904 kb
Host smart-8c42014f-0aa3-461f-868a-4add5c01a494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995416945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.1995416945
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.1415200414
Short name T947
Test name
Test status
Simulation time 24045494258 ps
CPU time 20.11 seconds
Started Jun 27 04:55:21 PM PDT 24
Finished Jun 27 04:55:42 PM PDT 24
Peak memory 199960 kb
Host smart-1a6cd7cf-44ab-436a-8281-a05e0345aaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415200414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1415200414
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.4215545438
Short name T794
Test name
Test status
Simulation time 31691408112 ps
CPU time 56.63 seconds
Started Jun 27 04:55:10 PM PDT 24
Finished Jun 27 04:56:10 PM PDT 24
Peak memory 199900 kb
Host smart-41660564-68f7-4ae6-a898-0a7dac1e3977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215545438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.4215545438
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.4226533782
Short name T426
Test name
Test status
Simulation time 39863522223 ps
CPU time 46.74 seconds
Started Jun 27 04:55:13 PM PDT 24
Finished Jun 27 04:56:02 PM PDT 24
Peak memory 199920 kb
Host smart-2c281720-6a49-4a56-8f3a-ed4d372e36c4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226533782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.4226533782
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.1699937323
Short name T849
Test name
Test status
Simulation time 186776390380 ps
CPU time 535.97 seconds
Started Jun 27 04:55:30 PM PDT 24
Finished Jun 27 05:04:27 PM PDT 24
Peak memory 199936 kb
Host smart-649c8f02-14d3-4c57-947a-089bde9c25d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1699937323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1699937323
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.3936700300
Short name T374
Test name
Test status
Simulation time 3362906340 ps
CPU time 2.43 seconds
Started Jun 27 04:55:23 PM PDT 24
Finished Jun 27 04:55:27 PM PDT 24
Peak memory 196020 kb
Host smart-75e9bfe5-a6bf-4678-8337-141c6556052c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936700300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3936700300
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_perf.3214503114
Short name T263
Test name
Test status
Simulation time 7539222596 ps
CPU time 415.1 seconds
Started Jun 27 04:55:23 PM PDT 24
Finished Jun 27 05:02:19 PM PDT 24
Peak memory 199708 kb
Host smart-0fed3b4e-625d-4c7a-9966-96fa9f52dcbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3214503114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.3214503114
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.1795047293
Short name T421
Test name
Test status
Simulation time 2170663822 ps
CPU time 2.17 seconds
Started Jun 27 04:55:09 PM PDT 24
Finished Jun 27 04:55:15 PM PDT 24
Peak memory 198268 kb
Host smart-05f16c2f-467f-4018-90fa-1883371429db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1795047293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.1795047293
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.3104163119
Short name T334
Test name
Test status
Simulation time 66678863958 ps
CPU time 112.02 seconds
Started Jun 27 04:55:10 PM PDT 24
Finished Jun 27 04:57:06 PM PDT 24
Peak memory 199964 kb
Host smart-2531df71-052e-4381-b10a-fe5457df0a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104163119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3104163119
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.1176331684
Short name T541
Test name
Test status
Simulation time 46333706159 ps
CPU time 68.17 seconds
Started Jun 27 04:55:09 PM PDT 24
Finished Jun 27 04:56:21 PM PDT 24
Peak memory 195700 kb
Host smart-80f48a11-df62-43cc-9fa4-6a0eb907510d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176331684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1176331684
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3148155792
Short name T762
Test name
Test status
Simulation time 656093213 ps
CPU time 1.82 seconds
Started Jun 27 04:55:22 PM PDT 24
Finished Jun 27 04:55:25 PM PDT 24
Peak memory 199716 kb
Host smart-ce2dbf5d-9513-465f-8651-4af0cb20ac66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148155792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3148155792
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2408060480
Short name T961
Test name
Test status
Simulation time 6780268040 ps
CPU time 32.8 seconds
Started Jun 27 04:55:23 PM PDT 24
Finished Jun 27 04:55:57 PM PDT 24
Peak memory 199412 kb
Host smart-68b4c99a-8de3-413c-8bc9-78c113f25795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408060480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2408060480
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.2809468118
Short name T273
Test name
Test status
Simulation time 104243271452 ps
CPU time 80 seconds
Started Jun 27 04:55:21 PM PDT 24
Finished Jun 27 04:56:42 PM PDT 24
Peak memory 199908 kb
Host smart-cb75a251-3de1-4fd4-8849-fff402d0470e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809468118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2809468118
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1701429680
Short name T340
Test name
Test status
Simulation time 31117610 ps
CPU time 0.55 seconds
Started Jun 27 04:55:33 PM PDT 24
Finished Jun 27 04:55:36 PM PDT 24
Peak memory 195160 kb
Host smart-3fb30870-1a1d-47c3-8a98-9deb1052b73c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701429680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1701429680
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.2132737099
Short name T495
Test name
Test status
Simulation time 52178372410 ps
CPU time 63.8 seconds
Started Jun 27 04:55:32 PM PDT 24
Finished Jun 27 04:56:37 PM PDT 24
Peak memory 199804 kb
Host smart-bc39f65c-54ff-486f-9c6a-6f331e8f7aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132737099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.2132737099
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3526514559
Short name T467
Test name
Test status
Simulation time 58117557632 ps
CPU time 35.95 seconds
Started Jun 27 04:55:34 PM PDT 24
Finished Jun 27 04:56:12 PM PDT 24
Peak memory 199952 kb
Host smart-069a1ba3-be29-4b22-8b30-8a666f1bcdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526514559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3526514559
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.1230456406
Short name T282
Test name
Test status
Simulation time 27653203653 ps
CPU time 41.34 seconds
Started Jun 27 04:55:33 PM PDT 24
Finished Jun 27 04:56:16 PM PDT 24
Peak memory 199848 kb
Host smart-05127bda-dcdd-4c16-9bbe-5d1e117bb836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230456406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1230456406
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.4137042377
Short name T1030
Test name
Test status
Simulation time 76319752688 ps
CPU time 117.35 seconds
Started Jun 27 04:55:37 PM PDT 24
Finished Jun 27 04:57:36 PM PDT 24
Peak memory 199880 kb
Host smart-0afa2bc0-3d85-4651-a1de-1c88009aa1dd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137042377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.4137042377
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.943534444
Short name T838
Test name
Test status
Simulation time 196915679722 ps
CPU time 498.08 seconds
Started Jun 27 04:55:33 PM PDT 24
Finished Jun 27 05:03:52 PM PDT 24
Peak memory 200192 kb
Host smart-08b1b83e-864b-4eb2-a188-9aeda3d5e400
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=943534444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.943534444
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.1823120605
Short name T801
Test name
Test status
Simulation time 10190139104 ps
CPU time 5.69 seconds
Started Jun 27 04:55:31 PM PDT 24
Finished Jun 27 04:55:37 PM PDT 24
Peak memory 199924 kb
Host smart-4f388b64-526c-4810-969d-d156a4032ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823120605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1823120605
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_perf.280440159
Short name T734
Test name
Test status
Simulation time 22826848356 ps
CPU time 302.89 seconds
Started Jun 27 04:55:33 PM PDT 24
Finished Jun 27 05:00:37 PM PDT 24
Peak memory 199912 kb
Host smart-4b5d367b-e808-4d58-9bf0-bc7e74d8a2b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=280440159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.280440159
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.1895143069
Short name T649
Test name
Test status
Simulation time 6581317820 ps
CPU time 59.77 seconds
Started Jun 27 04:55:35 PM PDT 24
Finished Jun 27 04:56:37 PM PDT 24
Peak memory 198752 kb
Host smart-6e0f8a96-2749-4e19-9072-4bd974ea5c44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1895143069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1895143069
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1655765486
Short name T642
Test name
Test status
Simulation time 28053335602 ps
CPU time 46.14 seconds
Started Jun 27 04:55:32 PM PDT 24
Finished Jun 27 04:56:20 PM PDT 24
Peak memory 199776 kb
Host smart-e6ebb4c0-003c-4ae6-b877-b2ac266523af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655765486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1655765486
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1823416315
Short name T833
Test name
Test status
Simulation time 43714534599 ps
CPU time 28.41 seconds
Started Jun 27 04:55:32 PM PDT 24
Finished Jun 27 04:56:02 PM PDT 24
Peak memory 196320 kb
Host smart-2cb637a3-9660-4276-932b-5c1f3401cc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823416315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1823416315
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.2207487588
Short name T401
Test name
Test status
Simulation time 648828599 ps
CPU time 4.53 seconds
Started Jun 27 04:55:31 PM PDT 24
Finished Jun 27 04:55:37 PM PDT 24
Peak memory 198964 kb
Host smart-2933e027-bbd4-4ecd-919a-47524185c46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207487588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2207487588
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.3821461567
Short name T580
Test name
Test status
Simulation time 81586241827 ps
CPU time 265.02 seconds
Started Jun 27 04:55:33 PM PDT 24
Finished Jun 27 04:59:59 PM PDT 24
Peak memory 216432 kb
Host smart-a8e98a18-102e-44ae-bed1-c905fbe3b905
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821461567 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.3821461567
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.3295855572
Short name T1041
Test name
Test status
Simulation time 1088255211 ps
CPU time 2.98 seconds
Started Jun 27 04:55:33 PM PDT 24
Finished Jun 27 04:55:38 PM PDT 24
Peak memory 198976 kb
Host smart-efd837ab-3007-4b0b-8ab1-d2f96b692b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295855572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3295855572
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.3145283784
Short name T1050
Test name
Test status
Simulation time 70925912769 ps
CPU time 31.6 seconds
Started Jun 27 04:55:32 PM PDT 24
Finished Jun 27 04:56:05 PM PDT 24
Peak memory 199920 kb
Host smart-1d1bb62f-8c5a-4683-8ae4-75661720134d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145283784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3145283784
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.2791147610
Short name T337
Test name
Test status
Simulation time 20727394 ps
CPU time 0.55 seconds
Started Jun 27 04:55:31 PM PDT 24
Finished Jun 27 04:55:32 PM PDT 24
Peak memory 195588 kb
Host smart-5b72d0ba-f12e-40e3-96cf-f0a5babd389b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791147610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2791147610
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.801852277
Short name T410
Test name
Test status
Simulation time 264468455396 ps
CPU time 128.53 seconds
Started Jun 27 04:55:31 PM PDT 24
Finished Jun 27 04:57:41 PM PDT 24
Peak memory 199956 kb
Host smart-88e70da0-ad41-465f-be53-1292f54559c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801852277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.801852277
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2016806625
Short name T251
Test name
Test status
Simulation time 64050077707 ps
CPU time 99.84 seconds
Started Jun 27 04:55:30 PM PDT 24
Finished Jun 27 04:57:11 PM PDT 24
Peak memory 199888 kb
Host smart-e16ba68a-ba7e-483d-aac0-e08bedaf69ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016806625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2016806625
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.2030235812
Short name T238
Test name
Test status
Simulation time 36519205869 ps
CPU time 36.67 seconds
Started Jun 27 04:55:33 PM PDT 24
Finished Jun 27 04:56:12 PM PDT 24
Peak memory 199844 kb
Host smart-370d806b-5dd1-4535-980d-81da9861785c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030235812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2030235812
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.2962505475
Short name T409
Test name
Test status
Simulation time 13099704233 ps
CPU time 20.17 seconds
Started Jun 27 04:55:33 PM PDT 24
Finished Jun 27 04:55:55 PM PDT 24
Peak memory 198712 kb
Host smart-101df0a1-de9e-4133-9757-0dde633e76eb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962505475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2962505475
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.991324652
Short name T266
Test name
Test status
Simulation time 137674996258 ps
CPU time 265.33 seconds
Started Jun 27 04:55:30 PM PDT 24
Finished Jun 27 04:59:57 PM PDT 24
Peak memory 199924 kb
Host smart-0d8bec4a-c835-4b31-b676-e1ff28672fc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=991324652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.991324652
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.2574719665
Short name T349
Test name
Test status
Simulation time 2995111688 ps
CPU time 5.99 seconds
Started Jun 27 04:55:36 PM PDT 24
Finished Jun 27 04:55:44 PM PDT 24
Peak memory 198756 kb
Host smart-7fc49bf9-4e60-40ea-8ed5-c86b7dbb2e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574719665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2574719665
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_perf.1903983443
Short name T775
Test name
Test status
Simulation time 8822792108 ps
CPU time 27.88 seconds
Started Jun 27 04:55:33 PM PDT 24
Finished Jun 27 04:56:02 PM PDT 24
Peak memory 199912 kb
Host smart-d8fd5a74-b384-420f-a9e1-fb0649bd898a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1903983443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1903983443
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.1018260699
Short name T918
Test name
Test status
Simulation time 3883918655 ps
CPU time 33.26 seconds
Started Jun 27 04:55:36 PM PDT 24
Finished Jun 27 04:56:11 PM PDT 24
Peak memory 198052 kb
Host smart-8dbd8d94-d6ca-4682-9c8d-60e0136c4b50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1018260699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.1018260699
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.883542240
Short name T982
Test name
Test status
Simulation time 41654174949 ps
CPU time 23 seconds
Started Jun 27 04:55:32 PM PDT 24
Finished Jun 27 04:55:57 PM PDT 24
Peak memory 199900 kb
Host smart-ced3cbcd-263e-4be2-9db1-86b9f9821780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883542240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.883542240
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.405431824
Short name T1071
Test name
Test status
Simulation time 3474676306 ps
CPU time 2.03 seconds
Started Jun 27 04:55:32 PM PDT 24
Finished Jun 27 04:55:36 PM PDT 24
Peak memory 196484 kb
Host smart-c716b7b2-0e06-49ac-b123-beef61140c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405431824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.405431824
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.1861142876
Short name T1006
Test name
Test status
Simulation time 297738753 ps
CPU time 1.18 seconds
Started Jun 27 04:55:32 PM PDT 24
Finished Jun 27 04:55:34 PM PDT 24
Peak memory 198544 kb
Host smart-85c6e0b6-e267-4474-8b90-ceb52a8a7140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861142876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.1861142876
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.1834222561
Short name T1059
Test name
Test status
Simulation time 2059019544 ps
CPU time 1.76 seconds
Started Jun 27 04:55:34 PM PDT 24
Finished Jun 27 04:55:38 PM PDT 24
Peak memory 198640 kb
Host smart-06868bd7-c25e-41eb-9c44-51edbd8cff7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834222561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.1834222561
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.2433647914
Short name T819
Test name
Test status
Simulation time 127513682691 ps
CPU time 59.53 seconds
Started Jun 27 04:55:34 PM PDT 24
Finished Jun 27 04:56:36 PM PDT 24
Peak memory 199996 kb
Host smart-f355e1c9-088a-4c49-b8ca-78b0ab998693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433647914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2433647914
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.8579855
Short name T593
Test name
Test status
Simulation time 11222973 ps
CPU time 0.57 seconds
Started Jun 27 04:55:31 PM PDT 24
Finished Jun 27 04:55:33 PM PDT 24
Peak memory 195284 kb
Host smart-6ed68180-6190-4c27-abdd-c2dbe2f3e0d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8579855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.8579855
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.650237914
Short name T840
Test name
Test status
Simulation time 132259903397 ps
CPU time 42.26 seconds
Started Jun 27 04:55:33 PM PDT 24
Finished Jun 27 04:56:17 PM PDT 24
Peak memory 200108 kb
Host smart-1d7e30f6-d069-4cca-a9c9-cf3683fbccd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650237914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.650237914
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.1208095879
Short name T729
Test name
Test status
Simulation time 67824098999 ps
CPU time 90.38 seconds
Started Jun 27 04:55:35 PM PDT 24
Finished Jun 27 04:57:07 PM PDT 24
Peak memory 199828 kb
Host smart-18eb9f82-f8bd-4e49-9b76-ded8d4af35a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208095879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1208095879
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_intr.1936207733
Short name T621
Test name
Test status
Simulation time 9661260800 ps
CPU time 13.88 seconds
Started Jun 27 04:55:41 PM PDT 24
Finished Jun 27 04:55:55 PM PDT 24
Peak memory 196612 kb
Host smart-64ff7048-c58a-4a2b-9c6d-6b9abd0a6a05
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936207733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.1936207733
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1343546415
Short name T985
Test name
Test status
Simulation time 88826857674 ps
CPU time 273.66 seconds
Started Jun 27 04:55:35 PM PDT 24
Finished Jun 27 05:00:10 PM PDT 24
Peak memory 199952 kb
Host smart-3ba50c8a-ca09-4b14-afa9-c665988e98ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1343546415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1343546415
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.269084275
Short name T929
Test name
Test status
Simulation time 3727053131 ps
CPU time 2.38 seconds
Started Jun 27 04:55:34 PM PDT 24
Finished Jun 27 04:55:39 PM PDT 24
Peak memory 197356 kb
Host smart-9e829da1-4de4-48eb-affd-de8d9290af91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269084275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.269084275
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.352322620
Short name T600
Test name
Test status
Simulation time 25507648359 ps
CPU time 11.84 seconds
Started Jun 27 04:55:34 PM PDT 24
Finished Jun 27 04:55:48 PM PDT 24
Peak memory 200060 kb
Host smart-6b51eb32-a250-4c3f-a51b-3862de75c832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352322620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.352322620
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.3647713393
Short name T719
Test name
Test status
Simulation time 17767034004 ps
CPU time 450.81 seconds
Started Jun 27 04:55:37 PM PDT 24
Finished Jun 27 05:03:09 PM PDT 24
Peak memory 199808 kb
Host smart-3dbf7e32-1509-41ab-a9bb-c0b6b702096f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3647713393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3647713393
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3693348996
Short name T765
Test name
Test status
Simulation time 5710907542 ps
CPU time 11.32 seconds
Started Jun 27 04:55:34 PM PDT 24
Finished Jun 27 04:55:47 PM PDT 24
Peak memory 199308 kb
Host smart-8fcab7c4-aa9a-4bf9-907f-64c5597d1e8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3693348996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3693348996
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.1524941540
Short name T875
Test name
Test status
Simulation time 167271229154 ps
CPU time 71.99 seconds
Started Jun 27 04:55:34 PM PDT 24
Finished Jun 27 04:56:48 PM PDT 24
Peak memory 199892 kb
Host smart-43424697-e85d-4dab-aa08-5b88fc609aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524941540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.1524941540
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.892783819
Short name T625
Test name
Test status
Simulation time 1857635108 ps
CPU time 2.27 seconds
Started Jun 27 04:55:33 PM PDT 24
Finished Jun 27 04:55:37 PM PDT 24
Peak memory 195580 kb
Host smart-13b0c568-7538-4d21-93d3-aacf1f9324e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892783819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.892783819
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1577758143
Short name T689
Test name
Test status
Simulation time 293493571 ps
CPU time 1.49 seconds
Started Jun 27 04:55:35 PM PDT 24
Finished Jun 27 04:55:38 PM PDT 24
Peak memory 198440 kb
Host smart-22842b29-7909-48c5-b5f7-c5ba21766d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577758143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1577758143
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.854182251
Short name T264
Test name
Test status
Simulation time 136555430651 ps
CPU time 98.42 seconds
Started Jun 27 04:55:36 PM PDT 24
Finished Jun 27 04:57:16 PM PDT 24
Peak memory 199944 kb
Host smart-e44c4c69-7594-4d67-97fd-57da0c116648
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854182251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.854182251
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.3292880559
Short name T935
Test name
Test status
Simulation time 868370270 ps
CPU time 4.55 seconds
Started Jun 27 04:55:36 PM PDT 24
Finished Jun 27 04:55:42 PM PDT 24
Peak memory 198980 kb
Host smart-f1b2a5e8-0ec0-4472-936c-467dd22c835c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292880559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.3292880559
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_alert_test.2325476601
Short name T870
Test name
Test status
Simulation time 14463490 ps
CPU time 0.56 seconds
Started Jun 27 04:55:54 PM PDT 24
Finished Jun 27 04:55:58 PM PDT 24
Peak memory 195232 kb
Host smart-dfdd65a9-87cc-48cf-8bfd-b8193a19c53c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325476601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2325476601
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.421985594
Short name T501
Test name
Test status
Simulation time 117495250304 ps
CPU time 267.42 seconds
Started Jun 27 04:55:37 PM PDT 24
Finished Jun 27 05:00:06 PM PDT 24
Peak memory 199932 kb
Host smart-d43c4e77-e785-4681-9781-9de9dc7eae77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421985594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.421985594
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.64888822
Short name T133
Test name
Test status
Simulation time 39292309803 ps
CPU time 15.92 seconds
Started Jun 27 04:55:37 PM PDT 24
Finished Jun 27 04:55:55 PM PDT 24
Peak memory 199640 kb
Host smart-f71fc76f-abea-4d4f-b71a-199c78654c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64888822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.64888822
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.2986683297
Short name T1042
Test name
Test status
Simulation time 69362218193 ps
CPU time 21.77 seconds
Started Jun 27 04:55:37 PM PDT 24
Finished Jun 27 04:56:00 PM PDT 24
Peak memory 199912 kb
Host smart-a93307ee-1d3d-4238-979d-0f54186f4dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986683297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2986683297
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.612975342
Short name T666
Test name
Test status
Simulation time 27772395263 ps
CPU time 9.37 seconds
Started Jun 27 04:55:33 PM PDT 24
Finished Jun 27 04:55:44 PM PDT 24
Peak memory 199544 kb
Host smart-ca8caad3-1631-4406-86c0-92c7de6815a4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612975342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.612975342
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.3326321867
Short name T400
Test name
Test status
Simulation time 32585887192 ps
CPU time 130.33 seconds
Started Jun 27 04:55:51 PM PDT 24
Finished Jun 27 04:58:03 PM PDT 24
Peak memory 199976 kb
Host smart-f23a8105-324d-4e0b-9094-9a296ffb496b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3326321867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3326321867
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3956364594
Short name T658
Test name
Test status
Simulation time 6425379985 ps
CPU time 3.39 seconds
Started Jun 27 04:55:52 PM PDT 24
Finished Jun 27 04:55:58 PM PDT 24
Peak memory 197992 kb
Host smart-53c1ac04-21ad-4d8e-8b65-586193d805f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956364594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3956364594
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.3362716886
Short name T1047
Test name
Test status
Simulation time 95747536368 ps
CPU time 38.67 seconds
Started Jun 27 04:55:41 PM PDT 24
Finished Jun 27 04:56:20 PM PDT 24
Peak memory 199956 kb
Host smart-7cc9560b-ecd4-48b2-b891-4b167425dbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362716886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.3362716886
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.3135111162
Short name T707
Test name
Test status
Simulation time 16869973435 ps
CPU time 481.46 seconds
Started Jun 27 04:55:54 PM PDT 24
Finished Jun 27 05:03:59 PM PDT 24
Peak memory 199764 kb
Host smart-9f3bb601-aa5f-4f89-9bad-472d6b8b3595
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3135111162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3135111162
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.377061739
Short name T429
Test name
Test status
Simulation time 2878652897 ps
CPU time 25.29 seconds
Started Jun 27 04:55:35 PM PDT 24
Finished Jun 27 04:56:02 PM PDT 24
Peak memory 198764 kb
Host smart-2482a864-5c04-4c95-8c55-286844af9bfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=377061739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.377061739
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.3093639616
Short name T544
Test name
Test status
Simulation time 2977147460 ps
CPU time 2.65 seconds
Started Jun 27 04:55:53 PM PDT 24
Finished Jun 27 04:55:58 PM PDT 24
Peak memory 195888 kb
Host smart-280f5eae-2179-4ded-b910-9f2df2afcb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093639616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3093639616
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.1187619177
Short name T664
Test name
Test status
Simulation time 5698483380 ps
CPU time 8.76 seconds
Started Jun 27 04:55:37 PM PDT 24
Finished Jun 27 04:55:47 PM PDT 24
Peak memory 199720 kb
Host smart-96cde1d7-61bd-4a06-ae9e-dcf1fae04afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187619177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.1187619177
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.3924119518
Short name T820
Test name
Test status
Simulation time 1139796564172 ps
CPU time 496.19 seconds
Started Jun 27 04:55:55 PM PDT 24
Finished Jun 27 05:04:15 PM PDT 24
Peak memory 199724 kb
Host smart-c5e12fab-fee3-49d1-b147-1f1f8d3291ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924119518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.3924119518
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1578303431
Short name T45
Test name
Test status
Simulation time 6428821154 ps
CPU time 17.42 seconds
Started Jun 27 04:55:57 PM PDT 24
Finished Jun 27 04:56:20 PM PDT 24
Peak memory 199040 kb
Host smart-f8f61aa4-0570-44e1-9eec-1de2c17e2a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578303431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1578303431
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.3041086474
Short name T696
Test name
Test status
Simulation time 17615954459 ps
CPU time 15.92 seconds
Started Jun 27 04:55:36 PM PDT 24
Finished Jun 27 04:55:54 PM PDT 24
Peak memory 199488 kb
Host smart-d233b58f-4cbb-4bd6-b26f-519e8a3f93ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041086474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3041086474
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.3312754059
Short name T750
Test name
Test status
Simulation time 45761695 ps
CPU time 0.54 seconds
Started Jun 27 04:55:54 PM PDT 24
Finished Jun 27 04:55:57 PM PDT 24
Peak memory 195280 kb
Host smart-ed324a39-6604-45a3-81b7-17863ebfd7ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312754059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3312754059
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.1536726623
Short name T683
Test name
Test status
Simulation time 89470612132 ps
CPU time 36.68 seconds
Started Jun 27 04:55:53 PM PDT 24
Finished Jun 27 04:56:33 PM PDT 24
Peak memory 199912 kb
Host smart-1d212710-af7a-4cd6-8014-75098343c2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536726623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1536726623
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.2743179911
Short name T395
Test name
Test status
Simulation time 38994483521 ps
CPU time 17.3 seconds
Started Jun 27 04:55:55 PM PDT 24
Finished Jun 27 04:56:16 PM PDT 24
Peak memory 199256 kb
Host smart-b351458f-9d8e-4fd3-84f5-a979cba26091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743179911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2743179911
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_intr.754884491
Short name T623
Test name
Test status
Simulation time 490218820023 ps
CPU time 166.22 seconds
Started Jun 27 04:55:54 PM PDT 24
Finished Jun 27 04:58:44 PM PDT 24
Peak memory 197752 kb
Host smart-dd9e4206-d353-4c49-8c0f-fad3112a83d9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754884491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.754884491
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.2880136815
Short name T676
Test name
Test status
Simulation time 83745352073 ps
CPU time 195.07 seconds
Started Jun 27 04:55:54 PM PDT 24
Finished Jun 27 04:59:13 PM PDT 24
Peak memory 199820 kb
Host smart-a01b6ee3-c1ec-4c47-9979-9304036d7d0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2880136815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2880136815
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3190741022
Short name T519
Test name
Test status
Simulation time 6219765343 ps
CPU time 3.93 seconds
Started Jun 27 04:55:53 PM PDT 24
Finished Jun 27 04:56:00 PM PDT 24
Peak memory 199176 kb
Host smart-374d47c1-1e38-4a24-99e4-9e693b37e62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190741022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3190741022
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.822962168
Short name T638
Test name
Test status
Simulation time 43051950766 ps
CPU time 10.07 seconds
Started Jun 27 04:55:55 PM PDT 24
Finished Jun 27 04:56:09 PM PDT 24
Peak memory 196896 kb
Host smart-94d1b1dc-bef9-4485-b18e-59ab3ba81e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822962168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.822962168
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.2815731006
Short name T1022
Test name
Test status
Simulation time 19302961344 ps
CPU time 976.38 seconds
Started Jun 27 04:55:53 PM PDT 24
Finished Jun 27 05:12:12 PM PDT 24
Peak memory 199772 kb
Host smart-20fe2ec6-c962-42cd-b47e-706331899a38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2815731006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2815731006
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.664571192
Short name T893
Test name
Test status
Simulation time 1928488191 ps
CPU time 3.41 seconds
Started Jun 27 04:55:54 PM PDT 24
Finished Jun 27 04:56:01 PM PDT 24
Peak memory 198020 kb
Host smart-2fa5d7ff-2e6f-4f57-a7b8-ff83798cdad6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=664571192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.664571192
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.2607447049
Short name T398
Test name
Test status
Simulation time 80328551203 ps
CPU time 105.94 seconds
Started Jun 27 04:55:55 PM PDT 24
Finished Jun 27 04:57:45 PM PDT 24
Peak memory 199956 kb
Host smart-c84e5736-7438-46c0-8031-1590f200438b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607447049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2607447049
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.768523939
Short name T547
Test name
Test status
Simulation time 3867093609 ps
CPU time 6.95 seconds
Started Jun 27 04:55:56 PM PDT 24
Finished Jun 27 04:56:08 PM PDT 24
Peak memory 195976 kb
Host smart-d69236a8-3875-4d3e-b1bf-8154711d0995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768523939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.768523939
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2251734701
Short name T244
Test name
Test status
Simulation time 5772023921 ps
CPU time 20.33 seconds
Started Jun 27 04:55:55 PM PDT 24
Finished Jun 27 04:56:19 PM PDT 24
Peak memory 199816 kb
Host smart-44a320a2-c9e8-4d3e-a8b0-a430230b32f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251734701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2251734701
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.2718896291
Short name T162
Test name
Test status
Simulation time 384556545508 ps
CPU time 160.56 seconds
Started Jun 27 04:55:53 PM PDT 24
Finished Jun 27 04:58:37 PM PDT 24
Peak memory 199888 kb
Host smart-a51f53a6-2ed1-4931-b7cf-6017f6801d50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718896291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2718896291
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.553030804
Short name T422
Test name
Test status
Simulation time 1343667439 ps
CPU time 2.78 seconds
Started Jun 27 04:55:57 PM PDT 24
Finished Jun 27 04:56:05 PM PDT 24
Peak memory 199656 kb
Host smart-3b147ba2-7fdb-4575-8fa3-d24a76cf4cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553030804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.553030804
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.4173515399
Short name T304
Test name
Test status
Simulation time 56131482084 ps
CPU time 24.65 seconds
Started Jun 27 04:55:54 PM PDT 24
Finished Jun 27 04:56:22 PM PDT 24
Peak memory 199992 kb
Host smart-bb16e35e-7d04-45f3-8e38-7732343698ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173515399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.4173515399
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.3791559907
Short name T1066
Test name
Test status
Simulation time 22171569 ps
CPU time 0.54 seconds
Started Jun 27 04:55:53 PM PDT 24
Finished Jun 27 04:55:57 PM PDT 24
Peak memory 194180 kb
Host smart-5e22150d-9fd7-44fa-bd38-a612ff4cd9c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791559907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3791559907
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2569151270
Short name T11
Test name
Test status
Simulation time 168705610679 ps
CPU time 94.4 seconds
Started Jun 27 04:55:54 PM PDT 24
Finished Jun 27 04:57:32 PM PDT 24
Peak memory 199928 kb
Host smart-0474c098-9310-42a3-89d6-05a896ac6f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569151270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2569151270
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.2183538042
Short name T690
Test name
Test status
Simulation time 154420094411 ps
CPU time 19.29 seconds
Started Jun 27 04:55:55 PM PDT 24
Finished Jun 27 04:56:18 PM PDT 24
Peak memory 199496 kb
Host smart-6f59b505-003d-4a38-b519-98637051a3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183538042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2183538042
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.2978280022
Short name T185
Test name
Test status
Simulation time 27502371420 ps
CPU time 40.01 seconds
Started Jun 27 04:55:54 PM PDT 24
Finished Jun 27 04:56:37 PM PDT 24
Peak memory 199880 kb
Host smart-7cf3f48f-ec71-4f34-9dc5-f520c2594308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978280022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.2978280022
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.2703038347
Short name T607
Test name
Test status
Simulation time 41864062090 ps
CPU time 52.86 seconds
Started Jun 27 04:55:55 PM PDT 24
Finished Jun 27 04:56:51 PM PDT 24
Peak memory 199832 kb
Host smart-814679fa-fce3-4c3e-86cf-1ef8483184e5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703038347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2703038347
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.4269553011
Short name T730
Test name
Test status
Simulation time 300839058720 ps
CPU time 205.13 seconds
Started Jun 27 04:55:58 PM PDT 24
Finished Jun 27 04:59:29 PM PDT 24
Peak memory 199828 kb
Host smart-d4a535ff-0f74-48dd-a95d-1c093f6c7c21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4269553011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.4269553011
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.1947759551
Short name T344
Test name
Test status
Simulation time 1386806959 ps
CPU time 1.14 seconds
Started Jun 27 04:55:54 PM PDT 24
Finished Jun 27 04:55:59 PM PDT 24
Peak memory 195324 kb
Host smart-11c4ccb6-ce22-40fa-807f-4bfbaceac67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947759551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1947759551
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_perf.3619302892
Short name T995
Test name
Test status
Simulation time 4743230349 ps
CPU time 132.73 seconds
Started Jun 27 04:55:55 PM PDT 24
Finished Jun 27 04:58:12 PM PDT 24
Peak memory 199968 kb
Host smart-51cedd56-aa47-4951-9a6e-a0831b3ea780
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3619302892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3619302892
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.1145836671
Short name T575
Test name
Test status
Simulation time 7109188780 ps
CPU time 60.65 seconds
Started Jun 27 04:55:53 PM PDT 24
Finished Jun 27 04:56:56 PM PDT 24
Peak memory 198052 kb
Host smart-2f994a1a-0fc9-4a60-9969-668d3b292551
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1145836671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.1145836671
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.2026348684
Short name T134
Test name
Test status
Simulation time 166315548858 ps
CPU time 68.87 seconds
Started Jun 27 04:55:53 PM PDT 24
Finished Jun 27 04:57:04 PM PDT 24
Peak memory 199880 kb
Host smart-07db6cdb-df45-44a3-965d-4adfdbfd67f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026348684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2026348684
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.3284260450
Short name T357
Test name
Test status
Simulation time 2456774504 ps
CPU time 2.88 seconds
Started Jun 27 04:55:51 PM PDT 24
Finished Jun 27 04:55:54 PM PDT 24
Peak memory 196360 kb
Host smart-d5fe33f9-b739-44c2-83be-11dc39acfb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284260450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3284260450
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1148242844
Short name T563
Test name
Test status
Simulation time 839565283 ps
CPU time 5.34 seconds
Started Jun 27 04:55:57 PM PDT 24
Finished Jun 27 04:56:07 PM PDT 24
Peak memory 199820 kb
Host smart-db43e019-f871-4b6c-be9f-0c475fa1a8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148242844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1148242844
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.3713468661
Short name T590
Test name
Test status
Simulation time 250729431171 ps
CPU time 539.31 seconds
Started Jun 27 04:55:54 PM PDT 24
Finished Jun 27 05:04:57 PM PDT 24
Peak memory 208312 kb
Host smart-dfba782a-eaef-451f-839a-fca08b7068ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713468661 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.3713468661
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3454965435
Short name T895
Test name
Test status
Simulation time 1338335640 ps
CPU time 2.29 seconds
Started Jun 27 04:55:55 PM PDT 24
Finished Jun 27 04:56:01 PM PDT 24
Peak memory 198588 kb
Host smart-5270b8af-1f85-4512-9966-564530f36e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454965435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3454965435
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.2127503397
Short name T709
Test name
Test status
Simulation time 43702283512 ps
CPU time 32.49 seconds
Started Jun 27 04:55:52 PM PDT 24
Finished Jun 27 04:56:26 PM PDT 24
Peak memory 199924 kb
Host smart-2af5b149-a793-4001-8f84-f0ad7c86760e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127503397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.2127503397
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.500914876
Short name T748
Test name
Test status
Simulation time 22337804 ps
CPU time 0.56 seconds
Started Jun 27 04:55:57 PM PDT 24
Finished Jun 27 04:56:03 PM PDT 24
Peak memory 194760 kb
Host smart-36f01348-6c87-4793-8e69-a1a1a8d286b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500914876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.500914876
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.215231498
Short name T281
Test name
Test status
Simulation time 154583040682 ps
CPU time 212.68 seconds
Started Jun 27 04:55:52 PM PDT 24
Finished Jun 27 04:59:26 PM PDT 24
Peak memory 200180 kb
Host smart-f3eb3fed-f21c-49f6-96d7-f140944234bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215231498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.215231498
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.2328717164
Short name T382
Test name
Test status
Simulation time 20001514354 ps
CPU time 12.97 seconds
Started Jun 27 04:55:55 PM PDT 24
Finished Jun 27 04:56:12 PM PDT 24
Peak memory 199880 kb
Host smart-58e9151b-15e5-492d-a515-fa0acd2a9afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328717164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.2328717164
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.1314397841
Short name T886
Test name
Test status
Simulation time 101625411099 ps
CPU time 41.06 seconds
Started Jun 27 04:55:57 PM PDT 24
Finished Jun 27 04:56:43 PM PDT 24
Peak memory 199984 kb
Host smart-fe3680dd-be43-4d49-8154-261bb45f5c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314397841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1314397841
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.2562608934
Short name T269
Test name
Test status
Simulation time 49733446700 ps
CPU time 20.06 seconds
Started Jun 27 04:55:57 PM PDT 24
Finished Jun 27 04:56:22 PM PDT 24
Peak memory 199888 kb
Host smart-e023eb32-478f-440c-8e3c-f246ad3f650f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562608934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2562608934
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.3491964041
Short name T431
Test name
Test status
Simulation time 99525609935 ps
CPU time 382.78 seconds
Started Jun 27 04:55:54 PM PDT 24
Finished Jun 27 05:02:19 PM PDT 24
Peak memory 199788 kb
Host smart-4982b2e6-6bf6-4115-b08f-4cd3523f7212
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3491964041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3491964041
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.1268761488
Short name T470
Test name
Test status
Simulation time 3060712157 ps
CPU time 1.96 seconds
Started Jun 27 04:55:58 PM PDT 24
Finished Jun 27 04:56:05 PM PDT 24
Peak memory 197908 kb
Host smart-eb95ea89-4e8b-466e-8e22-45c93fb4eb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268761488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1268761488
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_perf.2225792402
Short name T592
Test name
Test status
Simulation time 13988905371 ps
CPU time 686.75 seconds
Started Jun 27 04:55:56 PM PDT 24
Finished Jun 27 05:07:28 PM PDT 24
Peak memory 199968 kb
Host smart-f49768e3-dbe5-4c62-bb9d-d51829c338e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2225792402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2225792402
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.3091546507
Short name T1018
Test name
Test status
Simulation time 6370432396 ps
CPU time 52.53 seconds
Started Jun 27 04:55:56 PM PDT 24
Finished Jun 27 04:56:54 PM PDT 24
Peak memory 198284 kb
Host smart-147e8a8f-1804-48ef-9f23-bdf18f126178
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3091546507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3091546507
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.2705319299
Short name T825
Test name
Test status
Simulation time 108111858181 ps
CPU time 77.65 seconds
Started Jun 27 04:55:58 PM PDT 24
Finished Jun 27 04:57:20 PM PDT 24
Peak memory 199928 kb
Host smart-b012e6d8-93fb-4829-8cf2-779b9ae2de52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705319299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.2705319299
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.336016840
Short name T289
Test name
Test status
Simulation time 6065624295 ps
CPU time 1.95 seconds
Started Jun 27 04:55:53 PM PDT 24
Finished Jun 27 04:55:58 PM PDT 24
Peak memory 196220 kb
Host smart-039587ca-c802-49ee-8f10-113ad6ef2a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336016840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.336016840
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.310235202
Short name T879
Test name
Test status
Simulation time 848634779 ps
CPU time 3.02 seconds
Started Jun 27 04:55:54 PM PDT 24
Finished Jun 27 04:56:01 PM PDT 24
Peak memory 199416 kb
Host smart-b2739dcc-b7a8-4087-a978-4b055d840ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310235202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.310235202
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.1782161216
Short name T842
Test name
Test status
Simulation time 97475726493 ps
CPU time 360.41 seconds
Started Jun 27 04:55:54 PM PDT 24
Finished Jun 27 05:01:57 PM PDT 24
Peak memory 209880 kb
Host smart-21fe8142-9e8d-42be-ba05-97e2aee6299c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782161216 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1782161216
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.3245400551
Short name T10
Test name
Test status
Simulation time 1718066852 ps
CPU time 2.3 seconds
Started Jun 27 04:55:51 PM PDT 24
Finished Jun 27 04:55:54 PM PDT 24
Peak memory 198616 kb
Host smart-ac773d01-a69c-41b6-816a-9d25362da1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245400551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3245400551
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.3347988107
Short name T526
Test name
Test status
Simulation time 33649933385 ps
CPU time 11.85 seconds
Started Jun 27 04:55:53 PM PDT 24
Finished Jun 27 04:56:08 PM PDT 24
Peak memory 198688 kb
Host smart-a9fe3cb0-6ab5-4842-9558-644e88743dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347988107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3347988107
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3008454925
Short name T522
Test name
Test status
Simulation time 46465776 ps
CPU time 0.55 seconds
Started Jun 27 04:56:00 PM PDT 24
Finished Jun 27 04:56:05 PM PDT 24
Peak memory 195304 kb
Host smart-affc1cff-e410-4040-bb66-6c33fa3bd64a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008454925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3008454925
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.2615526507
Short name T680
Test name
Test status
Simulation time 122299424730 ps
CPU time 44.16 seconds
Started Jun 27 04:55:56 PM PDT 24
Finished Jun 27 04:56:45 PM PDT 24
Peak memory 199888 kb
Host smart-00ce7b1b-b729-4aef-b7d6-39e81bfc2d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615526507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2615526507
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1724939151
Short name T624
Test name
Test status
Simulation time 240817499703 ps
CPU time 69.54 seconds
Started Jun 27 04:55:56 PM PDT 24
Finished Jun 27 04:57:10 PM PDT 24
Peak memory 199912 kb
Host smart-c4a4b604-6cf8-4c3d-a468-f4184fc989d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724939151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1724939151
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.1332300872
Short name T153
Test name
Test status
Simulation time 117861796900 ps
CPU time 22.73 seconds
Started Jun 27 04:55:57 PM PDT 24
Finished Jun 27 04:56:25 PM PDT 24
Peak memory 199900 kb
Host smart-af91cf15-d961-4a44-ae62-411e7f4e57ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332300872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1332300872
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3655169630
Short name T93
Test name
Test status
Simulation time 15308904660 ps
CPU time 20.82 seconds
Started Jun 27 04:55:56 PM PDT 24
Finished Jun 27 04:56:21 PM PDT 24
Peak memory 199940 kb
Host smart-8b57a7e2-f41a-430d-a6b5-1353c9e5d97a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655169630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3655169630
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.1246274421
Short name T902
Test name
Test status
Simulation time 81525994522 ps
CPU time 367.62 seconds
Started Jun 27 04:55:59 PM PDT 24
Finished Jun 27 05:02:11 PM PDT 24
Peak memory 199908 kb
Host smart-ae089b6c-45f5-40fa-ae00-2998c2215e29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1246274421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1246274421
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1245812644
Short name T706
Test name
Test status
Simulation time 6481213924 ps
CPU time 17.06 seconds
Started Jun 27 04:55:59 PM PDT 24
Finished Jun 27 04:56:21 PM PDT 24
Peak memory 199904 kb
Host smart-1843c7c8-f666-4956-8190-d1578cc96b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245812644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1245812644
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_perf.3198471228
Short name T971
Test name
Test status
Simulation time 13290956206 ps
CPU time 185.26 seconds
Started Jun 27 04:55:59 PM PDT 24
Finished Jun 27 04:59:09 PM PDT 24
Peak memory 199904 kb
Host smart-134330fd-237d-45e4-8bbd-eb25e58eff29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3198471228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.3198471228
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.4074782643
Short name T396
Test name
Test status
Simulation time 4213362528 ps
CPU time 9.39 seconds
Started Jun 27 04:55:59 PM PDT 24
Finished Jun 27 04:56:13 PM PDT 24
Peak memory 198600 kb
Host smart-5a96d774-38a7-487e-ac28-a9b8e24f8728
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4074782643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.4074782643
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2505638700
Short name T1068
Test name
Test status
Simulation time 82361997461 ps
CPU time 145.89 seconds
Started Jun 27 04:55:56 PM PDT 24
Finished Jun 27 04:58:27 PM PDT 24
Peak memory 199928 kb
Host smart-06e51c07-f989-46ff-9f0c-e2ce7110ec94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505638700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2505638700
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.1571920620
Short name T308
Test name
Test status
Simulation time 4365963092 ps
CPU time 5.84 seconds
Started Jun 27 04:55:58 PM PDT 24
Finished Jun 27 04:56:09 PM PDT 24
Peak memory 196360 kb
Host smart-7768a5ec-9aba-4d93-b7a4-fbb4b67c9074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571920620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1571920620
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.1267934316
Short name T969
Test name
Test status
Simulation time 628914398 ps
CPU time 2.11 seconds
Started Jun 27 04:55:54 PM PDT 24
Finished Jun 27 04:56:00 PM PDT 24
Peak memory 198440 kb
Host smart-aecd40bd-011c-4dff-8598-83d3fea0f75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267934316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.1267934316
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.59785073
Short name T312
Test name
Test status
Simulation time 131378306973 ps
CPU time 66.4 seconds
Started Jun 27 04:55:59 PM PDT 24
Finished Jun 27 04:57:10 PM PDT 24
Peak memory 199876 kb
Host smart-32d82507-9fd4-43cd-97a1-23423fe3bdf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59785073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.59785073
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.1258017390
Short name T146
Test name
Test status
Simulation time 29559517509 ps
CPU time 302 seconds
Started Jun 27 04:55:58 PM PDT 24
Finished Jun 27 05:01:05 PM PDT 24
Peak memory 208204 kb
Host smart-634585ae-b873-4f24-9dec-cc68c896e404
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258017390 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1258017390
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.1131362994
Short name T1028
Test name
Test status
Simulation time 7179144301 ps
CPU time 16.91 seconds
Started Jun 27 04:55:57 PM PDT 24
Finished Jun 27 04:56:19 PM PDT 24
Peak memory 199404 kb
Host smart-90e21546-bf86-436d-bb26-a8e4f9fa90f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131362994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1131362994
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.142350699
Short name T430
Test name
Test status
Simulation time 70950597526 ps
CPU time 28.84 seconds
Started Jun 27 04:55:55 PM PDT 24
Finished Jun 27 04:56:28 PM PDT 24
Peak memory 199896 kb
Host smart-fdb93e22-b4b4-47af-9002-47d81cece64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142350699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.142350699
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.3565877747
Short name T702
Test name
Test status
Simulation time 58266785 ps
CPU time 0.56 seconds
Started Jun 27 04:56:04 PM PDT 24
Finished Jun 27 04:56:08 PM PDT 24
Peak memory 194888 kb
Host smart-a60d9bf7-c10d-497c-b7bb-d9fe95d61942
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565877747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.3565877747
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.126561305
Short name T506
Test name
Test status
Simulation time 102871400461 ps
CPU time 145.94 seconds
Started Jun 27 04:56:00 PM PDT 24
Finished Jun 27 04:58:31 PM PDT 24
Peak memory 199972 kb
Host smart-9b00bfeb-d472-4e0a-a1c3-65d1afd828c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126561305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.126561305
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.2161246732
Short name T665
Test name
Test status
Simulation time 57400420608 ps
CPU time 83.99 seconds
Started Jun 27 04:55:56 PM PDT 24
Finished Jun 27 04:57:25 PM PDT 24
Peak memory 199924 kb
Host smart-a5e3bcd7-f4a0-45c5-bffd-55dd5410efaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161246732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2161246732
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.3442043814
Short name T552
Test name
Test status
Simulation time 25464653288 ps
CPU time 17.18 seconds
Started Jun 27 04:56:00 PM PDT 24
Finished Jun 27 04:56:22 PM PDT 24
Peak memory 199896 kb
Host smart-fec14696-c971-4ed1-af7b-7f44d4514fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442043814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3442043814
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.2488561236
Short name T830
Test name
Test status
Simulation time 35737247673 ps
CPU time 29.46 seconds
Started Jun 27 04:55:55 PM PDT 24
Finished Jun 27 04:56:29 PM PDT 24
Peak memory 198208 kb
Host smart-14ff1018-27a8-413c-aa77-91b9e2187d63
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488561236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.2488561236
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.4215293901
Short name T504
Test name
Test status
Simulation time 120904625203 ps
CPU time 335.5 seconds
Started Jun 27 04:56:02 PM PDT 24
Finished Jun 27 05:01:41 PM PDT 24
Peak memory 199820 kb
Host smart-b412b858-331c-4d65-92f0-37bcad8d3d74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4215293901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.4215293901
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.878922676
Short name T763
Test name
Test status
Simulation time 1857135340 ps
CPU time 4.79 seconds
Started Jun 27 04:55:53 PM PDT 24
Finished Jun 27 04:56:01 PM PDT 24
Peak memory 198380 kb
Host smart-ec9fdb2d-13d3-42c9-bfc6-48db79aae5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878922676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.878922676
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_perf.1145186203
Short name T616
Test name
Test status
Simulation time 25925631827 ps
CPU time 551.48 seconds
Started Jun 27 04:56:02 PM PDT 24
Finished Jun 27 05:05:17 PM PDT 24
Peak memory 199848 kb
Host smart-ae0c886b-bcad-4db7-87f9-704b0f2cf7d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1145186203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1145186203
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.2735001121
Short name T15
Test name
Test status
Simulation time 4125700543 ps
CPU time 2.12 seconds
Started Jun 27 04:56:00 PM PDT 24
Finished Jun 27 04:56:07 PM PDT 24
Peak memory 198376 kb
Host smart-b903e280-f979-47b0-bc9c-73b9cf487886
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2735001121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2735001121
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.259207111
Short name T802
Test name
Test status
Simulation time 144919627250 ps
CPU time 123.79 seconds
Started Jun 27 04:56:02 PM PDT 24
Finished Jun 27 04:58:10 PM PDT 24
Peak memory 199448 kb
Host smart-a3523685-7248-4207-97e0-e6581b616e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259207111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.259207111
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.2323793894
Short name T298
Test name
Test status
Simulation time 38117157461 ps
CPU time 16.34 seconds
Started Jun 27 04:55:54 PM PDT 24
Finished Jun 27 04:56:14 PM PDT 24
Peak memory 196100 kb
Host smart-9739a329-5668-4fe2-8f7c-e0c0d650e41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323793894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2323793894
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.3853336723
Short name T852
Test name
Test status
Simulation time 318420232 ps
CPU time 1.46 seconds
Started Jun 27 04:56:00 PM PDT 24
Finished Jun 27 04:56:06 PM PDT 24
Peak memory 198772 kb
Host smart-573f6adc-ea92-407b-94c1-bb788e19659b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853336723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3853336723
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.3406863686
Short name T950
Test name
Test status
Simulation time 565624337250 ps
CPU time 429.67 seconds
Started Jun 27 04:55:54 PM PDT 24
Finished Jun 27 05:03:07 PM PDT 24
Peak memory 199824 kb
Host smart-c0f8a507-acda-432a-8d89-23dc776a48f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406863686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3406863686
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.1189090005
Short name T318
Test name
Test status
Simulation time 97337369065 ps
CPU time 375.27 seconds
Started Jun 27 04:55:56 PM PDT 24
Finished Jun 27 05:02:16 PM PDT 24
Peak memory 210104 kb
Host smart-4c185782-ed3c-4280-923e-666d9c1888be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189090005 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.1189090005
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1152248339
Short name T414
Test name
Test status
Simulation time 8232222411 ps
CPU time 13.04 seconds
Started Jun 27 04:56:02 PM PDT 24
Finished Jun 27 04:56:19 PM PDT 24
Peak memory 199680 kb
Host smart-550621bb-513e-4b2f-9aea-6af15dea890c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152248339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1152248339
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1185722527
Short name T790
Test name
Test status
Simulation time 23312427392 ps
CPU time 9.33 seconds
Started Jun 27 04:55:58 PM PDT 24
Finished Jun 27 04:56:13 PM PDT 24
Peak memory 199640 kb
Host smart-788bdc21-ff50-430c-a1d2-55170da910c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185722527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1185722527
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.707324207
Short name T28
Test name
Test status
Simulation time 37932782 ps
CPU time 0.63 seconds
Started Jun 27 04:53:59 PM PDT 24
Finished Jun 27 04:54:02 PM PDT 24
Peak memory 195368 kb
Host smart-7a8039f0-d371-42a6-b4ca-288c5ca72406
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707324207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.707324207
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.2621029984
Short name T114
Test name
Test status
Simulation time 36468674935 ps
CPU time 18.41 seconds
Started Jun 27 04:53:55 PM PDT 24
Finished Jun 27 04:54:16 PM PDT 24
Peak memory 199908 kb
Host smart-402dd218-3eec-4b63-9ce3-e8cf5c77e87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621029984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2621029984
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3687548041
Short name T380
Test name
Test status
Simulation time 22130261800 ps
CPU time 19.54 seconds
Started Jun 27 04:53:53 PM PDT 24
Finished Jun 27 04:54:15 PM PDT 24
Peak memory 199880 kb
Host smart-5cfc615e-5414-4b33-99cb-650e09b83a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687548041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3687548041
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.1071152624
Short name T117
Test name
Test status
Simulation time 19093419881 ps
CPU time 11.87 seconds
Started Jun 27 04:53:53 PM PDT 24
Finished Jun 27 04:54:06 PM PDT 24
Peak memory 199928 kb
Host smart-3159678a-1e6e-4283-aa05-6a37bc5d2562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071152624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1071152624
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.2088888980
Short name T996
Test name
Test status
Simulation time 26208669265 ps
CPU time 44.82 seconds
Started Jun 27 04:53:54 PM PDT 24
Finished Jun 27 04:54:42 PM PDT 24
Peak memory 199952 kb
Host smart-e4190dfc-f8e5-4092-ae6d-ffa41f7fd237
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088888980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2088888980
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.589570460
Short name T497
Test name
Test status
Simulation time 116270383800 ps
CPU time 300.28 seconds
Started Jun 27 04:53:56 PM PDT 24
Finished Jun 27 04:58:59 PM PDT 24
Peak memory 199808 kb
Host smart-9b49dba2-fa69-44d2-9dcf-db63313261d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=589570460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.589570460
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.1351510292
Short name T900
Test name
Test status
Simulation time 9530436323 ps
CPU time 18.5 seconds
Started Jun 27 04:53:52 PM PDT 24
Finished Jun 27 04:54:11 PM PDT 24
Peak memory 199948 kb
Host smart-07e37e10-ee42-47e8-856f-1b8f39434dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351510292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.1351510292
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_perf.340569120
Short name T261
Test name
Test status
Simulation time 26353063613 ps
CPU time 1016.8 seconds
Started Jun 27 04:53:55 PM PDT 24
Finished Jun 27 05:10:55 PM PDT 24
Peak memory 199896 kb
Host smart-836006c0-dfbc-4342-899c-046948b335f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=340569120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.340569120
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.4277179197
Short name T1005
Test name
Test status
Simulation time 1588891839 ps
CPU time 4.75 seconds
Started Jun 27 04:53:54 PM PDT 24
Finished Jun 27 04:54:01 PM PDT 24
Peak memory 198196 kb
Host smart-0412a100-1089-44d2-b7bd-d30ebdfcd711
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4277179197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.4277179197
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2826547012
Short name T645
Test name
Test status
Simulation time 70393088781 ps
CPU time 27.22 seconds
Started Jun 27 04:54:08 PM PDT 24
Finished Jun 27 04:54:37 PM PDT 24
Peak memory 199716 kb
Host smart-dbadd546-5a4d-4c1a-bebb-eea7c9e4a9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826547012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2826547012
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.3181637635
Short name T365
Test name
Test status
Simulation time 3591661450 ps
CPU time 5.41 seconds
Started Jun 27 04:53:53 PM PDT 24
Finished Jun 27 04:54:00 PM PDT 24
Peak memory 196356 kb
Host smart-97cb55a2-0283-4d03-af1d-2bdbb29044c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181637635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.3181637635
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.1353770569
Short name T84
Test name
Test status
Simulation time 118072597 ps
CPU time 0.87 seconds
Started Jun 27 04:53:56 PM PDT 24
Finished Jun 27 04:53:59 PM PDT 24
Peak memory 218148 kb
Host smart-8b665691-94a5-4f5c-bcd5-e6b0a9abf1e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353770569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.1353770569
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.960480882
Short name T933
Test name
Test status
Simulation time 6001883549 ps
CPU time 10.77 seconds
Started Jun 27 04:53:54 PM PDT 24
Finished Jun 27 04:54:07 PM PDT 24
Peak memory 199784 kb
Host smart-729ecf19-7d35-4654-a4bc-da5101e4407e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960480882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.960480882
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.1679448275
Short name T859
Test name
Test status
Simulation time 2271110362 ps
CPU time 2.1 seconds
Started Jun 27 04:53:57 PM PDT 24
Finished Jun 27 04:54:02 PM PDT 24
Peak memory 198700 kb
Host smart-182c23f5-1a93-4081-ae72-9e7a103e1b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679448275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.1679448275
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.796723085
Short name T644
Test name
Test status
Simulation time 60453371536 ps
CPU time 140.55 seconds
Started Jun 27 04:53:54 PM PDT 24
Finished Jun 27 04:56:16 PM PDT 24
Peak memory 199860 kb
Host smart-54fc38b6-629c-403b-ade9-adf97521befd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796723085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.796723085
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.3878362309
Short name T1024
Test name
Test status
Simulation time 11641894 ps
CPU time 0.54 seconds
Started Jun 27 04:56:02 PM PDT 24
Finished Jun 27 04:56:07 PM PDT 24
Peak memory 195516 kb
Host smart-2fec507c-ba3e-4d7c-997f-8555a3a2b8fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878362309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3878362309
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.1946747896
Short name T542
Test name
Test status
Simulation time 124458123164 ps
CPU time 61.96 seconds
Started Jun 27 04:56:04 PM PDT 24
Finished Jun 27 04:57:10 PM PDT 24
Peak memory 199892 kb
Host smart-711b608c-f69c-4751-b5b7-fb4594585c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946747896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1946747896
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.2267298316
Short name T181
Test name
Test status
Simulation time 39020646325 ps
CPU time 35.03 seconds
Started Jun 27 04:55:56 PM PDT 24
Finished Jun 27 04:56:37 PM PDT 24
Peak memory 199916 kb
Host smart-4e07accd-9a94-4c0a-8b2d-cfec9ae35b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267298316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.2267298316
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.931122518
Short name T883
Test name
Test status
Simulation time 13763934036 ps
CPU time 20.87 seconds
Started Jun 27 04:56:04 PM PDT 24
Finished Jun 27 04:56:29 PM PDT 24
Peak memory 197104 kb
Host smart-a55bfa48-da55-4214-9eca-973504fef139
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931122518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.931122518
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.3290028983
Short name T960
Test name
Test status
Simulation time 67417454913 ps
CPU time 377.65 seconds
Started Jun 27 04:56:04 PM PDT 24
Finished Jun 27 05:02:25 PM PDT 24
Peak memory 199864 kb
Host smart-5e6370cc-cb6e-4124-8ed4-272bc979a659
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3290028983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3290028983
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.3864660735
Short name T60
Test name
Test status
Simulation time 10197559417 ps
CPU time 19.4 seconds
Started Jun 27 04:56:02 PM PDT 24
Finished Jun 27 04:56:26 PM PDT 24
Peak memory 199800 kb
Host smart-be2f3f33-f0a6-4ec9-b7b5-618a5d25a2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864660735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3864660735
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_perf.2995158865
Short name T712
Test name
Test status
Simulation time 23608762408 ps
CPU time 1164.35 seconds
Started Jun 27 04:56:04 PM PDT 24
Finished Jun 27 05:15:32 PM PDT 24
Peak memory 199992 kb
Host smart-15abfaaa-2547-4b6a-8308-c369c361a9af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2995158865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2995158865
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.2090052630
Short name T408
Test name
Test status
Simulation time 7117296997 ps
CPU time 17.74 seconds
Started Jun 27 04:56:03 PM PDT 24
Finished Jun 27 04:56:24 PM PDT 24
Peak memory 199072 kb
Host smart-1cdd7a74-0805-4985-9023-a79dddf20b38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2090052630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.2090052630
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.3012748034
Short name T485
Test name
Test status
Simulation time 25992249580 ps
CPU time 15.84 seconds
Started Jun 27 04:56:00 PM PDT 24
Finished Jun 27 04:56:20 PM PDT 24
Peak memory 199880 kb
Host smart-f958bb7b-36ec-451a-a4ca-90b0071404d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012748034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3012748034
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.1687617948
Short name T979
Test name
Test status
Simulation time 6190436865 ps
CPU time 9.15 seconds
Started Jun 27 04:55:56 PM PDT 24
Finished Jun 27 04:56:10 PM PDT 24
Peak memory 195980 kb
Host smart-068a2a31-af07-41b0-baad-f48c31724e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687617948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1687617948
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.1749494274
Short name T445
Test name
Test status
Simulation time 669681209 ps
CPU time 1.61 seconds
Started Jun 27 04:55:58 PM PDT 24
Finished Jun 27 04:56:04 PM PDT 24
Peak memory 199748 kb
Host smart-711077d8-5bec-4b7e-97f7-dfb089ad88f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749494274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.1749494274
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.2208812515
Short name T1033
Test name
Test status
Simulation time 5951016120 ps
CPU time 14.46 seconds
Started Jun 27 04:56:03 PM PDT 24
Finished Jun 27 04:56:22 PM PDT 24
Peak memory 199752 kb
Host smart-2bdfc656-9fd0-4818-92f1-d1185f59a138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208812515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2208812515
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.1862397425
Short name T608
Test name
Test status
Simulation time 70122468517 ps
CPU time 32.74 seconds
Started Jun 27 04:56:01 PM PDT 24
Finished Jun 27 04:56:38 PM PDT 24
Peak memory 199812 kb
Host smart-3515014d-0286-4539-b9b4-fa81a7be1b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862397425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1862397425
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.2998826358
Short name T339
Test name
Test status
Simulation time 17028450 ps
CPU time 0.55 seconds
Started Jun 27 04:56:10 PM PDT 24
Finished Jun 27 04:56:12 PM PDT 24
Peak memory 195584 kb
Host smart-e0d70f1b-00af-46b9-99ba-799e7dcc5b15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998826358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2998826358
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3743561714
Short name T692
Test name
Test status
Simulation time 126914474570 ps
CPU time 62.93 seconds
Started Jun 27 04:55:58 PM PDT 24
Finished Jun 27 04:57:06 PM PDT 24
Peak memory 199900 kb
Host smart-53fc74a5-8f8b-4cb3-8399-17c46010286e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743561714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3743561714
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.597863986
Short name T1038
Test name
Test status
Simulation time 316356709108 ps
CPU time 92.03 seconds
Started Jun 27 04:56:00 PM PDT 24
Finished Jun 27 04:57:36 PM PDT 24
Peak memory 199916 kb
Host smart-03ad33e6-bbc2-4f54-88fd-aa4caa4bb090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597863986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.597863986
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.2409133447
Short name T14
Test name
Test status
Simulation time 15755460554 ps
CPU time 21.96 seconds
Started Jun 27 04:55:58 PM PDT 24
Finished Jun 27 04:56:25 PM PDT 24
Peak memory 199896 kb
Host smart-62d1b319-4d52-4ddd-9947-4f0c94b6ae39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409133447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2409133447
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.3075821750
Short name T502
Test name
Test status
Simulation time 12382356987 ps
CPU time 27.5 seconds
Started Jun 27 04:55:59 PM PDT 24
Finished Jun 27 04:56:32 PM PDT 24
Peak memory 199912 kb
Host smart-e212f22a-c524-4ee8-a071-6f548c1c25ba
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075821750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.3075821750
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.2952251725
Short name T278
Test name
Test status
Simulation time 144156427152 ps
CPU time 250.74 seconds
Started Jun 27 04:55:59 PM PDT 24
Finished Jun 27 05:00:14 PM PDT 24
Peak memory 199884 kb
Host smart-55ed5acc-6a8f-466c-87f6-349d169fd019
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2952251725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.2952251725
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.3539600055
Short name T1045
Test name
Test status
Simulation time 10702114610 ps
CPU time 4.06 seconds
Started Jun 27 04:56:06 PM PDT 24
Finished Jun 27 04:56:13 PM PDT 24
Peak memory 198220 kb
Host smart-7c256c2a-d6fb-46bc-a31e-f4c0ada5a791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539600055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3539600055
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_perf.49047519
Short name T989
Test name
Test status
Simulation time 6093830584 ps
CPU time 71.05 seconds
Started Jun 27 04:56:00 PM PDT 24
Finished Jun 27 04:57:16 PM PDT 24
Peak memory 199860 kb
Host smart-e48c9a9d-2cb2-4cb5-8092-4a0493b6b283
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=49047519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.49047519
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.3618334628
Short name T347
Test name
Test status
Simulation time 4798551501 ps
CPU time 10.04 seconds
Started Jun 27 04:55:57 PM PDT 24
Finished Jun 27 04:56:12 PM PDT 24
Peak memory 199028 kb
Host smart-93e811bf-b878-481a-b21f-7663d363c1d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3618334628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3618334628
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.888468613
Short name T631
Test name
Test status
Simulation time 76731695036 ps
CPU time 7.18 seconds
Started Jun 27 04:55:58 PM PDT 24
Finished Jun 27 04:56:11 PM PDT 24
Peak memory 199860 kb
Host smart-fd553a39-7958-492d-bb54-49a341e49a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888468613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.888468613
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.3609477341
Short name T449
Test name
Test status
Simulation time 1022102788 ps
CPU time 1.91 seconds
Started Jun 27 04:55:56 PM PDT 24
Finished Jun 27 04:56:03 PM PDT 24
Peak memory 195572 kb
Host smart-aa9ac901-5c0f-4f2e-9c31-e2f4e3d37d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609477341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3609477341
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.1990771168
Short name T405
Test name
Test status
Simulation time 525210927 ps
CPU time 1.37 seconds
Started Jun 27 04:55:56 PM PDT 24
Finished Jun 27 04:56:03 PM PDT 24
Peak memory 198764 kb
Host smart-bea7e4d9-9d6e-4b86-a3cd-c33a38d71858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990771168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.1990771168
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.3299220381
Short name T100
Test name
Test status
Simulation time 77195343089 ps
CPU time 126.73 seconds
Started Jun 27 04:56:13 PM PDT 24
Finished Jun 27 04:58:22 PM PDT 24
Peak memory 199960 kb
Host smart-1f6d283f-31c5-4d02-bdd7-a98e7e20a3c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299220381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3299220381
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.100624785
Short name T944
Test name
Test status
Simulation time 7690120371 ps
CPU time 12.62 seconds
Started Jun 27 04:56:00 PM PDT 24
Finished Jun 27 04:56:17 PM PDT 24
Peak memory 199812 kb
Host smart-552f3d0b-753a-4780-9673-c25e715149db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100624785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.100624785
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.379167285
Short name T990
Test name
Test status
Simulation time 122799392606 ps
CPU time 261.78 seconds
Started Jun 27 04:56:00 PM PDT 24
Finished Jun 27 05:00:26 PM PDT 24
Peak memory 199932 kb
Host smart-ea53da9b-d58d-4e6a-832a-83299fc95bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379167285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.379167285
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.2265906083
Short name T27
Test name
Test status
Simulation time 12663501 ps
CPU time 0.56 seconds
Started Jun 27 04:56:14 PM PDT 24
Finished Jun 27 04:56:17 PM PDT 24
Peak memory 194280 kb
Host smart-25739db9-1b8d-46fe-9690-745dbe06f0dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265906083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.2265906083
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.315069451
Short name T309
Test name
Test status
Simulation time 51248999052 ps
CPU time 36.17 seconds
Started Jun 27 04:56:12 PM PDT 24
Finished Jun 27 04:56:50 PM PDT 24
Peak memory 199848 kb
Host smart-9097143a-5cd4-4398-8107-6dfc9ca620f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315069451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.315069451
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1728179632
Short name T397
Test name
Test status
Simulation time 152390868391 ps
CPU time 56.88 seconds
Started Jun 27 04:56:14 PM PDT 24
Finished Jun 27 04:57:13 PM PDT 24
Peak memory 199868 kb
Host smart-28808edc-d7fd-4a99-9e05-a334f852b61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728179632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1728179632
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.1813625013
Short name T924
Test name
Test status
Simulation time 114803147677 ps
CPU time 50.53 seconds
Started Jun 27 04:56:10 PM PDT 24
Finished Jun 27 04:57:02 PM PDT 24
Peak memory 199944 kb
Host smart-d2a9f91f-407d-45a2-b185-29e7c9e4e999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813625013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.1813625013
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.4237676225
Short name T362
Test name
Test status
Simulation time 3252192133 ps
CPU time 1.82 seconds
Started Jun 27 04:56:09 PM PDT 24
Finished Jun 27 04:56:13 PM PDT 24
Peak memory 195868 kb
Host smart-39e76142-263c-44d4-a800-9092259a7a1e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237676225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.4237676225
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.2972837092
Short name T465
Test name
Test status
Simulation time 53583552520 ps
CPU time 159.06 seconds
Started Jun 27 04:56:15 PM PDT 24
Finished Jun 27 04:58:56 PM PDT 24
Peak memory 199828 kb
Host smart-649b3ef0-fdb8-440f-8301-173fdd51f2ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2972837092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2972837092
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.2810157607
Short name T646
Test name
Test status
Simulation time 81812124 ps
CPU time 0.66 seconds
Started Jun 27 04:56:09 PM PDT 24
Finished Jun 27 04:56:12 PM PDT 24
Peak memory 195848 kb
Host smart-36fdd68a-33ed-4258-942e-3723a901e529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810157607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.2810157607
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_perf.2910714937
Short name T803
Test name
Test status
Simulation time 18172011779 ps
CPU time 700.92 seconds
Started Jun 27 04:56:13 PM PDT 24
Finished Jun 27 05:07:56 PM PDT 24
Peak memory 199676 kb
Host smart-4a8c59cc-8cd3-4fd0-bfd0-a35fa9c1605d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2910714937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2910714937
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.176240449
Short name T359
Test name
Test status
Simulation time 1489716689 ps
CPU time 3.09 seconds
Started Jun 27 04:56:10 PM PDT 24
Finished Jun 27 04:56:15 PM PDT 24
Peak memory 197936 kb
Host smart-8ccb7cb3-807f-4d40-a9b8-570f7583caf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=176240449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.176240449
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.3397254868
Short name T545
Test name
Test status
Simulation time 8468827572 ps
CPU time 17.04 seconds
Started Jun 27 04:56:10 PM PDT 24
Finished Jun 27 04:56:29 PM PDT 24
Peak memory 199796 kb
Host smart-2be46a88-9ed2-4358-a3fa-ac45f3f47d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397254868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3397254868
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.1261616216
Short name T478
Test name
Test status
Simulation time 2053574717 ps
CPU time 2.1 seconds
Started Jun 27 04:56:09 PM PDT 24
Finished Jun 27 04:56:13 PM PDT 24
Peak memory 195344 kb
Host smart-ac31a76b-cac9-44a1-a637-b606a504bbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261616216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1261616216
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3666493968
Short name T488
Test name
Test status
Simulation time 918593535 ps
CPU time 1.67 seconds
Started Jun 27 04:56:10 PM PDT 24
Finished Jun 27 04:56:14 PM PDT 24
Peak memory 198772 kb
Host smart-1a9d83bb-b87a-499c-9361-e4c1e241bb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666493968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3666493968
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.3737839669
Short name T110
Test name
Test status
Simulation time 333486333424 ps
CPU time 111.77 seconds
Started Jun 27 04:56:10 PM PDT 24
Finished Jun 27 04:58:03 PM PDT 24
Peak memory 199756 kb
Host smart-b5faf338-6930-4372-a93d-b7326f82b537
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737839669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.3737839669
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3043989287
Short name T943
Test name
Test status
Simulation time 69993164921 ps
CPU time 352.23 seconds
Started Jun 27 04:56:14 PM PDT 24
Finished Jun 27 05:02:08 PM PDT 24
Peak memory 216344 kb
Host smart-29b32682-2594-4719-81de-cb1c365506ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043989287 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3043989287
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.2040080881
Short name T274
Test name
Test status
Simulation time 1217675327 ps
CPU time 4.09 seconds
Started Jun 27 04:56:10 PM PDT 24
Finished Jun 27 04:56:16 PM PDT 24
Peak memory 199784 kb
Host smart-1c151026-b821-4607-bd86-da9e06df2734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040080881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2040080881
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.666906373
Short name T499
Test name
Test status
Simulation time 115932731327 ps
CPU time 113.69 seconds
Started Jun 27 04:56:11 PM PDT 24
Finished Jun 27 04:58:07 PM PDT 24
Peak memory 199996 kb
Host smart-4c29109e-c424-4863-aa0b-91bab9dea56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666906373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.666906373
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.3105792578
Short name T701
Test name
Test status
Simulation time 28808393 ps
CPU time 0.55 seconds
Started Jun 27 04:56:13 PM PDT 24
Finished Jun 27 04:56:16 PM PDT 24
Peak memory 195304 kb
Host smart-a128686c-3ea0-47f6-bacd-a63a60580501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105792578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3105792578
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.273802950
Short name T797
Test name
Test status
Simulation time 42255883356 ps
CPU time 18.07 seconds
Started Jun 27 04:56:19 PM PDT 24
Finished Jun 27 04:56:39 PM PDT 24
Peak memory 199980 kb
Host smart-d1c469cb-7c6c-4eed-8c68-498b2a4b9069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273802950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.273802950
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.465571483
Short name T653
Test name
Test status
Simulation time 16262629710 ps
CPU time 28.65 seconds
Started Jun 27 04:56:08 PM PDT 24
Finished Jun 27 04:56:38 PM PDT 24
Peak memory 199884 kb
Host smart-3ae0d703-c1f5-4858-b3c3-2807263dee07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465571483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.465571483
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.3699265571
Short name T301
Test name
Test status
Simulation time 65840820721 ps
CPU time 127.7 seconds
Started Jun 27 04:56:15 PM PDT 24
Finished Jun 27 04:58:25 PM PDT 24
Peak memory 199672 kb
Host smart-4d658b23-a147-413c-9736-22ed03dfbf15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699265571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3699265571
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.4087686480
Short name T654
Test name
Test status
Simulation time 7924618708 ps
CPU time 11.72 seconds
Started Jun 27 04:56:12 PM PDT 24
Finished Jun 27 04:56:26 PM PDT 24
Peak memory 196416 kb
Host smart-243b7ecc-a6b3-4cae-be40-442af5a54b2e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087686480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.4087686480
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.4262416933
Short name T292
Test name
Test status
Simulation time 158707523832 ps
CPU time 90.95 seconds
Started Jun 27 04:56:12 PM PDT 24
Finished Jun 27 04:57:45 PM PDT 24
Peak memory 199972 kb
Host smart-460a2643-e3c6-4158-886c-8b48e2bf8f00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4262416933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.4262416933
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.2917876628
Short name T1013
Test name
Test status
Simulation time 8287094491 ps
CPU time 8.43 seconds
Started Jun 27 04:56:09 PM PDT 24
Finished Jun 27 04:56:20 PM PDT 24
Peak memory 199872 kb
Host smart-75bb3cd9-9193-4120-b4bb-2af935602e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917876628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.2917876628
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.2240398026
Short name T686
Test name
Test status
Simulation time 10192878325 ps
CPU time 8.44 seconds
Started Jun 27 04:56:11 PM PDT 24
Finished Jun 27 04:56:22 PM PDT 24
Peak memory 197104 kb
Host smart-5982741e-1d47-4ccb-8a26-140512d65e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240398026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2240398026
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.3017570574
Short name T257
Test name
Test status
Simulation time 13748366294 ps
CPU time 188.58 seconds
Started Jun 27 04:56:13 PM PDT 24
Finished Jun 27 04:59:24 PM PDT 24
Peak memory 199716 kb
Host smart-4f0a6499-20db-4e45-b698-6e5ce5f07570
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3017570574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.3017570574
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.405241403
Short name T415
Test name
Test status
Simulation time 3270859807 ps
CPU time 18.15 seconds
Started Jun 27 04:56:15 PM PDT 24
Finished Jun 27 04:56:35 PM PDT 24
Peak memory 197964 kb
Host smart-6eb125b3-9f32-467f-a263-ab05b391325c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=405241403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.405241403
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.825852666
Short name T451
Test name
Test status
Simulation time 18729573445 ps
CPU time 14.38 seconds
Started Jun 27 04:56:20 PM PDT 24
Finished Jun 27 04:56:36 PM PDT 24
Peak memory 199984 kb
Host smart-cbe545cc-5108-4fbf-a04f-b405d33e8f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825852666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.825852666
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.4063465497
Short name T447
Test name
Test status
Simulation time 1566412245 ps
CPU time 1.25 seconds
Started Jun 27 04:56:09 PM PDT 24
Finished Jun 27 04:56:12 PM PDT 24
Peak memory 195452 kb
Host smart-968bd307-01f5-4f96-8e14-c4fbb5052f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063465497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.4063465497
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.2454395428
Short name T856
Test name
Test status
Simulation time 289047712 ps
CPU time 1.05 seconds
Started Jun 27 04:56:14 PM PDT 24
Finished Jun 27 04:56:17 PM PDT 24
Peak memory 198236 kb
Host smart-28c13a4a-1581-436c-ba0f-8ea287890a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454395428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.2454395428
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.3271055048
Short name T637
Test name
Test status
Simulation time 132837839812 ps
CPU time 976.16 seconds
Started Jun 27 04:56:20 PM PDT 24
Finished Jun 27 05:12:38 PM PDT 24
Peak memory 216212 kb
Host smart-daa7b0ee-4866-479d-9074-0a02b741d979
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271055048 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.3271055048
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3512708238
Short name T549
Test name
Test status
Simulation time 505361845 ps
CPU time 1.73 seconds
Started Jun 27 04:56:15 PM PDT 24
Finished Jun 27 04:56:19 PM PDT 24
Peak memory 198020 kb
Host smart-649d0a17-a7ec-4a56-be56-d86fd6cb2766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512708238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3512708238
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.4073340941
Short name T799
Test name
Test status
Simulation time 18615114969 ps
CPU time 26.52 seconds
Started Jun 27 04:56:14 PM PDT 24
Finished Jun 27 04:56:43 PM PDT 24
Peak memory 199912 kb
Host smart-0714d3fe-bb7b-4d44-b103-711dcc213859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073340941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.4073340941
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.3348813307
Short name T351
Test name
Test status
Simulation time 12083843 ps
CPU time 0.54 seconds
Started Jun 27 04:56:13 PM PDT 24
Finished Jun 27 04:56:16 PM PDT 24
Peak memory 195304 kb
Host smart-17003eb3-692e-454a-a751-2685c01d9516
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348813307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3348813307
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.168670342
Short name T387
Test name
Test status
Simulation time 58636841087 ps
CPU time 57.94 seconds
Started Jun 27 04:56:11 PM PDT 24
Finished Jun 27 04:57:10 PM PDT 24
Peak memory 199992 kb
Host smart-6815edaa-ae77-421a-adf5-df1392c3df5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168670342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.168670342
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.473664724
Short name T123
Test name
Test status
Simulation time 42021358851 ps
CPU time 17.33 seconds
Started Jun 27 04:56:11 PM PDT 24
Finished Jun 27 04:56:30 PM PDT 24
Peak memory 199896 kb
Host smart-f2ee79d6-bf9a-4c69-8f22-40083ad149b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473664724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.473664724
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.1926912267
Short name T330
Test name
Test status
Simulation time 330975308400 ps
CPU time 191.79 seconds
Started Jun 27 04:56:11 PM PDT 24
Finished Jun 27 04:59:25 PM PDT 24
Peak memory 199988 kb
Host smart-d2ce2e62-f95f-480a-9d0c-ffc8d8ce112b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926912267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.1926912267
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.4212107961
Short name T366
Test name
Test status
Simulation time 298463298391 ps
CPU time 465.36 seconds
Started Jun 27 04:56:12 PM PDT 24
Finished Jun 27 05:03:59 PM PDT 24
Peak memory 198404 kb
Host smart-ad076183-ff59-4f85-8fed-9d6baf5394ca
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212107961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.4212107961
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.1956909178
Short name T490
Test name
Test status
Simulation time 73034383888 ps
CPU time 171.52 seconds
Started Jun 27 04:56:13 PM PDT 24
Finished Jun 27 04:59:07 PM PDT 24
Peak memory 199976 kb
Host smart-bf1ad195-ce7b-4aca-ae3b-d3ad2a357575
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1956909178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1956909178
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1053086541
Short name T393
Test name
Test status
Simulation time 3829101295 ps
CPU time 10.55 seconds
Started Jun 27 04:56:17 PM PDT 24
Finished Jun 27 04:56:29 PM PDT 24
Peak memory 199548 kb
Host smart-fe4a7341-67c8-4956-a412-6b3a99f35037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053086541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1053086541
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_perf.113869512
Short name T493
Test name
Test status
Simulation time 9991476793 ps
CPU time 107.88 seconds
Started Jun 27 04:56:20 PM PDT 24
Finished Jun 27 04:58:10 PM PDT 24
Peak memory 199748 kb
Host smart-38c069a5-5c83-46ec-a8ba-1dc09bd775c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=113869512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.113869512
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.3782904824
Short name T567
Test name
Test status
Simulation time 4530947224 ps
CPU time 9.88 seconds
Started Jun 27 04:56:19 PM PDT 24
Finished Jun 27 04:56:30 PM PDT 24
Peak memory 198112 kb
Host smart-62183981-289d-4d8c-8b8d-5933960a7529
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3782904824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3782904824
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1825864382
Short name T147
Test name
Test status
Simulation time 109787377189 ps
CPU time 18.61 seconds
Started Jun 27 04:56:14 PM PDT 24
Finished Jun 27 04:56:35 PM PDT 24
Peak memory 199900 kb
Host smart-b04e5ff2-b2bd-448d-b71c-a459edbc0ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825864382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1825864382
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.2478627958
Short name T1026
Test name
Test status
Simulation time 2163553916 ps
CPU time 3.57 seconds
Started Jun 27 04:56:13 PM PDT 24
Finished Jun 27 04:56:19 PM PDT 24
Peak memory 195396 kb
Host smart-a078d069-4fa3-40f9-abfc-ad43b1e6d377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478627958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2478627958
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.3320148872
Short name T9
Test name
Test status
Simulation time 121315939 ps
CPU time 1.02 seconds
Started Jun 27 04:56:09 PM PDT 24
Finished Jun 27 04:56:12 PM PDT 24
Peak memory 198700 kb
Host smart-082e8a84-1d8f-42a0-bda8-b97401893ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320148872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3320148872
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.1787243088
Short name T90
Test name
Test status
Simulation time 49155466003 ps
CPU time 170.64 seconds
Started Jun 27 04:56:20 PM PDT 24
Finished Jun 27 04:59:12 PM PDT 24
Peak memory 216392 kb
Host smart-e0f7627a-8deb-4e52-8bda-0bb5fa3ec2f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787243088 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.1787243088
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.1415651983
Short name T253
Test name
Test status
Simulation time 7807335333 ps
CPU time 17.86 seconds
Started Jun 27 04:56:19 PM PDT 24
Finished Jun 27 04:56:37 PM PDT 24
Peak memory 199848 kb
Host smart-dd48db31-d5f1-4d04-bb45-9d69a699e3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415651983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1415651983
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.3256617787
Short name T385
Test name
Test status
Simulation time 50804400717 ps
CPU time 77.17 seconds
Started Jun 27 04:56:10 PM PDT 24
Finished Jun 27 04:57:29 PM PDT 24
Peak memory 199988 kb
Host smart-f89de2fb-287e-40cb-9bf4-5bb6c7344a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256617787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3256617787
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.2723200716
Short name T353
Test name
Test status
Simulation time 15387879 ps
CPU time 0.57 seconds
Started Jun 27 04:56:20 PM PDT 24
Finished Jun 27 04:56:23 PM PDT 24
Peak memory 195088 kb
Host smart-232a0185-2a01-49fb-b34e-7a41ba584343
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723200716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2723200716
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.806566873
Short name T584
Test name
Test status
Simulation time 196637909341 ps
CPU time 24.27 seconds
Started Jun 27 04:56:15 PM PDT 24
Finished Jun 27 04:56:41 PM PDT 24
Peak memory 199904 kb
Host smart-93ae1fda-0de0-4b64-a5bc-86a9dae2d2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806566873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.806566873
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.4171056241
Short name T595
Test name
Test status
Simulation time 26880897169 ps
CPU time 23.57 seconds
Started Jun 27 04:56:19 PM PDT 24
Finished Jun 27 04:56:44 PM PDT 24
Peak memory 199932 kb
Host smart-6a8eb631-4189-4ffc-b23c-a95ba82fff7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171056241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.4171056241
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.507231018
Short name T206
Test name
Test status
Simulation time 18077502592 ps
CPU time 17.64 seconds
Started Jun 27 04:56:20 PM PDT 24
Finished Jun 27 04:56:39 PM PDT 24
Peak memory 199944 kb
Host smart-611ac283-afca-47cd-83d3-1fee5dfcbf20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507231018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.507231018
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.2583927045
Short name T480
Test name
Test status
Simulation time 270347435203 ps
CPU time 107.74 seconds
Started Jun 27 04:56:12 PM PDT 24
Finished Jun 27 04:58:02 PM PDT 24
Peak memory 197024 kb
Host smart-f7da463a-3d4a-4cd2-9ee3-860723c4f243
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583927045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.2583927045
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.2428929159
Short name T643
Test name
Test status
Simulation time 149346725702 ps
CPU time 139.44 seconds
Started Jun 27 04:56:15 PM PDT 24
Finished Jun 27 04:58:36 PM PDT 24
Peak memory 199908 kb
Host smart-99823bb2-15f9-4770-8823-4a5a8fe38dd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2428929159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.2428929159
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.314499555
Short name T778
Test name
Test status
Simulation time 6053627639 ps
CPU time 2.07 seconds
Started Jun 27 04:56:16 PM PDT 24
Finished Jun 27 04:56:20 PM PDT 24
Peak memory 197468 kb
Host smart-0169971d-bca1-4fae-8d73-007efceab28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314499555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.314499555
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_perf.2439312940
Short name T796
Test name
Test status
Simulation time 18067464346 ps
CPU time 833.29 seconds
Started Jun 27 04:56:20 PM PDT 24
Finished Jun 27 05:10:15 PM PDT 24
Peak memory 199968 kb
Host smart-c50efb62-f359-4b0a-8360-bc5f421a74c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2439312940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2439312940
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.2437383880
Short name T520
Test name
Test status
Simulation time 1598203232 ps
CPU time 3.11 seconds
Started Jun 27 04:56:17 PM PDT 24
Finished Jun 27 04:56:21 PM PDT 24
Peak memory 197632 kb
Host smart-93f9a7c8-428b-418b-8738-7dd35c500b09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2437383880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2437383880
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3866551093
Short name T791
Test name
Test status
Simulation time 45078786554 ps
CPU time 8.77 seconds
Started Jun 27 04:56:21 PM PDT 24
Finished Jun 27 04:56:31 PM PDT 24
Peak memory 199720 kb
Host smart-22d12d83-93c1-468a-944d-22469acb4793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866551093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3866551093
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.2576943883
Short name T872
Test name
Test status
Simulation time 1296072551 ps
CPU time 2.36 seconds
Started Jun 27 04:56:17 PM PDT 24
Finished Jun 27 04:56:20 PM PDT 24
Peak memory 195032 kb
Host smart-f30ef7f4-e809-47cb-a95e-5b157aea51a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576943883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2576943883
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.1573598707
Short name T793
Test name
Test status
Simulation time 567573540 ps
CPU time 1.72 seconds
Started Jun 27 04:56:12 PM PDT 24
Finished Jun 27 04:56:16 PM PDT 24
Peak memory 199840 kb
Host smart-5bb27696-a766-4641-8995-baa1c550fcef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573598707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.1573598707
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1257061953
Short name T682
Test name
Test status
Simulation time 83343586893 ps
CPU time 1220.99 seconds
Started Jun 27 04:56:20 PM PDT 24
Finished Jun 27 05:16:43 PM PDT 24
Peak memory 228056 kb
Host smart-93500214-d8da-4359-ac06-b1f38f7016b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257061953 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1257061953
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.1298539486
Short name T998
Test name
Test status
Simulation time 1329833706 ps
CPU time 3.25 seconds
Started Jun 27 04:56:20 PM PDT 24
Finished Jun 27 04:56:25 PM PDT 24
Peak memory 199396 kb
Host smart-e73858c7-b786-42d0-9a89-2d2a1e64b3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298539486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.1298539486
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.4038574949
Short name T1046
Test name
Test status
Simulation time 39928666587 ps
CPU time 34.03 seconds
Started Jun 27 04:56:13 PM PDT 24
Finished Jun 27 04:56:50 PM PDT 24
Peak memory 199996 kb
Host smart-12303a94-ba48-4077-b841-bbd8e83630a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038574949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.4038574949
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.1368232193
Short name T8
Test name
Test status
Simulation time 13075500 ps
CPU time 0.58 seconds
Started Jun 27 04:56:27 PM PDT 24
Finished Jun 27 04:56:30 PM PDT 24
Peak memory 195156 kb
Host smart-b738f34f-7186-4390-a17c-96f1549ea0dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368232193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.1368232193
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.3588065414
Short name T967
Test name
Test status
Simulation time 68038531130 ps
CPU time 45.78 seconds
Started Jun 27 04:56:28 PM PDT 24
Finished Jun 27 04:57:16 PM PDT 24
Peak memory 200156 kb
Host smart-9264fcb2-1710-4822-a9ed-cd6f418cf634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588065414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.3588065414
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.3489712595
Short name T125
Test name
Test status
Simulation time 82808146456 ps
CPU time 8 seconds
Started Jun 27 04:56:28 PM PDT 24
Finished Jun 27 04:56:38 PM PDT 24
Peak memory 199536 kb
Host smart-ecff60d9-be10-49dc-b8e6-b02c59aee94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489712595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3489712595
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.2513428680
Short name T1039
Test name
Test status
Simulation time 7136320582 ps
CPU time 13.44 seconds
Started Jun 27 04:56:27 PM PDT 24
Finished Jun 27 04:56:43 PM PDT 24
Peak memory 199912 kb
Host smart-efaf1b6f-da85-4dee-b40e-90c8050d3541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513428680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2513428680
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.1271561824
Short name T772
Test name
Test status
Simulation time 32008305994 ps
CPU time 22.25 seconds
Started Jun 27 04:56:28 PM PDT 24
Finished Jun 27 04:56:53 PM PDT 24
Peak memory 198412 kb
Host smart-5b3b8c71-e1b9-4d56-a6ef-e0c50f0efe36
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271561824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.1271561824
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3302019424
Short name T880
Test name
Test status
Simulation time 84520439586 ps
CPU time 347.25 seconds
Started Jun 27 04:56:36 PM PDT 24
Finished Jun 27 05:02:24 PM PDT 24
Peak memory 199956 kb
Host smart-19ff9987-6dc0-446e-a060-e7f42640ad72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3302019424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3302019424
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.3000931846
Short name T355
Test name
Test status
Simulation time 6877815868 ps
CPU time 15.57 seconds
Started Jun 27 04:56:30 PM PDT 24
Finished Jun 27 04:56:47 PM PDT 24
Peak memory 199740 kb
Host smart-a73aa6e6-af26-47af-a847-3a896d29acea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000931846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3000931846
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_perf.1257345672
Short name T626
Test name
Test status
Simulation time 5276127667 ps
CPU time 87.34 seconds
Started Jun 27 04:56:26 PM PDT 24
Finished Jun 27 04:57:55 PM PDT 24
Peak memory 199896 kb
Host smart-d2caf316-7b1f-46a3-8765-d706022f75c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1257345672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1257345672
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.1062556062
Short name T976
Test name
Test status
Simulation time 1925519160 ps
CPU time 3.24 seconds
Started Jun 27 04:56:31 PM PDT 24
Finished Jun 27 04:56:36 PM PDT 24
Peak memory 198920 kb
Host smart-dac3cb3b-f356-4b65-8dfa-81ec6d5ec197
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1062556062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.1062556062
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.839526394
Short name T813
Test name
Test status
Simulation time 165116361457 ps
CPU time 91.24 seconds
Started Jun 27 04:56:26 PM PDT 24
Finished Jun 27 04:57:59 PM PDT 24
Peak memory 199988 kb
Host smart-b245a94f-6f78-4636-b85c-f4f5891a870e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839526394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.839526394
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.2093606231
Short name T290
Test name
Test status
Simulation time 2175223490 ps
CPU time 1.59 seconds
Started Jun 27 04:56:30 PM PDT 24
Finished Jun 27 04:56:34 PM PDT 24
Peak memory 195496 kb
Host smart-4cb08c24-406c-424b-a1ab-ecdd35ea0390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093606231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2093606231
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.3662405380
Short name T973
Test name
Test status
Simulation time 332844675 ps
CPU time 1.31 seconds
Started Jun 27 04:56:19 PM PDT 24
Finished Jun 27 04:56:22 PM PDT 24
Peak memory 199404 kb
Host smart-c00b4ded-549a-46f1-84f8-dd4c7d426ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662405380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3662405380
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.3004161306
Short name T462
Test name
Test status
Simulation time 1048555301 ps
CPU time 5.46 seconds
Started Jun 27 04:56:27 PM PDT 24
Finished Jun 27 04:56:34 PM PDT 24
Peak memory 198876 kb
Host smart-678cee3a-404e-423f-841b-da7d90fdde9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004161306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3004161306
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.630742677
Short name T774
Test name
Test status
Simulation time 62200296373 ps
CPU time 106.99 seconds
Started Jun 27 04:56:20 PM PDT 24
Finished Jun 27 04:58:09 PM PDT 24
Peak memory 199784 kb
Host smart-7cce1df7-dfd4-40bf-b39d-5a06625d73d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630742677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.630742677
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.2516217306
Short name T766
Test name
Test status
Simulation time 13249680 ps
CPU time 0.54 seconds
Started Jun 27 04:56:27 PM PDT 24
Finished Jun 27 04:56:30 PM PDT 24
Peak memory 195280 kb
Host smart-e577e465-1516-4ecd-9d37-5dd009060bc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516217306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2516217306
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.3527831166
Short name T805
Test name
Test status
Simulation time 33429977063 ps
CPU time 27.43 seconds
Started Jun 27 04:56:26 PM PDT 24
Finished Jun 27 04:56:54 PM PDT 24
Peak memory 199824 kb
Host smart-74321dc6-e876-48eb-93cb-577541d1313e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527831166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3527831166
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.2522367766
Short name T1004
Test name
Test status
Simulation time 47846168674 ps
CPU time 61.5 seconds
Started Jun 27 04:56:27 PM PDT 24
Finished Jun 27 04:57:30 PM PDT 24
Peak memory 200176 kb
Host smart-9e189878-f685-4d73-8a34-3dd4d937e03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522367766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.2522367766
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.3083478307
Short name T224
Test name
Test status
Simulation time 25874375604 ps
CPU time 25.74 seconds
Started Jun 27 04:56:33 PM PDT 24
Finished Jun 27 04:57:00 PM PDT 24
Peak memory 199888 kb
Host smart-bfc558a7-de76-4f38-977e-752facd55b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083478307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3083478307
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.1449815355
Short name T693
Test name
Test status
Simulation time 34596594823 ps
CPU time 15.6 seconds
Started Jun 27 04:56:29 PM PDT 24
Finished Jun 27 04:56:47 PM PDT 24
Peak memory 198260 kb
Host smart-e04dd3b1-e2cb-4aa3-bf01-0466597f6f82
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449815355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1449815355
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.259774617
Short name T317
Test name
Test status
Simulation time 44903590972 ps
CPU time 177.01 seconds
Started Jun 27 04:56:26 PM PDT 24
Finished Jun 27 04:59:25 PM PDT 24
Peak memory 199836 kb
Host smart-d186438c-8189-4321-a09d-bb1badedf09e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=259774617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.259774617
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.2069078699
Short name T358
Test name
Test status
Simulation time 5933785366 ps
CPU time 9.29 seconds
Started Jun 27 04:56:32 PM PDT 24
Finished Jun 27 04:56:42 PM PDT 24
Peak memory 199708 kb
Host smart-3018b707-4eac-45ca-bd24-f826ea841546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069078699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2069078699
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_perf.3068598472
Short name T587
Test name
Test status
Simulation time 16105064422 ps
CPU time 409.97 seconds
Started Jun 27 04:56:27 PM PDT 24
Finished Jun 27 05:03:19 PM PDT 24
Peak memory 199968 kb
Host smart-a7bd0063-f793-4643-b886-f747833025d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3068598472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.3068598472
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.1522673004
Short name T17
Test name
Test status
Simulation time 5585162527 ps
CPU time 5.47 seconds
Started Jun 27 04:56:26 PM PDT 24
Finished Jun 27 04:56:32 PM PDT 24
Peak memory 198688 kb
Host smart-4dab41a8-7e45-470a-b529-bd7a132849d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1522673004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1522673004
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3072788257
Short name T554
Test name
Test status
Simulation time 84089570896 ps
CPU time 32.71 seconds
Started Jun 27 04:56:26 PM PDT 24
Finished Jun 27 04:57:01 PM PDT 24
Peak memory 199736 kb
Host smart-5901ed7c-d823-458e-b8f6-552392beb3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072788257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3072788257
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.4129696083
Short name T307
Test name
Test status
Simulation time 26601355359 ps
CPU time 9.59 seconds
Started Jun 27 04:56:28 PM PDT 24
Finished Jun 27 04:56:39 PM PDT 24
Peak memory 196092 kb
Host smart-efacb1b9-856e-403f-b7ad-68ee3a5810f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129696083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.4129696083
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.2566777910
Short name T452
Test name
Test status
Simulation time 866448522 ps
CPU time 2.84 seconds
Started Jun 27 04:56:34 PM PDT 24
Finished Jun 27 04:56:37 PM PDT 24
Peak memory 198356 kb
Host smart-5638367e-ff21-4133-82f3-c6f3f704b131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566777910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.2566777910
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2218891626
Short name T784
Test name
Test status
Simulation time 1039889985 ps
CPU time 2.47 seconds
Started Jun 27 04:56:26 PM PDT 24
Finished Jun 27 04:56:30 PM PDT 24
Peak memory 199856 kb
Host smart-073adad4-78db-47b7-9595-5dabe755355f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218891626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2218891626
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.203557787
Short name T836
Test name
Test status
Simulation time 28389903448 ps
CPU time 40.63 seconds
Started Jun 27 04:56:28 PM PDT 24
Finished Jun 27 04:57:11 PM PDT 24
Peak memory 199900 kb
Host smart-30668691-77a5-43d2-a86a-bebb08f1413e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203557787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.203557787
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.2245016213
Short name T343
Test name
Test status
Simulation time 25829179 ps
CPU time 0.57 seconds
Started Jun 27 04:56:28 PM PDT 24
Finished Jun 27 04:56:31 PM PDT 24
Peak memory 195280 kb
Host smart-80ff74c5-ba97-4ab0-8e3e-114be7c82048
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245016213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2245016213
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1150684414
Short name T724
Test name
Test status
Simulation time 114732423013 ps
CPU time 33.81 seconds
Started Jun 27 04:56:33 PM PDT 24
Finished Jun 27 04:57:08 PM PDT 24
Peak memory 199892 kb
Host smart-37294208-3f5e-4c1d-9588-e87969f81b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150684414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1150684414
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1460511536
Short name T742
Test name
Test status
Simulation time 27106825496 ps
CPU time 28.36 seconds
Started Jun 27 04:56:28 PM PDT 24
Finished Jun 27 04:56:58 PM PDT 24
Peak memory 199900 kb
Host smart-f4b7533e-d601-4791-87ec-dac2da80cec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460511536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1460511536
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.873564322
Short name T512
Test name
Test status
Simulation time 8658671237 ps
CPU time 15.05 seconds
Started Jun 27 04:56:34 PM PDT 24
Finished Jun 27 04:56:50 PM PDT 24
Peak memory 199716 kb
Host smart-66c7d1ba-d306-4e9b-acc5-49781ff86ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873564322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.873564322
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.51405951
Short name T571
Test name
Test status
Simulation time 46268362042 ps
CPU time 89.46 seconds
Started Jun 27 04:56:27 PM PDT 24
Finished Jun 27 04:57:58 PM PDT 24
Peak memory 199932 kb
Host smart-cc4ba2b0-d065-4487-8924-cf49e0c9004d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51405951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.51405951
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.988278589
Short name T511
Test name
Test status
Simulation time 213102080007 ps
CPU time 377.26 seconds
Started Jun 27 04:56:33 PM PDT 24
Finished Jun 27 05:02:51 PM PDT 24
Peak memory 199992 kb
Host smart-1aff630d-5730-4b58-8fd6-f31ac47ecf86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=988278589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.988278589
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.255788964
Short name T417
Test name
Test status
Simulation time 8924890387 ps
CPU time 3.98 seconds
Started Jun 27 04:56:26 PM PDT 24
Finished Jun 27 04:56:32 PM PDT 24
Peak memory 199964 kb
Host smart-47df27b1-1a2e-4aba-b641-61d5b7626423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255788964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.255788964
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_perf.2853941325
Short name T503
Test name
Test status
Simulation time 16924270613 ps
CPU time 731.81 seconds
Started Jun 27 04:56:29 PM PDT 24
Finished Jun 27 05:08:43 PM PDT 24
Peak memory 199928 kb
Host smart-76dfa59a-84e4-48f5-8ed2-16c0885c52aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2853941325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2853941325
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.745598576
Short name T420
Test name
Test status
Simulation time 5105114958 ps
CPU time 47.44 seconds
Started Jun 27 04:56:38 PM PDT 24
Finished Jun 27 04:57:27 PM PDT 24
Peak memory 198400 kb
Host smart-4689393e-4b06-4b68-9c64-f0fde8ff9d1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=745598576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.745598576
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.1611049840
Short name T364
Test name
Test status
Simulation time 55275955873 ps
CPU time 74.73 seconds
Started Jun 27 04:56:30 PM PDT 24
Finished Jun 27 04:57:47 PM PDT 24
Peak memory 199928 kb
Host smart-be5b5415-28f5-4abe-80eb-df8b02141dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611049840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1611049840
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.2092532204
Short name T743
Test name
Test status
Simulation time 73370403095 ps
CPU time 116.44 seconds
Started Jun 27 04:56:37 PM PDT 24
Finished Jun 27 04:58:34 PM PDT 24
Peak memory 195936 kb
Host smart-a23b37ae-1784-41e1-ba54-93724e23162c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092532204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.2092532204
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3346632139
Short name T459
Test name
Test status
Simulation time 677827323 ps
CPU time 1.69 seconds
Started Jun 27 04:56:31 PM PDT 24
Finished Jun 27 04:56:34 PM PDT 24
Peak memory 198712 kb
Host smart-75913ac5-ef02-456b-a6f8-33e33cf36a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346632139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3346632139
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.2685888260
Short name T640
Test name
Test status
Simulation time 6783795992 ps
CPU time 27.75 seconds
Started Jun 27 04:56:27 PM PDT 24
Finished Jun 27 04:56:57 PM PDT 24
Peak memory 199884 kb
Host smart-fe798b50-c338-493e-a6e7-9d323dc6ab4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685888260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.2685888260
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.3415284484
Short name T262
Test name
Test status
Simulation time 355342593568 ps
CPU time 167.21 seconds
Started Jun 27 04:56:30 PM PDT 24
Finished Jun 27 04:59:20 PM PDT 24
Peak memory 199808 kb
Host smart-17be3510-6d31-4204-b81b-9c384d889aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415284484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3415284484
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.1085000150
Short name T377
Test name
Test status
Simulation time 106331361 ps
CPU time 0.57 seconds
Started Jun 27 04:56:29 PM PDT 24
Finished Jun 27 04:56:32 PM PDT 24
Peak memory 195232 kb
Host smart-6c5dd800-dcbb-40d6-b20f-d3f5342e79d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085000150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1085000150
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.1591884651
Short name T963
Test name
Test status
Simulation time 113437717493 ps
CPU time 160.94 seconds
Started Jun 27 04:56:28 PM PDT 24
Finished Jun 27 04:59:11 PM PDT 24
Peak memory 199904 kb
Host smart-c6b72ab0-80c7-406e-b20a-d37b1aa6632f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591884651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1591884651
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.1535882672
Short name T102
Test name
Test status
Simulation time 152276962051 ps
CPU time 215.25 seconds
Started Jun 27 04:56:26 PM PDT 24
Finished Jun 27 05:00:03 PM PDT 24
Peak memory 199824 kb
Host smart-d91cb507-58ce-4ce7-93f7-28bbcf1ba7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535882672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1535882672
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.2450748187
Short name T717
Test name
Test status
Simulation time 61659041976 ps
CPU time 33.11 seconds
Started Jun 27 04:56:30 PM PDT 24
Finished Jun 27 04:57:05 PM PDT 24
Peak memory 199924 kb
Host smart-75d77aee-44f2-4d4b-a178-34e3489861c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450748187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2450748187
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.2083927596
Short name T955
Test name
Test status
Simulation time 25862446109 ps
CPU time 12.19 seconds
Started Jun 27 04:56:33 PM PDT 24
Finished Jun 27 04:56:45 PM PDT 24
Peak memory 199976 kb
Host smart-9f87108b-4f0d-4bca-a64a-feabf0de9df4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083927596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.2083927596
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.2702068092
Short name T811
Test name
Test status
Simulation time 144974074157 ps
CPU time 1159.26 seconds
Started Jun 27 04:56:29 PM PDT 24
Finished Jun 27 05:15:51 PM PDT 24
Peak memory 199852 kb
Host smart-cf6129d9-84a1-4f5f-84a0-bdf9595208dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2702068092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.2702068092
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.686071798
Short name T346
Test name
Test status
Simulation time 5742458068 ps
CPU time 10.84 seconds
Started Jun 27 04:56:29 PM PDT 24
Finished Jun 27 04:56:42 PM PDT 24
Peak memory 199556 kb
Host smart-2e585ef7-4c89-4c6d-b596-c8796f2dd2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686071798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.686071798
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_perf.4053762665
Short name T599
Test name
Test status
Simulation time 29964627618 ps
CPU time 828.32 seconds
Started Jun 27 04:56:30 PM PDT 24
Finished Jun 27 05:10:20 PM PDT 24
Peak memory 199932 kb
Host smart-35c179c2-82de-457a-bc85-e64677734e76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4053762665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.4053762665
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.819960315
Short name T972
Test name
Test status
Simulation time 3461105136 ps
CPU time 22.01 seconds
Started Jun 27 04:56:29 PM PDT 24
Finished Jun 27 04:56:54 PM PDT 24
Peak memory 198360 kb
Host smart-8ab7f9d2-5c9a-41e7-9ce4-a422a9ee9578
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=819960315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.819960315
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.674440799
Short name T448
Test name
Test status
Simulation time 2395824885 ps
CPU time 1.45 seconds
Started Jun 27 04:56:38 PM PDT 24
Finished Jun 27 04:56:40 PM PDT 24
Peak memory 196460 kb
Host smart-0b7c1702-8d97-40ba-bd4c-f02f354209c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674440799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.674440799
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.712879991
Short name T974
Test name
Test status
Simulation time 930054098 ps
CPU time 3.96 seconds
Started Jun 27 04:56:30 PM PDT 24
Finished Jun 27 04:56:36 PM PDT 24
Peak memory 198996 kb
Host smart-b4e8b888-85de-4ff6-9665-8175eb791130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712879991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.712879991
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.1748340857
Short name T958
Test name
Test status
Simulation time 310869328875 ps
CPU time 305.68 seconds
Started Jun 27 04:56:29 PM PDT 24
Finished Jun 27 05:01:37 PM PDT 24
Peak memory 199888 kb
Host smart-abc7e28f-3af0-4563-ae87-568c1ebf32b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748340857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1748340857
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.1519078421
Short name T88
Test name
Test status
Simulation time 165241558925 ps
CPU time 299.6 seconds
Started Jun 27 04:56:28 PM PDT 24
Finished Jun 27 05:01:30 PM PDT 24
Peak memory 216728 kb
Host smart-e1d2f708-319f-4771-a810-c3e1e23fab4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519078421 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1519078421
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.1927828804
Short name T618
Test name
Test status
Simulation time 6300100851 ps
CPU time 15.04 seconds
Started Jun 27 04:56:29 PM PDT 24
Finished Jun 27 04:56:46 PM PDT 24
Peak memory 199308 kb
Host smart-62b945f9-9732-4cb4-967e-f5978c0ed00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927828804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1927828804
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.1084895252
Short name T970
Test name
Test status
Simulation time 68773681675 ps
CPU time 25.87 seconds
Started Jun 27 04:56:30 PM PDT 24
Finished Jun 27 04:56:58 PM PDT 24
Peak memory 199932 kb
Host smart-6ddf78e7-daac-4323-8ae7-f4c6d8276182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084895252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1084895252
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.1769696253
Short name T341
Test name
Test status
Simulation time 44520426 ps
CPU time 0.56 seconds
Started Jun 27 04:53:58 PM PDT 24
Finished Jun 27 04:54:01 PM PDT 24
Peak memory 195240 kb
Host smart-fdeed51f-f586-4f75-84a0-2c5e4a25c38a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769696253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.1769696253
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.2251312886
Short name T688
Test name
Test status
Simulation time 50313649863 ps
CPU time 93.23 seconds
Started Jun 27 04:53:55 PM PDT 24
Finished Jun 27 04:55:31 PM PDT 24
Peak memory 199564 kb
Host smart-af543d0a-8804-49ba-9bae-dd904f34653b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251312886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.2251312886
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.2878922392
Short name T155
Test name
Test status
Simulation time 135061001621 ps
CPU time 31.02 seconds
Started Jun 27 04:53:56 PM PDT 24
Finished Jun 27 04:54:29 PM PDT 24
Peak memory 199956 kb
Host smart-7c8aea59-776b-4ef4-99e7-4fb81cbc0270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878922392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.2878922392
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.2624151254
Short name T1053
Test name
Test status
Simulation time 33295179204 ps
CPU time 25.53 seconds
Started Jun 27 04:53:53 PM PDT 24
Finished Jun 27 04:54:21 PM PDT 24
Peak memory 199812 kb
Host smart-e73f66c7-fa04-497f-8dd9-a2799a796ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624151254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.2624151254
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.3315045268
Short name T1019
Test name
Test status
Simulation time 22667155604 ps
CPU time 16.78 seconds
Started Jun 27 04:53:57 PM PDT 24
Finished Jun 27 04:54:17 PM PDT 24
Peak memory 197256 kb
Host smart-8e6039ad-20b7-4818-96ee-056e3e262f68
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315045268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3315045268
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.954665018
Short name T436
Test name
Test status
Simulation time 162412086814 ps
CPU time 381.88 seconds
Started Jun 27 04:53:59 PM PDT 24
Finished Jun 27 05:00:23 PM PDT 24
Peak memory 200020 kb
Host smart-130f1f54-59f3-4970-842b-a15cb7ad5f59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=954665018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.954665018
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.1240889127
Short name T1074
Test name
Test status
Simulation time 2785462451 ps
CPU time 6.14 seconds
Started Jun 27 04:53:58 PM PDT 24
Finished Jun 27 04:54:07 PM PDT 24
Peak memory 198860 kb
Host smart-385dc2e8-9efa-4a3e-a843-f621e13249d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240889127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.1240889127
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_perf.158450385
Short name T1012
Test name
Test status
Simulation time 20720218005 ps
CPU time 707.38 seconds
Started Jun 27 04:53:57 PM PDT 24
Finished Jun 27 05:05:48 PM PDT 24
Peak memory 199916 kb
Host smart-942c0819-cb2f-45a3-8c01-8bd3c721a8a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=158450385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.158450385
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.2033101198
Short name T407
Test name
Test status
Simulation time 4451188520 ps
CPU time 9.27 seconds
Started Jun 27 04:53:55 PM PDT 24
Finished Jun 27 04:54:07 PM PDT 24
Peak memory 198092 kb
Host smart-56029e4a-2da6-4623-9d77-81a61293b5a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2033101198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2033101198
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1647321259
Short name T932
Test name
Test status
Simulation time 31966243994 ps
CPU time 55.24 seconds
Started Jun 27 04:53:55 PM PDT 24
Finished Jun 27 04:54:53 PM PDT 24
Peak memory 199492 kb
Host smart-ef98e70c-94fc-447a-a554-ed3552928ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647321259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1647321259
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.3992218557
Short name T816
Test name
Test status
Simulation time 1359853654 ps
CPU time 2.85 seconds
Started Jun 27 04:53:59 PM PDT 24
Finished Jun 27 04:54:04 PM PDT 24
Peak memory 195436 kb
Host smart-770b9b07-d31d-42f8-9d5a-7a565251946c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992218557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3992218557
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.3715351662
Short name T630
Test name
Test status
Simulation time 940372659 ps
CPU time 2.6 seconds
Started Jun 27 04:53:54 PM PDT 24
Finished Jun 27 04:54:00 PM PDT 24
Peak memory 198808 kb
Host smart-48edc6fe-1258-42c3-b86b-e87a568fed9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715351662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3715351662
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.846178354
Short name T877
Test name
Test status
Simulation time 147544438815 ps
CPU time 855.59 seconds
Started Jun 27 04:53:58 PM PDT 24
Finished Jun 27 05:08:16 PM PDT 24
Peak memory 199960 kb
Host smart-85751acc-3907-4825-93fe-7d6336dcbc33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846178354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.846178354
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.3699469723
Short name T38
Test name
Test status
Simulation time 26888959403 ps
CPU time 303.42 seconds
Started Jun 27 04:53:56 PM PDT 24
Finished Jun 27 04:59:02 PM PDT 24
Peak memory 216340 kb
Host smart-46e7891c-a3a7-450e-8f8d-f70291aa8932
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699469723 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.3699469723
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.2148987335
Short name T1063
Test name
Test status
Simulation time 6409404534 ps
CPU time 22.98 seconds
Started Jun 27 04:54:08 PM PDT 24
Finished Jun 27 04:54:33 PM PDT 24
Peak memory 199656 kb
Host smart-61d0297a-9029-40bf-bfc8-34a8be67d73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148987335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.2148987335
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.3288106087
Short name T736
Test name
Test status
Simulation time 43612325651 ps
CPU time 77.9 seconds
Started Jun 27 04:53:53 PM PDT 24
Finished Jun 27 04:55:13 PM PDT 24
Peak memory 199956 kb
Host smart-352d3eea-0645-4100-a892-b75cdbb9272e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288106087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.3288106087
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.2809040217
Short name T788
Test name
Test status
Simulation time 63227030367 ps
CPU time 97.54 seconds
Started Jun 27 04:56:28 PM PDT 24
Finished Jun 27 04:58:08 PM PDT 24
Peak memory 199880 kb
Host smart-ddf41041-aecd-4fe9-af12-405c67597e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809040217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2809040217
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.3824763883
Short name T1055
Test name
Test status
Simulation time 274459704080 ps
CPU time 131.03 seconds
Started Jun 27 04:56:34 PM PDT 24
Finished Jun 27 04:58:46 PM PDT 24
Peak memory 199824 kb
Host smart-1dfe0d06-4d93-4e85-9269-44cff12e9345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824763883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.3824763883
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.3228855197
Short name T548
Test name
Test status
Simulation time 71155449531 ps
CPU time 338.62 seconds
Started Jun 27 04:56:44 PM PDT 24
Finished Jun 27 05:02:23 PM PDT 24
Peak memory 216052 kb
Host smart-4b15e874-a784-4a9d-9616-97afb0b4826b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228855197 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.3228855197
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.6946712
Short name T864
Test name
Test status
Simulation time 57396489336 ps
CPU time 262.21 seconds
Started Jun 27 04:56:42 PM PDT 24
Finished Jun 27 05:01:05 PM PDT 24
Peak memory 199700 kb
Host smart-695e7be0-a1a6-498f-9e42-01db63e5ab20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6946712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.6946712
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.164423543
Short name T49
Test name
Test status
Simulation time 106755746883 ps
CPU time 307.18 seconds
Started Jun 27 04:56:44 PM PDT 24
Finished Jun 27 05:01:52 PM PDT 24
Peak memory 215792 kb
Host smart-05eb6cde-5cfd-4d74-b4fc-3c1165afecdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164423543 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.164423543
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.3014828123
Short name T829
Test name
Test status
Simulation time 207433307802 ps
CPU time 335 seconds
Started Jun 27 04:56:42 PM PDT 24
Finished Jun 27 05:02:18 PM PDT 24
Peak memory 199760 kb
Host smart-e394fc42-5bb6-4b4e-b4cf-86b6b74351dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014828123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3014828123
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.1933994442
Short name T890
Test name
Test status
Simulation time 17649201371 ps
CPU time 30.11 seconds
Started Jun 27 04:56:42 PM PDT 24
Finished Jun 27 04:57:13 PM PDT 24
Peak memory 199716 kb
Host smart-4cab9640-7677-42e2-a225-28844afe8a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933994442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1933994442
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.2766401569
Short name T681
Test name
Test status
Simulation time 21826345553 ps
CPU time 606.1 seconds
Started Jun 27 04:56:44 PM PDT 24
Finished Jun 27 05:06:51 PM PDT 24
Peak memory 216412 kb
Host smart-c4505d63-ae59-47d6-9010-c5c32c33449e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766401569 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.2766401569
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.914640026
Short name T140
Test name
Test status
Simulation time 51324165277 ps
CPU time 74.58 seconds
Started Jun 27 04:56:52 PM PDT 24
Finished Jun 27 04:58:10 PM PDT 24
Peak memory 200220 kb
Host smart-6b772daf-bb9a-4594-abd4-50e6439bbc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914640026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.914640026
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3742295537
Short name T86
Test name
Test status
Simulation time 180630718500 ps
CPU time 179.68 seconds
Started Jun 27 04:56:51 PM PDT 24
Finished Jun 27 04:59:52 PM PDT 24
Peak memory 216268 kb
Host smart-71fe6e6e-557e-472d-b2fe-90055f32eac1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742295537 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3742295537
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.874525728
Short name T124
Test name
Test status
Simulation time 31130274393 ps
CPU time 25.83 seconds
Started Jun 27 04:56:51 PM PDT 24
Finished Jun 27 04:57:19 PM PDT 24
Peak memory 199788 kb
Host smart-2576d9c3-9cb9-47d9-92d7-8da8dde4f7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874525728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.874525728
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.2709984310
Short name T948
Test name
Test status
Simulation time 22841673117 ps
CPU time 269.77 seconds
Started Jun 27 04:56:51 PM PDT 24
Finished Jun 27 05:01:23 PM PDT 24
Peak memory 208236 kb
Host smart-7d9f5f20-b837-4044-81b5-beccf0356350
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709984310 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.2709984310
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.3932080367
Short name T668
Test name
Test status
Simulation time 8749211526 ps
CPU time 13.3 seconds
Started Jun 27 04:56:53 PM PDT 24
Finished Jun 27 04:57:09 PM PDT 24
Peak memory 199904 kb
Host smart-ac41dd40-b29a-4a9c-a11d-b7e1946edfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932080367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3932080367
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.3582359247
Short name T1073
Test name
Test status
Simulation time 28749053229 ps
CPU time 15.72 seconds
Started Jun 27 04:56:55 PM PDT 24
Finished Jun 27 04:57:13 PM PDT 24
Peak memory 199780 kb
Host smart-2cb596fe-ab63-4c32-8320-32adb2d87298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582359247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3582359247
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.25748931
Short name T661
Test name
Test status
Simulation time 34579895879 ps
CPU time 14.32 seconds
Started Jun 27 04:56:50 PM PDT 24
Finished Jun 27 04:57:06 PM PDT 24
Peak memory 199832 kb
Host smart-fd6976d8-2f46-4773-ae29-8a381ae6cc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25748931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.25748931
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3082821378
Short name T48
Test name
Test status
Simulation time 41895269988 ps
CPU time 148.76 seconds
Started Jun 27 04:56:52 PM PDT 24
Finished Jun 27 04:59:24 PM PDT 24
Peak memory 215912 kb
Host smart-7d8d4680-e6bf-4b49-9c90-bf58f99ed51d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082821378 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3082821378
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3936261325
Short name T368
Test name
Test status
Simulation time 71815038 ps
CPU time 0.55 seconds
Started Jun 27 04:54:00 PM PDT 24
Finished Jun 27 04:54:03 PM PDT 24
Peak memory 195340 kb
Host smart-00557d9a-3c37-489a-8866-68c119ee55fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936261325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3936261325
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.1891214761
Short name T529
Test name
Test status
Simulation time 34255853344 ps
CPU time 68.47 seconds
Started Jun 27 04:53:56 PM PDT 24
Finished Jun 27 04:55:07 PM PDT 24
Peak memory 199884 kb
Host smart-2becaafc-5042-4d24-9ce3-a5e3d9de776b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891214761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1891214761
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.240091873
Short name T286
Test name
Test status
Simulation time 20288831112 ps
CPU time 38.2 seconds
Started Jun 27 04:53:59 PM PDT 24
Finished Jun 27 04:54:39 PM PDT 24
Peak memory 199952 kb
Host smart-9a74d569-7236-4b41-847a-287e0797ad0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240091873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.240091873
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.726583044
Short name T848
Test name
Test status
Simulation time 99270368187 ps
CPU time 83.19 seconds
Started Jun 27 04:54:07 PM PDT 24
Finished Jun 27 04:55:32 PM PDT 24
Peak memory 199848 kb
Host smart-42630a82-a959-4551-880a-34e41e517327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726583044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.726583044
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.2420179306
Short name T107
Test name
Test status
Simulation time 48862510777 ps
CPU time 20.58 seconds
Started Jun 27 04:54:08 PM PDT 24
Finished Jun 27 04:54:30 PM PDT 24
Peak memory 199604 kb
Host smart-b581b584-e566-4de2-abda-a522aab7968a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420179306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2420179306
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.787582126
Short name T892
Test name
Test status
Simulation time 36271574656 ps
CPU time 270.4 seconds
Started Jun 27 04:54:09 PM PDT 24
Finished Jun 27 04:58:40 PM PDT 24
Peak memory 199896 kb
Host smart-5b7a1d06-f067-444d-adff-b328c8f88d92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=787582126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.787582126
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.3069679604
Short name T342
Test name
Test status
Simulation time 4818808900 ps
CPU time 8.91 seconds
Started Jun 27 04:53:57 PM PDT 24
Finished Jun 27 04:54:09 PM PDT 24
Peak memory 199952 kb
Host smart-df1549af-ff6d-416e-ae01-27f46eed8842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069679604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.3069679604
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_perf.2436717751
Short name T718
Test name
Test status
Simulation time 11068991234 ps
CPU time 139.93 seconds
Started Jun 27 04:54:08 PM PDT 24
Finished Jun 27 04:56:29 PM PDT 24
Peak memory 199888 kb
Host smart-549b4ec0-536c-4ab3-aecb-4a9d9b9c70bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2436717751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.2436717751
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.2312474465
Short name T615
Test name
Test status
Simulation time 1506558103 ps
CPU time 1.85 seconds
Started Jun 27 04:53:56 PM PDT 24
Finished Jun 27 04:54:01 PM PDT 24
Peak memory 196776 kb
Host smart-b3e438e9-9656-4cb3-a210-93ced55b3723
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2312474465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.2312474465
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1191564664
Short name T129
Test name
Test status
Simulation time 188933226154 ps
CPU time 215.62 seconds
Started Jun 27 04:54:07 PM PDT 24
Finished Jun 27 04:57:44 PM PDT 24
Peak memory 199904 kb
Host smart-f1dbafa8-2cc1-4289-9bba-6106ba9a0ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191564664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1191564664
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1574103149
Short name T891
Test name
Test status
Simulation time 47070374954 ps
CPU time 61.66 seconds
Started Jun 27 04:53:59 PM PDT 24
Finished Jun 27 04:55:03 PM PDT 24
Peak memory 196436 kb
Host smart-81669e9b-c559-422d-975f-475bb01df8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574103149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1574103149
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.2570383140
Short name T868
Test name
Test status
Simulation time 492902473 ps
CPU time 1.62 seconds
Started Jun 27 04:53:58 PM PDT 24
Finished Jun 27 04:54:02 PM PDT 24
Peak memory 199000 kb
Host smart-9c529724-aa37-494b-b899-c0c1d85776fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570383140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.2570383140
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.740030274
Short name T537
Test name
Test status
Simulation time 71915143351 ps
CPU time 111.61 seconds
Started Jun 27 04:54:08 PM PDT 24
Finished Jun 27 04:56:01 PM PDT 24
Peak memory 199856 kb
Host smart-c54a0ac6-909f-42f2-ac45-ee1c13dcd086
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740030274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.740030274
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.3027430616
Short name T306
Test name
Test status
Simulation time 7454067718 ps
CPU time 12.46 seconds
Started Jun 27 04:54:09 PM PDT 24
Finished Jun 27 04:54:23 PM PDT 24
Peak memory 199852 kb
Host smart-68c49e29-c30c-4257-a625-53ec1cc6b81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027430616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.3027430616
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.2367164059
Short name T1003
Test name
Test status
Simulation time 42660446377 ps
CPU time 68.88 seconds
Started Jun 27 04:53:58 PM PDT 24
Finished Jun 27 04:55:09 PM PDT 24
Peak memory 199860 kb
Host smart-38f4734a-1c98-4e40-8a96-fcb039e5de35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367164059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2367164059
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.849207486
Short name T1025
Test name
Test status
Simulation time 39613897639 ps
CPU time 72.71 seconds
Started Jun 27 04:56:52 PM PDT 24
Finished Jun 27 04:58:08 PM PDT 24
Peak memory 199168 kb
Host smart-60d456e3-f5a2-4461-829c-a4909f7a9c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849207486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.849207486
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.1584149352
Short name T827
Test name
Test status
Simulation time 18454935684 ps
CPU time 31.37 seconds
Started Jun 27 04:56:53 PM PDT 24
Finished Jun 27 04:57:27 PM PDT 24
Peak memory 199864 kb
Host smart-36cbd35b-468b-4d3e-8595-7db763228c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584149352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1584149352
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2101227527
Short name T34
Test name
Test status
Simulation time 36961311674 ps
CPU time 186.21 seconds
Started Jun 27 04:56:54 PM PDT 24
Finished Jun 27 05:00:03 PM PDT 24
Peak memory 215452 kb
Host smart-2802e3d9-cc60-47f4-96be-08f73598665a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101227527 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2101227527
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.4273122374
Short name T122
Test name
Test status
Simulation time 16104431168 ps
CPU time 28.09 seconds
Started Jun 27 04:56:51 PM PDT 24
Finished Jun 27 04:57:21 PM PDT 24
Peak memory 199876 kb
Host smart-5a9d5ddd-e1b4-4711-99c4-cc89972d66b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273122374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.4273122374
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.593742304
Short name T35
Test name
Test status
Simulation time 29689274524 ps
CPU time 368.34 seconds
Started Jun 27 04:56:55 PM PDT 24
Finished Jun 27 05:03:06 PM PDT 24
Peak memory 216416 kb
Host smart-a8aedfaf-6cf9-417b-9ba8-36c3c503e0be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593742304 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.593742304
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.2403778280
Short name T505
Test name
Test status
Simulation time 50317873053 ps
CPU time 47.61 seconds
Started Jun 27 04:56:51 PM PDT 24
Finished Jun 27 04:57:40 PM PDT 24
Peak memory 199888 kb
Host smart-463014df-6cf5-43ac-ab35-bdf482b4abd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403778280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2403778280
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.2802749533
Short name T553
Test name
Test status
Simulation time 109057040732 ps
CPU time 397.54 seconds
Started Jun 27 04:56:59 PM PDT 24
Finished Jun 27 05:03:38 PM PDT 24
Peak memory 210228 kb
Host smart-a0385297-d5f9-4d8a-948f-16fca9527fc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802749533 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.2802749533
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.3515034812
Short name T243
Test name
Test status
Simulation time 65198798076 ps
CPU time 36.46 seconds
Started Jun 27 04:56:53 PM PDT 24
Finished Jun 27 04:57:33 PM PDT 24
Peak memory 199828 kb
Host smart-36ab176b-bb52-4f90-8ef4-077501f82580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515034812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3515034812
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.539102918
Short name T204
Test name
Test status
Simulation time 38567835082 ps
CPU time 30.01 seconds
Started Jun 27 04:56:52 PM PDT 24
Finished Jun 27 04:57:25 PM PDT 24
Peak memory 198996 kb
Host smart-8f26a120-0b81-40ba-af70-0bf59c2be244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539102918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.539102918
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.2795060030
Short name T215
Test name
Test status
Simulation time 46940812082 ps
CPU time 33.61 seconds
Started Jun 27 04:56:56 PM PDT 24
Finished Jun 27 04:57:32 PM PDT 24
Peak memory 199976 kb
Host smart-9d02ae9e-b13f-4609-b51a-00f4033e3550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795060030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.2795060030
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.3809860180
Short name T419
Test name
Test status
Simulation time 29484052505 ps
CPU time 18.44 seconds
Started Jun 27 04:56:56 PM PDT 24
Finished Jun 27 04:57:16 PM PDT 24
Peak memory 199980 kb
Host smart-8bcdaaf2-6bae-4eae-b72b-21b1359d0496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809860180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3809860180
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.1636027810
Short name T272
Test name
Test status
Simulation time 33044039112 ps
CPU time 29.84 seconds
Started Jun 27 04:56:53 PM PDT 24
Finished Jun 27 04:57:25 PM PDT 24
Peak memory 199864 kb
Host smart-31f151e9-b83b-486e-8954-304eaea0eb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636027810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1636027810
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.962869253
Short name T61
Test name
Test status
Simulation time 17092693 ps
CPU time 0.57 seconds
Started Jun 27 04:54:11 PM PDT 24
Finished Jun 27 04:54:14 PM PDT 24
Peak memory 195204 kb
Host smart-8c525df8-55c9-4008-8a1d-e33ab70865ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962869253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.962869253
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.1837287107
Short name T159
Test name
Test status
Simulation time 148948311043 ps
CPU time 69.87 seconds
Started Jun 27 04:54:12 PM PDT 24
Finished Jun 27 04:55:25 PM PDT 24
Peak memory 199916 kb
Host smart-03d5a950-e41d-49b2-94d7-02bb02a327b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837287107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.1837287107
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.3473040064
Short name T754
Test name
Test status
Simulation time 88257933180 ps
CPU time 72.83 seconds
Started Jun 27 04:54:09 PM PDT 24
Finished Jun 27 04:55:24 PM PDT 24
Peak memory 199872 kb
Host smart-afd799b6-a8c1-4388-9e98-d4de1726bb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473040064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3473040064
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1776876518
Short name T543
Test name
Test status
Simulation time 215210549140 ps
CPU time 51.52 seconds
Started Jun 27 04:54:11 PM PDT 24
Finished Jun 27 04:55:06 PM PDT 24
Peak memory 199832 kb
Host smart-320f8c09-c8b0-44ec-a061-982a990b14e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776876518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1776876518
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.3459920911
Short name T927
Test name
Test status
Simulation time 37838362704 ps
CPU time 62.95 seconds
Started Jun 27 04:54:07 PM PDT 24
Finished Jun 27 04:55:11 PM PDT 24
Peak memory 199836 kb
Host smart-2c11fb3d-0310-4419-bdf4-05fdf4e086ba
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459920911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3459920911
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.3402324331
Short name T423
Test name
Test status
Simulation time 100105636570 ps
CPU time 380.17 seconds
Started Jun 27 04:54:10 PM PDT 24
Finished Jun 27 05:00:32 PM PDT 24
Peak memory 199884 kb
Host smart-14b87a59-ede1-4133-929a-48895dbaaef7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3402324331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3402324331
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.2974066391
Short name T444
Test name
Test status
Simulation time 2829166931 ps
CPU time 2.43 seconds
Started Jun 27 04:54:09 PM PDT 24
Finished Jun 27 04:54:13 PM PDT 24
Peak memory 198832 kb
Host smart-b69c5b90-623c-4b22-9e65-14b025db7bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974066391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2974066391
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_perf.1467409323
Short name T1020
Test name
Test status
Simulation time 26520077918 ps
CPU time 1269.76 seconds
Started Jun 27 04:54:09 PM PDT 24
Finished Jun 27 05:15:20 PM PDT 24
Peak memory 199852 kb
Host smart-646a4fbc-9b37-431c-a254-65e3a0140c06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1467409323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1467409323
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.3532702684
Short name T354
Test name
Test status
Simulation time 1612480250 ps
CPU time 2.95 seconds
Started Jun 27 04:54:07 PM PDT 24
Finished Jun 27 04:54:11 PM PDT 24
Peak memory 198956 kb
Host smart-b8bc6699-804c-4e94-9b3f-d894843e5a83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3532702684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3532702684
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1646379349
Short name T383
Test name
Test status
Simulation time 55767663094 ps
CPU time 46.42 seconds
Started Jun 27 04:54:12 PM PDT 24
Finished Jun 27 04:55:01 PM PDT 24
Peak memory 199916 kb
Host smart-4646b48b-c2bb-45e8-b8c0-1c15e114698a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646379349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1646379349
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.694006744
Short name T726
Test name
Test status
Simulation time 4246913314 ps
CPU time 2.15 seconds
Started Jun 27 04:54:09 PM PDT 24
Finished Jun 27 04:54:13 PM PDT 24
Peak memory 196112 kb
Host smart-7d3b2388-9520-49bd-8aaa-00ff30d18ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694006744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.694006744
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.2942294484
Short name T356
Test name
Test status
Simulation time 115931464 ps
CPU time 1.06 seconds
Started Jun 27 04:53:57 PM PDT 24
Finished Jun 27 04:54:01 PM PDT 24
Peak memory 198824 kb
Host smart-1508e576-3961-46b1-ba9f-8a3107d84fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942294484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2942294484
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.2615372195
Short name T324
Test name
Test status
Simulation time 34274144959 ps
CPU time 86.05 seconds
Started Jun 27 04:54:08 PM PDT 24
Finished Jun 27 04:55:36 PM PDT 24
Peak memory 208232 kb
Host smart-0b8ccb0b-3a7d-49f6-ba5e-4adb3b599c1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615372195 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.2615372195
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3071693425
Short name T896
Test name
Test status
Simulation time 1028374765 ps
CPU time 3.99 seconds
Started Jun 27 04:54:09 PM PDT 24
Finished Jun 27 04:54:14 PM PDT 24
Peak memory 199540 kb
Host smart-5793e380-5c8b-460b-9e90-e082fbdfd94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071693425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3071693425
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.3825087490
Short name T815
Test name
Test status
Simulation time 7616918783 ps
CPU time 14.33 seconds
Started Jun 27 04:53:52 PM PDT 24
Finished Jun 27 04:54:08 PM PDT 24
Peak memory 199572 kb
Host smart-a6215fc2-d4ee-416f-addc-a6e7bba3d998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825087490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.3825087490
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.275617035
Short name T218
Test name
Test status
Simulation time 128395674811 ps
CPU time 171.87 seconds
Started Jun 27 04:56:54 PM PDT 24
Finished Jun 27 04:59:48 PM PDT 24
Peak memory 199844 kb
Host smart-fd6dc8c6-f52e-42ea-a86e-ae00115162a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275617035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.275617035
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.2210528544
Short name T32
Test name
Test status
Simulation time 11258562158 ps
CPU time 114.72 seconds
Started Jun 27 04:56:53 PM PDT 24
Finished Jun 27 04:58:51 PM PDT 24
Peak memory 215564 kb
Host smart-a2263b71-5410-4837-8e2c-7c3ce4e49581
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210528544 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.2210528544
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.27924175
Short name T611
Test name
Test status
Simulation time 32408930243 ps
CPU time 15.53 seconds
Started Jun 27 04:56:53 PM PDT 24
Finished Jun 27 04:57:12 PM PDT 24
Peak memory 199912 kb
Host smart-733561a2-f4d4-495f-857a-cf1200cd9cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27924175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.27924175
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.884914375
Short name T694
Test name
Test status
Simulation time 124724833593 ps
CPU time 37.02 seconds
Started Jun 27 04:56:53 PM PDT 24
Finished Jun 27 04:57:33 PM PDT 24
Peak memory 199920 kb
Host smart-432fa4a2-be2f-4458-9a8a-1d2c0e253327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884914375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.884914375
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.1814446298
Short name T186
Test name
Test status
Simulation time 26335270975 ps
CPU time 18.68 seconds
Started Jun 27 04:56:53 PM PDT 24
Finished Jun 27 04:57:15 PM PDT 24
Peak memory 199772 kb
Host smart-4deb41d0-a8d5-47f3-adb6-610fa355082b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814446298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.1814446298
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.2586393526
Short name T783
Test name
Test status
Simulation time 99417714419 ps
CPU time 66.29 seconds
Started Jun 27 04:56:51 PM PDT 24
Finished Jun 27 04:57:59 PM PDT 24
Peak memory 199904 kb
Host smart-e20e6f3e-e324-4717-9bf9-0e47d2f72ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586393526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2586393526
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.2732549452
Short name T633
Test name
Test status
Simulation time 72904699039 ps
CPU time 60.16 seconds
Started Jun 27 04:56:51 PM PDT 24
Finished Jun 27 04:57:54 PM PDT 24
Peak memory 199904 kb
Host smart-fea5770c-f251-46cf-8e79-9f7da41adb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732549452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2732549452
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.3412307538
Short name T975
Test name
Test status
Simulation time 135732554006 ps
CPU time 770.21 seconds
Started Jun 27 04:56:53 PM PDT 24
Finished Jun 27 05:09:46 PM PDT 24
Peak memory 216436 kb
Host smart-0076951c-aa87-4f71-9a36-f215a04f53d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412307538 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.3412307538
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.3632766426
Short name T636
Test name
Test status
Simulation time 11910142883 ps
CPU time 12.12 seconds
Started Jun 27 04:56:53 PM PDT 24
Finished Jun 27 04:57:08 PM PDT 24
Peak memory 199912 kb
Host smart-e81c4004-d62b-40b4-b1d4-1ff34602a4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632766426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3632766426
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.259483125
Short name T177
Test name
Test status
Simulation time 104500698116 ps
CPU time 163.57 seconds
Started Jun 27 04:56:56 PM PDT 24
Finished Jun 27 04:59:41 PM PDT 24
Peak memory 199952 kb
Host smart-bfc80cd9-d6b3-467b-a64a-a90f7387d8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259483125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.259483125
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.494030874
Short name T731
Test name
Test status
Simulation time 25070115860 ps
CPU time 28.68 seconds
Started Jun 27 04:56:52 PM PDT 24
Finished Jun 27 04:57:23 PM PDT 24
Peak memory 199992 kb
Host smart-e4fbac4f-90d7-4d51-bb5d-57d1145c9803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494030874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.494030874
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.3565172790
Short name T381
Test name
Test status
Simulation time 80497873 ps
CPU time 0.55 seconds
Started Jun 27 04:54:10 PM PDT 24
Finished Jun 27 04:54:12 PM PDT 24
Peak memory 195204 kb
Host smart-42ba1266-545a-449c-bc88-f75a43561b5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565172790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.3565172790
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.2509197852
Short name T388
Test name
Test status
Simulation time 48904588303 ps
CPU time 112.51 seconds
Started Jun 27 04:54:10 PM PDT 24
Finished Jun 27 04:56:05 PM PDT 24
Peak memory 199860 kb
Host smart-f1d02da0-7632-493b-a214-c35f98210f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509197852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2509197852
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.1191098212
Short name T767
Test name
Test status
Simulation time 56152224678 ps
CPU time 88.64 seconds
Started Jun 27 04:54:08 PM PDT 24
Finished Jun 27 04:55:38 PM PDT 24
Peak memory 199892 kb
Host smart-63596a37-b882-4daf-a95d-dc32cb0ca426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191098212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.1191098212
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.898323911
Short name T106
Test name
Test status
Simulation time 7458569327 ps
CPU time 6.76 seconds
Started Jun 27 04:54:11 PM PDT 24
Finished Jun 27 04:54:21 PM PDT 24
Peak memory 196556 kb
Host smart-2a964d4a-b0d8-4b3c-bcf3-14edfe882500
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898323911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.898323911
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.1288048836
Short name T352
Test name
Test status
Simulation time 200965080612 ps
CPU time 1305.68 seconds
Started Jun 27 04:54:10 PM PDT 24
Finished Jun 27 05:15:58 PM PDT 24
Peak memory 199968 kb
Host smart-47c65656-c07a-42e7-9537-e1a1aa5686f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1288048836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.1288048836
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.3866132978
Short name T491
Test name
Test status
Simulation time 56250721 ps
CPU time 0.7 seconds
Started Jun 27 04:54:10 PM PDT 24
Finished Jun 27 04:54:12 PM PDT 24
Peak memory 195832 kb
Host smart-9855f8f1-5841-43c4-972c-8f7332b24429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866132978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.3866132978
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_perf.3783100426
Short name T733
Test name
Test status
Simulation time 8323139742 ps
CPU time 430 seconds
Started Jun 27 04:54:10 PM PDT 24
Finished Jun 27 05:01:23 PM PDT 24
Peak memory 199892 kb
Host smart-ba80a2fe-40a5-41da-8937-3f1a41ac1a56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3783100426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3783100426
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.448091649
Short name T1034
Test name
Test status
Simulation time 4088948756 ps
CPU time 34.03 seconds
Started Jun 27 04:54:10 PM PDT 24
Finished Jun 27 04:54:46 PM PDT 24
Peak memory 198176 kb
Host smart-a7bb3a28-d25d-4972-b654-c2827eca5fb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=448091649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.448091649
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.2137023465
Short name T591
Test name
Test status
Simulation time 18273494814 ps
CPU time 30.51 seconds
Started Jun 27 04:54:09 PM PDT 24
Finished Jun 27 04:54:42 PM PDT 24
Peak memory 199828 kb
Host smart-3280a7fa-7911-415a-a47c-b694a3564380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137023465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2137023465
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.601457083
Short name T402
Test name
Test status
Simulation time 3070829195 ps
CPU time 2.94 seconds
Started Jun 27 04:54:10 PM PDT 24
Finished Jun 27 04:54:15 PM PDT 24
Peak memory 196196 kb
Host smart-2977753c-e277-4c8e-96d2-51997159dce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601457083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.601457083
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.2159600582
Short name T908
Test name
Test status
Simulation time 6077677241 ps
CPU time 9.75 seconds
Started Jun 27 04:54:10 PM PDT 24
Finished Jun 27 04:54:21 PM PDT 24
Peak memory 199900 kb
Host smart-267b9a34-1ef6-46b3-98f5-8717f0f39077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159600582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.2159600582
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3875279979
Short name T463
Test name
Test status
Simulation time 1407651346 ps
CPU time 4.79 seconds
Started Jun 27 04:54:11 PM PDT 24
Finished Jun 27 04:54:19 PM PDT 24
Peak memory 198344 kb
Host smart-83993cdc-2afb-4873-a695-5a9105f26592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875279979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3875279979
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3429719833
Short name T265
Test name
Test status
Simulation time 45546779205 ps
CPU time 89.66 seconds
Started Jun 27 04:54:10 PM PDT 24
Finished Jun 27 04:55:42 PM PDT 24
Peak memory 199972 kb
Host smart-09414278-5cc0-4adc-a95d-decd2af78ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429719833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3429719833
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.1102910184
Short name T42
Test name
Test status
Simulation time 33961490937 ps
CPU time 11.97 seconds
Started Jun 27 04:56:52 PM PDT 24
Finished Jun 27 04:57:06 PM PDT 24
Peak memory 199640 kb
Host smart-07a57c72-8eeb-4f9c-9faf-a9097ea9942d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102910184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.1102910184
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.3325483979
Short name T62
Test name
Test status
Simulation time 47247798164 ps
CPU time 89.23 seconds
Started Jun 27 04:56:53 PM PDT 24
Finished Jun 27 04:58:25 PM PDT 24
Peak memory 199832 kb
Host smart-0d217d58-f465-4cd6-8fc2-c59c9b36b329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325483979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3325483979
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.209789918
Short name T321
Test name
Test status
Simulation time 28249899540 ps
CPU time 117.87 seconds
Started Jun 27 04:57:11 PM PDT 24
Finished Jun 27 04:59:11 PM PDT 24
Peak memory 216360 kb
Host smart-a7aedf10-7a79-4aa9-bbf8-d572f02ac361
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209789918 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.209789918
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.3045564176
Short name T311
Test name
Test status
Simulation time 256242618360 ps
CPU time 490.52 seconds
Started Jun 27 04:57:11 PM PDT 24
Finished Jun 27 05:05:24 PM PDT 24
Peak memory 216452 kb
Host smart-a3ae788e-9acc-4cd5-8adc-504ecd674b50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045564176 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.3045564176
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.3180239329
Short name T533
Test name
Test status
Simulation time 49402367029 ps
CPU time 79.32 seconds
Started Jun 27 04:57:12 PM PDT 24
Finished Jun 27 04:58:34 PM PDT 24
Peak memory 199924 kb
Host smart-04352d94-75a8-4e18-ad6f-76df59309837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180239329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3180239329
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.90487809
Short name T85
Test name
Test status
Simulation time 114021398233 ps
CPU time 701.37 seconds
Started Jun 27 04:57:04 PM PDT 24
Finished Jun 27 05:08:47 PM PDT 24
Peak memory 216488 kb
Host smart-7496a4e8-1272-498c-9849-3d5b0b99b84f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90487809 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.90487809
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.1627487336
Short name T434
Test name
Test status
Simulation time 47756931982 ps
CPU time 15.9 seconds
Started Jun 27 04:57:12 PM PDT 24
Finished Jun 27 04:57:31 PM PDT 24
Peak memory 199948 kb
Host smart-a11608ed-9e68-49fd-bc8b-3a8cd58116f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627487336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1627487336
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.3797947295
Short name T227
Test name
Test status
Simulation time 51334311715 ps
CPU time 152.61 seconds
Started Jun 27 04:57:05 PM PDT 24
Finished Jun 27 04:59:39 PM PDT 24
Peak memory 216228 kb
Host smart-736e2e09-765f-43fc-938b-c4652dce1aa9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797947295 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.3797947295
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.3621227498
Short name T574
Test name
Test status
Simulation time 24075484146 ps
CPU time 48.33 seconds
Started Jun 27 04:57:10 PM PDT 24
Finished Jun 27 04:58:00 PM PDT 24
Peak memory 199960 kb
Host smart-f65b330c-a5c0-446b-858f-a65c1c7090cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621227498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3621227498
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.1854129571
Short name T634
Test name
Test status
Simulation time 40626141526 ps
CPU time 100.69 seconds
Started Jun 27 04:57:03 PM PDT 24
Finished Jun 27 04:58:45 PM PDT 24
Peak memory 208292 kb
Host smart-d2c57370-48b8-49b6-b0f8-e995fddb03fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854129571 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.1854129571
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.1540296020
Short name T173
Test name
Test status
Simulation time 119470552626 ps
CPU time 223.05 seconds
Started Jun 27 04:57:03 PM PDT 24
Finished Jun 27 05:00:47 PM PDT 24
Peak memory 199988 kb
Host smart-0c79333a-3185-4e26-9e02-3e9d7ad599a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540296020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1540296020
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.3026833077
Short name T128
Test name
Test status
Simulation time 99634314061 ps
CPU time 41.11 seconds
Started Jun 27 04:57:07 PM PDT 24
Finished Jun 27 04:57:49 PM PDT 24
Peak memory 199700 kb
Host smart-65cc1f06-5dce-43cc-9b6f-ad4a1b9023a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026833077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3026833077
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.1927728471
Short name T92
Test name
Test status
Simulation time 50917291468 ps
CPU time 79.31 seconds
Started Jun 27 04:57:05 PM PDT 24
Finished Jun 27 04:58:26 PM PDT 24
Peak memory 199716 kb
Host smart-4f10fe03-e21b-4e9d-b3a9-6ce59251277b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927728471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1927728471
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.3565933550
Short name T792
Test name
Test status
Simulation time 742668383199 ps
CPU time 544.8 seconds
Started Jun 27 04:57:07 PM PDT 24
Finished Jun 27 05:06:13 PM PDT 24
Peak memory 216476 kb
Host smart-7af54d4a-ec23-45f3-bdd5-9903a2814a2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565933550 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.3565933550
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3942933107
Short name T704
Test name
Test status
Simulation time 95130576584 ps
CPU time 148.12 seconds
Started Jun 27 04:57:05 PM PDT 24
Finished Jun 27 04:59:34 PM PDT 24
Peak memory 199728 kb
Host smart-f28c6e2b-78f6-4eb8-9e44-4ea3f9c5277c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942933107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3942933107
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.1809735702
Short name T516
Test name
Test status
Simulation time 16443751 ps
CPU time 0.57 seconds
Started Jun 27 04:54:17 PM PDT 24
Finished Jun 27 04:54:18 PM PDT 24
Peak memory 195192 kb
Host smart-62dc5bce-19a7-49fa-9f4e-e9df358cddea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809735702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.1809735702
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.3814206825
Short name T610
Test name
Test status
Simulation time 76884420149 ps
CPU time 136.87 seconds
Started Jun 27 04:54:12 PM PDT 24
Finished Jun 27 04:56:31 PM PDT 24
Peak memory 199876 kb
Host smart-0ec702a8-484a-44ab-a136-65eb60ef49d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814206825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3814206825
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.3932893398
Short name T464
Test name
Test status
Simulation time 23307657839 ps
CPU time 31.33 seconds
Started Jun 27 04:54:08 PM PDT 24
Finished Jun 27 04:54:40 PM PDT 24
Peak memory 199756 kb
Host smart-ec1e3643-4e73-4606-ac74-7fca374f9c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932893398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.3932893398
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.4025485563
Short name T609
Test name
Test status
Simulation time 226136344921 ps
CPU time 419.72 seconds
Started Jun 27 04:54:11 PM PDT 24
Finished Jun 27 05:01:14 PM PDT 24
Peak memory 199848 kb
Host smart-a5219684-59af-45f0-a5e0-3845c5547ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025485563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.4025485563
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.2854386112
Short name T427
Test name
Test status
Simulation time 37871946239 ps
CPU time 37.89 seconds
Started Jun 27 04:54:12 PM PDT 24
Finished Jun 27 04:54:53 PM PDT 24
Peak memory 199924 kb
Host smart-e6d2dbef-5048-4977-879b-da5dae70dd36
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854386112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2854386112
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.1125613004
Short name T725
Test name
Test status
Simulation time 57402432953 ps
CPU time 237.07 seconds
Started Jun 27 04:54:14 PM PDT 24
Finished Jun 27 04:58:13 PM PDT 24
Peak memory 199948 kb
Host smart-ab00500a-e662-42a6-a64c-e36426a041b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1125613004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1125613004
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1057129107
Short name T418
Test name
Test status
Simulation time 9612639538 ps
CPU time 12.11 seconds
Started Jun 27 04:54:12 PM PDT 24
Finished Jun 27 04:54:27 PM PDT 24
Peak memory 199732 kb
Host smart-ae91fb46-7edf-47ed-b031-594ea960d6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057129107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1057129107
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_perf.1423781694
Short name T685
Test name
Test status
Simulation time 18606173369 ps
CPU time 208.94 seconds
Started Jun 27 04:54:14 PM PDT 24
Finished Jun 27 04:57:45 PM PDT 24
Peak memory 199888 kb
Host smart-4ca92d81-c411-48b8-a110-fedfd719919a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1423781694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1423781694
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.271419627
Short name T698
Test name
Test status
Simulation time 2126500408 ps
CPU time 2.67 seconds
Started Jun 27 04:54:09 PM PDT 24
Finished Jun 27 04:54:14 PM PDT 24
Peak memory 198004 kb
Host smart-310c5c51-cc9c-4ea1-82a0-ad80c0ad6b46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=271419627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.271419627
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.2173875806
Short name T711
Test name
Test status
Simulation time 114932304023 ps
CPU time 44.82 seconds
Started Jun 27 04:54:13 PM PDT 24
Finished Jun 27 04:55:01 PM PDT 24
Peak memory 199808 kb
Host smart-d02b54bb-c94d-487c-b20d-1db0007074e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173875806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2173875806
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.231556398
Short name T923
Test name
Test status
Simulation time 1474022964 ps
CPU time 1.52 seconds
Started Jun 27 04:54:12 PM PDT 24
Finished Jun 27 04:54:16 PM PDT 24
Peak memory 195392 kb
Host smart-b51d4d7f-7a0f-4684-8eb4-6b6e242b0c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231556398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.231556398
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.3497205368
Short name T404
Test name
Test status
Simulation time 6208485436 ps
CPU time 24.96 seconds
Started Jun 27 04:54:10 PM PDT 24
Finished Jun 27 04:54:37 PM PDT 24
Peak memory 199072 kb
Host smart-a924d872-6717-4d15-8f71-6736e541c40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497205368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3497205368
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.1144585996
Short name T831
Test name
Test status
Simulation time 159162279258 ps
CPU time 471.2 seconds
Started Jun 27 04:54:14 PM PDT 24
Finished Jun 27 05:02:08 PM PDT 24
Peak memory 199824 kb
Host smart-bcb96d84-ae63-4316-94db-4a64a844cf62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144585996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.1144585996
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.1159093982
Short name T319
Test name
Test status
Simulation time 74975516380 ps
CPU time 385.05 seconds
Started Jun 27 04:54:17 PM PDT 24
Finished Jun 27 05:00:43 PM PDT 24
Peak memory 216416 kb
Host smart-7ed1d3e6-8004-4d16-96b5-35ba0c78da36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159093982 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.1159093982
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.553733131
Short name T837
Test name
Test status
Simulation time 1177518512 ps
CPU time 1.2 seconds
Started Jun 27 04:54:15 PM PDT 24
Finished Jun 27 04:54:18 PM PDT 24
Peak memory 196868 kb
Host smart-b84b8879-25da-46bd-8658-a93ae2bd32d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553733131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.553733131
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.1759242855
Short name T781
Test name
Test status
Simulation time 108381137322 ps
CPU time 85.93 seconds
Started Jun 27 04:54:11 PM PDT 24
Finished Jun 27 04:55:39 PM PDT 24
Peak memory 199928 kb
Host smart-9891e302-295e-4cf1-b762-1f01f9171e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759242855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.1759242855
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.4058629484
Short name T104
Test name
Test status
Simulation time 90535660699 ps
CPU time 133.32 seconds
Started Jun 27 04:57:04 PM PDT 24
Finished Jun 27 04:59:18 PM PDT 24
Peak memory 199704 kb
Host smart-35ca27b9-e690-4208-ac1b-784b35e3c2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058629484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.4058629484
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.1263443237
Short name T659
Test name
Test status
Simulation time 33803232855 ps
CPU time 56.21 seconds
Started Jun 27 04:57:06 PM PDT 24
Finished Jun 27 04:58:03 PM PDT 24
Peak memory 199960 kb
Host smart-64c34c01-f9df-461c-93d1-815441c7788e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263443237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.1263443237
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.2579117917
Short name T1035
Test name
Test status
Simulation time 60811636169 ps
CPU time 541.01 seconds
Started Jun 27 04:57:04 PM PDT 24
Finished Jun 27 05:06:06 PM PDT 24
Peak memory 216288 kb
Host smart-a448fdb8-339e-4f53-b226-5f751f02436c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579117917 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.2579117917
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.2398795499
Short name T915
Test name
Test status
Simulation time 104350003151 ps
CPU time 39.04 seconds
Started Jun 27 04:57:05 PM PDT 24
Finished Jun 27 04:57:45 PM PDT 24
Peak memory 199928 kb
Host smart-74441767-b3df-45c7-97c7-d96ec4ae78c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398795499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.2398795499
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.41444740
Short name T1029
Test name
Test status
Simulation time 74901272589 ps
CPU time 692.57 seconds
Started Jun 27 04:57:13 PM PDT 24
Finished Jun 27 05:08:48 PM PDT 24
Peak memory 225848 kb
Host smart-5c378b5c-f9ad-4759-be05-ac1db1272fde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41444740 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.41444740
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.811969257
Short name T1052
Test name
Test status
Simulation time 295956326054 ps
CPU time 25.94 seconds
Started Jun 27 04:57:03 PM PDT 24
Finished Jun 27 04:57:30 PM PDT 24
Peak memory 199896 kb
Host smart-03869e8c-f370-4a7c-8fd6-d1c9b4a08472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811969257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.811969257
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3506021701
Short name T795
Test name
Test status
Simulation time 72646407670 ps
CPU time 29.52 seconds
Started Jun 27 04:57:08 PM PDT 24
Finished Jun 27 04:57:38 PM PDT 24
Peak memory 199840 kb
Host smart-953448fb-c56d-4c6a-b393-99fba1a01578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506021701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3506021701
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.2341155692
Short name T953
Test name
Test status
Simulation time 299119215710 ps
CPU time 754 seconds
Started Jun 27 04:57:07 PM PDT 24
Finished Jun 27 05:09:42 PM PDT 24
Peak memory 216492 kb
Host smart-97398d96-9f21-41c5-a90a-3d1d19984d0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341155692 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.2341155692
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.1017313521
Short name T936
Test name
Test status
Simulation time 123177102509 ps
CPU time 52.32 seconds
Started Jun 27 04:57:05 PM PDT 24
Finished Jun 27 04:57:59 PM PDT 24
Peak memory 199968 kb
Host smart-5e7eaa8c-0a6f-4fdf-b9c7-aaccb4dbed2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017313521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1017313521
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.3218041894
Short name T47
Test name
Test status
Simulation time 136374197512 ps
CPU time 317.13 seconds
Started Jun 27 04:57:07 PM PDT 24
Finished Jun 27 05:02:25 PM PDT 24
Peak memory 216308 kb
Host smart-02dd7bc7-bd3d-4d24-8bb7-a212ed46b60a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218041894 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.3218041894
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.4136564095
Short name T13
Test name
Test status
Simulation time 52961266551 ps
CPU time 36.2 seconds
Started Jun 27 04:57:09 PM PDT 24
Finished Jun 27 04:57:46 PM PDT 24
Peak memory 199708 kb
Host smart-ce375147-c673-44b8-b1b7-995b77def014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136564095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.4136564095
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.3194951083
Short name T331
Test name
Test status
Simulation time 25406962482 ps
CPU time 11.88 seconds
Started Jun 27 04:57:11 PM PDT 24
Finished Jun 27 04:57:24 PM PDT 24
Peak memory 200004 kb
Host smart-2b3247be-21ed-4920-b16a-4245d067414b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194951083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.3194951083
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.1783236287
Short name T604
Test name
Test status
Simulation time 188308748697 ps
CPU time 881.86 seconds
Started Jun 27 04:57:12 PM PDT 24
Finished Jun 27 05:11:57 PM PDT 24
Peak memory 216436 kb
Host smart-3c07816a-b90d-4ea4-ac6b-960a78c5842f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783236287 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1783236287
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.2117616646
Short name T205
Test name
Test status
Simulation time 42986171746 ps
CPU time 50.23 seconds
Started Jun 27 04:57:11 PM PDT 24
Finished Jun 27 04:58:03 PM PDT 24
Peak memory 200004 kb
Host smart-fc9630c9-1328-41a8-9c6e-6949b19c43ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117616646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2117616646
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.3678783083
Short name T1044
Test name
Test status
Simulation time 42897768621 ps
CPU time 16.99 seconds
Started Jun 27 04:57:05 PM PDT 24
Finished Jun 27 04:57:23 PM PDT 24
Peak memory 199004 kb
Host smart-16db1e2f-f57f-4944-af82-d006a2b858c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678783083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.3678783083
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1891792847
Short name T498
Test name
Test status
Simulation time 24381506389 ps
CPU time 179.29 seconds
Started Jun 27 04:57:11 PM PDT 24
Finished Jun 27 05:00:12 PM PDT 24
Peak memory 208280 kb
Host smart-97d42d39-5e91-438f-aeb9-da14f84dfdc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891792847 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1891792847
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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