Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100365	1			T1	16		T2	60		T3	1
all_values[1]	100365	1			T1	16		T2	60		T3	1
all_values[2]	100365	1			T1	16		T2	60		T3	1
all_values[3]	100365	1			T1	16		T2	60		T3	1
all_values[4]	100365	1			T1	16		T2	60		T3	1
all_values[5]	100365	1			T1	16		T2	60		T3	1
all_values[6]	100365	1			T1	16		T2	60		T3	1
all_values[7]	100365	1			T1	16		T2	60		T3	1
all_values[8]	100365	1			T1	16		T2	60		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

430716

1

T1

73

T2

263

T3

7

auto[1]

472569

1

T1

71

T2

277

T3

2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

825741

1

T1

114

T2

534

T3

7

auto[1]

77544

1

T1

30

T2

6

T3

2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	33529	1			T1	9		T2	20		T5	36
all_values[0]	auto[0]	auto[1]	18797	1			T1	3		T2	1		T3	1
all_values[0]	auto[1]	auto[0]	28715	1			T2	39		T5	125		T6	295
all_values[0]	auto[1]	auto[1]	19324	1			T1	4		T5	214		T6	91
all_values[1]	auto[0]	auto[0]	47314	1			T1	5		T2	22		T3	1
all_values[1]	auto[0]	auto[1]	1527	1			T5	13		T14	15		T12	42
all_values[1]	auto[1]	auto[0]	50028	1			T1	3		T2	38		T5	255
all_values[1]	auto[1]	auto[1]	1496	1			T1	8		T5	3		T8	13
all_values[2]	auto[0]	auto[0]	50367	1			T1	10		T2	38		T3	1
all_values[2]	auto[0]	auto[1]	2261	1			T1	6		T2	1		T4	1
all_values[2]	auto[1]	auto[0]	45647	1			T2	18		T5	120		T6	474
all_values[2]	auto[1]	auto[1]	2090	1			T2	3		T5	13		T6	4
all_values[3]	auto[0]	auto[0]	48116	1			T2	20		T3	1		T4	2
all_values[3]	auto[0]	auto[1]	235	1			T5	7		T12	7		T13	2
all_values[3]	auto[1]	auto[0]	51725	1			T1	16		T2	40		T5	215
all_values[3]	auto[1]	auto[1]	289	1			T5	2		T35	1		T27	4
all_values[4]	auto[0]	auto[0]	48628	1			T1	4		T2	41		T4	2
all_values[4]	auto[0]	auto[1]	360	1			T5	3		T14	6		T12	5
all_values[4]	auto[1]	auto[0]	50971	1			T1	12		T2	19		T3	1
all_values[4]	auto[1]	auto[1]	406	1			T5	10		T12	1		T27	3
all_values[5]	auto[0]	auto[0]	45115	1			T1	14		T2	20		T3	1
all_values[5]	auto[0]	auto[1]	132	1			T5	6		T27	2		T16	1
all_values[5]	auto[1]	auto[0]	54968	1			T1	2		T2	40		T5	193
all_values[5]	auto[1]	auto[1]	150	1			T5	5		T16	4		T28	3
all_values[6]	auto[0]	auto[0]	46707	1			T1	5		T2	1		T4	2
all_values[6]	auto[0]	auto[1]	128	1			T5	4		T27	1		T16	1
all_values[6]	auto[1]	auto[0]	53423	1			T1	11		T2	59		T3	1
all_values[6]	auto[1]	auto[1]	107	1			T5	3		T27	4		T16	2
all_values[7]	auto[0]	auto[0]	44262	1			T1	9		T2	58		T3	1
all_values[7]	auto[0]	auto[1]	264	1			T1	3		T5	1		T26	3
all_values[7]	auto[1]	auto[0]	55516	1			T1	3		T2	2		T5	342
all_values[7]	auto[1]	auto[1]	323	1			T1	1		T5	7		T14	2
all_values[8]	auto[0]	auto[0]	30555	1			T1	2		T2	41		T5	121
all_values[8]	auto[0]	auto[1]	12419	1			T1	3		T3	1		T4	2
all_values[8]	auto[1]	auto[0]	40155	1			T1	9		T2	18		T5	83
all_values[8]	auto[1]	auto[1]	17236	1			T1	2		T2	1		T5	36