Summary for Variable cp_dir
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_dir
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[UartTx] |
2272 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[UartRx] |
2272 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_rst_pos
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
11 |
0 |
11 |
100.00 |
User Defined Bins for cp_rst_pos
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0] |
4108 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
values[1] |
27 |
1 |
|
|
T5 |
1 |
|
T208 |
1 |
|
T299 |
1 |
values[2] |
46 |
1 |
|
|
T5 |
1 |
|
T26 |
1 |
|
T29 |
3 |
values[3] |
28 |
1 |
|
|
T5 |
2 |
|
T6 |
1 |
|
T13 |
1 |
values[4] |
33 |
1 |
|
|
T5 |
1 |
|
T13 |
1 |
|
T27 |
2 |
values[5] |
44 |
1 |
|
|
T13 |
1 |
|
T26 |
2 |
|
T30 |
2 |
values[6] |
44 |
1 |
|
|
T13 |
1 |
|
T27 |
1 |
|
T31 |
2 |
values[7] |
45 |
1 |
|
|
T5 |
4 |
|
T13 |
2 |
|
T27 |
1 |
values[8] |
36 |
1 |
|
|
T27 |
1 |
|
T30 |
2 |
|
T31 |
1 |
values[9] |
52 |
1 |
|
|
T5 |
1 |
|
T13 |
3 |
|
T28 |
3 |
values[10] |
54 |
1 |
|
|
T6 |
1 |
|
T13 |
2 |
|
T27 |
1 |
Summary for Cross uart_reset_cg_cc
Samples crossed: cp_dir cp_rst_pos
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
22 |
0 |
22 |
100.00 |
|
Automatically Generated Cross Bins for uart_reset_cg_cc
Bins
cp_dir | cp_rst_pos | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[UartTx] |
values[0] |
2118 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[UartTx] |
values[1] |
3 |
1 |
|
|
T300 |
1 |
|
T301 |
1 |
|
T302 |
1 |
auto[UartTx] |
values[2] |
21 |
1 |
|
|
T5 |
1 |
|
T26 |
1 |
|
T29 |
2 |
auto[UartTx] |
values[3] |
8 |
1 |
|
|
T5 |
2 |
|
T300 |
1 |
|
T303 |
1 |
auto[UartTx] |
values[4] |
13 |
1 |
|
|
T5 |
1 |
|
T13 |
1 |
|
T27 |
1 |
auto[UartTx] |
values[5] |
21 |
1 |
|
|
T13 |
1 |
|
T26 |
1 |
|
T30 |
1 |
auto[UartTx] |
values[6] |
11 |
1 |
|
|
T27 |
1 |
|
T31 |
1 |
|
T32 |
1 |
auto[UartTx] |
values[7] |
18 |
1 |
|
|
T5 |
1 |
|
T28 |
1 |
|
T30 |
3 |
auto[UartTx] |
values[8] |
12 |
1 |
|
|
T31 |
1 |
|
T208 |
1 |
|
T303 |
1 |
auto[UartTx] |
values[9] |
19 |
1 |
|
|
T5 |
1 |
|
T13 |
1 |
|
T28 |
1 |
auto[UartTx] |
values[10] |
14 |
1 |
|
|
T13 |
1 |
|
T97 |
1 |
|
T304 |
1 |
auto[UartRx] |
values[0] |
1990 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[UartRx] |
values[1] |
24 |
1 |
|
|
T5 |
1 |
|
T208 |
1 |
|
T299 |
1 |
auto[UartRx] |
values[2] |
25 |
1 |
|
|
T29 |
1 |
|
T30 |
1 |
|
T97 |
2 |
auto[UartRx] |
values[3] |
20 |
1 |
|
|
T6 |
1 |
|
T13 |
1 |
|
T27 |
1 |
auto[UartRx] |
values[4] |
20 |
1 |
|
|
T27 |
1 |
|
T28 |
1 |
|
T32 |
1 |
auto[UartRx] |
values[5] |
23 |
1 |
|
|
T26 |
1 |
|
T30 |
1 |
|
T31 |
1 |
auto[UartRx] |
values[6] |
33 |
1 |
|
|
T13 |
1 |
|
T31 |
1 |
|
T32 |
1 |
auto[UartRx] |
values[7] |
27 |
1 |
|
|
T5 |
3 |
|
T13 |
2 |
|
T27 |
1 |
auto[UartRx] |
values[8] |
24 |
1 |
|
|
T27 |
1 |
|
T30 |
2 |
|
T208 |
1 |
auto[UartRx] |
values[9] |
33 |
1 |
|
|
T13 |
2 |
|
T28 |
2 |
|
T29 |
2 |
auto[UartRx] |
values[10] |
40 |
1 |
|
|
T6 |
1 |
|
T13 |
1 |
|
T27 |
1 |