Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2038	1			T3	14		T5	20		T6	1
auto[BaudRate115200]	1734	1			T5	18		T6	2		T9	1
auto[BaudRate230400]	1550	1			T1	1		T4	1		T5	17
auto[BaudRate128Kbps]	1700	1			T4	1		T5	10		T6	3
auto[BaudRate256Kbps]	1841	1			T1	2		T2	2		T5	25
auto[BaudRate1Mbps]	1589	1			T1	2		T2	1		T5	16
auto[BaudRate1p5Mbps]	1167	1			T2	6		T6	5		T8	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1089	1			T12	4		T19	32		T75	5
freqs[25]	883	1			T4	2		T116	5		T35	8
freqs[48]	660	1			T1	5		T3	14		T7	6
freqs[50]	557	1			T110	9		T305	8		T113	6
freqs[100]	782	1			T6	15		T8	10		T10	9

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	198	1			T19	6		T75	2		T26	2
auto[BaudRate9600]	freqs[25]	127	1			T116	2		T306	6		T222	4
auto[BaudRate9600]	freqs[48]	115	1			T3	14		T7	1		T13	4
auto[BaudRate9600]	freqs[50]	112	1			T110	1		T305	8		T113	1
auto[BaudRate9600]	freqs[100]	140	1			T6	1		T107	1		T307	1
auto[BaudRate115200]	freqs[24]	135	1			T19	5		T26	5		T231	2
auto[BaudRate115200]	freqs[25]	137	1			T35	1		T306	6		T38	3
auto[BaudRate115200]	freqs[48]	97	1			T13	5		T169	2		T117	3
auto[BaudRate115200]	freqs[50]	66	1			T110	1		T129	1		T252	1
auto[BaudRate115200]	freqs[100]	110	1			T6	2		T14	1		T263	1
auto[BaudRate230400]	freqs[24]	147	1			T12	2		T19	7		T75	1
auto[BaudRate230400]	freqs[25]	110	1			T4	1		T116	1		T35	2
auto[BaudRate230400]	freqs[48]	88	1			T1	1		T7	1		T13	5
auto[BaudRate230400]	freqs[50]	62	1			T110	5		T113	1		T120	1
auto[BaudRate230400]	freqs[100]	104	1			T6	3		T8	2		T14	1
auto[BaudRate128Kbps]	freqs[24]	152	1			T12	2		T19	1		T75	1
auto[BaudRate128Kbps]	freqs[25]	143	1			T4	1		T306	5		T38	3
auto[BaudRate128Kbps]	freqs[48]	79	1			T7	1		T13	5		T169	1
auto[BaudRate128Kbps]	freqs[50]	82	1			T110	1		T113	1		T129	2
auto[BaudRate128Kbps]	freqs[100]	97	1			T6	3		T8	2		T268	1
auto[BaudRate256Kbps]	freqs[24]	206	1			T19	5		T227	5		T26	4
auto[BaudRate256Kbps]	freqs[25]	147	1			T116	2		T35	2		T306	9
auto[BaudRate256Kbps]	freqs[48]	97	1			T1	2		T7	2		T13	12
auto[BaudRate256Kbps]	freqs[50]	80	1			T129	1		T242	1		T292	1
auto[BaudRate256Kbps]	freqs[100]	110	1			T8	1		T10	4		T268	1
auto[BaudRate1Mbps]	freqs[24]	167	1			T19	8		T75	1		T227	1
auto[BaudRate1Mbps]	freqs[25]	133	1			T35	3		T306	3		T222	2
auto[BaudRate1Mbps]	freqs[48]	106	1			T1	2		T7	1		T13	5
auto[BaudRate1Mbps]	freqs[50]	80	1			T110	1		T113	1		T129	1
auto[BaudRate1Mbps]	freqs[100]	117	1			T6	1		T8	3		T10	1
auto[BaudRate1p5Mbps]	freqs[25]	86	1			T306	3		T38	1		T222	1
auto[BaudRate1p5Mbps]	freqs[48]	78	1			T13	5		T169	1		T117	2
auto[BaudRate1p5Mbps]	freqs[50]	75	1			T113	2		T129	2		T252	1
auto[BaudRate1p5Mbps]	freqs[100]	104	1			T6	5		T8	2		T10	4

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded