Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	11	119	91.54

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	11	119	91.54	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	28408245	1			T1	13		T2	93637		T3	1
all_levels[1]	187966	1			T2	3288		T5	135		T6	170
all_levels[2]	1860	1			T5	1		T6	2		T8	4
all_levels[3]	993	1			T5	1		T8	2		T19	4
all_levels[4]	659	1			T8	1		T19	1		T13	2
all_levels[5]	479	1			T5	2		T8	2		T19	1
all_levels[6]	384	1			T1	1		T5	1		T19	1
all_levels[7]	308	1			T8	1		T19	2		T13	1
all_levels[8]	281	1			T110	1		T34	5		T111	1
all_levels[9]	246	1			T110	1		T36	1		T112	1
all_levels[10]	233	1			T1	1		T5	1		T13	1
all_levels[11]	189	1			T1	1		T5	1		T8	1
all_levels[12]	132	1			T5	1		T13	1		T113	2
all_levels[13]	147	1			T1	2		T8	1		T13	2
all_levels[14]	122	1			T1	1		T8	2		T19	2
all_levels[15]	93	1			T13	1		T114	2		T115	1
all_levels[16]	95	1			T1	1		T116	1		T35	1
all_levels[17]	92	1			T8	2		T117	1		T115	1
all_levels[18]	89	1			T1	1		T8	1		T36	1
all_levels[19]	76	1			T5	1		T8	1		T115	1
all_levels[20]	83	1			T13	2		T36	2		T118	1
all_levels[21]	60	1			T13	1		T119	1		T16	1
all_levels[22]	68	1			T8	1		T13	2		T114	1
all_levels[23]	59	1			T120	1		T121	2		T122	1
all_levels[24]	72	1			T5	1		T26	1		T111	1
all_levels[25]	71	1			T35	2		T123	1		T115	1
all_levels[26]	34	1			T5	1		T13	1		T119	1
all_levels[27]	31	1			T5	1		T124	1		T125	1
all_levels[28]	38	1			T114	1		T124	1		T125	1
all_levels[29]	39	1			T123	1		T126	1		T125	1
all_levels[30]	39	1			T1	1		T13	1		T110	1
all_levels[31]	48	1			T8	1		T114	1		T119	1
all_levels[32]	40	1			T116	1		T118	1		T127	1
all_levels[33]	38	1			T1	1		T5	1		T119	2
all_levels[34]	24	1			T118	1		T121	1		T127	1
all_levels[35]	30	1			T1	1		T26	1		T128	1
all_levels[36]	24	1			T26	1		T129	1		T120	1
all_levels[37]	21	1			T130	1		T131	1		T132	2
all_levels[38]	15	1			T26	1		T16	1		T127	1
all_levels[39]	12	1			T26	1		T133	1		T134	2
all_levels[40]	21	1			T114	1		T135	1		T136	1
all_levels[41]	19	1			T13	2		T137	1		T138	2
all_levels[42]	25	1			T114	1		T104	2		T16	1
all_levels[43]	14	1			T139	1		T140	1		T141	1
all_levels[44]	12	1			T142	1		T143	1		T138	1
all_levels[45]	19	1			T144	1		T145	1		T143	1
all_levels[46]	9	1			T5	1		T145	1		T143	1
all_levels[47]	11	1			T143	1		T146	1		T147	1
all_levels[48]	15	1			T8	1		T104	2		T123	3
all_levels[49]	11	1			T144	1		T148	1		T32	1
all_levels[50]	8	1			T35	1		T120	1		T149	3
all_levels[51]	15	1			T105	1		T150	1		T151	1
all_levels[52]	8	1			T118	1		T152	1		T153	1
all_levels[53]	7	1			T138	1		T154	2		T155	1
all_levels[54]	14	1			T125	1		T137	1		T32	2
all_levels[55]	5	1			T156	1		T153	1		T157	1
all_levels[56]	10	1			T35	1		T158	1		T159	1
all_levels[57]	15	1			T13	1		T35	1		T160	6
all_levels[58]	8	1			T118	1		T130	1		T138	2
all_levels[59]	13	1			T5	1		T118	1		T127	1
all_levels[60]	10	1			T1	1		T5	1		T161	1
all_levels[61]	6	1			T144	1		T162	1		T163	1
all_levels[62]	11	1			T133	2		T143	1		T155	1
all_levels[63]	11	1			T5	2		T164	1		T149	3
all_levels[64]	96	1			T5	2		T13	1		T35	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28599617

1

T1

25

T2

96925

T5

51447

auto[1]

4311

1

T3

1

T5

20

T6

1

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	11	119	91.54	11

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[34]]	[auto[1]]	0	1	1
[all_levels[43] , all_levels[44]]	[auto[1]]	--	--	2
[all_levels[51] , all_levels[52]]	[auto[1]]	--	--	2
[all_levels[55] , all_levels[56]]	[auto[1]]	--	--	2
[all_levels[58] , all_levels[59] , all_levels[60] , all_levels[61]]	[auto[1]]	--	--	4

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	28404370	1			T1	13		T2	93637		T5	51292
all_levels[0]	auto[1]	3875	1			T3	1		T5	20		T6	1
all_levels[1]	auto[0]	187908	1			T2	3288		T5	135		T6	170
all_levels[1]	auto[1]	58	1			T116	1		T36	2		T114	3
all_levels[2]	auto[0]	1825	1			T5	1		T6	2		T8	4
all_levels[2]	auto[1]	35	1			T165	1		T123	1		T166	2
all_levels[3]	auto[0]	971	1			T5	1		T8	2		T19	4
all_levels[3]	auto[1]	22	1			T121	1		T140	2		T136	2
all_levels[4]	auto[0]	637	1			T8	1		T19	1		T13	2
all_levels[4]	auto[1]	22	1			T36	1		T167	1		T168	4
all_levels[5]	auto[0]	458	1			T5	2		T8	2		T19	1
all_levels[5]	auto[1]	21	1			T169	2		T36	1		T170	4
all_levels[6]	auto[0]	368	1			T1	1		T5	1		T19	1
all_levels[6]	auto[1]	16	1			T104	1		T144	2		T171	3
all_levels[7]	auto[0]	301	1			T8	1		T19	2		T13	1
all_levels[7]	auto[1]	7	1			T96	2		T102	1		T172	1
all_levels[8]	auto[0]	258	1			T110	1		T34	1		T111	1
all_levels[8]	auto[1]	23	1			T34	4		T173	1		T158	1
all_levels[9]	auto[0]	230	1			T110	1		T36	1		T112	1
all_levels[9]	auto[1]	16	1			T47	1		T174	1		T175	1
all_levels[10]	auto[0]	214	1			T1	1		T5	1		T13	1
all_levels[10]	auto[1]	19	1			T129	1		T27	3		T137	1
all_levels[11]	auto[0]	183	1			T1	1		T5	1		T8	1
all_levels[11]	auto[1]	6	1			T144	1		T176	2		T177	1
all_levels[12]	auto[0]	118	1			T5	1		T13	1		T113	1
all_levels[12]	auto[1]	14	1			T113	1		T140	2		T178	2
all_levels[13]	auto[0]	141	1			T1	2		T8	1		T13	2
all_levels[13]	auto[1]	6	1			T158	1		T179	1		T180	1
all_levels[14]	auto[0]	118	1			T1	1		T8	2		T19	2
all_levels[14]	auto[1]	4	1			T181	1		T182	1		T183	2
all_levels[15]	auto[0]	90	1			T13	1		T114	1		T115	1
all_levels[15]	auto[1]	3	1			T114	1		T96	1		T150	1
all_levels[16]	auto[0]	87	1			T1	1		T116	1		T35	1
all_levels[16]	auto[1]	8	1			T184	4		T185	1		T186	2
all_levels[17]	auto[0]	80	1			T8	2		T117	1		T115	1
all_levels[17]	auto[1]	12	1			T128	1		T187	2		T188	1
all_levels[18]	auto[0]	84	1			T1	1		T8	1		T36	1
all_levels[18]	auto[1]	5	1			T106	1		T189	1		T190	1
all_levels[19]	auto[0]	71	1			T5	1		T8	1		T115	1
all_levels[19]	auto[1]	5	1			T16	3		T191	1		T192	1
all_levels[20]	auto[0]	76	1			T13	2		T36	1		T118	1
all_levels[20]	auto[1]	7	1			T36	1		T139	1		T130	1
all_levels[21]	auto[0]	58	1			T13	1		T119	1		T16	1
all_levels[21]	auto[1]	2	1			T193	1		T194	1		-	-
all_levels[22]	auto[0]	65	1			T8	1		T13	2		T114	1
all_levels[22]	auto[1]	3	1			T195	2		T196	1		-	-
all_levels[23]	auto[0]	56	1			T120	1		T121	2		T122	1
all_levels[23]	auto[1]	3	1			T158	1		T130	1		T197	1
all_levels[24]	auto[0]	63	1			T5	1		T26	1		T111	1
all_levels[24]	auto[1]	9	1			T187	1		T130	1		T198	1
all_levels[25]	auto[0]	64	1			T35	2		T123	1		T115	1
all_levels[25]	auto[1]	7	1			T145	1		T168	1		T96	1
all_levels[26]	auto[0]	31	1			T5	1		T13	1		T119	1
all_levels[26]	auto[1]	3	1			T161	1		T40	1		T199	1
all_levels[27]	auto[0]	29	1			T5	1		T124	1		T125	1
all_levels[27]	auto[1]	2	1			T107	2		-	-		-	-
all_levels[28]	auto[0]	35	1			T114	1		T124	1		T125	1
all_levels[28]	auto[1]	3	1			T200	3		-	-		-	-
all_levels[29]	auto[0]	34	1			T123	1		T126	1		T125	1
all_levels[29]	auto[1]	5	1			T199	1		T201	1		T202	1
all_levels[30]	auto[0]	38	1			T1	1		T13	1		T110	1
all_levels[30]	auto[1]	1	1			T203	1		-	-		-	-
all_levels[31]	auto[0]	43	1			T8	1		T114	1		T119	1
all_levels[31]	auto[1]	5	1			T200	2		T204	1		T192	1
all_levels[32]	auto[0]	29	1			T116	1		T118	1		T127	1
all_levels[32]	auto[1]	11	1			T136	2		T205	2		T206	1
all_levels[33]	auto[0]	31	1			T1	1		T5	1		T119	1
all_levels[33]	auto[1]	7	1			T119	1		T127	1		T207	1
all_levels[34]	auto[0]	24	1			T118	1		T121	1		T127	1
all_levels[35]	auto[0]	24	1			T1	1		T26	1		T128	1
all_levels[35]	auto[1]	6	1			T208	2		T209	2		T210	1
all_levels[36]	auto[0]	22	1			T26	1		T129	1		T120	1
all_levels[36]	auto[1]	2	1			T211	2		-	-		-	-
all_levels[37]	auto[0]	20	1			T130	1		T131	1		T132	1
all_levels[37]	auto[1]	1	1			T132	1		-	-		-	-
all_levels[38]	auto[0]	14	1			T26	1		T16	1		T127	1
all_levels[38]	auto[1]	1	1			T212	1		-	-		-	-
all_levels[39]	auto[0]	11	1			T26	1		T133	1		T134	1
all_levels[39]	auto[1]	1	1			T134	1		-	-		-	-
all_levels[40]	auto[0]	20	1			T114	1		T135	1		T136	1
all_levels[40]	auto[1]	1	1			T213	1		-	-		-	-
all_levels[41]	auto[0]	14	1			T13	2		T137	1		T138	2
all_levels[41]	auto[1]	5	1			T214	4		T215	1		-	-
all_levels[42]	auto[0]	23	1			T114	1		T104	2		T16	1
all_levels[42]	auto[1]	2	1			T173	1		T161	1		-	-
all_levels[43]	auto[0]	14	1			T139	1		T140	1		T141	1
all_levels[44]	auto[0]	12	1			T142	1		T143	1		T138	1
all_levels[45]	auto[0]	14	1			T144	1		T145	1		T143	1
all_levels[45]	auto[1]	5	1			T216	1		T177	1		T217	3
all_levels[46]	auto[0]	8	1			T5	1		T145	1		T143	1
all_levels[46]	auto[1]	1	1			T162	1		-	-		-	-
all_levels[47]	auto[0]	6	1			T143	1		T146	1		T147	1
all_levels[47]	auto[1]	5	1			T218	5		-	-		-	-
all_levels[48]	auto[0]	12	1			T8	1		T104	1		T123	1
all_levels[48]	auto[1]	3	1			T104	1		T123	2		-	-
all_levels[49]	auto[0]	9	1			T144	1		T148	1		T32	1
all_levels[49]	auto[1]	2	1			T177	2		-	-		-	-
all_levels[50]	auto[0]	6	1			T35	1		T120	1		T149	1
all_levels[50]	auto[1]	2	1			T149	2		-	-		-	-
all_levels[51]	auto[0]	15	1			T105	1		T150	1		T151	1
all_levels[52]	auto[0]	8	1			T118	1		T152	1		T153	1
all_levels[53]	auto[0]	6	1			T138	1		T154	1		T155	1
all_levels[53]	auto[1]	1	1			T154	1		-	-		-	-
all_levels[54]	auto[0]	11	1			T125	1		T137	1		T32	1
all_levels[54]	auto[1]	3	1			T32	1		T219	1		T220	1
all_levels[55]	auto[0]	5	1			T156	1		T153	1		T157	1
all_levels[56]	auto[0]	10	1			T35	1		T158	1		T159	1
all_levels[57]	auto[0]	10	1			T13	1		T35	1		T160	1
all_levels[57]	auto[1]	5	1			T160	5		-	-		-	-
all_levels[58]	auto[0]	8	1			T118	1		T130	1		T138	2
all_levels[59]	auto[0]	13	1			T5	1		T118	1		T127	1
all_levels[60]	auto[0]	10	1			T1	1		T5	1		T161	1
all_levels[61]	auto[0]	6	1			T144	1		T162	1		T163	1
all_levels[62]	auto[0]	9	1			T133	1		T143	1		T155	1
all_levels[62]	auto[1]	2	1			T133	1		T221	1		-	-
all_levels[63]	auto[0]	9	1			T5	2		T164	1		T149	1
all_levels[63]	auto[1]	2	1			T149	2		-	-		-	-
all_levels[64]	auto[0]	80	1			T5	2		T13	1		T35	1
all_levels[64]	auto[1]	16	1			T104	1		T141	1		T96	1