Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100365	1			T1	16		T2	60		T3	1
all_pins[1]	100365	1			T1	16		T2	60		T3	1
all_pins[2]	100365	1			T1	16		T2	60		T3	1
all_pins[3]	100365	1			T1	16		T2	60		T3	1
all_pins[4]	100365	1			T1	16		T2	60		T3	1
all_pins[5]	100365	1			T1	16		T2	60		T3	1
all_pins[6]	100365	1			T1	16		T2	60		T3	1
all_pins[7]	100365	1			T1	16		T2	60		T3	1
all_pins[8]	100365	1			T1	16		T2	60		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	861007	1			T1	125		T2	536		T3	9
values[0x1]	42278	1			T1	19		T2	4		T5	296
transitions[0x0=>0x1]	31664	1			T1	17		T2	4		T5	273
transitions[0x1=>0x0]	31482	1			T1	16		T2	4		T5	273

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	80953	1			T1	12		T2	60		T3	1
all_pins[0]	values[0x1]	19412	1			T1	4		T5	214		T6	91
all_pins[0]	transitions[0x0=>0x1]	18925	1			T1	4		T5	213		T6	91
all_pins[0]	transitions[0x1=>0x0]	1007	1			T1	8		T5	2		T8	13
all_pins[1]	values[0x0]	98871	1			T1	8		T2	60		T3	1
all_pins[1]	values[0x1]	1494	1			T1	8		T5	3		T8	13
all_pins[1]	transitions[0x0=>0x1]	1388	1			T1	8		T5	3		T8	12
all_pins[1]	transitions[0x1=>0x0]	2032	1			T2	3		T5	15		T6	4
all_pins[2]	values[0x0]	98227	1			T1	16		T2	57		T3	1
all_pins[2]	values[0x1]	2138	1			T2	3		T5	15		T6	4
all_pins[2]	transitions[0x0=>0x1]	2060	1			T2	3		T5	14		T6	4
all_pins[2]	transitions[0x1=>0x0]	211	1			T5	1		T27	3		T133	5
all_pins[3]	values[0x0]	100076	1			T1	16		T2	60		T3	1
all_pins[3]	values[0x1]	289	1			T5	2		T35	1		T27	4
all_pins[3]	transitions[0x0=>0x1]	243	1			T5	2		T35	1		T27	2
all_pins[3]	transitions[0x1=>0x0]	360	1			T5	10		T12	1		T27	1
all_pins[4]	values[0x0]	99959	1			T1	16		T2	60		T3	1
all_pins[4]	values[0x1]	406	1			T5	10		T12	1		T27	3
all_pins[4]	transitions[0x0=>0x1]	334	1			T5	8		T12	1		T27	3
all_pins[4]	transitions[0x1=>0x0]	135	1			T5	3		T14	1		T16	4
all_pins[5]	values[0x0]	100158	1			T1	16		T2	60		T3	1
all_pins[5]	values[0x1]	207	1			T5	5		T14	1		T16	4
all_pins[5]	transitions[0x0=>0x1]	172	1			T5	3		T14	1		T16	2
all_pins[5]	transitions[0x1=>0x0]	658	1			T1	4		T5	2		T19	2
all_pins[6]	values[0x0]	99672	1			T1	12		T2	60		T3	1
all_pins[6]	values[0x1]	693	1			T1	4		T5	4		T19	2
all_pins[6]	transitions[0x0=>0x1]	651	1			T1	4		T5	2		T19	2
all_pins[6]	transitions[0x1=>0x0]	281	1			T1	1		T5	5		T14	2
all_pins[7]	values[0x0]	100042	1			T1	15		T2	60		T3	1
all_pins[7]	values[0x1]	323	1			T1	1		T5	7		T14	2
all_pins[7]	transitions[0x0=>0x1]	179	1			T5	3		T14	2		T16	2
all_pins[7]	transitions[0x1=>0x0]	17172	1			T1	1		T2	1		T5	32
all_pins[8]	values[0x0]	83049	1			T1	14		T2	59		T3	1
all_pins[8]	values[0x1]	17316	1			T1	2		T2	1		T5	36
all_pins[8]	transitions[0x0=>0x1]	7712	1			T1	1		T2	1		T5	25
all_pins[8]	transitions[0x1=>0x0]	9626	1			T1	2		T5	203		T6	90