Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	6420558	1			T1	14		T2	2315		T5	25689
all_levels[1]	1299893	1			T1	1		T2	176		T5	474
all_levels[2]	308861	1			T2	160		T5	406		T6	3812
all_levels[3]	289210	1			T1	4		T2	158		T5	600
all_levels[4]	272852	1			T1	2		T2	177		T5	410
all_levels[5]	202764	1			T2	161		T5	383		T6	4624
all_levels[6]	342759	1			T2	165		T5	546		T6	3813
all_levels[7]	203581	1			T1	1		T2	157		T5	615
all_levels[8]	261376	1			T2	164		T5	221		T6	4170
all_levels[9]	203744	1			T2	170		T5	447		T6	3763
all_levels[10]	202204	1			T2	160		T5	721		T6	4716
all_levels[11]	366979	1			T2	170		T5	718		T6	3882
all_levels[12]	286862	1			T2	167		T5	549		T6	4745
all_levels[13]	212209	1			T2	158		T5	480		T6	4294
all_levels[14]	213794	1			T2	161		T5	496		T6	4462
all_levels[15]	225989	1			T2	148		T5	547		T6	3664
all_levels[16]	244371	1			T2	176		T5	421		T6	4010
all_levels[17]	224046	1			T2	154		T5	495		T6	4320
all_levels[18]	224615	1			T2	145		T5	593		T6	2197
all_levels[19]	357304	1			T2	167		T5	643		T6	2318
all_levels[20]	195637	1			T2	164		T5	488		T6	4252
all_levels[21]	190069	1			T2	170		T5	440		T6	3214
all_levels[22]	272536	1			T2	166		T5	497		T6	3977
all_levels[23]	256065	1			T2	157		T5	593		T6	3972
all_levels[24]	176125	1			T2	184		T5	401		T6	3812
all_levels[25]	199317	1			T2	170		T5	361		T6	4112
all_levels[26]	193237	1			T2	167		T5	452		T6	3845
all_levels[27]	201958	1			T2	154		T5	318		T6	4261
all_levels[28]	160731	1			T2	171		T5	546		T6	4200
all_levels[29]	299992	1			T2	169		T5	531		T6	4093
all_levels[30]	203190	1			T1	1		T2	161		T5	474
all_levels[31]	618420	1			T2	5023		T5	763		T6	6402
all_levels[32]	13272286	1			T1	3		T2	84661		T5	10138

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28599617

1

T1

25

T2

96925

T5

51447

auto[1]

3917

1

T1

1

T2

1

T5

9

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	6418215	1			T1	14		T2	2315		T5	25680
all_levels[0]	auto[1]	2343	1			T5	9		T7	1		T8	5
all_levels[1]	auto[0]	1299644	1			T1	1		T2	176		T5	474
all_levels[1]	auto[1]	249	1			T36	1		T104	1		T123	1
all_levels[2]	auto[0]	308826	1			T2	160		T5	406		T6	3812
all_levels[2]	auto[1]	35	1			T169	2		T27	1		T128	1
all_levels[3]	auto[0]	289121	1			T1	4		T2	158		T5	600
all_levels[3]	auto[1]	89	1			T12	16		T119	1		T165	1
all_levels[4]	auto[0]	272813	1			T1	2		T2	177		T5	410
all_levels[4]	auto[1]	39	1			T7	1		T140	2		T141	1
all_levels[5]	auto[0]	202737	1			T2	161		T5	383		T6	4624
all_levels[5]	auto[1]	27	1			T127	2		T130	1		T181	1
all_levels[6]	auto[0]	342736	1			T2	165		T5	546		T6	3813
all_levels[6]	auto[1]	23	1			T8	2		T119	1		T230	2
all_levels[7]	auto[0]	203492	1			T1	1		T2	157		T5	615
all_levels[7]	auto[1]	89	1			T12	3		T273	3		T309	2
all_levels[8]	auto[0]	261353	1			T2	164		T5	221		T6	4170
all_levels[8]	auto[1]	23	1			T32	1		T208	2		T179	2
all_levels[9]	auto[0]	203715	1			T2	170		T5	447		T6	3763
all_levels[9]	auto[1]	29	1			T36	1		T239	1		T310	1
all_levels[10]	auto[0]	202181	1			T2	160		T5	721		T6	4716
all_levels[10]	auto[1]	23	1			T241	2		T127	1		T171	3
all_levels[11]	auto[0]	366956	1			T2	170		T5	718		T6	3882
all_levels[11]	auto[1]	23	1			T36	1		T104	2		T144	2
all_levels[12]	auto[0]	286844	1			T2	167		T5	549		T6	4745
all_levels[12]	auto[1]	18	1			T130	1		T219	1		T311	1
all_levels[13]	auto[0]	212181	1			T2	158		T5	480		T6	4294
all_levels[13]	auto[1]	28	1			T34	4		T36	1		T129	1
all_levels[14]	auto[0]	213774	1			T2	161		T5	496		T6	4462
all_levels[14]	auto[1]	20	1			T173	2		T312	1		T313	1
all_levels[15]	auto[0]	225899	1			T2	148		T5	547		T6	3664
all_levels[15]	auto[1]	90	1			T253	1		T105	13		T106	4
all_levels[16]	auto[0]	244355	1			T2	176		T5	421		T6	4010
all_levels[16]	auto[1]	16	1			T129	1		T119	1		T141	1
all_levels[17]	auto[0]	224030	1			T2	154		T5	495		T6	4320
all_levels[17]	auto[1]	16	1			T121	1		T246	1		T32	1
all_levels[18]	auto[0]	224600	1			T2	145		T5	593		T6	2197
all_levels[18]	auto[1]	15	1			T114	1		T129	3		T243	1
all_levels[19]	auto[0]	357287	1			T2	167		T5	643		T6	2318
all_levels[19]	auto[1]	17	1			T165	1		T291	2		T314	1
all_levels[20]	auto[0]	195616	1			T2	164		T5	488		T6	4252
all_levels[20]	auto[1]	21	1			T219	2		T315	1		T204	1
all_levels[21]	auto[0]	190053	1			T2	170		T5	440		T6	3214
all_levels[21]	auto[1]	16	1			T36	1		T251	1		T167	1
all_levels[22]	auto[0]	272530	1			T2	166		T5	497		T6	3977
all_levels[22]	auto[1]	6	1			T230	1		T137	1		T316	1
all_levels[23]	auto[0]	256049	1			T2	157		T5	593		T6	3972
all_levels[23]	auto[1]	16	1			T114	1		T133	1		T135	2
all_levels[24]	auto[0]	176099	1			T2	184		T5	401		T6	3812
all_levels[24]	auto[1]	26	1			T19	1		T169	1		T148	2
all_levels[25]	auto[0]	199303	1			T2	170		T5	361		T6	4112
all_levels[25]	auto[1]	14	1			T38	1		T294	1		T317	1
all_levels[26]	auto[0]	193224	1			T2	167		T5	452		T6	3845
all_levels[26]	auto[1]	13	1			T100	1		T145	1		T283	1
all_levels[27]	auto[0]	201939	1			T2	154		T5	318		T6	4261
all_levels[27]	auto[1]	19	1			T169	1		T40	3		T150	1
all_levels[28]	auto[0]	160722	1			T2	171		T5	546		T6	4200
all_levels[28]	auto[1]	9	1			T107	1		T318	1		T96	3
all_levels[29]	auto[0]	299974	1			T2	169		T5	531		T6	4093
all_levels[29]	auto[1]	18	1			T133	4		T187	2		T319	1
all_levels[30]	auto[0]	203171	1			T1	1		T2	161		T5	474
all_levels[30]	auto[1]	19	1			T34	1		T239	2		T144	1
all_levels[31]	auto[0]	618402	1			T2	5023		T5	763		T6	6402
all_levels[31]	auto[1]	18	1			T169	1		T110	3		T133	1
all_levels[32]	auto[0]	13271776	1			T1	2		T2	84660		T5	10138
all_levels[32]	auto[1]	510	1			T1	1		T2	1		T7	2