Group : uart_env_pkg::uart_env_cov::tx_watermark_cg
Summary for Group uart_env_pkg::uart_env_cov::tx_watermark_cg
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
7 |
2 |
5 |
71.43 |
Variables for Group uart_env_pkg::uart_env_cov::tx_watermark_cg
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_watermark_lvl |
7 |
2 |
5 |
71.43 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_watermark_lvl
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
7 |
2 |
5 |
71.43 |
User Defined Bins for cp_watermark_lvl
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
all_levels[5] |
0 |
1 |
1 |
|
all_levels[6] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_levels[0] |
6495 |
1 |
|
|
T4 |
2 |
|
T5 |
22 |
|
T6 |
30 |
all_levels[1] |
6432 |
1 |
|
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
1 |
all_levels[2] |
9254 |
1 |
|
|
T1 |
3 |
|
T5 |
18 |
|
T6 |
33 |
all_levels[3] |
7318 |
1 |
|
|
T1 |
2 |
|
T5 |
5 |
|
T9 |
98 |
all_levels[4] |
8768 |
1 |
|
|
T5 |
224 |
|
T6 |
237 |
|
T7 |
4 |
0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |