Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	560	1			T5	19		T27	7		T16	7
all_values[1]	560	1			T5	19		T27	7		T16	7
all_values[2]	560	1			T5	19		T27	7		T16	7
all_values[3]	560	1			T5	19		T27	7		T16	7
all_values[4]	560	1			T5	19		T27	7		T16	7
all_values[5]	560	1			T5	19		T27	7		T16	7
all_values[6]	560	1			T5	19		T27	7		T16	7
all_values[7]	560	1			T5	19		T27	7		T16	7
all_values[8]	560	1			T5	19		T27	7		T16	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2676

1

T5

89

T27

38

T16

28

auto[1]

2364

1

T5

82

T27

25

T16

35

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1680

1

T5

48

T27

19

T16

21

auto[1]

3360

1

T5

123

T27

44

T16

42

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2991

1

T5

93

T27

37

T16

37

auto[1]

2049

1

T5

78

T27

26

T16

26

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	151	1			T5	2		T27	5		T16	1
all_values[0]	auto[0]	auto[1]	auto[1]	182	1			T5	10		T16	2		T28	1
all_values[0]	auto[1]	auto[0]	auto[1]	128	1			T5	3		T27	2		T16	2
all_values[0]	auto[1]	auto[1]	auto[1]	99	1			T5	4		T16	2		T100	2
all_values[1]	auto[0]	auto[0]	auto[0]	176	1			T5	5		T27	2		T16	2
all_values[1]	auto[0]	auto[1]	auto[0]	159	1			T5	7		T27	1		T16	2
all_values[1]	auto[1]	auto[0]	auto[1]	107	1			T5	6		T27	3		T16	1
all_values[1]	auto[1]	auto[1]	auto[1]	118	1			T5	1		T27	1		T16	2
all_values[2]	auto[0]	auto[0]	auto[0]	130	1			T5	1		T27	4		T28	1
all_values[2]	auto[0]	auto[0]	auto[1]	55	1			T5	3		T107	1		T88	3
all_values[2]	auto[0]	auto[1]	auto[0]	91	1			T27	2		T16	2		T28	2
all_values[2]	auto[0]	auto[1]	auto[1]	48	1			T5	3		T16	1		T100	2
all_values[2]	auto[1]	auto[0]	auto[1]	124	1			T5	7		T16	1		T28	2
all_values[2]	auto[1]	auto[1]	auto[1]	112	1			T5	5		T27	1		T16	3
all_values[3]	auto[0]	auto[0]	auto[0]	118	1			T5	6		T27	1		T16	2
all_values[3]	auto[0]	auto[0]	auto[1]	48	1			T5	3		T27	1		T16	1
all_values[3]	auto[0]	auto[1]	auto[0]	97	1			T5	2		T16	1		T28	1
all_values[3]	auto[0]	auto[1]	auto[1]	61	1			T27	2		T28	1		T100	1
all_values[3]	auto[1]	auto[0]	auto[1]	122	1			T5	6		T27	2		T16	1
all_values[3]	auto[1]	auto[1]	auto[1]	114	1			T5	2		T27	1		T16	2
all_values[4]	auto[0]	auto[0]	auto[0]	135	1			T5	1		T27	2		T16	4
all_values[4]	auto[0]	auto[0]	auto[1]	49	1			T16	1		T28	2		T100	2
all_values[4]	auto[0]	auto[1]	auto[0]	93	1			T5	3		T27	1		T16	1
all_values[4]	auto[0]	auto[1]	auto[1]	50	1			T5	7		T27	1		T100	1
all_values[4]	auto[1]	auto[0]	auto[1]	112	1			T5	4		T16	1		T28	4
all_values[4]	auto[1]	auto[1]	auto[1]	121	1			T5	4		T27	3		T28	1
all_values[5]	auto[0]	auto[0]	auto[0]	121	1			T5	3		T27	2		T28	1
all_values[5]	auto[0]	auto[0]	auto[1]	55	1			T5	3		T101	1		T106	1
all_values[5]	auto[0]	auto[1]	auto[0]	86	1			T5	2		T27	2		T16	1
all_values[5]	auto[0]	auto[1]	auto[1]	64	1			T5	2		T27	1		T16	1
all_values[5]	auto[1]	auto[0]	auto[1]	132	1			T5	5		T27	2		T16	1
all_values[5]	auto[1]	auto[1]	auto[1]	102	1			T5	4		T16	4		T28	3
all_values[6]	auto[0]	auto[0]	auto[0]	135	1			T5	5		T16	2		T28	5
all_values[6]	auto[0]	auto[0]	auto[1]	57	1			T27	1		T106	1		T88	1
all_values[6]	auto[0]	auto[1]	auto[0]	110	1			T5	3		T16	2		T28	1
all_values[6]	auto[0]	auto[1]	auto[1]	39	1			T5	1		T27	1		T16	1
all_values[6]	auto[1]	auto[0]	auto[1]	131	1			T5	9		T27	1		T16	1
all_values[6]	auto[1]	auto[1]	auto[1]	88	1			T5	1		T27	4		T16	1
all_values[7]	auto[0]	auto[0]	auto[0]	124	1			T5	7		T27	2		T16	2
all_values[7]	auto[0]	auto[0]	auto[1]	55	1			T27	2		T16	1		T100	2
all_values[7]	auto[0]	auto[1]	auto[0]	105	1			T5	3		T28	2		T106	2
all_values[7]	auto[0]	auto[1]	auto[1]	59	1			T5	2		T16	1		T28	1
all_values[7]	auto[1]	auto[0]	auto[1]	119	1			T5	3		T27	3		T28	3
all_values[7]	auto[1]	auto[1]	auto[1]	98	1			T5	4		T16	3		T28	1
all_values[8]	auto[0]	auto[0]	auto[1]	170	1			T5	2		T27	2		T16	3
all_values[8]	auto[0]	auto[1]	auto[1]	168	1			T5	7		T27	2		T16	3
all_values[8]	auto[1]	auto[0]	auto[1]	122	1			T5	5		T27	1		T16	1
all_values[8]	auto[1]	auto[1]	auto[1]	100	1			T5	5		T27	2		T28	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal