Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.10 97.65 100.00 98.38 100.00 99.53


Total test records in report: 1227
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T302 /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2522757318 Jun 28 04:40:51 PM PDT 24 Jun 28 05:14:35 PM PDT 24 104492864189 ps
T1036 /workspace/coverage/default/40.uart_rx_start_bit_filter.374596845 Jun 28 04:39:50 PM PDT 24 Jun 28 04:39:51 PM PDT 24 557461010 ps
T1037 /workspace/coverage/default/4.uart_perf.446329878 Jun 28 04:36:46 PM PDT 24 Jun 28 04:40:42 PM PDT 24 16818486218 ps
T1038 /workspace/coverage/default/39.uart_rx_start_bit_filter.2095143474 Jun 28 04:39:37 PM PDT 24 Jun 28 04:40:25 PM PDT 24 38299837014 ps
T1039 /workspace/coverage/default/11.uart_tx_ovrd.293112838 Jun 28 04:37:23 PM PDT 24 Jun 28 04:37:25 PM PDT 24 1503741602 ps
T1040 /workspace/coverage/default/46.uart_long_xfer_wo_dly.3105998414 Jun 28 04:40:18 PM PDT 24 Jun 28 04:46:20 PM PDT 24 98165816415 ps
T1041 /workspace/coverage/default/28.uart_fifo_overflow.1310419024 Jun 28 04:38:43 PM PDT 24 Jun 28 04:39:59 PM PDT 24 120508085402 ps
T1042 /workspace/coverage/default/44.uart_alert_test.1853260217 Jun 28 04:40:08 PM PDT 24 Jun 28 04:40:09 PM PDT 24 28281770 ps
T1043 /workspace/coverage/default/94.uart_stress_all_with_rand_reset.1235778140 Jun 28 04:40:59 PM PDT 24 Jun 28 04:50:41 PM PDT 24 54999997477 ps
T1044 /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1576656393 Jun 28 04:39:23 PM PDT 24 Jun 28 04:47:28 PM PDT 24 39440524517 ps
T1045 /workspace/coverage/default/9.uart_rx_start_bit_filter.1063259430 Jun 28 04:37:16 PM PDT 24 Jun 28 04:37:18 PM PDT 24 6447010973 ps
T1046 /workspace/coverage/default/30.uart_fifo_full.2823527504 Jun 28 04:38:53 PM PDT 24 Jun 28 04:42:37 PM PDT 24 110640575179 ps
T1047 /workspace/coverage/default/48.uart_fifo_overflow.3040204888 Jun 28 04:40:36 PM PDT 24 Jun 28 04:40:45 PM PDT 24 22721585258 ps
T1048 /workspace/coverage/default/253.uart_fifo_reset.3301159072 Jun 28 04:42:03 PM PDT 24 Jun 28 04:44:49 PM PDT 24 219755766052 ps
T1049 /workspace/coverage/default/54.uart_fifo_reset.1053186783 Jun 28 04:40:47 PM PDT 24 Jun 28 04:42:30 PM PDT 24 114297084079 ps
T1050 /workspace/coverage/default/3.uart_fifo_full.695480119 Jun 28 04:36:38 PM PDT 24 Jun 28 04:39:02 PM PDT 24 209891122189 ps
T1051 /workspace/coverage/default/46.uart_fifo_reset.1964835080 Jun 28 04:40:21 PM PDT 24 Jun 28 04:41:05 PM PDT 24 121678584010 ps
T196 /workspace/coverage/default/274.uart_fifo_reset.598067089 Jun 28 04:42:14 PM PDT 24 Jun 28 04:44:08 PM PDT 24 65076404305 ps
T1052 /workspace/coverage/default/3.uart_fifo_overflow.2709932045 Jun 28 04:36:36 PM PDT 24 Jun 28 04:37:58 PM PDT 24 106425073409 ps
T1053 /workspace/coverage/default/131.uart_fifo_reset.2320533467 Jun 28 04:41:19 PM PDT 24 Jun 28 04:41:33 PM PDT 24 163098708693 ps
T1054 /workspace/coverage/default/71.uart_fifo_reset.379554 Jun 28 04:40:49 PM PDT 24 Jun 28 04:41:19 PM PDT 24 34665721341 ps
T1055 /workspace/coverage/default/15.uart_fifo_overflow.1275074382 Jun 28 04:37:36 PM PDT 24 Jun 28 04:38:03 PM PDT 24 29737396554 ps
T1056 /workspace/coverage/default/256.uart_fifo_reset.3910472731 Jun 28 04:42:02 PM PDT 24 Jun 28 04:56:04 PM PDT 24 104003458299 ps
T1057 /workspace/coverage/default/8.uart_rx_parity_err.2845286344 Jun 28 04:37:14 PM PDT 24 Jun 28 04:37:31 PM PDT 24 174266468958 ps
T1058 /workspace/coverage/default/36.uart_rx_parity_err.2578783714 Jun 28 04:39:24 PM PDT 24 Jun 28 04:43:23 PM PDT 24 144137328264 ps
T1059 /workspace/coverage/default/272.uart_fifo_reset.1767006090 Jun 28 04:42:13 PM PDT 24 Jun 28 04:42:34 PM PDT 24 14805471990 ps
T1060 /workspace/coverage/default/207.uart_fifo_reset.2036097740 Jun 28 04:41:41 PM PDT 24 Jun 28 04:42:38 PM PDT 24 151894280447 ps
T1061 /workspace/coverage/default/28.uart_tx_rx.2242123208 Jun 28 04:38:46 PM PDT 24 Jun 28 04:39:05 PM PDT 24 54425014341 ps
T1062 /workspace/coverage/default/212.uart_fifo_reset.2330979680 Jun 28 04:41:45 PM PDT 24 Jun 28 04:45:47 PM PDT 24 207466378738 ps
T1063 /workspace/coverage/default/242.uart_fifo_reset.1030512268 Jun 28 04:42:01 PM PDT 24 Jun 28 04:43:01 PM PDT 24 126875787805 ps
T1064 /workspace/coverage/default/24.uart_rx_parity_err.3120404650 Jun 28 04:38:21 PM PDT 24 Jun 28 04:41:17 PM PDT 24 121347456153 ps
T1065 /workspace/coverage/default/31.uart_fifo_reset.3480216870 Jun 28 04:39:06 PM PDT 24 Jun 28 04:42:44 PM PDT 24 121142376080 ps
T1066 /workspace/coverage/default/127.uart_fifo_reset.2658979004 Jun 28 04:41:11 PM PDT 24 Jun 28 04:43:40 PM PDT 24 49346373073 ps
T1067 /workspace/coverage/default/44.uart_smoke.2386029619 Jun 28 04:39:58 PM PDT 24 Jun 28 04:40:00 PM PDT 24 1074162927 ps
T1068 /workspace/coverage/default/36.uart_fifo_reset.220283888 Jun 28 04:39:23 PM PDT 24 Jun 28 04:40:08 PM PDT 24 18531795363 ps
T1069 /workspace/coverage/default/4.uart_long_xfer_wo_dly.89250691 Jun 28 04:36:47 PM PDT 24 Jun 28 04:54:48 PM PDT 24 155417221149 ps
T1070 /workspace/coverage/default/19.uart_loopback.3391205497 Jun 28 04:38:07 PM PDT 24 Jun 28 04:38:21 PM PDT 24 8997953905 ps
T1071 /workspace/coverage/default/17.uart_stress_all_with_rand_reset.4019769337 Jun 28 04:37:54 PM PDT 24 Jun 28 04:40:31 PM PDT 24 29459033677 ps
T1072 /workspace/coverage/default/14.uart_tx_ovrd.34008717 Jun 28 04:37:33 PM PDT 24 Jun 28 04:37:36 PM PDT 24 1654207329 ps
T1073 /workspace/coverage/default/37.uart_rx_start_bit_filter.1255877267 Jun 28 04:39:25 PM PDT 24 Jun 28 04:39:34 PM PDT 24 4900249769 ps
T1074 /workspace/coverage/default/32.uart_smoke.2238113361 Jun 28 04:39:04 PM PDT 24 Jun 28 04:39:07 PM PDT 24 566656439 ps
T218 /workspace/coverage/default/19.uart_fifo_reset.2925345720 Jun 28 04:37:56 PM PDT 24 Jun 28 04:38:10 PM PDT 24 28377780861 ps
T1075 /workspace/coverage/default/48.uart_alert_test.3438282285 Jun 28 04:40:36 PM PDT 24 Jun 28 04:40:38 PM PDT 24 92857083 ps
T1076 /workspace/coverage/default/44.uart_fifo_overflow.3475997317 Jun 28 04:40:00 PM PDT 24 Jun 28 04:40:14 PM PDT 24 20330955882 ps
T1077 /workspace/coverage/default/156.uart_fifo_reset.3187745301 Jun 28 04:41:21 PM PDT 24 Jun 28 04:43:18 PM PDT 24 50818210962 ps
T1078 /workspace/coverage/default/35.uart_rx_oversample.3684010181 Jun 28 04:39:23 PM PDT 24 Jun 28 04:40:28 PM PDT 24 6310204720 ps
T1079 /workspace/coverage/default/13.uart_long_xfer_wo_dly.56802185 Jun 28 04:37:26 PM PDT 24 Jun 28 04:47:25 PM PDT 24 111360552024 ps
T1080 /workspace/coverage/default/83.uart_stress_all_with_rand_reset.1912616032 Jun 28 04:40:59 PM PDT 24 Jun 28 04:42:04 PM PDT 24 21791535791 ps
T1081 /workspace/coverage/default/219.uart_fifo_reset.1900490630 Jun 28 04:41:53 PM PDT 24 Jun 28 04:43:33 PM PDT 24 73918224731 ps
T1082 /workspace/coverage/default/8.uart_stress_all_with_rand_reset.3899670542 Jun 28 04:37:11 PM PDT 24 Jun 28 04:54:02 PM PDT 24 236467101922 ps
T1083 /workspace/coverage/default/44.uart_fifo_full.3348116218 Jun 28 04:40:02 PM PDT 24 Jun 28 04:42:39 PM PDT 24 118211531868 ps
T1084 /workspace/coverage/default/0.uart_rx_oversample.1331267350 Jun 28 04:36:27 PM PDT 24 Jun 28 04:36:37 PM PDT 24 7040803598 ps
T1085 /workspace/coverage/default/48.uart_fifo_full.840578435 Jun 28 04:40:36 PM PDT 24 Jun 28 04:41:50 PM PDT 24 43511242655 ps
T1086 /workspace/coverage/default/234.uart_fifo_reset.141477931 Jun 28 04:41:57 PM PDT 24 Jun 28 04:42:56 PM PDT 24 169486462086 ps
T1087 /workspace/coverage/default/20.uart_fifo_overflow.2112794154 Jun 28 04:38:07 PM PDT 24 Jun 28 04:38:43 PM PDT 24 77947968369 ps
T1088 /workspace/coverage/default/6.uart_tx_ovrd.911688362 Jun 28 04:37:02 PM PDT 24 Jun 28 04:37:25 PM PDT 24 6509315276 ps
T87 /workspace/coverage/default/4.uart_sec_cm.1606705775 Jun 28 04:36:47 PM PDT 24 Jun 28 04:36:49 PM PDT 24 112688566 ps
T1089 /workspace/coverage/default/22.uart_intr.4236219104 Jun 28 04:38:22 PM PDT 24 Jun 28 04:38:25 PM PDT 24 3824955374 ps
T1090 /workspace/coverage/default/149.uart_fifo_reset.325182223 Jun 28 04:41:21 PM PDT 24 Jun 28 04:41:42 PM PDT 24 18630683965 ps
T1091 /workspace/coverage/default/7.uart_stress_all_with_rand_reset.1652154382 Jun 28 04:37:02 PM PDT 24 Jun 28 04:39:27 PM PDT 24 11852609938 ps
T1092 /workspace/coverage/default/218.uart_fifo_reset.2792474552 Jun 28 04:41:52 PM PDT 24 Jun 28 04:43:12 PM PDT 24 49099258605 ps
T1093 /workspace/coverage/default/259.uart_fifo_reset.698865101 Jun 28 04:42:15 PM PDT 24 Jun 28 04:42:53 PM PDT 24 23350260394 ps
T66 /workspace/coverage/cover_reg_top/16.uart_csr_rw.1265116419 Jun 28 04:31:35 PM PDT 24 Jun 28 04:31:36 PM PDT 24 17278522 ps
T1094 /workspace/coverage/cover_reg_top/19.uart_csr_rw.1885796281 Jun 28 04:31:44 PM PDT 24 Jun 28 04:31:46 PM PDT 24 15944289 ps
T1095 /workspace/coverage/cover_reg_top/7.uart_intr_test.1205370158 Jun 28 04:31:21 PM PDT 24 Jun 28 04:31:22 PM PDT 24 35492960 ps
T55 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3181257523 Jun 28 04:30:58 PM PDT 24 Jun 28 04:31:00 PM PDT 24 53693489 ps
T1096 /workspace/coverage/cover_reg_top/35.uart_intr_test.2246414630 Jun 28 04:31:39 PM PDT 24 Jun 28 04:31:41 PM PDT 24 16123052 ps
T1097 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2997359363 Jun 28 04:31:17 PM PDT 24 Jun 28 04:31:19 PM PDT 24 18990400 ps
T1098 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2593559186 Jun 28 04:31:14 PM PDT 24 Jun 28 04:31:16 PM PDT 24 86001635 ps
T77 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3959003033 Jun 28 04:31:31 PM PDT 24 Jun 28 04:31:34 PM PDT 24 123786132 ps
T1099 /workspace/coverage/cover_reg_top/10.uart_tl_errors.2518396865 Jun 28 04:31:38 PM PDT 24 Jun 28 04:31:41 PM PDT 24 32984974 ps
T1100 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.4153988724 Jun 28 04:31:19 PM PDT 24 Jun 28 04:31:21 PM PDT 24 20965078 ps
T1101 /workspace/coverage/cover_reg_top/32.uart_intr_test.597785778 Jun 28 04:31:33 PM PDT 24 Jun 28 04:31:35 PM PDT 24 15328357 ps
T78 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2114068151 Jun 28 04:31:15 PM PDT 24 Jun 28 04:31:17 PM PDT 24 117218587 ps
T1102 /workspace/coverage/cover_reg_top/17.uart_tl_errors.3658909406 Jun 28 04:31:40 PM PDT 24 Jun 28 04:31:44 PM PDT 24 392160203 ps
T79 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.171724474 Jun 28 04:31:22 PM PDT 24 Jun 28 04:31:25 PM PDT 24 203979765 ps
T1103 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2618892327 Jun 28 04:31:13 PM PDT 24 Jun 28 04:31:15 PM PDT 24 359673353 ps
T56 /workspace/coverage/cover_reg_top/15.uart_csr_rw.4102320346 Jun 28 04:31:27 PM PDT 24 Jun 28 04:31:28 PM PDT 24 15648984 ps
T1104 /workspace/coverage/cover_reg_top/25.uart_intr_test.1040331265 Jun 28 04:31:32 PM PDT 24 Jun 28 04:31:34 PM PDT 24 38957067 ps
T67 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1182451084 Jun 28 04:31:23 PM PDT 24 Jun 28 04:31:25 PM PDT 24 67784416 ps
T1105 /workspace/coverage/cover_reg_top/45.uart_intr_test.3668017418 Jun 28 04:31:28 PM PDT 24 Jun 28 04:31:29 PM PDT 24 13422335 ps
T1106 /workspace/coverage/cover_reg_top/13.uart_tl_errors.2663244351 Jun 28 04:31:17 PM PDT 24 Jun 28 04:31:19 PM PDT 24 85974044 ps
T1107 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1651133030 Jun 28 04:31:27 PM PDT 24 Jun 28 04:31:28 PM PDT 24 28338280 ps
T1108 /workspace/coverage/cover_reg_top/18.uart_intr_test.3475375986 Jun 28 04:31:36 PM PDT 24 Jun 28 04:31:38 PM PDT 24 60329354 ps
T57 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3850337177 Jun 28 04:31:22 PM PDT 24 Jun 28 04:31:24 PM PDT 24 13643583 ps
T82 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2130688341 Jun 28 04:31:29 PM PDT 24 Jun 28 04:31:30 PM PDT 24 170297514 ps
T1109 /workspace/coverage/cover_reg_top/20.uart_intr_test.3336105711 Jun 28 04:31:34 PM PDT 24 Jun 28 04:31:35 PM PDT 24 16494091 ps
T1110 /workspace/coverage/cover_reg_top/37.uart_intr_test.3393826193 Jun 28 04:31:41 PM PDT 24 Jun 28 04:31:43 PM PDT 24 17302962 ps
T1111 /workspace/coverage/cover_reg_top/10.uart_intr_test.627088812 Jun 28 04:31:22 PM PDT 24 Jun 28 04:31:24 PM PDT 24 71998406 ps
T1112 /workspace/coverage/cover_reg_top/6.uart_tl_errors.838761011 Jun 28 04:31:17 PM PDT 24 Jun 28 04:31:20 PM PDT 24 1938732225 ps
T1113 /workspace/coverage/cover_reg_top/38.uart_intr_test.2600947324 Jun 28 04:31:27 PM PDT 24 Jun 28 04:31:28 PM PDT 24 15084677 ps
T1114 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1774185550 Jun 28 04:31:18 PM PDT 24 Jun 28 04:31:20 PM PDT 24 93654633 ps
T83 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.791540067 Jun 28 04:31:31 PM PDT 24 Jun 28 04:31:33 PM PDT 24 94555617 ps
T68 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2905555899 Jun 28 04:31:42 PM PDT 24 Jun 28 04:31:45 PM PDT 24 92539338 ps
T65 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1274467798 Jun 28 04:31:25 PM PDT 24 Jun 28 04:31:26 PM PDT 24 35994442 ps
T1115 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2490315472 Jun 28 04:31:03 PM PDT 24 Jun 28 04:31:06 PM PDT 24 25145139 ps
T69 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3649692185 Jun 28 04:31:37 PM PDT 24 Jun 28 04:31:39 PM PDT 24 68000562 ps
T1116 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1872798197 Jun 28 04:31:35 PM PDT 24 Jun 28 04:31:38 PM PDT 24 87411575 ps
T80 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3310744506 Jun 28 04:31:29 PM PDT 24 Jun 28 04:31:31 PM PDT 24 52772899 ps
T70 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3334559831 Jun 28 04:31:52 PM PDT 24 Jun 28 04:31:54 PM PDT 24 26692093 ps
T71 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1361468035 Jun 28 04:31:21 PM PDT 24 Jun 28 04:31:22 PM PDT 24 86839505 ps
T1117 /workspace/coverage/cover_reg_top/27.uart_intr_test.3392661106 Jun 28 04:31:22 PM PDT 24 Jun 28 04:31:24 PM PDT 24 17249865 ps
T1118 /workspace/coverage/cover_reg_top/13.uart_intr_test.2482163920 Jun 28 04:31:32 PM PDT 24 Jun 28 04:31:34 PM PDT 24 16447255 ps
T1119 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1279349519 Jun 28 04:31:22 PM PDT 24 Jun 28 04:31:24 PM PDT 24 39110917 ps
T1120 /workspace/coverage/cover_reg_top/23.uart_intr_test.2925027781 Jun 28 04:31:35 PM PDT 24 Jun 28 04:31:37 PM PDT 24 51123290 ps
T58 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1118876549 Jun 28 04:31:05 PM PDT 24 Jun 28 04:31:08 PM PDT 24 15576035 ps
T1121 /workspace/coverage/cover_reg_top/11.uart_intr_test.4127310112 Jun 28 04:31:20 PM PDT 24 Jun 28 04:31:21 PM PDT 24 27686015 ps
T1122 /workspace/coverage/cover_reg_top/14.uart_intr_test.3019667054 Jun 28 04:31:59 PM PDT 24 Jun 28 04:32:00 PM PDT 24 154340356 ps
T1123 /workspace/coverage/cover_reg_top/34.uart_intr_test.1417380126 Jun 28 04:31:35 PM PDT 24 Jun 28 04:31:37 PM PDT 24 31179937 ps
T1124 /workspace/coverage/cover_reg_top/4.uart_csr_rw.3106197519 Jun 28 04:31:13 PM PDT 24 Jun 28 04:31:14 PM PDT 24 51961806 ps
T1125 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1934291461 Jun 28 04:31:27 PM PDT 24 Jun 28 04:31:28 PM PDT 24 18121671 ps
T1126 /workspace/coverage/cover_reg_top/42.uart_intr_test.4148077665 Jun 28 04:31:27 PM PDT 24 Jun 28 04:31:29 PM PDT 24 29233987 ps
T1127 /workspace/coverage/cover_reg_top/39.uart_intr_test.337842354 Jun 28 04:31:37 PM PDT 24 Jun 28 04:31:39 PM PDT 24 11297359 ps
T1128 /workspace/coverage/cover_reg_top/47.uart_intr_test.939757203 Jun 28 04:31:41 PM PDT 24 Jun 28 04:31:44 PM PDT 24 33255998 ps
T1129 /workspace/coverage/cover_reg_top/3.uart_intr_test.3985212607 Jun 28 04:31:20 PM PDT 24 Jun 28 04:31:21 PM PDT 24 83884880 ps
T1130 /workspace/coverage/cover_reg_top/4.uart_intr_test.2991141680 Jun 28 04:31:26 PM PDT 24 Jun 28 04:31:28 PM PDT 24 14065066 ps
T1131 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2591779792 Jun 28 04:31:38 PM PDT 24 Jun 28 04:31:40 PM PDT 24 32014889 ps
T1132 /workspace/coverage/cover_reg_top/36.uart_intr_test.1487277291 Jun 28 04:31:31 PM PDT 24 Jun 28 04:31:33 PM PDT 24 45393596 ps
T1133 /workspace/coverage/cover_reg_top/1.uart_tl_errors.3276639046 Jun 28 04:31:06 PM PDT 24 Jun 28 04:31:09 PM PDT 24 22497719 ps
T1134 /workspace/coverage/cover_reg_top/5.uart_tl_errors.1260741570 Jun 28 04:31:15 PM PDT 24 Jun 28 04:31:17 PM PDT 24 124351998 ps
T1135 /workspace/coverage/cover_reg_top/15.uart_intr_test.3422720845 Jun 28 04:31:39 PM PDT 24 Jun 28 04:31:40 PM PDT 24 53701151 ps
T1136 /workspace/coverage/cover_reg_top/8.uart_intr_test.3716917646 Jun 28 04:31:19 PM PDT 24 Jun 28 04:31:21 PM PDT 24 26797570 ps
T1137 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3335764258 Jun 28 04:31:23 PM PDT 24 Jun 28 04:31:25 PM PDT 24 263943052 ps
T1138 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3544679280 Jun 28 04:31:22 PM PDT 24 Jun 28 04:31:24 PM PDT 24 96750097 ps
T59 /workspace/coverage/cover_reg_top/6.uart_csr_rw.2242085442 Jun 28 04:31:26 PM PDT 24 Jun 28 04:31:27 PM PDT 24 98744973 ps
T81 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3460085096 Jun 28 04:31:56 PM PDT 24 Jun 28 04:31:58 PM PDT 24 165790567 ps
T1139 /workspace/coverage/cover_reg_top/29.uart_intr_test.457904202 Jun 28 04:31:42 PM PDT 24 Jun 28 04:31:48 PM PDT 24 19690124 ps
T1140 /workspace/coverage/cover_reg_top/24.uart_intr_test.2322730254 Jun 28 04:31:31 PM PDT 24 Jun 28 04:31:33 PM PDT 24 15734444 ps
T1141 /workspace/coverage/cover_reg_top/2.uart_intr_test.3053520047 Jun 28 04:31:22 PM PDT 24 Jun 28 04:31:24 PM PDT 24 32890679 ps
T72 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.939360306 Jun 28 04:31:23 PM PDT 24 Jun 28 04:31:24 PM PDT 24 72325395 ps
T1142 /workspace/coverage/cover_reg_top/16.uart_intr_test.2528483889 Jun 28 04:31:30 PM PDT 24 Jun 28 04:31:32 PM PDT 24 26753407 ps
T60 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1477552400 Jun 28 04:31:00 PM PDT 24 Jun 28 04:31:04 PM PDT 24 1774695235 ps
T1143 /workspace/coverage/cover_reg_top/5.uart_intr_test.3047558938 Jun 28 04:31:18 PM PDT 24 Jun 28 04:31:19 PM PDT 24 66287993 ps
T1144 /workspace/coverage/cover_reg_top/4.uart_tl_errors.585710189 Jun 28 04:31:26 PM PDT 24 Jun 28 04:31:28 PM PDT 24 53490582 ps
T61 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.5887069 Jun 28 04:31:18 PM PDT 24 Jun 28 04:31:21 PM PDT 24 58852226 ps
T1145 /workspace/coverage/cover_reg_top/2.uart_csr_rw.699762607 Jun 28 04:31:35 PM PDT 24 Jun 28 04:31:37 PM PDT 24 66679955 ps
T1146 /workspace/coverage/cover_reg_top/26.uart_intr_test.343220406 Jun 28 04:31:34 PM PDT 24 Jun 28 04:31:35 PM PDT 24 13013105 ps
T1147 /workspace/coverage/cover_reg_top/10.uart_csr_rw.3092118712 Jun 28 04:31:32 PM PDT 24 Jun 28 04:31:33 PM PDT 24 103068719 ps
T1148 /workspace/coverage/cover_reg_top/28.uart_intr_test.398839183 Jun 28 04:31:18 PM PDT 24 Jun 28 04:31:20 PM PDT 24 29122194 ps
T1149 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.692888330 Jun 28 04:31:00 PM PDT 24 Jun 28 04:31:02 PM PDT 24 126730992 ps
T1150 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2070960482 Jun 28 04:31:17 PM PDT 24 Jun 28 04:31:18 PM PDT 24 46969363 ps
T1151 /workspace/coverage/cover_reg_top/0.uart_intr_test.1602990645 Jun 28 04:31:01 PM PDT 24 Jun 28 04:31:02 PM PDT 24 26594336 ps
T1152 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.4134900162 Jun 28 04:31:45 PM PDT 24 Jun 28 04:31:49 PM PDT 24 40906122 ps
T62 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2208185860 Jun 28 04:31:35 PM PDT 24 Jun 28 04:31:36 PM PDT 24 18348760 ps
T1153 /workspace/coverage/cover_reg_top/48.uart_intr_test.209717107 Jun 28 04:31:30 PM PDT 24 Jun 28 04:31:32 PM PDT 24 42905068 ps
T73 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3521215666 Jun 28 04:31:02 PM PDT 24 Jun 28 04:31:04 PM PDT 24 64790369 ps
T1154 /workspace/coverage/cover_reg_top/12.uart_intr_test.1007395767 Jun 28 04:31:20 PM PDT 24 Jun 28 04:31:21 PM PDT 24 29166758 ps
T84 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1266525669 Jun 28 04:31:39 PM PDT 24 Jun 28 04:31:42 PM PDT 24 149934213 ps
T1155 /workspace/coverage/cover_reg_top/18.uart_tl_errors.2772664854 Jun 28 04:31:29 PM PDT 24 Jun 28 04:31:32 PM PDT 24 382849384 ps
T1156 /workspace/coverage/cover_reg_top/9.uart_intr_test.1026372228 Jun 28 04:31:43 PM PDT 24 Jun 28 04:31:45 PM PDT 24 17550988 ps
T74 /workspace/coverage/cover_reg_top/12.uart_csr_rw.1054473685 Jun 28 04:31:19 PM PDT 24 Jun 28 04:31:20 PM PDT 24 52650333 ps
T1157 /workspace/coverage/cover_reg_top/14.uart_csr_rw.3140876305 Jun 28 04:31:18 PM PDT 24 Jun 28 04:31:19 PM PDT 24 59512678 ps
T1158 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1483472824 Jun 28 04:31:33 PM PDT 24 Jun 28 04:31:35 PM PDT 24 178900771 ps
T1159 /workspace/coverage/cover_reg_top/7.uart_csr_rw.163223294 Jun 28 04:31:20 PM PDT 24 Jun 28 04:31:22 PM PDT 24 14803232 ps
T1160 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2556697129 Jun 28 04:31:21 PM PDT 24 Jun 28 04:31:22 PM PDT 24 96097108 ps
T1161 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2082588868 Jun 28 04:31:41 PM PDT 24 Jun 28 04:31:44 PM PDT 24 46243076 ps
T1162 /workspace/coverage/cover_reg_top/1.uart_intr_test.637068061 Jun 28 04:31:05 PM PDT 24 Jun 28 04:31:08 PM PDT 24 107412413 ps
T1163 /workspace/coverage/cover_reg_top/17.uart_intr_test.3764077158 Jun 28 04:31:29 PM PDT 24 Jun 28 04:31:30 PM PDT 24 25533040 ps
T1164 /workspace/coverage/cover_reg_top/6.uart_intr_test.2198586727 Jun 28 04:31:15 PM PDT 24 Jun 28 04:31:16 PM PDT 24 42943483 ps
T1165 /workspace/coverage/cover_reg_top/19.uart_tl_errors.605173366 Jun 28 04:31:44 PM PDT 24 Jun 28 04:31:47 PM PDT 24 142572365 ps
T1166 /workspace/coverage/cover_reg_top/3.uart_tl_errors.3484109477 Jun 28 04:31:18 PM PDT 24 Jun 28 04:31:20 PM PDT 24 38463356 ps
T1167 /workspace/coverage/cover_reg_top/2.uart_tl_errors.2403469135 Jun 28 04:31:11 PM PDT 24 Jun 28 04:31:13 PM PDT 24 189031784 ps
T1168 /workspace/coverage/cover_reg_top/19.uart_intr_test.2148526834 Jun 28 04:31:23 PM PDT 24 Jun 28 04:31:25 PM PDT 24 12233640 ps
T1169 /workspace/coverage/cover_reg_top/9.uart_tl_errors.2872525677 Jun 28 04:31:18 PM PDT 24 Jun 28 04:31:20 PM PDT 24 285791137 ps
T1170 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2706832377 Jun 28 04:31:13 PM PDT 24 Jun 28 04:31:14 PM PDT 24 20713728 ps
T1171 /workspace/coverage/cover_reg_top/0.uart_tl_errors.4257595101 Jun 28 04:31:03 PM PDT 24 Jun 28 04:31:07 PM PDT 24 98475971 ps
T1172 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2394615580 Jun 28 04:31:02 PM PDT 24 Jun 28 04:31:05 PM PDT 24 481284950 ps
T1173 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3133212717 Jun 28 04:31:28 PM PDT 24 Jun 28 04:31:29 PM PDT 24 65279210 ps
T1174 /workspace/coverage/cover_reg_top/14.uart_tl_errors.2536003497 Jun 28 04:31:22 PM PDT 24 Jun 28 04:31:24 PM PDT 24 131941221 ps
T85 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.820894028 Jun 28 04:31:26 PM PDT 24 Jun 28 04:31:28 PM PDT 24 319668404 ps
T1175 /workspace/coverage/cover_reg_top/43.uart_intr_test.1334603725 Jun 28 04:31:31 PM PDT 24 Jun 28 04:31:32 PM PDT 24 11719850 ps
T1176 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1098863997 Jun 28 04:31:44 PM PDT 24 Jun 28 04:31:46 PM PDT 24 12657925 ps
T1177 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.532300274 Jun 28 04:31:58 PM PDT 24 Jun 28 04:32:00 PM PDT 24 43458570 ps
T1178 /workspace/coverage/cover_reg_top/40.uart_intr_test.2322471880 Jun 28 04:31:33 PM PDT 24 Jun 28 04:31:35 PM PDT 24 14273453 ps
T1179 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3632549625 Jun 28 04:31:25 PM PDT 24 Jun 28 04:31:27 PM PDT 24 41755541 ps
T1180 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1469244967 Jun 28 04:31:20 PM PDT 24 Jun 28 04:31:22 PM PDT 24 85121718 ps
T1181 /workspace/coverage/cover_reg_top/22.uart_intr_test.2544751747 Jun 28 04:31:28 PM PDT 24 Jun 28 04:31:29 PM PDT 24 20743259 ps
T1182 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2751029557 Jun 28 04:31:30 PM PDT 24 Jun 28 04:31:31 PM PDT 24 98052957 ps
T1183 /workspace/coverage/cover_reg_top/13.uart_csr_rw.2619493573 Jun 28 04:31:30 PM PDT 24 Jun 28 04:31:31 PM PDT 24 38412226 ps
T1184 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.730632686 Jun 28 04:31:41 PM PDT 24 Jun 28 04:31:43 PM PDT 24 140712573 ps
T1185 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.648622247 Jun 28 04:31:22 PM PDT 24 Jun 28 04:31:24 PM PDT 24 18610640 ps
T1186 /workspace/coverage/cover_reg_top/9.uart_csr_rw.1887399904 Jun 28 04:31:13 PM PDT 24 Jun 28 04:31:14 PM PDT 24 12328498 ps
T1187 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1798696875 Jun 28 04:31:26 PM PDT 24 Jun 28 04:31:27 PM PDT 24 23269658 ps
T1188 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1084763655 Jun 28 04:31:15 PM PDT 24 Jun 28 04:31:17 PM PDT 24 283803480 ps
T1189 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2936846109 Jun 28 04:31:41 PM PDT 24 Jun 28 04:31:43 PM PDT 24 67499353 ps
T1190 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1828753544 Jun 28 04:31:26 PM PDT 24 Jun 28 04:31:28 PM PDT 24 53108205 ps
T1191 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1520138176 Jun 28 04:31:35 PM PDT 24 Jun 28 04:31:37 PM PDT 24 19451074 ps
T1192 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.4159070949 Jun 28 04:31:36 PM PDT 24 Jun 28 04:31:38 PM PDT 24 42593351 ps
T1193 /workspace/coverage/cover_reg_top/44.uart_intr_test.3858934441 Jun 28 04:31:30 PM PDT 24 Jun 28 04:31:32 PM PDT 24 19261219 ps
T1194 /workspace/coverage/cover_reg_top/46.uart_intr_test.1132456961 Jun 28 04:31:29 PM PDT 24 Jun 28 04:31:31 PM PDT 24 38503812 ps
T1195 /workspace/coverage/cover_reg_top/8.uart_tl_errors.1563114115 Jun 28 04:31:30 PM PDT 24 Jun 28 04:31:32 PM PDT 24 72856899 ps
T1196 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3842987144 Jun 28 04:31:34 PM PDT 24 Jun 28 04:31:37 PM PDT 24 24065110 ps
T1197 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2687795446 Jun 28 04:31:18 PM PDT 24 Jun 28 04:31:19 PM PDT 24 37891259 ps
T1198 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1008855992 Jun 28 04:31:27 PM PDT 24 Jun 28 04:31:28 PM PDT 24 22219134 ps
T1199 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2561918283 Jun 28 04:31:30 PM PDT 24 Jun 28 04:31:31 PM PDT 24 15185508 ps
T1200 /workspace/coverage/cover_reg_top/17.uart_csr_rw.3764367981 Jun 28 04:31:33 PM PDT 24 Jun 28 04:31:35 PM PDT 24 14562418 ps
T1201 /workspace/coverage/cover_reg_top/33.uart_intr_test.1545424312 Jun 28 04:31:42 PM PDT 24 Jun 28 04:31:45 PM PDT 24 27809605 ps
T1202 /workspace/coverage/cover_reg_top/41.uart_intr_test.312522933 Jun 28 04:31:39 PM PDT 24 Jun 28 04:31:41 PM PDT 24 13570143 ps
T1203 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.999199925 Jun 28 04:31:13 PM PDT 24 Jun 28 04:31:15 PM PDT 24 131793944 ps
T63 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1822509259 Jun 28 04:31:05 PM PDT 24 Jun 28 04:31:08 PM PDT 24 35211791 ps
T1204 /workspace/coverage/cover_reg_top/49.uart_intr_test.2660229346 Jun 28 04:31:22 PM PDT 24 Jun 28 04:31:24 PM PDT 24 60516251 ps
T1205 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3862543661 Jun 28 04:31:30 PM PDT 24 Jun 28 04:31:32 PM PDT 24 65691927 ps
T64 /workspace/coverage/cover_reg_top/3.uart_csr_rw.1670459800 Jun 28 04:31:22 PM PDT 24 Jun 28 04:31:24 PM PDT 24 36334625 ps
T1206 /workspace/coverage/cover_reg_top/11.uart_csr_rw.2401213434 Jun 28 04:31:36 PM PDT 24 Jun 28 04:31:38 PM PDT 24 168257026 ps
T1207 /workspace/coverage/cover_reg_top/18.uart_csr_rw.632011562 Jun 28 04:31:33 PM PDT 24 Jun 28 04:31:35 PM PDT 24 16292227 ps
T1208 /workspace/coverage/cover_reg_top/8.uart_csr_rw.1156869520 Jun 28 04:31:18 PM PDT 24 Jun 28 04:31:19 PM PDT 24 181265485 ps
T1209 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.176618428 Jun 28 04:31:19 PM PDT 24 Jun 28 04:31:21 PM PDT 24 62074792 ps
T1210 /workspace/coverage/cover_reg_top/15.uart_tl_errors.320000461 Jun 28 04:31:31 PM PDT 24 Jun 28 04:31:34 PM PDT 24 99035732 ps
T1211 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.751178046 Jun 28 04:31:25 PM PDT 24 Jun 28 04:31:26 PM PDT 24 15981606 ps
T1212 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1040750677 Jun 28 04:31:02 PM PDT 24 Jun 28 04:31:05 PM PDT 24 243629415 ps
T1213 /workspace/coverage/cover_reg_top/31.uart_intr_test.3916875497 Jun 28 04:31:38 PM PDT 24 Jun 28 04:31:40 PM PDT 24 13306287 ps
T1214 /workspace/coverage/cover_reg_top/30.uart_intr_test.1478336824 Jun 28 04:31:40 PM PDT 24 Jun 28 04:31:42 PM PDT 24 41252873 ps
T1215 /workspace/coverage/cover_reg_top/0.uart_csr_rw.1474768259 Jun 28 04:30:58 PM PDT 24 Jun 28 04:31:00 PM PDT 24 13095047 ps
T108 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.4168448069 Jun 28 04:31:37 PM PDT 24 Jun 28 04:31:39 PM PDT 24 52362681 ps
T1216 /workspace/coverage/cover_reg_top/1.uart_csr_rw.3858629471 Jun 28 04:31:51 PM PDT 24 Jun 28 04:31:52 PM PDT 24 36229157 ps
T1217 /workspace/coverage/cover_reg_top/11.uart_tl_errors.378420806 Jun 28 04:31:31 PM PDT 24 Jun 28 04:31:35 PM PDT 24 204605135 ps
T1218 /workspace/coverage/cover_reg_top/7.uart_tl_errors.2921707211 Jun 28 04:31:19 PM PDT 24 Jun 28 04:31:22 PM PDT 24 111706706 ps
T1219 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3487402597 Jun 28 04:31:12 PM PDT 24 Jun 28 04:31:14 PM PDT 24 204930516 ps
T1220 /workspace/coverage/cover_reg_top/21.uart_intr_test.3568673218 Jun 28 04:31:30 PM PDT 24 Jun 28 04:31:32 PM PDT 24 23706753 ps
T1221 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1913079749 Jun 28 04:31:07 PM PDT 24 Jun 28 04:31:09 PM PDT 24 32197926 ps
T1222 /workspace/coverage/cover_reg_top/5.uart_csr_rw.675947844 Jun 28 04:31:09 PM PDT 24 Jun 28 04:31:10 PM PDT 24 19991712 ps
T1223 /workspace/coverage/cover_reg_top/16.uart_tl_errors.4116159602 Jun 28 04:31:44 PM PDT 24 Jun 28 04:31:48 PM PDT 24 78908196 ps
T1224 /workspace/coverage/cover_reg_top/12.uart_tl_errors.497853833 Jun 28 04:31:16 PM PDT 24 Jun 28 04:31:17 PM PDT 24 134943734 ps
T1225 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3275497558 Jun 28 04:31:15 PM PDT 24 Jun 28 04:31:16 PM PDT 24 66520223 ps
T1226 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3877120018 Jun 28 04:31:22 PM PDT 24 Jun 28 04:31:24 PM PDT 24 57533402 ps
T1227 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.4027753010 Jun 28 04:31:28 PM PDT 24 Jun 28 04:31:31 PM PDT 24 63392356 ps
T109 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2951802873 Jun 28 04:31:31 PM PDT 24 Jun 28 04:31:33 PM PDT 24 58626798 ps

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.4089043411
Short name T5
Test name
Test status
Simulation time 137422405082 ps
CPU time 394.56 seconds
Started Jun 28 04:38:33 PM PDT 24
Finished Jun 28 04:45:09 PM PDT 24
Peak memory 216612 kb
Host smart-0da0d63f-70b1-4892-b959-622035e379b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089043411 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.4089043411
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.4179296901
Short name T13
Test name
Test status
Simulation time 185150379461 ps
CPU time 879.95 seconds
Started Jun 28 04:40:53 PM PDT 24
Finished Jun 28 04:55:33 PM PDT 24
Peak memory 216260 kb
Host smart-a7a1731d-5293-40e5-b80d-abc6743c0bec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179296901 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.4179296901
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_stress_all.1693784287
Short name T16
Test name
Test status
Simulation time 571622333695 ps
CPU time 1544.05 seconds
Started Jun 28 04:40:00 PM PDT 24
Finished Jun 28 05:05:45 PM PDT 24
Peak memory 199752 kb
Host smart-629dd7ff-3c1c-4576-bb8b-a08ffb7329f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693784287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1693784287
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all.3953004612
Short name T170
Test name
Test status
Simulation time 1004552920188 ps
CPU time 246.17 seconds
Started Jun 28 04:37:37 PM PDT 24
Finished Jun 28 04:41:44 PM PDT 24
Peak memory 199884 kb
Host smart-e1fd9c83-403d-4d71-b855-1ded2253c7aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953004612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3953004612
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.2498108496
Short name T32
Test name
Test status
Simulation time 249621967824 ps
CPU time 1268.28 seconds
Started Jun 28 04:40:47 PM PDT 24
Finished Jun 28 05:01:57 PM PDT 24
Peak memory 224684 kb
Host smart-2bb09eaf-16e9-464e-b7c9-bb538f7c5b4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498108496 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.2498108496
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.1125634891
Short name T10
Test name
Test status
Simulation time 138973747539 ps
CPU time 807.36 seconds
Started Jun 28 04:37:00 PM PDT 24
Finished Jun 28 04:50:28 PM PDT 24
Peak memory 199688 kb
Host smart-1f631a74-75a2-4567-bfce-d2ef3070e258
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1125634891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.1125634891
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_stress_all.4117745568
Short name T105
Test name
Test status
Simulation time 717348349067 ps
CPU time 179.39 seconds
Started Jun 28 04:40:16 PM PDT 24
Finished Jun 28 04:43:16 PM PDT 24
Peak memory 199808 kb
Host smart-2ca62c8f-6364-40fa-b874-74313c84790c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117745568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.4117745568
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all.2378026335
Short name T130
Test name
Test status
Simulation time 438046740297 ps
CPU time 133.4 seconds
Started Jun 28 04:39:23 PM PDT 24
Finished Jun 28 04:41:37 PM PDT 24
Peak memory 199824 kb
Host smart-7df73946-4cd9-4f73-a9d5-5a5fe70dab1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378026335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2378026335
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.171724474
Short name T79
Test name
Test status
Simulation time 203979765 ps
CPU time 1.44 seconds
Started Jun 28 04:31:22 PM PDT 24
Finished Jun 28 04:31:25 PM PDT 24
Peak memory 198644 kb
Host smart-420acf7f-80fb-4a22-ac9b-a533794af2d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171724474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.171724474
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/default/10.uart_alert_test.2435123453
Short name T20
Test name
Test status
Simulation time 140149947 ps
CPU time 0.55 seconds
Started Jun 28 04:37:14 PM PDT 24
Finished Jun 28 04:37:16 PM PDT 24
Peak memory 195184 kb
Host smart-9af21c68-8219-4e96-b3f4-642458667088
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435123453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2435123453
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.3998595515
Short name T2
Test name
Test status
Simulation time 73318374829 ps
CPU time 636.06 seconds
Started Jun 28 04:37:54 PM PDT 24
Finished Jun 28 04:48:31 PM PDT 24
Peak memory 199860 kb
Host smart-2885a29e-9254-4ad9-a60c-03e5ad6e461c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3998595515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3998595515
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1560846552
Short name T236
Test name
Test status
Simulation time 217619772843 ps
CPU time 144.24 seconds
Started Jun 28 04:36:59 PM PDT 24
Finished Jun 28 04:39:25 PM PDT 24
Peak memory 199764 kb
Host smart-c4bca34e-bb50-4970-b454-ffd828440acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560846552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1560846552
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.1236663472
Short name T114
Test name
Test status
Simulation time 101983727103 ps
CPU time 136.78 seconds
Started Jun 28 04:41:23 PM PDT 24
Finished Jun 28 04:43:41 PM PDT 24
Peak memory 199916 kb
Host smart-b4cf9aca-1034-4eb0-b88a-6780abdd7ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236663472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.1236663472
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.1177194996
Short name T26
Test name
Test status
Simulation time 93345049745 ps
CPU time 246.26 seconds
Started Jun 28 04:39:57 PM PDT 24
Finished Jun 28 04:44:04 PM PDT 24
Peak memory 215824 kb
Host smart-0a7a27c6-3f2b-40f1-9e1c-d52441bf4ebb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177194996 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.1177194996
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_sec_cm.4239604003
Short name T86
Test name
Test status
Simulation time 224081354 ps
CPU time 0.85 seconds
Started Jun 28 04:36:26 PM PDT 24
Finished Jun 28 04:36:27 PM PDT 24
Peak memory 218188 kb
Host smart-81f4d271-0a1c-4999-84a1-89e1020d5bda
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239604003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.4239604003
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2668775240
Short name T36
Test name
Test status
Simulation time 120463899148 ps
CPU time 224.75 seconds
Started Jun 28 04:41:10 PM PDT 24
Finished Jun 28 04:44:56 PM PDT 24
Peak memory 199916 kb
Host smart-40ed574b-b346-4f64-abb6-71d313665d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668775240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2668775240
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.2242085442
Short name T59
Test name
Test status
Simulation time 98744973 ps
CPU time 0.62 seconds
Started Jun 28 04:31:26 PM PDT 24
Finished Jun 28 04:31:27 PM PDT 24
Peak memory 195604 kb
Host smart-92c0a673-763e-4438-b2f4-956d07c022ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242085442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.2242085442
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/default/16.uart_stress_all.2996251382
Short name T271
Test name
Test status
Simulation time 351163851762 ps
CPU time 374.14 seconds
Started Jun 28 04:37:41 PM PDT 24
Finished Jun 28 04:43:55 PM PDT 24
Peak memory 199836 kb
Host smart-19caa2e8-fcc0-409d-939e-74e2f5e17a00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996251382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.2996251382
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.3170512127
Short name T136
Test name
Test status
Simulation time 249629569979 ps
CPU time 151.8 seconds
Started Jun 28 04:41:42 PM PDT 24
Finished Jun 28 04:44:16 PM PDT 24
Peak memory 199772 kb
Host smart-eed2aa08-4684-4327-bc74-af93e1b24852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170512127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.3170512127
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_tx_rx.732933650
Short name T222
Test name
Test status
Simulation time 97409864187 ps
CPU time 46.57 seconds
Started Jun 28 04:37:35 PM PDT 24
Finished Jun 28 04:38:22 PM PDT 24
Peak memory 199804 kb
Host smart-99d60e9f-94ee-47c2-a796-c063080259b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732933650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.732933650
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.2586142772
Short name T299
Test name
Test status
Simulation time 303560977869 ps
CPU time 736.25 seconds
Started Jun 28 04:38:21 PM PDT 24
Finished Jun 28 04:50:39 PM PDT 24
Peak memory 212364 kb
Host smart-66161441-7034-4b2b-9a58-17239bbd0e9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586142772 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2586142772
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_stress_all.2857482422
Short name T107
Test name
Test status
Simulation time 78295788732 ps
CPU time 125.37 seconds
Started Jun 28 04:39:49 PM PDT 24
Finished Jun 28 04:41:55 PM PDT 24
Peak memory 199848 kb
Host smart-d74b6e44-94b0-45f6-baca-6efaae987995
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857482422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2857482422
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2280541675
Short name T239
Test name
Test status
Simulation time 150524282908 ps
CPU time 457.66 seconds
Started Jun 28 04:36:32 PM PDT 24
Finished Jun 28 04:44:11 PM PDT 24
Peak memory 199596 kb
Host smart-17033c61-7741-4943-977e-c7e5ef6c2273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280541675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2280541675
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.2089452781
Short name T143
Test name
Test status
Simulation time 93497173934 ps
CPU time 53.95 seconds
Started Jun 28 04:38:09 PM PDT 24
Finished Jun 28 04:39:04 PM PDT 24
Peak memory 199828 kb
Host smart-f09676c4-0861-49db-b50c-afd719166bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089452781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.2089452781
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.89172186
Short name T113
Test name
Test status
Simulation time 35353980266 ps
CPU time 30.08 seconds
Started Jun 28 04:41:13 PM PDT 24
Finished Jun 28 04:41:43 PM PDT 24
Peak memory 199104 kb
Host smart-bf3b857b-6010-41cf-bbad-1f6add505ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89172186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.89172186
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3959003033
Short name T77
Test name
Test status
Simulation time 123786132 ps
CPU time 1.39 seconds
Started Jun 28 04:31:31 PM PDT 24
Finished Jun 28 04:31:34 PM PDT 24
Peak memory 198688 kb
Host smart-413fce16-6042-493c-ad4b-9d8e3bbcceca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959003033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3959003033
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.2961628593
Short name T181
Test name
Test status
Simulation time 82387851018 ps
CPU time 126.54 seconds
Started Jun 28 04:41:08 PM PDT 24
Finished Jun 28 04:43:15 PM PDT 24
Peak memory 199768 kb
Host smart-a98e242d-f3a9-4be6-a78a-22358c877f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961628593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2961628593
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.349544597
Short name T8
Test name
Test status
Simulation time 23447594601 ps
CPU time 40.03 seconds
Started Jun 28 04:38:21 PM PDT 24
Finished Jun 28 04:39:03 PM PDT 24
Peak memory 199832 kb
Host smart-ada4a631-8deb-4ce9-8f52-886908778293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349544597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.349544597
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_stress_all.2713511092
Short name T106
Test name
Test status
Simulation time 213039150128 ps
CPU time 79.2 seconds
Started Jun 28 04:39:39 PM PDT 24
Finished Jun 28 04:40:59 PM PDT 24
Peak memory 199784 kb
Host smart-6e3f10d0-9529-4282-9a7e-735574e90422
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713511092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2713511092
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.2722821050
Short name T154
Test name
Test status
Simulation time 20058199625 ps
CPU time 23.75 seconds
Started Jun 28 04:40:58 PM PDT 24
Finished Jun 28 04:41:22 PM PDT 24
Peak memory 199912 kb
Host smart-6a76761e-a984-401c-87cf-70b63d963b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722821050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2722821050
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.3263932000
Short name T249
Test name
Test status
Simulation time 194026245672 ps
CPU time 266.82 seconds
Started Jun 28 04:40:11 PM PDT 24
Finished Jun 28 04:44:38 PM PDT 24
Peak memory 199908 kb
Host smart-76f5be07-a0ce-40e8-ae48-5d199a47ce0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263932000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.3263932000
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.3269941830
Short name T909
Test name
Test status
Simulation time 356495944262 ps
CPU time 901.81 seconds
Started Jun 28 04:40:53 PM PDT 24
Finished Jun 28 04:55:56 PM PDT 24
Peak memory 216400 kb
Host smart-9cd6261f-0a5a-4915-9478-7440c05f5912
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269941830 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.3269941830
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_full.1575383479
Short name T125
Test name
Test status
Simulation time 34200224187 ps
CPU time 27.2 seconds
Started Jun 28 04:37:34 PM PDT 24
Finished Jun 28 04:38:02 PM PDT 24
Peak memory 199852 kb
Host smart-082fec4f-d62b-476c-92c9-efb17cdd8c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575383479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.1575383479
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.346208484
Short name T177
Test name
Test status
Simulation time 54904117547 ps
CPU time 80.57 seconds
Started Jun 28 04:41:57 PM PDT 24
Finished Jun 28 04:43:18 PM PDT 24
Peak memory 199776 kb
Host smart-b47ef6ce-80d8-4b60-8149-f2262c64dffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346208484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.346208484
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.3131272945
Short name T169
Test name
Test status
Simulation time 38266398638 ps
CPU time 45.54 seconds
Started Jun 28 04:41:53 PM PDT 24
Finished Jun 28 04:42:40 PM PDT 24
Peak memory 199748 kb
Host smart-f03ebd40-5851-4184-a025-23a4b1294372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131272945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3131272945
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.3582830532
Short name T149
Test name
Test status
Simulation time 142942105643 ps
CPU time 70.34 seconds
Started Jun 28 04:41:52 PM PDT 24
Finished Jun 28 04:43:03 PM PDT 24
Peak memory 199900 kb
Host smart-1c302ecb-9bad-43db-afe8-0b5fefb3defa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582830532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3582830532
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.2934094269
Short name T184
Test name
Test status
Simulation time 42626881860 ps
CPU time 67.6 seconds
Started Jun 28 04:41:12 PM PDT 24
Finished Jun 28 04:42:20 PM PDT 24
Peak memory 199532 kb
Host smart-ca99ab88-0469-4d9a-a281-bc90158c738f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934094269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2934094269
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.1116395214
Short name T202
Test name
Test status
Simulation time 66724103982 ps
CPU time 621.82 seconds
Started Jun 28 04:37:55 PM PDT 24
Finished Jun 28 04:48:18 PM PDT 24
Peak memory 216252 kb
Host smart-34a240b5-fb12-4e38-bb69-0be849326059
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116395214 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.1116395214
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.593794151
Short name T301
Test name
Test status
Simulation time 65041871060 ps
CPU time 399.53 seconds
Started Jun 28 04:38:22 PM PDT 24
Finished Jun 28 04:45:03 PM PDT 24
Peak memory 216408 kb
Host smart-f1c38c16-81a0-481c-8812-427ba6dee310
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593794151 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.593794151
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.1369203558
Short name T175
Test name
Test status
Simulation time 162972732777 ps
CPU time 242.3 seconds
Started Jun 28 04:42:13 PM PDT 24
Finished Jun 28 04:46:17 PM PDT 24
Peak memory 199940 kb
Host smart-b31aa165-606b-4195-b6b6-aee395c0bcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369203558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1369203558
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.1552240171
Short name T162
Test name
Test status
Simulation time 179384827173 ps
CPU time 201.23 seconds
Started Jun 28 04:40:59 PM PDT 24
Finished Jun 28 04:44:22 PM PDT 24
Peak memory 199876 kb
Host smart-61cc44d2-9236-47a9-8e3e-b7962cc0a4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552240171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1552240171
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.1694399353
Short name T207
Test name
Test status
Simulation time 55964567988 ps
CPU time 74.06 seconds
Started Jun 28 04:41:11 PM PDT 24
Finished Jun 28 04:42:26 PM PDT 24
Peak memory 199684 kb
Host smart-b3c6adec-40e3-41ac-b509-f25a8f602367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694399353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1694399353
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.2939708769
Short name T153
Test name
Test status
Simulation time 75229795943 ps
CPU time 20.12 seconds
Started Jun 28 04:41:20 PM PDT 24
Finished Jun 28 04:41:41 PM PDT 24
Peak memory 199560 kb
Host smart-d18c0a0c-ef12-4ac0-a6ec-4e36abbae98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939708769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.2939708769
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2659255313
Short name T40
Test name
Test status
Simulation time 13232664438 ps
CPU time 21.5 seconds
Started Jun 28 04:37:34 PM PDT 24
Finished Jun 28 04:37:57 PM PDT 24
Peak memory 199752 kb
Host smart-55a0d460-a3d8-484a-8eb5-6d153ae11f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659255313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2659255313
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.411759222
Short name T204
Test name
Test status
Simulation time 58647807824 ps
CPU time 131.29 seconds
Started Jun 28 04:41:42 PM PDT 24
Finished Jun 28 04:43:55 PM PDT 24
Peak memory 199916 kb
Host smart-a31574f2-6e6c-41a0-8e97-9d629a7dabc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411759222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.411759222
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.2620222329
Short name T173
Test name
Test status
Simulation time 225856267513 ps
CPU time 55.76 seconds
Started Jun 28 04:42:03 PM PDT 24
Finished Jun 28 04:42:59 PM PDT 24
Peak memory 199884 kb
Host smart-9f6b9587-f611-4395-84fd-0cdb386bc9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620222329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2620222329
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2887841670
Short name T203
Test name
Test status
Simulation time 39002676932 ps
CPU time 50.21 seconds
Started Jun 28 04:42:13 PM PDT 24
Finished Jun 28 04:43:04 PM PDT 24
Peak memory 199912 kb
Host smart-03a930e7-4342-45e8-97d4-e55e3d5083d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887841670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2887841670
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.2636007900
Short name T494
Test name
Test status
Simulation time 92134171707 ps
CPU time 32.74 seconds
Started Jun 28 04:36:32 PM PDT 24
Finished Jun 28 04:37:06 PM PDT 24
Peak memory 199772 kb
Host smart-89f23d28-eae3-44bc-8ea9-97ec0a3bec85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636007900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.2636007900
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_perf.1795228428
Short name T9
Test name
Test status
Simulation time 15301486185 ps
CPU time 701.31 seconds
Started Jun 28 04:36:27 PM PDT 24
Finished Jun 28 04:48:09 PM PDT 24
Peak memory 199752 kb
Host smart-f40f3900-2881-4929-adf7-da512c788851
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1795228428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1795228428
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2727012877
Short name T188
Test name
Test status
Simulation time 191956456754 ps
CPU time 69.03 seconds
Started Jun 28 04:41:13 PM PDT 24
Finished Jun 28 04:42:22 PM PDT 24
Peak memory 199240 kb
Host smart-a3069368-b92d-4509-8a07-8bb62817dd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727012877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2727012877
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.2801160945
Short name T123
Test name
Test status
Simulation time 34189483269 ps
CPU time 15.21 seconds
Started Jun 28 04:41:10 PM PDT 24
Finished Jun 28 04:41:27 PM PDT 24
Peak memory 199752 kb
Host smart-50f9a5d0-888a-4564-a060-483798fb2f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801160945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2801160945
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.4082147067
Short name T195
Test name
Test status
Simulation time 197477663453 ps
CPU time 476.05 seconds
Started Jun 28 04:41:12 PM PDT 24
Finished Jun 28 04:49:09 PM PDT 24
Peak memory 199816 kb
Host smart-7b536cd6-0fa8-444c-b6dd-fb3409c2bd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082147067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.4082147067
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.3876192434
Short name T215
Test name
Test status
Simulation time 45868001137 ps
CPU time 40.22 seconds
Started Jun 28 04:41:21 PM PDT 24
Finished Jun 28 04:42:02 PM PDT 24
Peak memory 199752 kb
Host smart-b19ec9e4-e2c8-4e07-9a36-d25131796768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876192434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3876192434
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2450825239
Short name T194
Test name
Test status
Simulation time 138337985297 ps
CPU time 26.98 seconds
Started Jun 28 04:41:23 PM PDT 24
Finished Jun 28 04:41:51 PM PDT 24
Peak memory 199820 kb
Host smart-d0db55cc-d2db-4fd6-b44c-cbb9cf8b5f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450825239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2450825239
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.1045001301
Short name T211
Test name
Test status
Simulation time 20564192826 ps
CPU time 16.15 seconds
Started Jun 28 04:41:36 PM PDT 24
Finished Jun 28 04:41:52 PM PDT 24
Peak memory 199800 kb
Host smart-a89fceb7-873e-4f7d-969c-bca08b88948e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045001301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1045001301
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.3425434193
Short name T209
Test name
Test status
Simulation time 97539737950 ps
CPU time 31.43 seconds
Started Jun 28 04:41:33 PM PDT 24
Finished Jun 28 04:42:05 PM PDT 24
Peak memory 199756 kb
Host smart-50512424-b274-49c0-8b48-3c50d29864e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425434193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3425434193
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2925345720
Short name T218
Test name
Test status
Simulation time 28377780861 ps
CPU time 13.21 seconds
Started Jun 28 04:37:56 PM PDT 24
Finished Jun 28 04:38:10 PM PDT 24
Peak memory 199880 kb
Host smart-a956c7ca-61cf-4502-a223-d715614fcf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925345720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2925345720
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.2719803923
Short name T133
Test name
Test status
Simulation time 80007667907 ps
CPU time 132.53 seconds
Started Jun 28 04:38:24 PM PDT 24
Finished Jun 28 04:40:37 PM PDT 24
Peak memory 200024 kb
Host smart-0474b6b3-2167-4fa0-a941-4d362202e64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719803923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2719803923
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.1890885251
Short name T200
Test name
Test status
Simulation time 36320236465 ps
CPU time 16.15 seconds
Started Jun 28 04:42:05 PM PDT 24
Finished Jun 28 04:42:21 PM PDT 24
Peak memory 199812 kb
Host smart-eeec0fd6-dfc5-4efa-b7df-1d3de078cb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890885251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.1890885251
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.3731711844
Short name T132
Test name
Test status
Simulation time 134026121577 ps
CPU time 228.64 seconds
Started Jun 28 04:42:04 PM PDT 24
Finished Jun 28 04:45:53 PM PDT 24
Peak memory 199916 kb
Host smart-edd25bb1-23eb-45f6-88b2-6d7a6c0fea46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731711844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.3731711844
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.2282316916
Short name T160
Test name
Test status
Simulation time 32314889139 ps
CPU time 24.93 seconds
Started Jun 28 04:42:13 PM PDT 24
Finished Jun 28 04:42:39 PM PDT 24
Peak memory 199916 kb
Host smart-ebafecab-44d2-475d-b8d0-abd971e19a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282316916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2282316916
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.2446346280
Short name T134
Test name
Test status
Simulation time 122968969219 ps
CPU time 51.18 seconds
Started Jun 28 04:42:16 PM PDT 24
Finished Jun 28 04:43:08 PM PDT 24
Peak memory 199984 kb
Host smart-b9d6b510-36c5-440b-ab47-e62636731622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446346280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2446346280
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.2820513444
Short name T213
Test name
Test status
Simulation time 12223123140 ps
CPU time 20.25 seconds
Started Jun 28 04:42:14 PM PDT 24
Finished Jun 28 04:42:35 PM PDT 24
Peak memory 199824 kb
Host smart-40461c2c-5bf6-4b54-b232-259716c4f1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820513444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2820513444
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_stress_all.1298371080
Short name T212
Test name
Test status
Simulation time 179332387831 ps
CPU time 117.79 seconds
Started Jun 28 04:36:38 PM PDT 24
Finished Jun 28 04:38:37 PM PDT 24
Peak memory 199852 kb
Host smart-455c3ed0-9c9e-4964-989c-f78881a87e1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298371080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.1298371080
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3181257523
Short name T55
Test name
Test status
Simulation time 53693489 ps
CPU time 0.84 seconds
Started Jun 28 04:30:58 PM PDT 24
Finished Jun 28 04:31:00 PM PDT 24
Peak memory 195824 kb
Host smart-ed943538-ca98-40f1-96c5-cd2d9c2739d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181257523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3181257523
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.692888330
Short name T1149
Test name
Test status
Simulation time 126730992 ps
CPU time 1.44 seconds
Started Jun 28 04:31:00 PM PDT 24
Finished Jun 28 04:31:02 PM PDT 24
Peak memory 197852 kb
Host smart-85d9eb56-d41f-453e-9f80-8f65db02d643
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692888330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.692888330
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1822509259
Short name T63
Test name
Test status
Simulation time 35211791 ps
CPU time 0.63 seconds
Started Jun 28 04:31:05 PM PDT 24
Finished Jun 28 04:31:08 PM PDT 24
Peak memory 194808 kb
Host smart-b1109095-8ca0-4874-b7b0-90708d1b890c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822509259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1822509259
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2490315472
Short name T1115
Test name
Test status
Simulation time 25145139 ps
CPU time 1.2 seconds
Started Jun 28 04:31:03 PM PDT 24
Finished Jun 28 04:31:06 PM PDT 24
Peak memory 199468 kb
Host smart-2052cf14-3f2b-49b3-bf37-125331c4b79e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490315472 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2490315472
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.1474768259
Short name T1215
Test name
Test status
Simulation time 13095047 ps
CPU time 0.71 seconds
Started Jun 28 04:30:58 PM PDT 24
Finished Jun 28 04:31:00 PM PDT 24
Peak memory 195000 kb
Host smart-f9aa3c15-2f95-41f3-ac9d-7aec98b00b26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474768259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1474768259
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.1602990645
Short name T1151
Test name
Test status
Simulation time 26594336 ps
CPU time 0.66 seconds
Started Jun 28 04:31:01 PM PDT 24
Finished Jun 28 04:31:02 PM PDT 24
Peak memory 193772 kb
Host smart-49ab4b78-0b10-4bcd-9937-a7f363d1eda8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602990645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1602990645
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1913079749
Short name T1221
Test name
Test status
Simulation time 32197926 ps
CPU time 0.77 seconds
Started Jun 28 04:31:07 PM PDT 24
Finished Jun 28 04:31:09 PM PDT 24
Peak memory 195808 kb
Host smart-0316d852-6b24-4a1a-a326-cdb9d0064213
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913079749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1913079749
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.4257595101
Short name T1171
Test name
Test status
Simulation time 98475971 ps
CPU time 2.12 seconds
Started Jun 28 04:31:03 PM PDT 24
Finished Jun 28 04:31:07 PM PDT 24
Peak memory 200244 kb
Host smart-f7ce9ece-979f-4ffe-a293-d9dacf04ee38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257595101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.4257595101
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2394615580
Short name T1172
Test name
Test status
Simulation time 481284950 ps
CPU time 1.32 seconds
Started Jun 28 04:31:02 PM PDT 24
Finished Jun 28 04:31:05 PM PDT 24
Peak memory 199196 kb
Host smart-6d428f14-eb2b-4edc-92bb-4de72127a6bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394615580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2394615580
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1118876549
Short name T58
Test name
Test status
Simulation time 15576035 ps
CPU time 0.66 seconds
Started Jun 28 04:31:05 PM PDT 24
Finished Jun 28 04:31:08 PM PDT 24
Peak memory 195604 kb
Host smart-3145f20c-8ffe-4492-8fdc-e31f5b47eb33
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118876549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1118876549
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1477552400
Short name T60
Test name
Test status
Simulation time 1774695235 ps
CPU time 2.85 seconds
Started Jun 28 04:31:00 PM PDT 24
Finished Jun 28 04:31:04 PM PDT 24
Peak memory 197072 kb
Host smart-48345333-7f89-4f85-84d7-7531caefd300
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477552400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.1477552400
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2706832377
Short name T1170
Test name
Test status
Simulation time 20713728 ps
CPU time 0.56 seconds
Started Jun 28 04:31:13 PM PDT 24
Finished Jun 28 04:31:14 PM PDT 24
Peak memory 195608 kb
Host smart-3e34a78d-402f-41c9-be23-c63dfa41c88c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706832377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2706832377
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3842987144
Short name T1196
Test name
Test status
Simulation time 24065110 ps
CPU time 1.13 seconds
Started Jun 28 04:31:34 PM PDT 24
Finished Jun 28 04:31:37 PM PDT 24
Peak memory 199256 kb
Host smart-a222a588-7f27-4b21-bd14-51eb0da2935b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842987144 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.3842987144
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3858629471
Short name T1216
Test name
Test status
Simulation time 36229157 ps
CPU time 0.6 seconds
Started Jun 28 04:31:51 PM PDT 24
Finished Jun 28 04:31:52 PM PDT 24
Peak memory 195664 kb
Host smart-9ab4910b-a9d7-495d-a728-5a7c10b34a9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858629471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3858629471
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.637068061
Short name T1162
Test name
Test status
Simulation time 107412413 ps
CPU time 0.59 seconds
Started Jun 28 04:31:05 PM PDT 24
Finished Jun 28 04:31:08 PM PDT 24
Peak memory 194580 kb
Host smart-0af7acbb-4afe-461b-b48e-5f15faaa2938
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637068061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.637068061
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3521215666
Short name T73
Test name
Test status
Simulation time 64790369 ps
CPU time 0.75 seconds
Started Jun 28 04:31:02 PM PDT 24
Finished Jun 28 04:31:04 PM PDT 24
Peak memory 196336 kb
Host smart-072adb0a-2718-4e7a-843d-acbca98b9e9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521215666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3521215666
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.3276639046
Short name T1133
Test name
Test status
Simulation time 22497719 ps
CPU time 1.4 seconds
Started Jun 28 04:31:06 PM PDT 24
Finished Jun 28 04:31:09 PM PDT 24
Peak memory 199456 kb
Host smart-c7714afc-ff9d-42a1-955c-f5ec1d24e59a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276639046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3276639046
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1040750677
Short name T1212
Test name
Test status
Simulation time 243629415 ps
CPU time 1.2 seconds
Started Jun 28 04:31:02 PM PDT 24
Finished Jun 28 04:31:05 PM PDT 24
Peak memory 199524 kb
Host smart-9e6d9a5f-fee6-4836-b758-fb239ef25dea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040750677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1040750677
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3544679280
Short name T1138
Test name
Test status
Simulation time 96750097 ps
CPU time 0.74 seconds
Started Jun 28 04:31:22 PM PDT 24
Finished Jun 28 04:31:24 PM PDT 24
Peak memory 198356 kb
Host smart-6a6ac9d7-e39e-4721-9fec-9b3d5db026fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544679280 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3544679280
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3092118712
Short name T1147
Test name
Test status
Simulation time 103068719 ps
CPU time 0.58 seconds
Started Jun 28 04:31:32 PM PDT 24
Finished Jun 28 04:31:33 PM PDT 24
Peak memory 195676 kb
Host smart-dc75fdd9-3c10-45cf-b60d-a38af5925724
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092118712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3092118712
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.627088812
Short name T1111
Test name
Test status
Simulation time 71998406 ps
CPU time 0.56 seconds
Started Jun 28 04:31:22 PM PDT 24
Finished Jun 28 04:31:24 PM PDT 24
Peak memory 194592 kb
Host smart-a7d1fe42-0e0f-4de8-8c61-3a725b4c6457
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627088812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.627088812
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.648622247
Short name T1185
Test name
Test status
Simulation time 18610640 ps
CPU time 0.78 seconds
Started Jun 28 04:31:22 PM PDT 24
Finished Jun 28 04:31:24 PM PDT 24
Peak memory 197364 kb
Host smart-5016232d-1e2d-43e3-8b35-0c7cda4b0e7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648622247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr
_outstanding.648622247
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.2518396865
Short name T1099
Test name
Test status
Simulation time 32984974 ps
CPU time 1.82 seconds
Started Jun 28 04:31:38 PM PDT 24
Finished Jun 28 04:31:41 PM PDT 24
Peak memory 200652 kb
Host smart-da23d1df-4540-4aa3-b25e-b9e2dc315321
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518396865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.2518396865
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.791540067
Short name T83
Test name
Test status
Simulation time 94555617 ps
CPU time 1.29 seconds
Started Jun 28 04:31:31 PM PDT 24
Finished Jun 28 04:31:33 PM PDT 24
Peak memory 199604 kb
Host smart-cd67b648-dc2c-49c4-bccd-5ef10c2a2466
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791540067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.791540067
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3335764258
Short name T1137
Test name
Test status
Simulation time 263943052 ps
CPU time 1.01 seconds
Started Jun 28 04:31:23 PM PDT 24
Finished Jun 28 04:31:25 PM PDT 24
Peak memory 200420 kb
Host smart-a2823642-e1d8-4253-9151-a8076a3e8477
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335764258 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.3335764258
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.2401213434
Short name T1206
Test name
Test status
Simulation time 168257026 ps
CPU time 0.6 seconds
Started Jun 28 04:31:36 PM PDT 24
Finished Jun 28 04:31:38 PM PDT 24
Peak memory 195640 kb
Host smart-5cb77296-f59c-4000-a304-f7ebde532c34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401213434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2401213434
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.4127310112
Short name T1121
Test name
Test status
Simulation time 27686015 ps
CPU time 0.55 seconds
Started Jun 28 04:31:20 PM PDT 24
Finished Jun 28 04:31:21 PM PDT 24
Peak memory 194804 kb
Host smart-2c0e0698-100b-42f0-b7da-953ce7e53a5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127310112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.4127310112
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2556697129
Short name T1160
Test name
Test status
Simulation time 96097108 ps
CPU time 0.71 seconds
Started Jun 28 04:31:21 PM PDT 24
Finished Jun 28 04:31:22 PM PDT 24
Peak memory 197676 kb
Host smart-606d85a1-0303-483f-b6d7-57533479b272
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556697129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.2556697129
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.378420806
Short name T1217
Test name
Test status
Simulation time 204605135 ps
CPU time 2.19 seconds
Started Jun 28 04:31:31 PM PDT 24
Finished Jun 28 04:31:35 PM PDT 24
Peak memory 199416 kb
Host smart-1a97aca4-193e-4cbd-914e-843957b5bfc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378420806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.378420806
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.820894028
Short name T85
Test name
Test status
Simulation time 319668404 ps
CPU time 1.41 seconds
Started Jun 28 04:31:26 PM PDT 24
Finished Jun 28 04:31:28 PM PDT 24
Peak memory 198784 kb
Host smart-b776d722-d775-410e-8ab1-42fc74635fff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820894028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.820894028
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2687795446
Short name T1197
Test name
Test status
Simulation time 37891259 ps
CPU time 0.98 seconds
Started Jun 28 04:31:18 PM PDT 24
Finished Jun 28 04:31:19 PM PDT 24
Peak memory 199956 kb
Host smart-078a800c-7e42-4904-9b90-cc3e599bde54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687795446 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.2687795446
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.1054473685
Short name T74
Test name
Test status
Simulation time 52650333 ps
CPU time 0.59 seconds
Started Jun 28 04:31:19 PM PDT 24
Finished Jun 28 04:31:20 PM PDT 24
Peak memory 195608 kb
Host smart-dbdd720a-a00f-4d16-bc35-09bf504d77ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054473685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1054473685
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.1007395767
Short name T1154
Test name
Test status
Simulation time 29166758 ps
CPU time 0.6 seconds
Started Jun 28 04:31:20 PM PDT 24
Finished Jun 28 04:31:21 PM PDT 24
Peak memory 194596 kb
Host smart-92be7548-6318-47ad-a28b-6c33e2ca00ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007395767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1007395767
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.4159070949
Short name T1192
Test name
Test status
Simulation time 42593351 ps
CPU time 0.63 seconds
Started Jun 28 04:31:36 PM PDT 24
Finished Jun 28 04:31:38 PM PDT 24
Peak memory 195688 kb
Host smart-36e2b7a8-8b1a-48be-bf49-a96aeba4516d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159070949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.4159070949
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.497853833
Short name T1224
Test name
Test status
Simulation time 134943734 ps
CPU time 1.07 seconds
Started Jun 28 04:31:16 PM PDT 24
Finished Jun 28 04:31:17 PM PDT 24
Peak memory 199236 kb
Host smart-1fe0ab75-73d2-4989-b0f1-a2a46e55145c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497853833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.497853833
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1266525669
Short name T84
Test name
Test status
Simulation time 149934213 ps
CPU time 1.37 seconds
Started Jun 28 04:31:39 PM PDT 24
Finished Jun 28 04:31:42 PM PDT 24
Peak memory 199820 kb
Host smart-6a2cf304-d401-4dd2-b0a0-a270968c989e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266525669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.1266525669
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1651133030
Short name T1107
Test name
Test status
Simulation time 28338280 ps
CPU time 0.72 seconds
Started Jun 28 04:31:27 PM PDT 24
Finished Jun 28 04:31:28 PM PDT 24
Peak memory 198080 kb
Host smart-aaad62e8-5f81-470b-ae03-b904314dba5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651133030 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1651133030
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.2619493573
Short name T1183
Test name
Test status
Simulation time 38412226 ps
CPU time 0.67 seconds
Started Jun 28 04:31:30 PM PDT 24
Finished Jun 28 04:31:31 PM PDT 24
Peak memory 195592 kb
Host smart-c18477ef-978c-49b8-9940-a535a3e78683
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619493573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2619493573
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.2482163920
Short name T1118
Test name
Test status
Simulation time 16447255 ps
CPU time 0.58 seconds
Started Jun 28 04:31:32 PM PDT 24
Finished Jun 28 04:31:34 PM PDT 24
Peak memory 194588 kb
Host smart-05b495a7-2cc3-4a00-975c-89ed9c852867
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482163920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.2482163920
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3133212717
Short name T1173
Test name
Test status
Simulation time 65279210 ps
CPU time 0.68 seconds
Started Jun 28 04:31:28 PM PDT 24
Finished Jun 28 04:31:29 PM PDT 24
Peak memory 195056 kb
Host smart-fb8af605-eb1d-43e1-a570-3e6fd0062805
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133212717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.3133212717
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.2663244351
Short name T1106
Test name
Test status
Simulation time 85974044 ps
CPU time 1.6 seconds
Started Jun 28 04:31:17 PM PDT 24
Finished Jun 28 04:31:19 PM PDT 24
Peak memory 200280 kb
Host smart-7b90f9d1-e786-4caf-9179-b70e5ab49523
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663244351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.2663244351
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2951802873
Short name T109
Test name
Test status
Simulation time 58626798 ps
CPU time 1.03 seconds
Started Jun 28 04:31:31 PM PDT 24
Finished Jun 28 04:31:33 PM PDT 24
Peak memory 198600 kb
Host smart-df4930d3-7978-4120-8878-b2a35f41902b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951802873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2951802873
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1520138176
Short name T1191
Test name
Test status
Simulation time 19451074 ps
CPU time 0.66 seconds
Started Jun 28 04:31:35 PM PDT 24
Finished Jun 28 04:31:37 PM PDT 24
Peak memory 197436 kb
Host smart-c2ed9fb2-27fa-4daf-9644-31e41ab807fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520138176 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.1520138176
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.3140876305
Short name T1157
Test name
Test status
Simulation time 59512678 ps
CPU time 0.61 seconds
Started Jun 28 04:31:18 PM PDT 24
Finished Jun 28 04:31:19 PM PDT 24
Peak memory 195708 kb
Host smart-96982379-6972-4c2d-a774-900a61911d1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140876305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3140876305
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.3019667054
Short name T1122
Test name
Test status
Simulation time 154340356 ps
CPU time 0.54 seconds
Started Jun 28 04:31:59 PM PDT 24
Finished Jun 28 04:32:00 PM PDT 24
Peak memory 194524 kb
Host smart-21b96a46-3b84-47a9-a1f7-0018f7f6ce1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019667054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3019667054
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.939360306
Short name T72
Test name
Test status
Simulation time 72325395 ps
CPU time 0.78 seconds
Started Jun 28 04:31:23 PM PDT 24
Finished Jun 28 04:31:24 PM PDT 24
Peak memory 197196 kb
Host smart-568c7789-0219-40e0-90d7-7dca6eb8015b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939360306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr
_outstanding.939360306
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.2536003497
Short name T1174
Test name
Test status
Simulation time 131941221 ps
CPU time 1.79 seconds
Started Jun 28 04:31:22 PM PDT 24
Finished Jun 28 04:31:24 PM PDT 24
Peak memory 200244 kb
Host smart-2e8e1f0e-1557-46be-8191-e9dfcba38d2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536003497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2536003497
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3460085096
Short name T81
Test name
Test status
Simulation time 165790567 ps
CPU time 1.36 seconds
Started Jun 28 04:31:56 PM PDT 24
Finished Jun 28 04:31:58 PM PDT 24
Peak memory 199528 kb
Host smart-b393adc7-4aa7-45fa-a546-55658dbd479e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460085096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3460085096
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1008855992
Short name T1198
Test name
Test status
Simulation time 22219134 ps
CPU time 0.68 seconds
Started Jun 28 04:31:27 PM PDT 24
Finished Jun 28 04:31:28 PM PDT 24
Peak memory 198696 kb
Host smart-170f3220-a1d7-4ff2-a6d9-e73b7c34f1f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008855992 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.1008855992
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.4102320346
Short name T56
Test name
Test status
Simulation time 15648984 ps
CPU time 0.57 seconds
Started Jun 28 04:31:27 PM PDT 24
Finished Jun 28 04:31:28 PM PDT 24
Peak memory 195604 kb
Host smart-fb40b954-e447-4d6c-b7d3-86a3a5da1e6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102320346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.4102320346
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.3422720845
Short name T1135
Test name
Test status
Simulation time 53701151 ps
CPU time 0.56 seconds
Started Jun 28 04:31:39 PM PDT 24
Finished Jun 28 04:31:40 PM PDT 24
Peak memory 194524 kb
Host smart-d34358d2-4023-4125-ab9e-1eef9549c9df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422720845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3422720845
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3649692185
Short name T69
Test name
Test status
Simulation time 68000562 ps
CPU time 0.65 seconds
Started Jun 28 04:31:37 PM PDT 24
Finished Jun 28 04:31:39 PM PDT 24
Peak memory 196108 kb
Host smart-d789db6d-dbb8-45d8-9875-373a0bfeacc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649692185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.3649692185
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.320000461
Short name T1210
Test name
Test status
Simulation time 99035732 ps
CPU time 1.39 seconds
Started Jun 28 04:31:31 PM PDT 24
Finished Jun 28 04:31:34 PM PDT 24
Peak memory 199224 kb
Host smart-8cec0850-b3f8-45f6-9207-22014080e7d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320000461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.320000461
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1483472824
Short name T1158
Test name
Test status
Simulation time 178900771 ps
CPU time 1.02 seconds
Started Jun 28 04:31:33 PM PDT 24
Finished Jun 28 04:31:35 PM PDT 24
Peak memory 198044 kb
Host smart-9f879a40-ed92-407a-ab1a-1cbb942547bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483472824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1483472824
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2751029557
Short name T1182
Test name
Test status
Simulation time 98052957 ps
CPU time 0.89 seconds
Started Jun 28 04:31:30 PM PDT 24
Finished Jun 28 04:31:31 PM PDT 24
Peak memory 200240 kb
Host smart-e47406ba-799b-4ad5-abf2-31fe8914ead6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751029557 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.2751029557
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1265116419
Short name T66
Test name
Test status
Simulation time 17278522 ps
CPU time 0.59 seconds
Started Jun 28 04:31:35 PM PDT 24
Finished Jun 28 04:31:36 PM PDT 24
Peak memory 195680 kb
Host smart-1fa388ee-32c7-4716-a9b1-bc8964e47bbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265116419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1265116419
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2528483889
Short name T1142
Test name
Test status
Simulation time 26753407 ps
CPU time 0.6 seconds
Started Jun 28 04:31:30 PM PDT 24
Finished Jun 28 04:31:32 PM PDT 24
Peak memory 194600 kb
Host smart-b9f1720a-681e-481a-9cb2-52a5d1ea0f9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528483889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2528483889
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2082588868
Short name T1161
Test name
Test status
Simulation time 46243076 ps
CPU time 0.7 seconds
Started Jun 28 04:31:41 PM PDT 24
Finished Jun 28 04:31:44 PM PDT 24
Peak memory 196996 kb
Host smart-3f9fb092-c888-402c-b9ec-b87796ef9041
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082588868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.2082588868
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.4116159602
Short name T1223
Test name
Test status
Simulation time 78908196 ps
CPU time 2.01 seconds
Started Jun 28 04:31:44 PM PDT 24
Finished Jun 28 04:31:48 PM PDT 24
Peak memory 200248 kb
Host smart-a2e26964-f60a-4fe6-a6af-b3507d250e97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116159602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.4116159602
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2591779792
Short name T1131
Test name
Test status
Simulation time 32014889 ps
CPU time 0.85 seconds
Started Jun 28 04:31:38 PM PDT 24
Finished Jun 28 04:31:40 PM PDT 24
Peak memory 200012 kb
Host smart-e7d09afd-ce93-4f02-8daf-d8ff0d532f1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591779792 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.2591779792
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.3764367981
Short name T1200
Test name
Test status
Simulation time 14562418 ps
CPU time 0.6 seconds
Started Jun 28 04:31:33 PM PDT 24
Finished Jun 28 04:31:35 PM PDT 24
Peak memory 195608 kb
Host smart-354079ef-1971-4ecd-b195-75f6cedccfb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764367981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3764367981
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.3764077158
Short name T1163
Test name
Test status
Simulation time 25533040 ps
CPU time 0.57 seconds
Started Jun 28 04:31:29 PM PDT 24
Finished Jun 28 04:31:30 PM PDT 24
Peak memory 194520 kb
Host smart-7717c8ee-2021-4f2c-a864-62baf9169086
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764077158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3764077158
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3632549625
Short name T1179
Test name
Test status
Simulation time 41755541 ps
CPU time 0.71 seconds
Started Jun 28 04:31:25 PM PDT 24
Finished Jun 28 04:31:27 PM PDT 24
Peak memory 198008 kb
Host smart-d990e297-4f27-43be-b7b3-c7eb590ffdbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632549625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.3632549625
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.3658909406
Short name T1102
Test name
Test status
Simulation time 392160203 ps
CPU time 2.1 seconds
Started Jun 28 04:31:40 PM PDT 24
Finished Jun 28 04:31:44 PM PDT 24
Peak memory 200652 kb
Host smart-3f5cb1a8-10de-4551-8fdb-f1d2660fb862
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658909406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3658909406
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3310744506
Short name T80
Test name
Test status
Simulation time 52772899 ps
CPU time 0.99 seconds
Started Jun 28 04:31:29 PM PDT 24
Finished Jun 28 04:31:31 PM PDT 24
Peak memory 199164 kb
Host smart-89ea150d-fb5d-4aef-b6c7-95b03662dede
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310744506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3310744506
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.730632686
Short name T1184
Test name
Test status
Simulation time 140712573 ps
CPU time 0.69 seconds
Started Jun 28 04:31:41 PM PDT 24
Finished Jun 28 04:31:43 PM PDT 24
Peak memory 198356 kb
Host smart-01fbbde6-63a7-4c21-af8a-340ae87ba09f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730632686 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.730632686
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.632011562
Short name T1207
Test name
Test status
Simulation time 16292227 ps
CPU time 0.61 seconds
Started Jun 28 04:31:33 PM PDT 24
Finished Jun 28 04:31:35 PM PDT 24
Peak memory 195608 kb
Host smart-b9feed0f-cbf2-472c-852d-e28b9f51e769
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632011562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.632011562
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3475375986
Short name T1108
Test name
Test status
Simulation time 60329354 ps
CPU time 0.62 seconds
Started Jun 28 04:31:36 PM PDT 24
Finished Jun 28 04:31:38 PM PDT 24
Peak memory 194652 kb
Host smart-33f15c53-4b1f-498c-8eeb-3c837320e8da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475375986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3475375986
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2905555899
Short name T68
Test name
Test status
Simulation time 92539338 ps
CPU time 0.79 seconds
Started Jun 28 04:31:42 PM PDT 24
Finished Jun 28 04:31:45 PM PDT 24
Peak memory 197132 kb
Host smart-4b4b822d-5b1f-4456-8282-504e8fba1d09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905555899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2905555899
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2772664854
Short name T1155
Test name
Test status
Simulation time 382849384 ps
CPU time 2.42 seconds
Started Jun 28 04:31:29 PM PDT 24
Finished Jun 28 04:31:32 PM PDT 24
Peak memory 200248 kb
Host smart-46f80e16-ef8f-4ecd-9817-349b9630c445
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772664854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2772664854
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3862543661
Short name T1205
Test name
Test status
Simulation time 65691927 ps
CPU time 1.26 seconds
Started Jun 28 04:31:30 PM PDT 24
Finished Jun 28 04:31:32 PM PDT 24
Peak memory 199372 kb
Host smart-35bfdfde-ad07-4e8c-8769-be627dbc3845
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862543661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3862543661
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1872798197
Short name T1116
Test name
Test status
Simulation time 87411575 ps
CPU time 0.81 seconds
Started Jun 28 04:31:35 PM PDT 24
Finished Jun 28 04:31:38 PM PDT 24
Peak memory 200040 kb
Host smart-70de1d41-e470-4e9a-9b50-51610b425382
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872798197 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1872798197
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1885796281
Short name T1094
Test name
Test status
Simulation time 15944289 ps
CPU time 0.61 seconds
Started Jun 28 04:31:44 PM PDT 24
Finished Jun 28 04:31:46 PM PDT 24
Peak memory 195696 kb
Host smart-da00b133-87e8-4aa1-a96d-ca0628b48589
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885796281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1885796281
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.2148526834
Short name T1168
Test name
Test status
Simulation time 12233640 ps
CPU time 0.62 seconds
Started Jun 28 04:31:23 PM PDT 24
Finished Jun 28 04:31:25 PM PDT 24
Peak memory 194256 kb
Host smart-ff4a1736-235d-4541-b08b-5d2fbbdfc7ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148526834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2148526834
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2561918283
Short name T1199
Test name
Test status
Simulation time 15185508 ps
CPU time 0.63 seconds
Started Jun 28 04:31:30 PM PDT 24
Finished Jun 28 04:31:31 PM PDT 24
Peak memory 196200 kb
Host smart-e144e3a3-b6ea-4ba5-9cc4-7f8a7ad4e1b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561918283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.2561918283
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.605173366
Short name T1165
Test name
Test status
Simulation time 142572365 ps
CPU time 1.92 seconds
Started Jun 28 04:31:44 PM PDT 24
Finished Jun 28 04:31:47 PM PDT 24
Peak memory 200232 kb
Host smart-9d8eeefb-7556-4f68-a704-d6a9ff14c728
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605173366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.605173366
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.4168448069
Short name T108
Test name
Test status
Simulation time 52362681 ps
CPU time 0.98 seconds
Started Jun 28 04:31:37 PM PDT 24
Finished Jun 28 04:31:39 PM PDT 24
Peak memory 199360 kb
Host smart-ab856f31-76d2-4f51-b99b-b14d36fad6fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168448069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.4168448069
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1274467798
Short name T65
Test name
Test status
Simulation time 35994442 ps
CPU time 0.83 seconds
Started Jun 28 04:31:25 PM PDT 24
Finished Jun 28 04:31:26 PM PDT 24
Peak memory 197252 kb
Host smart-dd41e85a-28ad-4d56-a4f8-ad8233ebc0b1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274467798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.1274467798
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1774185550
Short name T1114
Test name
Test status
Simulation time 93654633 ps
CPU time 1.51 seconds
Started Jun 28 04:31:18 PM PDT 24
Finished Jun 28 04:31:20 PM PDT 24
Peak memory 198004 kb
Host smart-360e243c-2af9-4319-af79-a7bf14d77878
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774185550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1774185550
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2593559186
Short name T1098
Test name
Test status
Simulation time 86001635 ps
CPU time 0.64 seconds
Started Jun 28 04:31:14 PM PDT 24
Finished Jun 28 04:31:16 PM PDT 24
Peak memory 194832 kb
Host smart-8a67cfe5-53a2-4c3f-818b-2c3f5e255651
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593559186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2593559186
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1934291461
Short name T1125
Test name
Test status
Simulation time 18121671 ps
CPU time 0.88 seconds
Started Jun 28 04:31:27 PM PDT 24
Finished Jun 28 04:31:28 PM PDT 24
Peak memory 200052 kb
Host smart-cea540e2-9952-4984-ade4-d70b9e21bd73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934291461 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1934291461
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.699762607
Short name T1145
Test name
Test status
Simulation time 66679955 ps
CPU time 0.67 seconds
Started Jun 28 04:31:35 PM PDT 24
Finished Jun 28 04:31:37 PM PDT 24
Peak memory 195840 kb
Host smart-23d9802c-3d9c-4f29-bddf-1529f7ecc6bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699762607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.699762607
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3053520047
Short name T1141
Test name
Test status
Simulation time 32890679 ps
CPU time 0.57 seconds
Started Jun 28 04:31:22 PM PDT 24
Finished Jun 28 04:31:24 PM PDT 24
Peak memory 194596 kb
Host smart-a3dcf71a-6dbc-4e2c-8ee1-59db78d2b1fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053520047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3053520047
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3334559831
Short name T70
Test name
Test status
Simulation time 26692093 ps
CPU time 0.75 seconds
Started Jun 28 04:31:52 PM PDT 24
Finished Jun 28 04:31:54 PM PDT 24
Peak memory 196252 kb
Host smart-0aadd954-fc2d-420a-a17d-82bb627ec651
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334559831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3334559831
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2403469135
Short name T1167
Test name
Test status
Simulation time 189031784 ps
CPU time 1.49 seconds
Started Jun 28 04:31:11 PM PDT 24
Finished Jun 28 04:31:13 PM PDT 24
Peak memory 199456 kb
Host smart-0e565de4-f864-4da4-a115-8ef053a2c21d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403469135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2403469135
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.999199925
Short name T1203
Test name
Test status
Simulation time 131793944 ps
CPU time 1.27 seconds
Started Jun 28 04:31:13 PM PDT 24
Finished Jun 28 04:31:15 PM PDT 24
Peak memory 199520 kb
Host smart-b238686e-cd23-4877-9afb-037555238d52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999199925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.999199925
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.3336105711
Short name T1109
Test name
Test status
Simulation time 16494091 ps
CPU time 0.59 seconds
Started Jun 28 04:31:34 PM PDT 24
Finished Jun 28 04:31:35 PM PDT 24
Peak memory 194596 kb
Host smart-c7962d6a-1530-4089-a571-990a0bd77e99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336105711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3336105711
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.3568673218
Short name T1220
Test name
Test status
Simulation time 23706753 ps
CPU time 0.58 seconds
Started Jun 28 04:31:30 PM PDT 24
Finished Jun 28 04:31:32 PM PDT 24
Peak memory 194640 kb
Host smart-96504de3-1b01-48f6-be7f-8d315b0971cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568673218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3568673218
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2544751747
Short name T1181
Test name
Test status
Simulation time 20743259 ps
CPU time 0.56 seconds
Started Jun 28 04:31:28 PM PDT 24
Finished Jun 28 04:31:29 PM PDT 24
Peak memory 194624 kb
Host smart-272b5ef6-366b-4073-bd69-ed1c2a1c9864
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544751747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2544751747
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2925027781
Short name T1120
Test name
Test status
Simulation time 51123290 ps
CPU time 0.57 seconds
Started Jun 28 04:31:35 PM PDT 24
Finished Jun 28 04:31:37 PM PDT 24
Peak memory 194588 kb
Host smart-6d4c4df8-f651-4198-9af8-c197fc136f3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925027781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2925027781
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.2322730254
Short name T1140
Test name
Test status
Simulation time 15734444 ps
CPU time 0.57 seconds
Started Jun 28 04:31:31 PM PDT 24
Finished Jun 28 04:31:33 PM PDT 24
Peak memory 194524 kb
Host smart-3b6ce79e-3e8d-46ce-823e-8d750519dbc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322730254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2322730254
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.1040331265
Short name T1104
Test name
Test status
Simulation time 38957067 ps
CPU time 0.57 seconds
Started Jun 28 04:31:32 PM PDT 24
Finished Jun 28 04:31:34 PM PDT 24
Peak memory 194660 kb
Host smart-e5cce433-74e5-4a9f-9888-f577863af46b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040331265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1040331265
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.343220406
Short name T1146
Test name
Test status
Simulation time 13013105 ps
CPU time 0.59 seconds
Started Jun 28 04:31:34 PM PDT 24
Finished Jun 28 04:31:35 PM PDT 24
Peak memory 194584 kb
Host smart-01837c40-75a2-4242-abc6-98e26ac839b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343220406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.343220406
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3392661106
Short name T1117
Test name
Test status
Simulation time 17249865 ps
CPU time 0.63 seconds
Started Jun 28 04:31:22 PM PDT 24
Finished Jun 28 04:31:24 PM PDT 24
Peak memory 193812 kb
Host smart-2d3f367a-534c-4f50-a436-df190710f2ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392661106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3392661106
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.398839183
Short name T1148
Test name
Test status
Simulation time 29122194 ps
CPU time 0.56 seconds
Started Jun 28 04:31:18 PM PDT 24
Finished Jun 28 04:31:20 PM PDT 24
Peak memory 194576 kb
Host smart-39bba244-d5ae-45d4-8fab-5ce824858bea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398839183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.398839183
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.457904202
Short name T1139
Test name
Test status
Simulation time 19690124 ps
CPU time 0.56 seconds
Started Jun 28 04:31:42 PM PDT 24
Finished Jun 28 04:31:48 PM PDT 24
Peak memory 194580 kb
Host smart-172e09af-71ef-470f-aaf1-53cdfcaaf81f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457904202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.457904202
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3877120018
Short name T1226
Test name
Test status
Simulation time 57533402 ps
CPU time 0.82 seconds
Started Jun 28 04:31:22 PM PDT 24
Finished Jun 28 04:31:24 PM PDT 24
Peak memory 196540 kb
Host smart-b8e503a3-08cb-4e3d-983d-d2b80f90173b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877120018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3877120018
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.5887069
Short name T61
Test name
Test status
Simulation time 58852226 ps
CPU time 2.37 seconds
Started Jun 28 04:31:18 PM PDT 24
Finished Jun 28 04:31:21 PM PDT 24
Peak memory 197376 kb
Host smart-b0d04354-9110-413b-8373-ae209b2baa5d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5887069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.5887069
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3850337177
Short name T57
Test name
Test status
Simulation time 13643583 ps
CPU time 0.6 seconds
Started Jun 28 04:31:22 PM PDT 24
Finished Jun 28 04:31:24 PM PDT 24
Peak memory 195636 kb
Host smart-80d89503-17a5-4dc6-842a-e366a0c8b11c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850337177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3850337177
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.4153988724
Short name T1100
Test name
Test status
Simulation time 20965078 ps
CPU time 0.76 seconds
Started Jun 28 04:31:19 PM PDT 24
Finished Jun 28 04:31:21 PM PDT 24
Peak memory 197924 kb
Host smart-753bbbc1-d5c6-4df5-a2d2-13cb20ebc091
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153988724 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.4153988724
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.1670459800
Short name T64
Test name
Test status
Simulation time 36334625 ps
CPU time 0.65 seconds
Started Jun 28 04:31:22 PM PDT 24
Finished Jun 28 04:31:24 PM PDT 24
Peak memory 194828 kb
Host smart-deb723b8-3efe-4f5e-99e3-c81a11f5d7c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670459800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.1670459800
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.3985212607
Short name T1129
Test name
Test status
Simulation time 83884880 ps
CPU time 0.63 seconds
Started Jun 28 04:31:20 PM PDT 24
Finished Jun 28 04:31:21 PM PDT 24
Peak memory 193816 kb
Host smart-abffdd4e-b777-402f-b8ef-3b0492a16b34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985212607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3985212607
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1361468035
Short name T71
Test name
Test status
Simulation time 86839505 ps
CPU time 0.67 seconds
Started Jun 28 04:31:21 PM PDT 24
Finished Jun 28 04:31:22 PM PDT 24
Peak memory 195820 kb
Host smart-68bcbe84-f409-483a-8134-09cbf5ee5fe7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361468035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.1361468035
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.3484109477
Short name T1166
Test name
Test status
Simulation time 38463356 ps
CPU time 1.09 seconds
Started Jun 28 04:31:18 PM PDT 24
Finished Jun 28 04:31:20 PM PDT 24
Peak memory 199236 kb
Host smart-fd21c168-4f46-4796-b66d-111a544fb090
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484109477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3484109477
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1828753544
Short name T1190
Test name
Test status
Simulation time 53108205 ps
CPU time 0.95 seconds
Started Jun 28 04:31:26 PM PDT 24
Finished Jun 28 04:31:28 PM PDT 24
Peak memory 199204 kb
Host smart-442c60ca-903d-491f-b763-9038c603c55d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828753544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1828753544
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.1478336824
Short name T1214
Test name
Test status
Simulation time 41252873 ps
CPU time 0.55 seconds
Started Jun 28 04:31:40 PM PDT 24
Finished Jun 28 04:31:42 PM PDT 24
Peak memory 194588 kb
Host smart-8995a0c0-96a5-424a-a750-5105817077d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478336824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1478336824
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3916875497
Short name T1213
Test name
Test status
Simulation time 13306287 ps
CPU time 0.59 seconds
Started Jun 28 04:31:38 PM PDT 24
Finished Jun 28 04:31:40 PM PDT 24
Peak memory 194584 kb
Host smart-418266d7-a754-488a-8160-1791cf661ea3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916875497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3916875497
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.597785778
Short name T1101
Test name
Test status
Simulation time 15328357 ps
CPU time 0.6 seconds
Started Jun 28 04:31:33 PM PDT 24
Finished Jun 28 04:31:35 PM PDT 24
Peak memory 194596 kb
Host smart-a0eb3349-55ea-42b3-bfbc-d11ba6ddcacb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597785778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.597785778
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.1545424312
Short name T1201
Test name
Test status
Simulation time 27809605 ps
CPU time 0.58 seconds
Started Jun 28 04:31:42 PM PDT 24
Finished Jun 28 04:31:45 PM PDT 24
Peak memory 194740 kb
Host smart-f5943860-d87e-4ac0-a292-4e63f41b8fb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545424312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.1545424312
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.1417380126
Short name T1123
Test name
Test status
Simulation time 31179937 ps
CPU time 0.6 seconds
Started Jun 28 04:31:35 PM PDT 24
Finished Jun 28 04:31:37 PM PDT 24
Peak memory 194584 kb
Host smart-f22e36b4-c6a9-4465-8ac8-b77bc712638c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417380126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.1417380126
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.2246414630
Short name T1096
Test name
Test status
Simulation time 16123052 ps
CPU time 0.6 seconds
Started Jun 28 04:31:39 PM PDT 24
Finished Jun 28 04:31:41 PM PDT 24
Peak memory 194584 kb
Host smart-1d6164ce-0393-479c-a9dd-434e1c455072
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246414630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.2246414630
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.1487277291
Short name T1132
Test name
Test status
Simulation time 45393596 ps
CPU time 0.63 seconds
Started Jun 28 04:31:31 PM PDT 24
Finished Jun 28 04:31:33 PM PDT 24
Peak memory 194260 kb
Host smart-e23372b5-b075-4333-abf8-bf4ad4bf3b00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487277291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1487277291
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.3393826193
Short name T1110
Test name
Test status
Simulation time 17302962 ps
CPU time 0.58 seconds
Started Jun 28 04:31:41 PM PDT 24
Finished Jun 28 04:31:43 PM PDT 24
Peak memory 194596 kb
Host smart-4e3b8344-e2d8-4363-8c63-1af890f285ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393826193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.3393826193
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.2600947324
Short name T1113
Test name
Test status
Simulation time 15084677 ps
CPU time 0.61 seconds
Started Jun 28 04:31:27 PM PDT 24
Finished Jun 28 04:31:28 PM PDT 24
Peak memory 194592 kb
Host smart-16163d1c-aee9-42d2-809f-e9ec0eccffec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600947324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2600947324
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.337842354
Short name T1127
Test name
Test status
Simulation time 11297359 ps
CPU time 0.57 seconds
Started Jun 28 04:31:37 PM PDT 24
Finished Jun 28 04:31:39 PM PDT 24
Peak memory 194776 kb
Host smart-5f60d9ce-1e1f-4216-a583-66ae4de515bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337842354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.337842354
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2070960482
Short name T1150
Test name
Test status
Simulation time 46969363 ps
CPU time 0.69 seconds
Started Jun 28 04:31:17 PM PDT 24
Finished Jun 28 04:31:18 PM PDT 24
Peak memory 195608 kb
Host smart-8b102e89-0b29-41d7-b81c-630af4aabb1d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070960482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2070960482
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2618892327
Short name T1103
Test name
Test status
Simulation time 359673353 ps
CPU time 1.62 seconds
Started Jun 28 04:31:13 PM PDT 24
Finished Jun 28 04:31:15 PM PDT 24
Peak memory 196872 kb
Host smart-d08a2a50-168a-4bf5-b756-c6fba3af71bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618892327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.2618892327
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2208185860
Short name T62
Test name
Test status
Simulation time 18348760 ps
CPU time 0.62 seconds
Started Jun 28 04:31:35 PM PDT 24
Finished Jun 28 04:31:36 PM PDT 24
Peak memory 195404 kb
Host smart-e372044a-d250-4e32-9404-4eca458e024e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208185860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2208185860
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.4027753010
Short name T1227
Test name
Test status
Simulation time 63392356 ps
CPU time 0.73 seconds
Started Jun 28 04:31:28 PM PDT 24
Finished Jun 28 04:31:31 PM PDT 24
Peak memory 196452 kb
Host smart-4a5c7cbf-8d79-48af-8e79-684eb8ab1873
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027753010 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.4027753010
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.3106197519
Short name T1124
Test name
Test status
Simulation time 51961806 ps
CPU time 0.62 seconds
Started Jun 28 04:31:13 PM PDT 24
Finished Jun 28 04:31:14 PM PDT 24
Peak memory 195872 kb
Host smart-59c33a65-2ea1-4233-ad10-9160e476db1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106197519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3106197519
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.2991141680
Short name T1130
Test name
Test status
Simulation time 14065066 ps
CPU time 0.65 seconds
Started Jun 28 04:31:26 PM PDT 24
Finished Jun 28 04:31:28 PM PDT 24
Peak memory 193820 kb
Host smart-b6f7a676-376e-4d58-9196-6594bfba75ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991141680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2991141680
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2936846109
Short name T1189
Test name
Test status
Simulation time 67499353 ps
CPU time 0.65 seconds
Started Jun 28 04:31:41 PM PDT 24
Finished Jun 28 04:31:43 PM PDT 24
Peak memory 195056 kb
Host smart-262cd6cb-f3e0-4d54-8dd4-f00763581059
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936846109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.2936846109
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.585710189
Short name T1144
Test name
Test status
Simulation time 53490582 ps
CPU time 1.34 seconds
Started Jun 28 04:31:26 PM PDT 24
Finished Jun 28 04:31:28 PM PDT 24
Peak memory 200160 kb
Host smart-1acbefab-66ce-45d1-a993-8d0aa8bcae8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585710189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.585710189
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2114068151
Short name T78
Test name
Test status
Simulation time 117218587 ps
CPU time 1.32 seconds
Started Jun 28 04:31:15 PM PDT 24
Finished Jun 28 04:31:17 PM PDT 24
Peak memory 199688 kb
Host smart-bf662d24-c4e8-4f93-889b-80dd8b2a05b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114068151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2114068151
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.2322471880
Short name T1178
Test name
Test status
Simulation time 14273453 ps
CPU time 0.55 seconds
Started Jun 28 04:31:33 PM PDT 24
Finished Jun 28 04:31:35 PM PDT 24
Peak memory 194372 kb
Host smart-f47efdf6-7adc-419b-b0c4-6009618b48c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322471880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2322471880
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.312522933
Short name T1202
Test name
Test status
Simulation time 13570143 ps
CPU time 0.61 seconds
Started Jun 28 04:31:39 PM PDT 24
Finished Jun 28 04:31:41 PM PDT 24
Peak memory 194640 kb
Host smart-dc1d6e0c-2a42-43fa-bff5-e142d16b6b9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312522933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.312522933
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.4148077665
Short name T1126
Test name
Test status
Simulation time 29233987 ps
CPU time 0.58 seconds
Started Jun 28 04:31:27 PM PDT 24
Finished Jun 28 04:31:29 PM PDT 24
Peak memory 194388 kb
Host smart-456d0b8f-ff4a-4d5b-a718-ee1b522609cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148077665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.4148077665
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.1334603725
Short name T1175
Test name
Test status
Simulation time 11719850 ps
CPU time 0.6 seconds
Started Jun 28 04:31:31 PM PDT 24
Finished Jun 28 04:31:32 PM PDT 24
Peak memory 194892 kb
Host smart-07477118-78a0-486b-a9d9-53868d029f25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334603725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1334603725
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3858934441
Short name T1193
Test name
Test status
Simulation time 19261219 ps
CPU time 0.61 seconds
Started Jun 28 04:31:30 PM PDT 24
Finished Jun 28 04:31:32 PM PDT 24
Peak memory 194600 kb
Host smart-409a1dd6-679f-4400-9d37-b5ee296a9aa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858934441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3858934441
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3668017418
Short name T1105
Test name
Test status
Simulation time 13422335 ps
CPU time 0.61 seconds
Started Jun 28 04:31:28 PM PDT 24
Finished Jun 28 04:31:29 PM PDT 24
Peak memory 194596 kb
Host smart-41203cc9-9b49-4616-be28-e3c94b1dc2ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668017418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3668017418
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.1132456961
Short name T1194
Test name
Test status
Simulation time 38503812 ps
CPU time 0.59 seconds
Started Jun 28 04:31:29 PM PDT 24
Finished Jun 28 04:31:31 PM PDT 24
Peak memory 193564 kb
Host smart-9df2b117-c0e9-4f4b-928e-06029fcb7d4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132456961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1132456961
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.939757203
Short name T1128
Test name
Test status
Simulation time 33255998 ps
CPU time 0.57 seconds
Started Jun 28 04:31:41 PM PDT 24
Finished Jun 28 04:31:44 PM PDT 24
Peak memory 194592 kb
Host smart-1eb2fc98-0d8a-4b39-9426-00ee64734dde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939757203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.939757203
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.209717107
Short name T1153
Test name
Test status
Simulation time 42905068 ps
CPU time 0.7 seconds
Started Jun 28 04:31:30 PM PDT 24
Finished Jun 28 04:31:32 PM PDT 24
Peak memory 193820 kb
Host smart-5b70af0e-a224-4b30-9b70-68021763715f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209717107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.209717107
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.2660229346
Short name T1204
Test name
Test status
Simulation time 60516251 ps
CPU time 0.6 seconds
Started Jun 28 04:31:22 PM PDT 24
Finished Jun 28 04:31:24 PM PDT 24
Peak memory 193820 kb
Host smart-2c674c7d-b275-4673-8a50-4fd78f52f2d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660229346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2660229346
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.4134900162
Short name T1152
Test name
Test status
Simulation time 40906122 ps
CPU time 0.65 seconds
Started Jun 28 04:31:45 PM PDT 24
Finished Jun 28 04:31:49 PM PDT 24
Peak memory 197448 kb
Host smart-21162008-7b15-4b82-8607-6566ca6c3029
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134900162 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.4134900162
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.675947844
Short name T1222
Test name
Test status
Simulation time 19991712 ps
CPU time 0.61 seconds
Started Jun 28 04:31:09 PM PDT 24
Finished Jun 28 04:31:10 PM PDT 24
Peak memory 195708 kb
Host smart-f018d1bb-ad3c-436b-a650-5891faf37fe7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675947844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.675947844
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3047558938
Short name T1143
Test name
Test status
Simulation time 66287993 ps
CPU time 0.56 seconds
Started Jun 28 04:31:18 PM PDT 24
Finished Jun 28 04:31:19 PM PDT 24
Peak memory 194584 kb
Host smart-7c418e65-0ae9-474b-b5d2-e4fbb083eeb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047558938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3047558938
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.532300274
Short name T1177
Test name
Test status
Simulation time 43458570 ps
CPU time 0.74 seconds
Started Jun 28 04:31:58 PM PDT 24
Finished Jun 28 04:32:00 PM PDT 24
Peak memory 197400 kb
Host smart-cef7b0f1-e1ac-452f-8fa2-78a454bc5dc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532300274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_
outstanding.532300274
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.1260741570
Short name T1134
Test name
Test status
Simulation time 124351998 ps
CPU time 1.72 seconds
Started Jun 28 04:31:15 PM PDT 24
Finished Jun 28 04:31:17 PM PDT 24
Peak memory 199456 kb
Host smart-dae14a0f-d65f-49d8-b4de-406db682b157
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260741570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1260741570
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1084763655
Short name T1188
Test name
Test status
Simulation time 283803480 ps
CPU time 1.38 seconds
Started Jun 28 04:31:15 PM PDT 24
Finished Jun 28 04:31:17 PM PDT 24
Peak memory 199392 kb
Host smart-0f04b1ff-8f64-4dc6-8e63-ba9a2c0246f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084763655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1084763655
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1279349519
Short name T1119
Test name
Test status
Simulation time 39110917 ps
CPU time 0.69 seconds
Started Jun 28 04:31:22 PM PDT 24
Finished Jun 28 04:31:24 PM PDT 24
Peak memory 197776 kb
Host smart-2cc64737-7e3f-40a9-afc8-8db593e547b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279349519 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1279349519
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.2198586727
Short name T1164
Test name
Test status
Simulation time 42943483 ps
CPU time 0.58 seconds
Started Jun 28 04:31:15 PM PDT 24
Finished Jun 28 04:31:16 PM PDT 24
Peak memory 194560 kb
Host smart-99e8bf7a-b7db-4386-ab71-0659b57aafe4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198586727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2198586727
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1798696875
Short name T1187
Test name
Test status
Simulation time 23269658 ps
CPU time 0.66 seconds
Started Jun 28 04:31:26 PM PDT 24
Finished Jun 28 04:31:27 PM PDT 24
Peak memory 195952 kb
Host smart-a1b52e22-5f56-4c0d-865c-f09c6eba9bf8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798696875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.1798696875
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.838761011
Short name T1112
Test name
Test status
Simulation time 1938732225 ps
CPU time 2.59 seconds
Started Jun 28 04:31:17 PM PDT 24
Finished Jun 28 04:31:20 PM PDT 24
Peak memory 200244 kb
Host smart-418e7655-b9ae-49b8-824f-10d0ba7de632
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838761011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.838761011
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2997359363
Short name T1097
Test name
Test status
Simulation time 18990400 ps
CPU time 0.94 seconds
Started Jun 28 04:31:17 PM PDT 24
Finished Jun 28 04:31:19 PM PDT 24
Peak memory 199996 kb
Host smart-6906eec4-94b6-4092-bcd8-1ab7ea341b26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997359363 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2997359363
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.163223294
Short name T1159
Test name
Test status
Simulation time 14803232 ps
CPU time 0.61 seconds
Started Jun 28 04:31:20 PM PDT 24
Finished Jun 28 04:31:22 PM PDT 24
Peak memory 195644 kb
Host smart-3c8a7985-fae2-4df5-80d5-1d3f2c5b1f5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163223294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.163223294
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1205370158
Short name T1095
Test name
Test status
Simulation time 35492960 ps
CPU time 0.55 seconds
Started Jun 28 04:31:21 PM PDT 24
Finished Jun 28 04:31:22 PM PDT 24
Peak memory 194796 kb
Host smart-569f62ca-8874-49c3-8fa2-e9dac8249ffa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205370158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1205370158
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1182451084
Short name T67
Test name
Test status
Simulation time 67784416 ps
CPU time 0.85 seconds
Started Jun 28 04:31:23 PM PDT 24
Finished Jun 28 04:31:25 PM PDT 24
Peak memory 197216 kb
Host smart-c13ab8b9-f439-4ef6-b61c-a82a60891a5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182451084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1182451084
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2921707211
Short name T1218
Test name
Test status
Simulation time 111706706 ps
CPU time 2.18 seconds
Started Jun 28 04:31:19 PM PDT 24
Finished Jun 28 04:31:22 PM PDT 24
Peak memory 200220 kb
Host smart-332032d1-3a2c-4117-8d19-8033acd58807
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921707211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2921707211
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1469244967
Short name T1180
Test name
Test status
Simulation time 85121718 ps
CPU time 0.95 seconds
Started Jun 28 04:31:20 PM PDT 24
Finished Jun 28 04:31:22 PM PDT 24
Peak memory 199196 kb
Host smart-30015cc9-c2d5-4b3d-a5ba-ae4917e1ab0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469244967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1469244967
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1098863997
Short name T1176
Test name
Test status
Simulation time 12657925 ps
CPU time 0.67 seconds
Started Jun 28 04:31:44 PM PDT 24
Finished Jun 28 04:31:46 PM PDT 24
Peak memory 198080 kb
Host smart-b04a2e47-a32a-49cd-acb4-6dbf606c5d5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098863997 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1098863997
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.1156869520
Short name T1208
Test name
Test status
Simulation time 181265485 ps
CPU time 0.58 seconds
Started Jun 28 04:31:18 PM PDT 24
Finished Jun 28 04:31:19 PM PDT 24
Peak memory 195620 kb
Host smart-31d0f3be-397d-481f-9c1c-1ca10d9aebd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156869520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1156869520
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.3716917646
Short name T1136
Test name
Test status
Simulation time 26797570 ps
CPU time 0.62 seconds
Started Jun 28 04:31:19 PM PDT 24
Finished Jun 28 04:31:21 PM PDT 24
Peak memory 193744 kb
Host smart-1804c388-961a-4145-ade0-076dbd5fd3b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716917646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.3716917646
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.176618428
Short name T1209
Test name
Test status
Simulation time 62074792 ps
CPU time 0.83 seconds
Started Jun 28 04:31:19 PM PDT 24
Finished Jun 28 04:31:21 PM PDT 24
Peak memory 196288 kb
Host smart-ca97690c-844d-4adf-96bf-f41ba95688e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176618428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_
outstanding.176618428
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.1563114115
Short name T1195
Test name
Test status
Simulation time 72856899 ps
CPU time 1.59 seconds
Started Jun 28 04:31:30 PM PDT 24
Finished Jun 28 04:31:32 PM PDT 24
Peak memory 200220 kb
Host smart-c7931147-bb28-434f-a9bb-8a8a4df9afef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563114115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1563114115
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2130688341
Short name T82
Test name
Test status
Simulation time 170297514 ps
CPU time 0.97 seconds
Started Jun 28 04:31:29 PM PDT 24
Finished Jun 28 04:31:30 PM PDT 24
Peak memory 199276 kb
Host smart-d332ca5d-aab6-4a6d-a3d7-67dc07611dce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130688341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2130688341
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3275497558
Short name T1225
Test name
Test status
Simulation time 66520223 ps
CPU time 0.75 seconds
Started Jun 28 04:31:15 PM PDT 24
Finished Jun 28 04:31:16 PM PDT 24
Peak memory 198604 kb
Host smart-d1035ce1-888c-4342-bcce-1dda8465ff9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275497558 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3275497558
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.1887399904
Short name T1186
Test name
Test status
Simulation time 12328498 ps
CPU time 0.63 seconds
Started Jun 28 04:31:13 PM PDT 24
Finished Jun 28 04:31:14 PM PDT 24
Peak memory 194828 kb
Host smart-e7ad8c28-5c71-4eea-a4da-9c736ee16a66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887399904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1887399904
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1026372228
Short name T1156
Test name
Test status
Simulation time 17550988 ps
CPU time 0.57 seconds
Started Jun 28 04:31:43 PM PDT 24
Finished Jun 28 04:31:45 PM PDT 24
Peak memory 194592 kb
Host smart-8a949b2b-4cdc-4cb8-b421-d5f0c087aa14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026372228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1026372228
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.751178046
Short name T1211
Test name
Test status
Simulation time 15981606 ps
CPU time 0.65 seconds
Started Jun 28 04:31:25 PM PDT 24
Finished Jun 28 04:31:26 PM PDT 24
Peak memory 195040 kb
Host smart-cf827238-8972-4fb6-8301-8f0cedb63c83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751178046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_
outstanding.751178046
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.2872525677
Short name T1169
Test name
Test status
Simulation time 285791137 ps
CPU time 1.52 seconds
Started Jun 28 04:31:18 PM PDT 24
Finished Jun 28 04:31:20 PM PDT 24
Peak memory 200184 kb
Host smart-406d6cba-adc0-456a-9251-4b0135ae5a9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872525677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2872525677
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3487402597
Short name T1219
Test name
Test status
Simulation time 204930516 ps
CPU time 1.34 seconds
Started Jun 28 04:31:12 PM PDT 24
Finished Jun 28 04:31:14 PM PDT 24
Peak memory 198840 kb
Host smart-940f6f2a-800f-41e3-a81c-bb25305c1db1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487402597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3487402597
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2330876225
Short name T417
Test name
Test status
Simulation time 11143459 ps
CPU time 0.56 seconds
Started Jun 28 04:36:27 PM PDT 24
Finished Jun 28 04:36:29 PM PDT 24
Peak memory 195424 kb
Host smart-a10c5653-78b0-4d34-85f9-ff441451cc36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330876225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2330876225
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.484272050
Short name T1003
Test name
Test status
Simulation time 11642468374 ps
CPU time 13.45 seconds
Started Jun 28 04:36:26 PM PDT 24
Finished Jun 28 04:36:40 PM PDT 24
Peak memory 199852 kb
Host smart-296ce392-aaa0-4714-bdbe-b700f0a54e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484272050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.484272050
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.2035366261
Short name T495
Test name
Test status
Simulation time 110179960591 ps
CPU time 46.14 seconds
Started Jun 28 04:36:28 PM PDT 24
Finished Jun 28 04:37:15 PM PDT 24
Peak memory 199684 kb
Host smart-ace1fda0-676a-4466-bf2f-8bdbea9e35a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035366261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.2035366261
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_intr.201589629
Short name T498
Test name
Test status
Simulation time 42741132866 ps
CPU time 24.77 seconds
Started Jun 28 04:36:26 PM PDT 24
Finished Jun 28 04:36:51 PM PDT 24
Peak memory 195808 kb
Host smart-940e6ba9-51f7-4394-996d-3a62dfbfdc83
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201589629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.201589629
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.3873415195
Short name T370
Test name
Test status
Simulation time 52196525246 ps
CPU time 84.05 seconds
Started Jun 28 04:36:29 PM PDT 24
Finished Jun 28 04:37:54 PM PDT 24
Peak memory 199892 kb
Host smart-baffdf0e-914a-4eff-bc23-b13f9385082c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3873415195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.3873415195
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2081208301
Short name T306
Test name
Test status
Simulation time 5566214934 ps
CPU time 3.82 seconds
Started Jun 28 04:36:32 PM PDT 24
Finished Jun 28 04:36:38 PM PDT 24
Peak memory 198760 kb
Host smart-85527ebb-2e13-46e7-a5a2-96638e7ceea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081208301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2081208301
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_perf.1318593320
Short name T821
Test name
Test status
Simulation time 27678107621 ps
CPU time 1194.08 seconds
Started Jun 28 04:36:32 PM PDT 24
Finished Jun 28 04:56:28 PM PDT 24
Peak memory 199824 kb
Host smart-e9837f24-3f2f-47f5-b1fd-97c3a0a43739
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1318593320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1318593320
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.1331267350
Short name T1084
Test name
Test status
Simulation time 7040803598 ps
CPU time 9.9 seconds
Started Jun 28 04:36:27 PM PDT 24
Finished Jun 28 04:36:37 PM PDT 24
Peak memory 197768 kb
Host smart-639ea2d9-09de-430d-b2b4-6540f15062da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1331267350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.1331267350
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2349697370
Short name T118
Test name
Test status
Simulation time 260093417712 ps
CPU time 65.53 seconds
Started Jun 28 04:36:29 PM PDT 24
Finished Jun 28 04:37:35 PM PDT 24
Peak memory 199828 kb
Host smart-b7f34727-c14c-4547-97b3-14e863af7317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349697370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2349697370
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.1037566213
Short name T4
Test name
Test status
Simulation time 4954050048 ps
CPU time 2.47 seconds
Started Jun 28 04:36:26 PM PDT 24
Finished Jun 28 04:36:29 PM PDT 24
Peak memory 195972 kb
Host smart-6eec7b73-7b3c-40f5-a5fb-8e21d73cd7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037566213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1037566213
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.1880613347
Short name T342
Test name
Test status
Simulation time 488094236 ps
CPU time 2.15 seconds
Started Jun 28 04:36:27 PM PDT 24
Finished Jun 28 04:36:30 PM PDT 24
Peak memory 199552 kb
Host smart-91db01d0-cfc8-4bf4-879f-143c0d946b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880613347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1880613347
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.826242308
Short name T1009
Test name
Test status
Simulation time 1877867145 ps
CPU time 2.17 seconds
Started Jun 28 04:36:31 PM PDT 24
Finished Jun 28 04:36:34 PM PDT 24
Peak memory 199100 kb
Host smart-402e2096-6c9c-483c-a769-c689043b811c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826242308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.826242308
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.1083201365
Short name T591
Test name
Test status
Simulation time 54763565449 ps
CPU time 100.22 seconds
Started Jun 28 04:36:31 PM PDT 24
Finished Jun 28 04:38:13 PM PDT 24
Peak memory 199852 kb
Host smart-18fc2e63-cde4-4bb5-8b71-3859770969ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083201365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1083201365
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.2480788845
Short name T630
Test name
Test status
Simulation time 10810319 ps
CPU time 0.55 seconds
Started Jun 28 04:36:27 PM PDT 24
Finished Jun 28 04:36:28 PM PDT 24
Peak memory 194120 kb
Host smart-a8434278-2fdc-4279-84fb-dcdad99f74db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480788845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.2480788845
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.2663222720
Short name T473
Test name
Test status
Simulation time 191470239308 ps
CPU time 251.32 seconds
Started Jun 28 04:36:30 PM PDT 24
Finished Jun 28 04:40:43 PM PDT 24
Peak memory 199856 kb
Host smart-88215605-0a13-40a4-9049-140a595f95bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663222720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.2663222720
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.238209567
Short name T900
Test name
Test status
Simulation time 75397392445 ps
CPU time 17.56 seconds
Started Jun 28 04:36:28 PM PDT 24
Finished Jun 28 04:36:47 PM PDT 24
Peak memory 199800 kb
Host smart-2a4422db-190a-4607-833b-69cb266cda5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238209567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.238209567
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2786213588
Short name T121
Test name
Test status
Simulation time 78622339721 ps
CPU time 126.9 seconds
Started Jun 28 04:36:27 PM PDT 24
Finished Jun 28 04:38:34 PM PDT 24
Peak memory 199928 kb
Host smart-955b0a36-79a0-488e-b419-a076068a77ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786213588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2786213588
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.776858959
Short name T537
Test name
Test status
Simulation time 62302910008 ps
CPU time 50.06 seconds
Started Jun 28 04:36:34 PM PDT 24
Finished Jun 28 04:37:25 PM PDT 24
Peak memory 198964 kb
Host smart-a45e8010-c6bb-4780-8eaf-d676ee20ee80
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776858959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.776858959
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.830392840
Short name T628
Test name
Test status
Simulation time 89661263134 ps
CPU time 435.19 seconds
Started Jun 28 04:36:29 PM PDT 24
Finished Jun 28 04:43:45 PM PDT 24
Peak memory 199916 kb
Host smart-21720566-0776-470b-8119-66077061c0b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=830392840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.830392840
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.3424935692
Short name T486
Test name
Test status
Simulation time 8108039097 ps
CPU time 6.25 seconds
Started Jun 28 04:36:31 PM PDT 24
Finished Jun 28 04:36:39 PM PDT 24
Peak memory 199836 kb
Host smart-7ef33e1f-9152-4b16-aa04-af3104f63c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424935692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3424935692
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.1252829388
Short name T670
Test name
Test status
Simulation time 1910761087 ps
CPU time 2.72 seconds
Started Jun 28 04:36:29 PM PDT 24
Finished Jun 28 04:36:33 PM PDT 24
Peak memory 198004 kb
Host smart-2cb9e43d-bd8d-441b-adf3-3047a291e952
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1252829388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.1252829388
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.1278236890
Short name T93
Test name
Test status
Simulation time 87270731423 ps
CPU time 504.85 seconds
Started Jun 28 04:36:29 PM PDT 24
Finished Jun 28 04:44:54 PM PDT 24
Peak memory 199848 kb
Host smart-24ebab7e-bea3-44dc-bb9e-215fa7fac731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278236890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.1278236890
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.3551385093
Short name T399
Test name
Test status
Simulation time 4583072230 ps
CPU time 4.5 seconds
Started Jun 28 04:36:32 PM PDT 24
Finished Jun 28 04:36:38 PM PDT 24
Peak memory 195976 kb
Host smart-89984bd5-8864-4f1d-a1c8-51e2bef66240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551385093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.3551385093
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.1501800984
Short name T24
Test name
Test status
Simulation time 382361578 ps
CPU time 0.89 seconds
Started Jun 28 04:36:32 PM PDT 24
Finished Jun 28 04:36:34 PM PDT 24
Peak memory 218140 kb
Host smart-092ab6f9-97c8-49cb-b9d5-6ab5e42b7eb0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501800984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1501800984
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.2207456956
Short name T874
Test name
Test status
Simulation time 106980459 ps
CPU time 0.92 seconds
Started Jun 28 04:37:04 PM PDT 24
Finished Jun 28 04:37:06 PM PDT 24
Peak memory 199192 kb
Host smart-83a76543-e7bb-4630-a5c3-ba7086a47970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207456956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2207456956
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.1437826317
Short name T723
Test name
Test status
Simulation time 72048863323 ps
CPU time 339.92 seconds
Started Jun 28 04:36:30 PM PDT 24
Finished Jun 28 04:42:12 PM PDT 24
Peak memory 199852 kb
Host smart-eef97dbe-5179-4f13-8e6f-9c9caa131d66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437826317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1437826317
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.340996640
Short name T279
Test name
Test status
Simulation time 42875936769 ps
CPU time 259.12 seconds
Started Jun 28 04:36:28 PM PDT 24
Finished Jun 28 04:40:48 PM PDT 24
Peak memory 215636 kb
Host smart-6d1adc2c-dbab-4a95-b33f-b8646a5a0b4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340996640 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.340996640
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.864988502
Short name T672
Test name
Test status
Simulation time 7851769730 ps
CPU time 11.08 seconds
Started Jun 28 04:37:07 PM PDT 24
Finished Jun 28 04:37:18 PM PDT 24
Peak memory 199836 kb
Host smart-ad7abe3a-0820-4428-87ac-41c680375d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864988502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.864988502
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.1597263189
Short name T536
Test name
Test status
Simulation time 112579451868 ps
CPU time 95.69 seconds
Started Jun 28 04:37:04 PM PDT 24
Finished Jun 28 04:38:40 PM PDT 24
Peak memory 199804 kb
Host smart-092890cb-0912-42ea-9148-b96dcd422c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597263189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1597263189
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_fifo_full.3844474161
Short name T766
Test name
Test status
Simulation time 150154109773 ps
CPU time 375.19 seconds
Started Jun 28 04:37:11 PM PDT 24
Finished Jun 28 04:43:28 PM PDT 24
Peak memory 199852 kb
Host smart-57c327b2-6a02-4390-b6a2-1262d0485748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844474161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.3844474161
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.3823046495
Short name T611
Test name
Test status
Simulation time 31325097694 ps
CPU time 45.82 seconds
Started Jun 28 04:37:13 PM PDT 24
Finished Jun 28 04:38:00 PM PDT 24
Peak memory 199840 kb
Host smart-45a3522c-f5a6-4d6d-80e4-36c4bd2141ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823046495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3823046495
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.3349576149
Short name T199
Test name
Test status
Simulation time 42185326723 ps
CPU time 41.21 seconds
Started Jun 28 04:37:13 PM PDT 24
Finished Jun 28 04:37:55 PM PDT 24
Peak memory 199768 kb
Host smart-eeafabc4-aac6-4d55-bc3d-91fd8db76e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349576149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3349576149
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.2816689250
Short name T597
Test name
Test status
Simulation time 40569847924 ps
CPU time 17.63 seconds
Started Jun 28 04:37:11 PM PDT 24
Finished Jun 28 04:37:30 PM PDT 24
Peak memory 199828 kb
Host smart-83947129-4dc6-4852-9625-1ead4413b895
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816689250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2816689250
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.3691388690
Short name T752
Test name
Test status
Simulation time 119963101507 ps
CPU time 162.41 seconds
Started Jun 28 04:37:12 PM PDT 24
Finished Jun 28 04:39:56 PM PDT 24
Peak memory 199816 kb
Host smart-0cccf061-93e1-4df0-9242-737159d2bb37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3691388690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3691388690
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.1275157162
Short name T598
Test name
Test status
Simulation time 4956926972 ps
CPU time 20.73 seconds
Started Jun 28 04:37:13 PM PDT 24
Finished Jun 28 04:37:35 PM PDT 24
Peak memory 199712 kb
Host smart-d969e25b-ebac-49f1-8786-0219c1340045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275157162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.1275157162
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.3813817430
Short name T992
Test name
Test status
Simulation time 6350362706 ps
CPU time 3.29 seconds
Started Jun 28 04:37:11 PM PDT 24
Finished Jun 28 04:37:15 PM PDT 24
Peak memory 199612 kb
Host smart-c570ab96-614a-445c-acab-17d64b17458f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813817430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.3813817430
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.3414212035
Short name T250
Test name
Test status
Simulation time 3047419843 ps
CPU time 41.15 seconds
Started Jun 28 04:37:15 PM PDT 24
Finished Jun 28 04:37:57 PM PDT 24
Peak memory 199808 kb
Host smart-9661734b-9f82-41aa-9c31-b21af138266f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3414212035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.3414212035
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.1809671532
Short name T416
Test name
Test status
Simulation time 5410890728 ps
CPU time 44.41 seconds
Started Jun 28 04:37:15 PM PDT 24
Finished Jun 28 04:38:00 PM PDT 24
Peak memory 199744 kb
Host smart-0c107309-23d8-49b9-83dc-97b80d7f8552
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1809671532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.1809671532
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.3130872945
Short name T607
Test name
Test status
Simulation time 121297706108 ps
CPU time 184.68 seconds
Started Jun 28 04:37:11 PM PDT 24
Finished Jun 28 04:40:17 PM PDT 24
Peak memory 199264 kb
Host smart-6e706ecc-94e7-4305-9979-c9f63eee0c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130872945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3130872945
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.1970333838
Short name T717
Test name
Test status
Simulation time 3009784272 ps
CPU time 3.22 seconds
Started Jun 28 04:37:10 PM PDT 24
Finished Jun 28 04:37:14 PM PDT 24
Peak memory 196260 kb
Host smart-8fbd054a-0b12-48c7-8080-43487a20ee5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970333838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1970333838
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.545983190
Short name T95
Test name
Test status
Simulation time 103874458 ps
CPU time 1.03 seconds
Started Jun 28 04:37:14 PM PDT 24
Finished Jun 28 04:37:16 PM PDT 24
Peak memory 198052 kb
Host smart-08228baa-5f9a-4d32-a06a-94c8ab209a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545983190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.545983190
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.727803016
Short name T796
Test name
Test status
Simulation time 207588973343 ps
CPU time 233.64 seconds
Started Jun 28 04:37:11 PM PDT 24
Finished Jun 28 04:41:05 PM PDT 24
Peak memory 199824 kb
Host smart-3e3d662c-d44f-40aa-82ad-da486eda0c73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727803016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.727803016
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.1918910685
Short name T451
Test name
Test status
Simulation time 6446936779 ps
CPU time 15.5 seconds
Started Jun 28 04:37:16 PM PDT 24
Finished Jun 28 04:37:32 PM PDT 24
Peak memory 199628 kb
Host smart-0d6efb4c-5e13-481b-bb26-33d48f0c329a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918910685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1918910685
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3893320100
Short name T45
Test name
Test status
Simulation time 31470725121 ps
CPU time 13.17 seconds
Started Jun 28 04:37:13 PM PDT 24
Finished Jun 28 04:37:27 PM PDT 24
Peak memory 199760 kb
Host smart-f43c8b77-0028-4e81-833c-8d8a9a1ee840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893320100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3893320100
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.25454464
Short name T191
Test name
Test status
Simulation time 7014244689 ps
CPU time 10.31 seconds
Started Jun 28 04:41:12 PM PDT 24
Finished Jun 28 04:41:23 PM PDT 24
Peak memory 199624 kb
Host smart-42bca764-2a8c-48e0-b52e-7d0f81d499a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25454464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.25454464
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.2042800097
Short name T425
Test name
Test status
Simulation time 126979420706 ps
CPU time 189.67 seconds
Started Jun 28 04:41:09 PM PDT 24
Finished Jun 28 04:44:20 PM PDT 24
Peak memory 199816 kb
Host smart-fcb33037-4a64-4aa0-bbee-b9eb51b3002e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042800097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2042800097
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.4225108444
Short name T862
Test name
Test status
Simulation time 117150235344 ps
CPU time 45.28 seconds
Started Jun 28 04:41:08 PM PDT 24
Finished Jun 28 04:41:54 PM PDT 24
Peak memory 199720 kb
Host smart-d2d60ab0-9a88-4b42-8a5e-39eadcf984fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225108444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.4225108444
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.2520430197
Short name T738
Test name
Test status
Simulation time 144359680555 ps
CPU time 13.38 seconds
Started Jun 28 04:41:12 PM PDT 24
Finished Jun 28 04:41:26 PM PDT 24
Peak memory 199544 kb
Host smart-3b9df017-8350-4e25-81ec-93423a6e840a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520430197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.2520430197
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.636156375
Short name T1010
Test name
Test status
Simulation time 119981970773 ps
CPU time 29.98 seconds
Started Jun 28 04:41:12 PM PDT 24
Finished Jun 28 04:41:43 PM PDT 24
Peak memory 199492 kb
Host smart-7c9efc3c-9365-433a-9473-19ae6891244b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636156375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.636156375
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.2463877373
Short name T182
Test name
Test status
Simulation time 54862893129 ps
CPU time 63.66 seconds
Started Jun 28 04:41:10 PM PDT 24
Finished Jun 28 04:42:15 PM PDT 24
Peak memory 199904 kb
Host smart-a3375a98-3ede-4c20-8bd4-ab85793dd3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463877373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.2463877373
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.2134111800
Short name T924
Test name
Test status
Simulation time 81715778113 ps
CPU time 108.9 seconds
Started Jun 28 04:41:13 PM PDT 24
Finished Jun 28 04:43:02 PM PDT 24
Peak memory 199856 kb
Host smart-99799439-f11a-4d3b-85f0-16e68a6253b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134111800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2134111800
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.505775569
Short name T514
Test name
Test status
Simulation time 102085735223 ps
CPU time 62.49 seconds
Started Jun 28 04:41:09 PM PDT 24
Finished Jun 28 04:42:13 PM PDT 24
Peak memory 199916 kb
Host smart-5eddcde8-5d0d-499d-a679-7c49ef9f589f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505775569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.505775569
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.152440384
Short name T907
Test name
Test status
Simulation time 112269280 ps
CPU time 0.56 seconds
Started Jun 28 04:37:26 PM PDT 24
Finished Jun 28 04:37:27 PM PDT 24
Peak memory 195512 kb
Host smart-39a0e180-df49-4521-bf9b-d656dc2292ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152440384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.152440384
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.1442174829
Short name T947
Test name
Test status
Simulation time 109550471311 ps
CPU time 42.62 seconds
Started Jun 28 04:37:14 PM PDT 24
Finished Jun 28 04:37:58 PM PDT 24
Peak memory 199880 kb
Host smart-51805202-1774-48d2-9783-821ff86e9f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442174829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.1442174829
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.2259128106
Short name T808
Test name
Test status
Simulation time 77125905618 ps
CPU time 204.67 seconds
Started Jun 28 04:37:21 PM PDT 24
Finished Jun 28 04:40:46 PM PDT 24
Peak memory 199816 kb
Host smart-f783d988-15a7-47f6-afb2-43892c3c9a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259128106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.2259128106
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.140684915
Short name T197
Test name
Test status
Simulation time 10679087784 ps
CPU time 29.21 seconds
Started Jun 28 04:37:22 PM PDT 24
Finished Jun 28 04:37:52 PM PDT 24
Peak memory 199932 kb
Host smart-6b35bf1f-3383-4311-9fe3-38df2349be74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140684915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.140684915
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.727039374
Short name T14
Test name
Test status
Simulation time 17871830991 ps
CPU time 30.96 seconds
Started Jun 28 04:37:22 PM PDT 24
Finished Jun 28 04:37:53 PM PDT 24
Peak memory 200088 kb
Host smart-fd0e367a-9d52-4458-b606-47823665e1dd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727039374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.727039374
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.3730346836
Short name T853
Test name
Test status
Simulation time 90863054738 ps
CPU time 823.63 seconds
Started Jun 28 04:37:22 PM PDT 24
Finished Jun 28 04:51:06 PM PDT 24
Peak memory 199896 kb
Host smart-d050dd7d-d674-458e-b0c0-d202efa75e65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3730346836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3730346836
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.3688223001
Short name T664
Test name
Test status
Simulation time 5089769843 ps
CPU time 5.78 seconds
Started Jun 28 04:37:24 PM PDT 24
Finished Jun 28 04:37:31 PM PDT 24
Peak memory 198432 kb
Host smart-41eecde0-c881-41b6-bc9d-cea5ee611977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688223001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.3688223001
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.1663479820
Short name T529
Test name
Test status
Simulation time 32547649035 ps
CPU time 13.76 seconds
Started Jun 28 04:37:22 PM PDT 24
Finished Jun 28 04:37:36 PM PDT 24
Peak memory 199852 kb
Host smart-a50eb6cc-98e4-4a30-9a29-9f726dd35ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663479820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1663479820
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.1944353540
Short name T614
Test name
Test status
Simulation time 28381917025 ps
CPU time 1713.94 seconds
Started Jun 28 04:37:22 PM PDT 24
Finished Jun 28 05:05:57 PM PDT 24
Peak memory 199856 kb
Host smart-64d14ef0-fa90-49b4-86ec-3d4ca38d9b34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1944353540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1944353540
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.2942240248
Short name T365
Test name
Test status
Simulation time 2838620149 ps
CPU time 17.48 seconds
Started Jun 28 04:37:22 PM PDT 24
Finished Jun 28 04:37:40 PM PDT 24
Peak memory 198360 kb
Host smart-de415c0e-52b0-4f9f-9fb8-39e9b99301d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2942240248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2942240248
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.733453951
Short name T452
Test name
Test status
Simulation time 26499951705 ps
CPU time 18.02 seconds
Started Jun 28 04:37:25 PM PDT 24
Finished Jun 28 04:37:44 PM PDT 24
Peak memory 199552 kb
Host smart-24474bc5-f4e0-4dd8-889f-c172a0393992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733453951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.733453951
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.4241831655
Short name T769
Test name
Test status
Simulation time 1909522569 ps
CPU time 2.66 seconds
Started Jun 28 04:37:25 PM PDT 24
Finished Jun 28 04:37:29 PM PDT 24
Peak memory 195228 kb
Host smart-e9d29d29-f7a9-4dba-83bc-864baef1544a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241831655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.4241831655
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.2388161934
Short name T478
Test name
Test status
Simulation time 82522883 ps
CPU time 0.89 seconds
Started Jun 28 04:37:14 PM PDT 24
Finished Jun 28 04:37:16 PM PDT 24
Peak memory 197600 kb
Host smart-08609035-870d-471c-a1ea-27c59f73e21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388161934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2388161934
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.3098055839
Short name T102
Test name
Test status
Simulation time 256830701352 ps
CPU time 372.06 seconds
Started Jun 28 04:37:25 PM PDT 24
Finished Jun 28 04:43:38 PM PDT 24
Peak memory 199784 kb
Host smart-d5c03a64-ed6a-4871-b19e-bb0a3e7632b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098055839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3098055839
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.2551147427
Short name T52
Test name
Test status
Simulation time 605632364543 ps
CPU time 1608.99 seconds
Started Jun 28 04:37:23 PM PDT 24
Finished Jun 28 05:04:13 PM PDT 24
Peak memory 224648 kb
Host smart-05fb9acc-edb2-4fb5-980a-51c9280459ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551147427 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.2551147427
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.293112838
Short name T1039
Test name
Test status
Simulation time 1503741602 ps
CPU time 1.53 seconds
Started Jun 28 04:37:23 PM PDT 24
Finished Jun 28 04:37:25 PM PDT 24
Peak memory 198612 kb
Host smart-be9a88fe-0236-4ef6-8ce8-5f00654ba516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293112838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.293112838
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.2279560585
Short name T645
Test name
Test status
Simulation time 51888946307 ps
CPU time 114.28 seconds
Started Jun 28 04:37:13 PM PDT 24
Finished Jun 28 04:39:09 PM PDT 24
Peak memory 199860 kb
Host smart-777cfc9a-9997-427a-8313-ef5832a4ec6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279560585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2279560585
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.4284128981
Short name T189
Test name
Test status
Simulation time 107625628373 ps
CPU time 48.1 seconds
Started Jun 28 04:41:13 PM PDT 24
Finished Jun 28 04:42:02 PM PDT 24
Peak memory 199732 kb
Host smart-8ff4b5a5-e947-487d-a0e2-276af51d1fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284128981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.4284128981
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.2433438004
Short name T183
Test name
Test status
Simulation time 124447232265 ps
CPU time 32.37 seconds
Started Jun 28 04:41:11 PM PDT 24
Finished Jun 28 04:41:44 PM PDT 24
Peak memory 199816 kb
Host smart-5b47c23c-e845-47d3-a9d0-2fbb54f6cb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433438004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.2433438004
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.1575385738
Short name T34
Test name
Test status
Simulation time 171640595245 ps
CPU time 55.93 seconds
Started Jun 28 04:41:09 PM PDT 24
Finished Jun 28 04:42:06 PM PDT 24
Peak memory 199912 kb
Host smart-afa9fae2-b6f4-4aba-bd66-0ffb83cc76f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575385738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.1575385738
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.3902747873
Short name T897
Test name
Test status
Simulation time 129236327288 ps
CPU time 172.84 seconds
Started Jun 28 04:41:11 PM PDT 24
Finished Jun 28 04:44:05 PM PDT 24
Peak memory 199772 kb
Host smart-7c5899b1-ab10-40c4-871c-410ac7dc60f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902747873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.3902747873
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.452472276
Short name T142
Test name
Test status
Simulation time 331927169995 ps
CPU time 68.03 seconds
Started Jun 28 04:41:12 PM PDT 24
Finished Jun 28 04:42:20 PM PDT 24
Peak memory 199792 kb
Host smart-69b0bd75-4a87-4777-be04-adbd37029844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452472276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.452472276
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.1421976417
Short name T145
Test name
Test status
Simulation time 115304537045 ps
CPU time 160.04 seconds
Started Jun 28 04:41:08 PM PDT 24
Finished Jun 28 04:43:49 PM PDT 24
Peak memory 199768 kb
Host smart-e8ad3ff8-e1e2-4a44-9ffc-f31eccecb58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421976417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1421976417
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.3184284303
Short name T216
Test name
Test status
Simulation time 148295419526 ps
CPU time 171.26 seconds
Started Jun 28 04:41:09 PM PDT 24
Finished Jun 28 04:44:02 PM PDT 24
Peak memory 199828 kb
Host smart-e76b5036-c817-4e92-a146-c824d6ac409d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184284303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.3184284303
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.367926444
Short name T782
Test name
Test status
Simulation time 161785320583 ps
CPU time 23.36 seconds
Started Jun 28 04:41:09 PM PDT 24
Finished Jun 28 04:41:34 PM PDT 24
Peak memory 199832 kb
Host smart-c22e686a-d6ea-4605-86ae-198667494f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367926444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.367926444
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.3085655227
Short name T669
Test name
Test status
Simulation time 42490221 ps
CPU time 0.56 seconds
Started Jun 28 04:37:24 PM PDT 24
Finished Jun 28 04:37:26 PM PDT 24
Peak memory 195500 kb
Host smart-b2aa100c-3a27-4fec-99ba-af0561a59b88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085655227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3085655227
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.1123439211
Short name T487
Test name
Test status
Simulation time 46774611342 ps
CPU time 62.14 seconds
Started Jun 28 04:37:22 PM PDT 24
Finished Jun 28 04:38:25 PM PDT 24
Peak memory 199772 kb
Host smart-4c5c58cc-1e84-4958-ab4a-b81a85cfc46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123439211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.1123439211
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.1595644654
Short name T459
Test name
Test status
Simulation time 153980901469 ps
CPU time 59.92 seconds
Started Jun 28 04:37:23 PM PDT 24
Finished Jun 28 04:38:24 PM PDT 24
Peak memory 199880 kb
Host smart-a3d63b31-c983-45b0-9d87-e0b11052ad06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595644654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1595644654
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.216216090
Short name T509
Test name
Test status
Simulation time 43370416320 ps
CPU time 8.5 seconds
Started Jun 28 04:37:25 PM PDT 24
Finished Jun 28 04:37:35 PM PDT 24
Peak memory 199772 kb
Host smart-b61f1fdd-b365-4b18-9fee-95147f3bec7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216216090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.216216090
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.134625611
Short name T480
Test name
Test status
Simulation time 221047575031 ps
CPU time 163.75 seconds
Started Jun 28 04:37:23 PM PDT 24
Finished Jun 28 04:40:08 PM PDT 24
Peak memory 199580 kb
Host smart-c69ac711-f967-49e9-83ea-d83e1eea06c4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134625611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.134625611
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_loopback.1722888205
Short name T18
Test name
Test status
Simulation time 3868892902 ps
CPU time 7.77 seconds
Started Jun 28 04:37:25 PM PDT 24
Finished Jun 28 04:37:33 PM PDT 24
Peak memory 199880 kb
Host smart-2404b306-4f4f-4ddb-9303-2c0437158e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722888205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.1722888205
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_perf.3645501091
Short name T449
Test name
Test status
Simulation time 13353265427 ps
CPU time 758.41 seconds
Started Jun 28 04:37:23 PM PDT 24
Finished Jun 28 04:50:02 PM PDT 24
Peak memory 199880 kb
Host smart-d45768df-3d19-420b-baee-cf393f4bf7bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3645501091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3645501091
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.1179319230
Short name T958
Test name
Test status
Simulation time 1496471147 ps
CPU time 4.55 seconds
Started Jun 28 04:37:20 PM PDT 24
Finished Jun 28 04:37:25 PM PDT 24
Peak memory 197972 kb
Host smart-a250d274-d386-4ed7-8aad-00fda6ba99d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1179319230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1179319230
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.3888493690
Short name T138
Test name
Test status
Simulation time 31096011706 ps
CPU time 15.26 seconds
Started Jun 28 04:37:25 PM PDT 24
Finished Jun 28 04:37:42 PM PDT 24
Peak memory 200052 kb
Host smart-d9ca0926-c8d6-4422-bfd9-d7015c30d57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888493690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.3888493690
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1493932408
Short name T515
Test name
Test status
Simulation time 2896318522 ps
CPU time 1.8 seconds
Started Jun 28 04:37:23 PM PDT 24
Finished Jun 28 04:37:26 PM PDT 24
Peak memory 195592 kb
Host smart-4b47519c-9c92-4951-af4d-8959dc3ef441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493932408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1493932408
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.1534453978
Short name T259
Test name
Test status
Simulation time 666055344 ps
CPU time 2.87 seconds
Started Jun 28 04:37:24 PM PDT 24
Finished Jun 28 04:37:28 PM PDT 24
Peak memory 198844 kb
Host smart-8ee3e102-e4de-4436-839d-734c30df3c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534453978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1534453978
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.2965572832
Short name T374
Test name
Test status
Simulation time 110125920321 ps
CPU time 248.88 seconds
Started Jun 28 04:37:24 PM PDT 24
Finished Jun 28 04:41:34 PM PDT 24
Peak memory 199796 kb
Host smart-d8554f80-48f9-4a3e-a3c0-9d46284e85c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965572832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.2965572832
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.4229761355
Short name T577
Test name
Test status
Simulation time 18885121123 ps
CPU time 77.52 seconds
Started Jun 28 04:37:26 PM PDT 24
Finished Jun 28 04:38:44 PM PDT 24
Peak memory 208152 kb
Host smart-8e8d7b6f-a873-4a53-b265-56e59c6e9c3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229761355 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.4229761355
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.1578152683
Short name T696
Test name
Test status
Simulation time 1592074058 ps
CPU time 1.68 seconds
Started Jun 28 04:37:23 PM PDT 24
Finished Jun 28 04:37:26 PM PDT 24
Peak memory 198504 kb
Host smart-404c5594-cc94-4df9-bed8-91fd07d863d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578152683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1578152683
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.4099933021
Short name T521
Test name
Test status
Simulation time 73130682324 ps
CPU time 134.74 seconds
Started Jun 28 04:37:23 PM PDT 24
Finished Jun 28 04:39:38 PM PDT 24
Peak memory 199836 kb
Host smart-4212cff6-fada-48cd-be4b-30703767c13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099933021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.4099933021
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.1065704926
Short name T926
Test name
Test status
Simulation time 57933743845 ps
CPU time 47.56 seconds
Started Jun 28 04:41:10 PM PDT 24
Finished Jun 28 04:41:58 PM PDT 24
Peak memory 199880 kb
Host smart-26ddf271-f947-4f9b-9cb9-52fdc9910809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065704926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1065704926
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.2699998641
Short name T656
Test name
Test status
Simulation time 12379118159 ps
CPU time 19.32 seconds
Started Jun 28 04:41:10 PM PDT 24
Finished Jun 28 04:41:30 PM PDT 24
Peak memory 199772 kb
Host smart-0eac78be-9b58-4835-8f56-e5bb80d86292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699998641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2699998641
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1292478641
Short name T75
Test name
Test status
Simulation time 41012943650 ps
CPU time 15.17 seconds
Started Jun 28 04:41:11 PM PDT 24
Finished Jun 28 04:41:27 PM PDT 24
Peak memory 199848 kb
Host smart-3b94ce7e-4c1a-4661-a180-b776f991c09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292478641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1292478641
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.2552517830
Short name T405
Test name
Test status
Simulation time 103763028847 ps
CPU time 14.52 seconds
Started Jun 28 04:41:10 PM PDT 24
Finished Jun 28 04:41:25 PM PDT 24
Peak memory 200048 kb
Host smart-4e59341d-ed85-4242-8810-cb3b7118b621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552517830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2552517830
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.2658979004
Short name T1066
Test name
Test status
Simulation time 49346373073 ps
CPU time 148.56 seconds
Started Jun 28 04:41:11 PM PDT 24
Finished Jun 28 04:43:40 PM PDT 24
Peak memory 199916 kb
Host smart-2461a7e6-aac6-4a57-a49d-b8f6cd5891bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658979004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2658979004
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.980505059
Short name T412
Test name
Test status
Simulation time 159617218186 ps
CPU time 145.02 seconds
Started Jun 28 04:41:09 PM PDT 24
Finished Jun 28 04:43:35 PM PDT 24
Peak memory 199916 kb
Host smart-28482755-7a45-45a0-bc73-1eab4e3a12e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980505059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.980505059
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.3226917531
Short name T957
Test name
Test status
Simulation time 11594805070 ps
CPU time 5.52 seconds
Started Jun 28 04:41:10 PM PDT 24
Finished Jun 28 04:41:16 PM PDT 24
Peak memory 199852 kb
Host smart-575922e8-38bf-4c06-8326-a10b531cc52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226917531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3226917531
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.1543941241
Short name T516
Test name
Test status
Simulation time 39684919 ps
CPU time 0.57 seconds
Started Jun 28 04:37:36 PM PDT 24
Finished Jun 28 04:37:38 PM PDT 24
Peak memory 195080 kb
Host smart-085afc8a-05d0-4318-92a5-36b9ed59f4f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543941241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1543941241
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.3220631538
Short name T391
Test name
Test status
Simulation time 15645134637 ps
CPU time 24.61 seconds
Started Jun 28 04:37:25 PM PDT 24
Finished Jun 28 04:37:51 PM PDT 24
Peak memory 200044 kb
Host smart-f56e4a0e-6c40-4820-951b-bedae5d021ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220631538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.3220631538
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2472689991
Short name T1034
Test name
Test status
Simulation time 83930915879 ps
CPU time 118.96 seconds
Started Jun 28 04:37:23 PM PDT 24
Finished Jun 28 04:39:23 PM PDT 24
Peak memory 199828 kb
Host smart-574b1714-44c3-434e-87b8-4e6db54dcf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472689991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2472689991
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.4194950575
Short name T508
Test name
Test status
Simulation time 41649178077 ps
CPU time 15.54 seconds
Started Jun 28 04:37:25 PM PDT 24
Finished Jun 28 04:37:42 PM PDT 24
Peak memory 199908 kb
Host smart-95638e06-4d6f-4f9c-b76d-74ff5f14b5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194950575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.4194950575
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.41773253
Short name T602
Test name
Test status
Simulation time 258686290405 ps
CPU time 397.69 seconds
Started Jun 28 04:37:25 PM PDT 24
Finished Jun 28 04:44:04 PM PDT 24
Peak memory 198824 kb
Host smart-fdca0f1a-9b30-4487-b81a-2fea6cf6c17c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41773253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.41773253
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.56802185
Short name T1079
Test name
Test status
Simulation time 111360552024 ps
CPU time 597.6 seconds
Started Jun 28 04:37:26 PM PDT 24
Finished Jun 28 04:47:25 PM PDT 24
Peak memory 199732 kb
Host smart-8180f6b3-b85b-4318-ab5a-6a05bf1a8c9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=56802185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.56802185
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.2836173380
Short name T756
Test name
Test status
Simulation time 1968823206 ps
CPU time 1.41 seconds
Started Jun 28 04:37:25 PM PDT 24
Finished Jun 28 04:37:27 PM PDT 24
Peak memory 199472 kb
Host smart-4f0b422e-2f7c-4bfe-b11b-7282afae5dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836173380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.2836173380
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_perf.1060838466
Short name T914
Test name
Test status
Simulation time 13859726521 ps
CPU time 149.55 seconds
Started Jun 28 04:37:28 PM PDT 24
Finished Jun 28 04:39:58 PM PDT 24
Peak memory 199748 kb
Host smart-6b749865-437c-40b0-9524-5a83456a7f72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1060838466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.1060838466
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.2668453399
Short name T410
Test name
Test status
Simulation time 2770252825 ps
CPU time 1.57 seconds
Started Jun 28 04:37:23 PM PDT 24
Finished Jun 28 04:37:26 PM PDT 24
Peak memory 199000 kb
Host smart-e18d6184-28de-4cc3-be26-231b303a2742
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2668453399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.2668453399
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.1825509056
Short name T294
Test name
Test status
Simulation time 29943989286 ps
CPU time 43.9 seconds
Started Jun 28 04:37:25 PM PDT 24
Finished Jun 28 04:38:10 PM PDT 24
Peak memory 199240 kb
Host smart-885af72a-a781-4056-8779-15d29bc3e78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825509056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.1825509056
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.1845024881
Short name T461
Test name
Test status
Simulation time 4687345311 ps
CPU time 2.3 seconds
Started Jun 28 04:37:24 PM PDT 24
Finished Jun 28 04:37:27 PM PDT 24
Peak memory 196360 kb
Host smart-86f2acda-b8a2-45d6-85d1-2e2753df81c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845024881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.1845024881
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.379120937
Short name T307
Test name
Test status
Simulation time 5468586541 ps
CPU time 31.49 seconds
Started Jun 28 04:37:28 PM PDT 24
Finished Jun 28 04:38:00 PM PDT 24
Peak memory 199704 kb
Host smart-967cfb93-bde6-4b79-886b-9411837984ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379120937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.379120937
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.4029173464
Short name T878
Test name
Test status
Simulation time 56212094581 ps
CPU time 680.96 seconds
Started Jun 28 04:37:24 PM PDT 24
Finished Jun 28 04:48:45 PM PDT 24
Peak memory 216316 kb
Host smart-a922d117-329c-4d8f-90e8-77f03b97bab6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029173464 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.4029173464
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.2526992750
Short name T764
Test name
Test status
Simulation time 900080252 ps
CPU time 3.18 seconds
Started Jun 28 04:37:26 PM PDT 24
Finished Jun 28 04:37:30 PM PDT 24
Peak memory 198144 kb
Host smart-5049f2f5-6fc4-4558-871f-82ecec66f7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526992750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.2526992750
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.410913615
Short name T275
Test name
Test status
Simulation time 117532637516 ps
CPU time 155.13 seconds
Started Jun 28 04:37:24 PM PDT 24
Finished Jun 28 04:40:00 PM PDT 24
Peak memory 199808 kb
Host smart-b24e17a9-1c59-4887-815c-53375fa6b760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410913615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.410913615
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.2320533467
Short name T1053
Test name
Test status
Simulation time 163098708693 ps
CPU time 13.32 seconds
Started Jun 28 04:41:19 PM PDT 24
Finished Jun 28 04:41:33 PM PDT 24
Peak memory 199948 kb
Host smart-b7f0feb2-981c-43a2-a859-c00f597bc1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320533467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2320533467
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.3538302084
Short name T800
Test name
Test status
Simulation time 172424607984 ps
CPU time 73.33 seconds
Started Jun 28 04:41:24 PM PDT 24
Finished Jun 28 04:42:38 PM PDT 24
Peak memory 199740 kb
Host smart-d62775b2-7c8c-4185-b5f8-4e5032864ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538302084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3538302084
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.1512727372
Short name T1007
Test name
Test status
Simulation time 153547207691 ps
CPU time 96.71 seconds
Started Jun 28 04:41:24 PM PDT 24
Finished Jun 28 04:43:02 PM PDT 24
Peak memory 199780 kb
Host smart-4e88f2d1-df4e-4abb-88da-5d5b82f6252a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512727372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.1512727372
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.3210435157
Short name T594
Test name
Test status
Simulation time 36677271589 ps
CPU time 17.87 seconds
Started Jun 28 04:41:23 PM PDT 24
Finished Jun 28 04:41:41 PM PDT 24
Peak memory 199744 kb
Host smart-2709bc32-5301-49f2-b16c-a4eadf83d3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210435157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3210435157
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.4079955666
Short name T532
Test name
Test status
Simulation time 27413387191 ps
CPU time 59.33 seconds
Started Jun 28 04:41:20 PM PDT 24
Finished Jun 28 04:42:21 PM PDT 24
Peak memory 199832 kb
Host smart-26553ca2-d3a2-452a-8fdd-7b5b64cae919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079955666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.4079955666
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.2062284136
Short name T146
Test name
Test status
Simulation time 16549961463 ps
CPU time 8.04 seconds
Started Jun 28 04:41:24 PM PDT 24
Finished Jun 28 04:41:33 PM PDT 24
Peak memory 199880 kb
Host smart-324d83b4-085e-4427-a374-68b92cde7913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062284136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.2062284136
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2371832724
Short name T338
Test name
Test status
Simulation time 63331774345 ps
CPU time 24.18 seconds
Started Jun 28 04:41:22 PM PDT 24
Finished Jun 28 04:41:47 PM PDT 24
Peak memory 199880 kb
Host smart-71c774af-edbc-483e-b114-76daed7f2fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371832724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2371832724
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.3517559605
Short name T137
Test name
Test status
Simulation time 45722555738 ps
CPU time 56.93 seconds
Started Jun 28 04:41:21 PM PDT 24
Finished Jun 28 04:42:19 PM PDT 24
Peak memory 199916 kb
Host smart-98c18e36-a7bc-4559-a3ac-13271a9037f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517559605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.3517559605
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.1077193184
Short name T463
Test name
Test status
Simulation time 17026031 ps
CPU time 0.61 seconds
Started Jun 28 04:37:33 PM PDT 24
Finished Jun 28 04:37:34 PM PDT 24
Peak memory 194872 kb
Host smart-183a94b3-b27a-41aa-963b-d832bcc1bef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077193184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1077193184
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.3180955148
Short name T469
Test name
Test status
Simulation time 178088991220 ps
CPU time 331.61 seconds
Started Jun 28 04:37:32 PM PDT 24
Finished Jun 28 04:43:04 PM PDT 24
Peak memory 199936 kb
Host smart-c8c1cbd1-93bc-45ec-bfd3-988d034583e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180955148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.3180955148
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.16616723
Short name T1000
Test name
Test status
Simulation time 85011622160 ps
CPU time 35.69 seconds
Started Jun 28 04:37:35 PM PDT 24
Finished Jun 28 04:38:11 PM PDT 24
Peak memory 199764 kb
Host smart-eb4929e6-e372-4b79-bc34-ed2ce642c1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16616723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.16616723
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.3492639463
Short name T116
Test name
Test status
Simulation time 123254441886 ps
CPU time 46.88 seconds
Started Jun 28 04:37:35 PM PDT 24
Finished Jun 28 04:38:23 PM PDT 24
Peak memory 199768 kb
Host smart-22b6e4a5-c83e-4a08-ad65-431846bbfb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492639463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.3492639463
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.1948027896
Short name T625
Test name
Test status
Simulation time 13146224652 ps
CPU time 10.37 seconds
Started Jun 28 04:37:35 PM PDT 24
Finished Jun 28 04:37:46 PM PDT 24
Peak memory 196708 kb
Host smart-9de68641-6dd8-4f85-9061-60ca78ca371c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948027896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.1948027896
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.3623131052
Short name T531
Test name
Test status
Simulation time 90557119434 ps
CPU time 160.55 seconds
Started Jun 28 04:37:34 PM PDT 24
Finished Jun 28 04:40:15 PM PDT 24
Peak memory 199728 kb
Host smart-1c4878f9-cb8d-4295-9a49-059c7cb0b26d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3623131052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.3623131052
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3455379346
Short name T744
Test name
Test status
Simulation time 13362975154 ps
CPU time 12.84 seconds
Started Jun 28 04:37:33 PM PDT 24
Finished Jun 28 04:37:47 PM PDT 24
Peak memory 199444 kb
Host smart-b7483792-b4f5-4a9b-b7cf-58afda4065e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455379346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3455379346
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_perf.3976887920
Short name T925
Test name
Test status
Simulation time 6655058380 ps
CPU time 347.27 seconds
Started Jun 28 04:37:32 PM PDT 24
Finished Jun 28 04:43:20 PM PDT 24
Peak memory 199800 kb
Host smart-cc5901b9-731f-46af-af0a-8917429d3588
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3976887920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3976887920
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.721435929
Short name T347
Test name
Test status
Simulation time 2428514299 ps
CPU time 3.56 seconds
Started Jun 28 04:37:34 PM PDT 24
Finished Jun 28 04:37:39 PM PDT 24
Peak memory 198968 kb
Host smart-e1ce2703-14ea-480a-95f6-a1a9ae684d82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=721435929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.721435929
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.2752164066
Short name T845
Test name
Test status
Simulation time 28699179143 ps
CPU time 37.03 seconds
Started Jun 28 04:37:33 PM PDT 24
Finished Jun 28 04:38:12 PM PDT 24
Peak memory 199844 kb
Host smart-fb7033b6-3cb0-406c-95de-92ec9a75a125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752164066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2752164066
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.3545527653
Short name T541
Test name
Test status
Simulation time 4384358905 ps
CPU time 2.17 seconds
Started Jun 28 04:37:35 PM PDT 24
Finished Jun 28 04:37:38 PM PDT 24
Peak memory 196092 kb
Host smart-f85c00dd-7310-4c30-a64d-aaf3e2cc2584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545527653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3545527653
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.3217391021
Short name T1027
Test name
Test status
Simulation time 499081412 ps
CPU time 2.02 seconds
Started Jun 28 04:37:32 PM PDT 24
Finished Jun 28 04:37:34 PM PDT 24
Peak memory 198740 kb
Host smart-d41e3032-1081-4769-ba6d-d70ddad8a19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217391021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3217391021
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.330667384
Short name T31
Test name
Test status
Simulation time 50660617022 ps
CPU time 425.48 seconds
Started Jun 28 04:37:34 PM PDT 24
Finished Jun 28 04:44:41 PM PDT 24
Peak memory 211872 kb
Host smart-f1a9031f-4562-40b5-b06c-8c673e06465d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330667384 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.330667384
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.34008717
Short name T1072
Test name
Test status
Simulation time 1654207329 ps
CPU time 1.76 seconds
Started Jun 28 04:37:33 PM PDT 24
Finished Jun 28 04:37:36 PM PDT 24
Peak memory 199680 kb
Host smart-346e2bc0-2aa0-4035-8092-55f2ac338234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34008717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.34008717
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.1735413233
Short name T530
Test name
Test status
Simulation time 51022424391 ps
CPU time 44.39 seconds
Started Jun 28 04:37:37 PM PDT 24
Finished Jun 28 04:38:22 PM PDT 24
Peak memory 199920 kb
Host smart-1216855b-05fd-4fc0-8886-425de6d5395b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735413233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1735413233
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.2876242162
Short name T283
Test name
Test status
Simulation time 45721945444 ps
CPU time 62.9 seconds
Started Jun 28 04:41:20 PM PDT 24
Finished Jun 28 04:42:24 PM PDT 24
Peak memory 199916 kb
Host smart-62bd842c-72d4-46c5-9101-bdf1ea4f4eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876242162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.2876242162
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.3353259342
Short name T922
Test name
Test status
Simulation time 26838479661 ps
CPU time 22.51 seconds
Started Jun 28 04:41:20 PM PDT 24
Finished Jun 28 04:41:43 PM PDT 24
Peak memory 199848 kb
Host smart-d43a969d-7f0f-4c06-bd19-785aa06cbfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353259342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.3353259342
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.2866903370
Short name T395
Test name
Test status
Simulation time 33323571116 ps
CPU time 38.7 seconds
Started Jun 28 04:41:23 PM PDT 24
Finished Jun 28 04:42:02 PM PDT 24
Peak memory 199880 kb
Host smart-4ae8b370-f636-49c7-984d-32268f89e546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866903370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2866903370
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.2365977547
Short name T708
Test name
Test status
Simulation time 73750932299 ps
CPU time 241.79 seconds
Started Jun 28 04:41:20 PM PDT 24
Finished Jun 28 04:45:23 PM PDT 24
Peak memory 199808 kb
Host smart-67391431-b45b-41b9-acff-9195bd533be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365977547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2365977547
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2504999790
Short name T772
Test name
Test status
Simulation time 38417153037 ps
CPU time 24.83 seconds
Started Jun 28 04:41:23 PM PDT 24
Finished Jun 28 04:41:49 PM PDT 24
Peak memory 199616 kb
Host smart-624bee90-8c99-4192-8de3-91c540374ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504999790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2504999790
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.1933057401
Short name T313
Test name
Test status
Simulation time 14842430225 ps
CPU time 13.66 seconds
Started Jun 28 04:41:20 PM PDT 24
Finished Jun 28 04:41:34 PM PDT 24
Peak memory 199832 kb
Host smart-adb5e412-9c3a-45b6-a53b-c79ab91b666c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933057401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1933057401
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.426214242
Short name T316
Test name
Test status
Simulation time 150320789085 ps
CPU time 230.95 seconds
Started Jun 28 04:41:20 PM PDT 24
Finished Jun 28 04:45:12 PM PDT 24
Peak memory 199772 kb
Host smart-cb15c1be-05df-47cf-ac8e-9a8f412169f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426214242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.426214242
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.2809479910
Short name T427
Test name
Test status
Simulation time 17248640903 ps
CPU time 13.03 seconds
Started Jun 28 04:41:25 PM PDT 24
Finished Jun 28 04:41:38 PM PDT 24
Peak memory 199524 kb
Host smart-9ee094c6-7c48-4ce8-b969-b0b929dcff24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809479910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.2809479910
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.1557640547
Short name T129
Test name
Test status
Simulation time 37552181917 ps
CPU time 31.44 seconds
Started Jun 28 04:41:22 PM PDT 24
Finished Jun 28 04:41:54 PM PDT 24
Peak memory 199856 kb
Host smart-19daad5e-d5e5-4e7e-a7de-76a59043798b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557640547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1557640547
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.325182223
Short name T1090
Test name
Test status
Simulation time 18630683965 ps
CPU time 20.71 seconds
Started Jun 28 04:41:21 PM PDT 24
Finished Jun 28 04:41:42 PM PDT 24
Peak memory 200052 kb
Host smart-0930ac88-8c0f-4ccd-a950-9c955839409f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325182223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.325182223
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.1070982996
Short name T779
Test name
Test status
Simulation time 23390852 ps
CPU time 0.55 seconds
Started Jun 28 04:37:32 PM PDT 24
Finished Jun 28 04:37:33 PM PDT 24
Peak memory 195148 kb
Host smart-5a6d08a8-3db2-44c3-8f0f-14d893be23c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070982996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1070982996
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.290818123
Short name T641
Test name
Test status
Simulation time 122926787903 ps
CPU time 50.26 seconds
Started Jun 28 04:37:33 PM PDT 24
Finished Jun 28 04:38:23 PM PDT 24
Peak memory 199900 kb
Host smart-ebee4df7-80bb-4256-8a85-09f292005bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290818123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.290818123
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1275074382
Short name T1055
Test name
Test status
Simulation time 29737396554 ps
CPU time 26.56 seconds
Started Jun 28 04:37:36 PM PDT 24
Finished Jun 28 04:38:03 PM PDT 24
Peak memory 199804 kb
Host smart-711664aa-80a3-4e68-b560-e8d4c9da6f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275074382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1275074382
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_intr.1166983125
Short name T720
Test name
Test status
Simulation time 6593304697 ps
CPU time 9.89 seconds
Started Jun 28 04:37:34 PM PDT 24
Finished Jun 28 04:37:45 PM PDT 24
Peak memory 196600 kb
Host smart-da80e917-b5d0-4afd-97a9-936cc2e52225
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166983125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1166983125
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.1888738908
Short name T375
Test name
Test status
Simulation time 78550752940 ps
CPU time 295.75 seconds
Started Jun 28 04:37:34 PM PDT 24
Finished Jun 28 04:42:31 PM PDT 24
Peak memory 199812 kb
Host smart-91842f21-13e8-4ece-a149-42d879fb99d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1888738908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1888738908
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.2430500767
Short name T806
Test name
Test status
Simulation time 7064110633 ps
CPU time 21.71 seconds
Started Jun 28 04:37:33 PM PDT 24
Finished Jun 28 04:37:56 PM PDT 24
Peak memory 199400 kb
Host smart-bb1a152e-2c94-45cf-b9c1-ce11ecbede8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430500767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2430500767
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_perf.3428033237
Short name T894
Test name
Test status
Simulation time 33965198091 ps
CPU time 581.35 seconds
Started Jun 28 04:37:34 PM PDT 24
Finished Jun 28 04:47:17 PM PDT 24
Peak memory 199796 kb
Host smart-29b23070-d8d7-4891-948b-045f207862ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3428033237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3428033237
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3965850957
Short name T695
Test name
Test status
Simulation time 3172168567 ps
CPU time 5.88 seconds
Started Jun 28 04:37:35 PM PDT 24
Finished Jun 28 04:37:42 PM PDT 24
Peak memory 198072 kb
Host smart-0fe83a2b-1905-4411-ac59-cf702f8883d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3965850957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3965850957
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.1023254490
Short name T826
Test name
Test status
Simulation time 119461375603 ps
CPU time 55.62 seconds
Started Jun 28 04:37:35 PM PDT 24
Finished Jun 28 04:38:31 PM PDT 24
Peak memory 199788 kb
Host smart-35fdbf53-0497-4379-bb66-390e1437fa53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023254490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1023254490
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.1889387615
Short name T447
Test name
Test status
Simulation time 4095399052 ps
CPU time 1.51 seconds
Started Jun 28 04:37:30 PM PDT 24
Finished Jun 28 04:37:32 PM PDT 24
Peak memory 196304 kb
Host smart-e0930f85-e351-4909-abbe-ee060cae7cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889387615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.1889387615
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.3165944555
Short name T286
Test name
Test status
Simulation time 11721109922 ps
CPU time 5.93 seconds
Started Jun 28 04:37:36 PM PDT 24
Finished Jun 28 04:37:43 PM PDT 24
Peak memory 199584 kb
Host smart-d74b594a-89a1-4487-abea-00c7148e30d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165944555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3165944555
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.1835425498
Short name T157
Test name
Test status
Simulation time 25506024026 ps
CPU time 220.06 seconds
Started Jun 28 04:37:33 PM PDT 24
Finished Jun 28 04:41:13 PM PDT 24
Peak memory 215328 kb
Host smart-e8cf09c9-6565-4268-82d3-c7c3a6d6eeb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835425498 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.1835425498
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.3854003646
Short name T426
Test name
Test status
Simulation time 657633327 ps
CPU time 1.92 seconds
Started Jun 28 04:37:37 PM PDT 24
Finished Jun 28 04:37:40 PM PDT 24
Peak memory 199660 kb
Host smart-731c81c0-c70a-4083-a859-7bfc225746a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854003646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3854003646
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3778287646
Short name T506
Test name
Test status
Simulation time 67521112741 ps
CPU time 30.19 seconds
Started Jun 28 04:37:35 PM PDT 24
Finished Jun 28 04:38:06 PM PDT 24
Peak memory 199836 kb
Host smart-b3cf7d47-1843-45d8-8fca-c10d330bf1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778287646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3778287646
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.2560698596
Short name T489
Test name
Test status
Simulation time 33439531835 ps
CPU time 12.29 seconds
Started Jun 28 04:41:21 PM PDT 24
Finished Jun 28 04:41:34 PM PDT 24
Peak memory 199620 kb
Host smart-a2e18539-4315-4e5e-a067-ff746b9329dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560698596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.2560698596
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1636926082
Short name T608
Test name
Test status
Simulation time 81066195793 ps
CPU time 42.7 seconds
Started Jun 28 04:41:20 PM PDT 24
Finished Jun 28 04:42:04 PM PDT 24
Peak memory 199856 kb
Host smart-66314209-502c-438c-9bb5-64d2e02d69fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636926082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1636926082
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.2864092852
Short name T748
Test name
Test status
Simulation time 51391764675 ps
CPU time 49.15 seconds
Started Jun 28 04:41:23 PM PDT 24
Finished Jun 28 04:42:13 PM PDT 24
Peak memory 199700 kb
Host smart-e1b5af34-33c8-4813-8d2c-c85e166bedd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864092852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2864092852
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.2043051910
Short name T131
Test name
Test status
Simulation time 224717850823 ps
CPU time 105.44 seconds
Started Jun 28 04:41:21 PM PDT 24
Finished Jun 28 04:43:07 PM PDT 24
Peak memory 199880 kb
Host smart-a48af87f-7a98-49a3-9dcf-b7602d273b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043051910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.2043051910
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.3187745301
Short name T1077
Test name
Test status
Simulation time 50818210962 ps
CPU time 116.66 seconds
Started Jun 28 04:41:21 PM PDT 24
Finished Jun 28 04:43:18 PM PDT 24
Peak memory 199856 kb
Host smart-fddbe1f2-0ffa-4057-8ea8-7beaf3da57e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187745301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3187745301
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.1322817659
Short name T975
Test name
Test status
Simulation time 44298127926 ps
CPU time 68.58 seconds
Started Jun 28 04:41:21 PM PDT 24
Finished Jun 28 04:42:31 PM PDT 24
Peak memory 199736 kb
Host smart-1922b91a-97cb-45f5-b691-c3080802c407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322817659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1322817659
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.2546550392
Short name T119
Test name
Test status
Simulation time 16488360771 ps
CPU time 30.57 seconds
Started Jun 28 04:41:21 PM PDT 24
Finished Jun 28 04:41:53 PM PDT 24
Peak memory 199832 kb
Host smart-7263cfc1-008b-4893-83e3-4ec543757662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546550392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2546550392
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.3310691945
Short name T454
Test name
Test status
Simulation time 17579947001 ps
CPU time 28.65 seconds
Started Jun 28 04:41:25 PM PDT 24
Finished Jun 28 04:41:54 PM PDT 24
Peak memory 199780 kb
Host smart-4a72d53a-0fad-4324-939d-f28ae5d295a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310691945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3310691945
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.915507952
Short name T818
Test name
Test status
Simulation time 20640327 ps
CPU time 0.57 seconds
Started Jun 28 04:37:48 PM PDT 24
Finished Jun 28 04:37:49 PM PDT 24
Peak memory 195404 kb
Host smart-417a1e84-8026-460c-b44d-8d7894631ff4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915507952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.915507952
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.3220773318
Short name T712
Test name
Test status
Simulation time 66565952780 ps
CPU time 51.07 seconds
Started Jun 28 04:37:33 PM PDT 24
Finished Jun 28 04:38:24 PM PDT 24
Peak memory 199000 kb
Host smart-39aae123-4cea-4a83-a7d3-db88c38b848c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220773318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3220773318
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.1206116702
Short name T982
Test name
Test status
Simulation time 107524777578 ps
CPU time 49.46 seconds
Started Jun 28 04:37:42 PM PDT 24
Finished Jun 28 04:38:33 PM PDT 24
Peak memory 199908 kb
Host smart-a46d34f2-6bc7-462d-9eee-497561c3412b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206116702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1206116702
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.3455739670
Short name T681
Test name
Test status
Simulation time 25789250469 ps
CPU time 19.95 seconds
Started Jun 28 04:37:48 PM PDT 24
Finished Jun 28 04:38:08 PM PDT 24
Peak memory 199384 kb
Host smart-f1e0b64a-6297-4409-8ab1-11f9c89348f0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455739670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.3455739670
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.4078665394
Short name T376
Test name
Test status
Simulation time 120776303555 ps
CPU time 727.56 seconds
Started Jun 28 04:37:42 PM PDT 24
Finished Jun 28 04:49:50 PM PDT 24
Peak memory 199752 kb
Host smart-197c9765-402c-4b99-bc8d-14d2f1e781ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4078665394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.4078665394
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.869240179
Short name T710
Test name
Test status
Simulation time 9080776373 ps
CPU time 4.16 seconds
Started Jun 28 04:37:47 PM PDT 24
Finished Jun 28 04:37:52 PM PDT 24
Peak memory 199240 kb
Host smart-1cdf89bc-140b-4522-9fe8-5c40bf1c229b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869240179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.869240179
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_perf.1760443078
Short name T267
Test name
Test status
Simulation time 14109693447 ps
CPU time 61.77 seconds
Started Jun 28 04:37:42 PM PDT 24
Finished Jun 28 04:38:44 PM PDT 24
Peak memory 199788 kb
Host smart-62ac06c8-fb63-46b2-9a30-5d66ff62cdfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1760443078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.1760443078
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.2402541854
Short name T660
Test name
Test status
Simulation time 3411232391 ps
CPU time 22.79 seconds
Started Jun 28 04:37:44 PM PDT 24
Finished Jun 28 04:38:08 PM PDT 24
Peak memory 198320 kb
Host smart-9871b693-2b00-4f4c-8063-df765f70c012
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2402541854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2402541854
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.2180076164
Short name T967
Test name
Test status
Simulation time 16657070423 ps
CPU time 37.36 seconds
Started Jun 28 04:37:43 PM PDT 24
Finished Jun 28 04:38:21 PM PDT 24
Peak memory 199740 kb
Host smart-8c89a578-8ac2-4dd7-a64d-8700a6ea8073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180076164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2180076164
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1849186516
Short name T408
Test name
Test status
Simulation time 5093834314 ps
CPU time 2.52 seconds
Started Jun 28 04:37:42 PM PDT 24
Finished Jun 28 04:37:46 PM PDT 24
Peak memory 196312 kb
Host smart-763ffad8-07a0-4f1d-be3e-c090bbbe3d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849186516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1849186516
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1941576817
Short name T616
Test name
Test status
Simulation time 299079923 ps
CPU time 0.92 seconds
Started Jun 28 04:37:33 PM PDT 24
Finished Jun 28 04:37:35 PM PDT 24
Peak memory 198156 kb
Host smart-72d65b0e-9ad2-4e0a-8883-b4ff45ddaf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941576817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1941576817
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.1703889633
Short name T955
Test name
Test status
Simulation time 129380940616 ps
CPU time 1032.06 seconds
Started Jun 28 04:37:44 PM PDT 24
Finished Jun 28 04:54:57 PM PDT 24
Peak memory 216424 kb
Host smart-4cdca245-e9be-449d-9c68-0bd63e23c026
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703889633 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.1703889633
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.2698016080
Short name T799
Test name
Test status
Simulation time 8467060590 ps
CPU time 12.7 seconds
Started Jun 28 04:37:43 PM PDT 24
Finished Jun 28 04:37:56 PM PDT 24
Peak memory 199880 kb
Host smart-0389e64d-6b95-4584-9a0e-ce460c649c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698016080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2698016080
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.2709122456
Short name T166
Test name
Test status
Simulation time 12430122081 ps
CPU time 19.47 seconds
Started Jun 28 04:41:25 PM PDT 24
Finished Jun 28 04:41:45 PM PDT 24
Peak memory 199868 kb
Host smart-c8e1f5b4-07bb-45ed-9dd1-f543d8118f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709122456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.2709122456
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2657968447
Short name T969
Test name
Test status
Simulation time 109740486043 ps
CPU time 61.74 seconds
Started Jun 28 04:41:21 PM PDT 24
Finished Jun 28 04:42:24 PM PDT 24
Peak memory 199836 kb
Host smart-e5240f45-4df4-45ad-8b3c-cde324450686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657968447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2657968447
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3242407400
Short name T811
Test name
Test status
Simulation time 36331503427 ps
CPU time 15.84 seconds
Started Jun 28 04:41:20 PM PDT 24
Finished Jun 28 04:41:37 PM PDT 24
Peak memory 199976 kb
Host smart-9a11d7ca-88d2-4395-aea7-8b097201a95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242407400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3242407400
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1596491320
Short name T235
Test name
Test status
Simulation time 119645594849 ps
CPU time 52.51 seconds
Started Jun 28 04:41:32 PM PDT 24
Finished Jun 28 04:42:25 PM PDT 24
Peak memory 199856 kb
Host smart-9a7da2d3-265f-403b-a8f7-9a55d439202f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596491320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1596491320
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.3950475189
Short name T164
Test name
Test status
Simulation time 99883476193 ps
CPU time 40.57 seconds
Started Jun 28 04:41:30 PM PDT 24
Finished Jun 28 04:42:11 PM PDT 24
Peak memory 199912 kb
Host smart-7e1ba7a0-051b-46f0-9e0c-55852eed1a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950475189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3950475189
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1149645169
Short name T896
Test name
Test status
Simulation time 92472074872 ps
CPU time 180.43 seconds
Started Jun 28 04:41:42 PM PDT 24
Finished Jun 28 04:44:44 PM PDT 24
Peak memory 199836 kb
Host smart-393e0751-df48-41a8-82c1-0395c85e4731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149645169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1149645169
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.546868690
Short name T466
Test name
Test status
Simulation time 99205430323 ps
CPU time 144.59 seconds
Started Jun 28 04:41:31 PM PDT 24
Finished Jun 28 04:43:57 PM PDT 24
Peak memory 199880 kb
Host smart-dddfa3f2-501a-4196-b0bf-05c45068b858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546868690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.546868690
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1943823500
Short name T875
Test name
Test status
Simulation time 110059665065 ps
CPU time 118.76 seconds
Started Jun 28 04:41:42 PM PDT 24
Finished Jun 28 04:43:42 PM PDT 24
Peak memory 199724 kb
Host smart-4b73e440-5257-40fb-893d-3e65d3151505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943823500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1943823500
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2238680453
Short name T185
Test name
Test status
Simulation time 32753528629 ps
CPU time 26.46 seconds
Started Jun 28 04:41:31 PM PDT 24
Finished Jun 28 04:41:58 PM PDT 24
Peak memory 199868 kb
Host smart-e272db24-c6e3-4320-9948-a7d9a5810e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238680453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2238680453
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.2288462348
Short name T872
Test name
Test status
Simulation time 39131014 ps
CPU time 0.55 seconds
Started Jun 28 04:37:54 PM PDT 24
Finished Jun 28 04:37:55 PM PDT 24
Peak memory 194784 kb
Host smart-4c45abb1-4eff-47f8-bcc2-c231651e893b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288462348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2288462348
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.3360625944
Short name T432
Test name
Test status
Simulation time 125228720539 ps
CPU time 196.4 seconds
Started Jun 28 04:37:45 PM PDT 24
Finished Jun 28 04:41:02 PM PDT 24
Peak memory 199924 kb
Host smart-3f6673a3-f2d0-4dd7-b1f3-667536c3960a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360625944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3360625944
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.3112853598
Short name T117
Test name
Test status
Simulation time 42666002322 ps
CPU time 30.41 seconds
Started Jun 28 04:37:48 PM PDT 24
Finished Jun 28 04:38:19 PM PDT 24
Peak memory 199828 kb
Host smart-50e4caa9-cc34-4d25-9344-51221a12baed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112853598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3112853598
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.1418336695
Short name T421
Test name
Test status
Simulation time 106081108022 ps
CPU time 121.18 seconds
Started Jun 28 04:37:42 PM PDT 24
Finished Jun 28 04:39:43 PM PDT 24
Peak memory 199912 kb
Host smart-2adf33c0-d488-4f2c-8190-9eb63be38c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418336695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1418336695
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.826514789
Short name T851
Test name
Test status
Simulation time 39310335668 ps
CPU time 28.05 seconds
Started Jun 28 04:37:44 PM PDT 24
Finished Jun 28 04:38:12 PM PDT 24
Peak memory 199736 kb
Host smart-50735783-dbcb-4a4f-b6c5-068f4edb7088
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826514789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.826514789
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2431431042
Short name T422
Test name
Test status
Simulation time 57188643990 ps
CPU time 187.86 seconds
Started Jun 28 04:37:54 PM PDT 24
Finished Jun 28 04:41:03 PM PDT 24
Peak memory 199816 kb
Host smart-3a500085-0399-4fcc-81cf-55c9fdac67cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2431431042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2431431042
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2472863682
Short name T839
Test name
Test status
Simulation time 8391308525 ps
CPU time 9.37 seconds
Started Jun 28 04:37:55 PM PDT 24
Finished Jun 28 04:38:05 PM PDT 24
Peak memory 199872 kb
Host smart-072c0f6e-68b9-41cb-99cc-215939036b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472863682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2472863682
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_perf.2470628218
Short name T226
Test name
Test status
Simulation time 15265796502 ps
CPU time 88 seconds
Started Jun 28 04:37:54 PM PDT 24
Finished Jun 28 04:39:23 PM PDT 24
Peak memory 199832 kb
Host smart-f1596aa6-92bb-41a0-9111-71cb5da00e1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2470628218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2470628218
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.896421438
Short name T615
Test name
Test status
Simulation time 3152304859 ps
CPU time 9.01 seconds
Started Jun 28 04:37:47 PM PDT 24
Finished Jun 28 04:37:57 PM PDT 24
Peak memory 198540 kb
Host smart-87ad8759-6a20-4de3-bd22-e115270befba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=896421438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.896421438
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.3354405994
Short name T372
Test name
Test status
Simulation time 28491624208 ps
CPU time 46.81 seconds
Started Jun 28 04:37:42 PM PDT 24
Finished Jun 28 04:38:29 PM PDT 24
Peak memory 199812 kb
Host smart-33264192-8fc5-4d55-8ab6-41f4acc74279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354405994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.3354405994
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.2235852908
Short name T223
Test name
Test status
Simulation time 5096236217 ps
CPU time 2.71 seconds
Started Jun 28 04:37:43 PM PDT 24
Finished Jun 28 04:37:46 PM PDT 24
Peak memory 195948 kb
Host smart-62023eb4-7f16-4bbf-8f7a-1eab06c559d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235852908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.2235852908
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.3312136448
Short name T268
Test name
Test status
Simulation time 666640934 ps
CPU time 2.21 seconds
Started Jun 28 04:37:47 PM PDT 24
Finished Jun 28 04:37:50 PM PDT 24
Peak memory 198124 kb
Host smart-855ac242-af5b-4ab8-bd90-95e54d748c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312136448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.3312136448
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.1662661170
Short name T868
Test name
Test status
Simulation time 105832469511 ps
CPU time 474.62 seconds
Started Jun 28 04:37:56 PM PDT 24
Finished Jun 28 04:45:52 PM PDT 24
Peak memory 199872 kb
Host smart-5f0c044a-87c0-48fb-8a0e-6b8edb98866a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662661170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1662661170
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.4019769337
Short name T1071
Test name
Test status
Simulation time 29459033677 ps
CPU time 155.89 seconds
Started Jun 28 04:37:54 PM PDT 24
Finished Jun 28 04:40:31 PM PDT 24
Peak memory 215584 kb
Host smart-cdf48bf3-468a-4a47-9319-712109a10ee3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019769337 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.4019769337
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1312837342
Short name T751
Test name
Test status
Simulation time 7097343610 ps
CPU time 22.89 seconds
Started Jun 28 04:37:55 PM PDT 24
Finished Jun 28 04:38:18 PM PDT 24
Peak memory 199884 kb
Host smart-19fffe59-ddc7-486f-90f4-599a222f17d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312837342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1312837342
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.787730488
Short name T419
Test name
Test status
Simulation time 65774571576 ps
CPU time 18.86 seconds
Started Jun 28 04:37:43 PM PDT 24
Finished Jun 28 04:38:02 PM PDT 24
Peak memory 199908 kb
Host smart-98a247e7-f80e-4325-994d-6912889bccdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787730488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.787730488
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.2053292559
Short name T140
Test name
Test status
Simulation time 7687522903 ps
CPU time 6.75 seconds
Started Jun 28 04:41:31 PM PDT 24
Finished Jun 28 04:41:39 PM PDT 24
Peak memory 199548 kb
Host smart-92d5b0c4-b695-40f5-aabf-0f47ae45d535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053292559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.2053292559
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.2444821496
Short name T661
Test name
Test status
Simulation time 21798553700 ps
CPU time 9.9 seconds
Started Jun 28 04:41:42 PM PDT 24
Finished Jun 28 04:41:53 PM PDT 24
Peak memory 199700 kb
Host smart-b13da163-2f48-438d-9f16-0d1f65e6b7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444821496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2444821496
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3736486645
Short name T179
Test name
Test status
Simulation time 28717489989 ps
CPU time 25.47 seconds
Started Jun 28 04:41:33 PM PDT 24
Finished Jun 28 04:41:59 PM PDT 24
Peak memory 199744 kb
Host smart-deaf023c-404b-446f-8fcc-ad8f5a72bfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736486645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3736486645
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.3885157568
Short name T724
Test name
Test status
Simulation time 175636520900 ps
CPU time 87.31 seconds
Started Jun 28 04:41:42 PM PDT 24
Finished Jun 28 04:43:11 PM PDT 24
Peak memory 199836 kb
Host smart-15991606-a353-444c-aa72-e607d98e3fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885157568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3885157568
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.2129852299
Short name T891
Test name
Test status
Simulation time 54967729349 ps
CPU time 89.03 seconds
Started Jun 28 04:41:30 PM PDT 24
Finished Jun 28 04:42:59 PM PDT 24
Peak memory 199912 kb
Host smart-5060af99-9313-4f69-ab2c-1799fb2146de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129852299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.2129852299
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.2137215311
Short name T740
Test name
Test status
Simulation time 24408184461 ps
CPU time 35.33 seconds
Started Jun 28 04:41:35 PM PDT 24
Finished Jun 28 04:42:10 PM PDT 24
Peak memory 199908 kb
Host smart-bac9bb6f-e094-4016-8900-a7024e0525f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137215311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2137215311
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2429072887
Short name T178
Test name
Test status
Simulation time 9195934417 ps
CPU time 15.37 seconds
Started Jun 28 04:41:31 PM PDT 24
Finished Jun 28 04:41:46 PM PDT 24
Peak memory 199836 kb
Host smart-24350795-e18e-4625-aa3a-017d3e9ff05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429072887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2429072887
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.1173114922
Short name T730
Test name
Test status
Simulation time 13834225215 ps
CPU time 27.28 seconds
Started Jun 28 04:41:31 PM PDT 24
Finished Jun 28 04:41:59 PM PDT 24
Peak memory 199904 kb
Host smart-569b8fd7-2db1-4996-bcaf-7d3410d511cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173114922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1173114922
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.267163503
Short name T192
Test name
Test status
Simulation time 24101770116 ps
CPU time 17.68 seconds
Started Jun 28 04:41:31 PM PDT 24
Finished Jun 28 04:41:50 PM PDT 24
Peak memory 199812 kb
Host smart-16defae8-82d2-4a52-b0e3-7832711c0259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267163503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.267163503
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.1897050154
Short name T550
Test name
Test status
Simulation time 28461767 ps
CPU time 0.55 seconds
Started Jun 28 04:37:56 PM PDT 24
Finished Jun 28 04:37:57 PM PDT 24
Peak memory 195228 kb
Host smart-d4526b68-cce3-4fc7-a4be-af20f11d027e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897050154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1897050154
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3435824886
Short name T270
Test name
Test status
Simulation time 129474148536 ps
CPU time 47.18 seconds
Started Jun 28 04:37:55 PM PDT 24
Finished Jun 28 04:38:43 PM PDT 24
Peak memory 199696 kb
Host smart-0af6707e-b53f-43c6-8de8-31f64dab635d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435824886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3435824886
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.3408672418
Short name T120
Test name
Test status
Simulation time 32417414018 ps
CPU time 28.04 seconds
Started Jun 28 04:37:56 PM PDT 24
Finished Jun 28 04:38:25 PM PDT 24
Peak memory 199840 kb
Host smart-3af6c5b4-051d-4610-9e90-a0a2811ba568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408672418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3408672418
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.726763425
Short name T749
Test name
Test status
Simulation time 51652139652 ps
CPU time 71.99 seconds
Started Jun 28 04:37:56 PM PDT 24
Finished Jun 28 04:39:09 PM PDT 24
Peak memory 199484 kb
Host smart-87bd70db-458e-40d8-bcc9-0712874a9b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726763425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.726763425
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.1188556871
Short name T386
Test name
Test status
Simulation time 28958887596 ps
CPU time 60.95 seconds
Started Jun 28 04:37:56 PM PDT 24
Finished Jun 28 04:38:58 PM PDT 24
Peak memory 199872 kb
Host smart-727a604f-105e-41dc-a237-473ab9db5a24
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188556871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.1188556871
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_loopback.30579780
Short name T348
Test name
Test status
Simulation time 10103592836 ps
CPU time 10.69 seconds
Started Jun 28 04:37:54 PM PDT 24
Finished Jun 28 04:38:05 PM PDT 24
Peak memory 199152 kb
Host smart-8c69c888-0ed3-4760-8e23-1bdc35b1acfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30579780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.30579780
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_perf.3297370314
Short name T994
Test name
Test status
Simulation time 17558053770 ps
CPU time 867.29 seconds
Started Jun 28 04:37:55 PM PDT 24
Finished Jun 28 04:52:23 PM PDT 24
Peak memory 199724 kb
Host smart-7358ee9d-b84a-42b7-add5-989fea79bc1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3297370314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3297370314
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2180399855
Short name T344
Test name
Test status
Simulation time 2208818408 ps
CPU time 12.51 seconds
Started Jun 28 04:37:54 PM PDT 24
Finished Jun 28 04:38:07 PM PDT 24
Peak memory 198388 kb
Host smart-0d6b4688-1402-462e-bed9-402c4321caf6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2180399855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2180399855
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2603529802
Short name T834
Test name
Test status
Simulation time 38035556510 ps
CPU time 32.69 seconds
Started Jun 28 04:37:56 PM PDT 24
Finished Jun 28 04:38:30 PM PDT 24
Peak memory 199832 kb
Host smart-fa2bda12-867d-4432-994f-6c0fe1102156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603529802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2603529802
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.3978471158
Short name T569
Test name
Test status
Simulation time 1676088114 ps
CPU time 3.03 seconds
Started Jun 28 04:37:53 PM PDT 24
Finished Jun 28 04:37:57 PM PDT 24
Peak memory 195508 kb
Host smart-40da7aac-cd6a-459b-9655-8e6d847e2d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978471158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3978471158
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.1475754134
Short name T379
Test name
Test status
Simulation time 486201171 ps
CPU time 1.47 seconds
Started Jun 28 04:37:56 PM PDT 24
Finished Jun 28 04:37:58 PM PDT 24
Peak memory 198684 kb
Host smart-1ddb833b-e0f2-411f-a980-8667f36342f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475754134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1475754134
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.1398525106
Short name T101
Test name
Test status
Simulation time 142870181438 ps
CPU time 82.1 seconds
Started Jun 28 04:37:56 PM PDT 24
Finished Jun 28 04:39:18 PM PDT 24
Peak memory 199752 kb
Host smart-3deb816c-e5b1-40f5-be47-2f159e5e2be1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398525106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.1398525106
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.1606795070
Short name T934
Test name
Test status
Simulation time 12340558395 ps
CPU time 33.84 seconds
Started Jun 28 04:37:55 PM PDT 24
Finished Jun 28 04:38:29 PM PDT 24
Peak memory 199772 kb
Host smart-1215297f-45db-4480-a3fb-1a0b761da846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606795070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1606795070
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.3368952815
Short name T657
Test name
Test status
Simulation time 57237610618 ps
CPU time 53.18 seconds
Started Jun 28 04:37:54 PM PDT 24
Finished Jun 28 04:38:47 PM PDT 24
Peak memory 200056 kb
Host smart-cbd81810-d4ae-4e12-9cb5-06f734af75ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368952815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.3368952815
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2296861958
Short name T791
Test name
Test status
Simulation time 17891933291 ps
CPU time 24.97 seconds
Started Jun 28 04:41:34 PM PDT 24
Finished Jun 28 04:41:59 PM PDT 24
Peak memory 199664 kb
Host smart-f49af73d-d574-4bd0-a5d4-bb0b94b515ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296861958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2296861958
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.1968488670
Short name T165
Test name
Test status
Simulation time 72822363972 ps
CPU time 228.24 seconds
Started Jun 28 04:41:31 PM PDT 24
Finished Jun 28 04:45:20 PM PDT 24
Peak memory 199844 kb
Host smart-4f157ccd-5846-4c12-9193-932735b0576c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968488670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1968488670
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3743642312
Short name T846
Test name
Test status
Simulation time 42420683810 ps
CPU time 72.2 seconds
Started Jun 28 04:41:34 PM PDT 24
Finished Jun 28 04:42:46 PM PDT 24
Peak memory 199816 kb
Host smart-7d5164f9-438c-44da-9629-6b01c940907c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743642312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3743642312
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.516580262
Short name T282
Test name
Test status
Simulation time 30426486262 ps
CPU time 59.12 seconds
Started Jun 28 04:41:35 PM PDT 24
Finished Jun 28 04:42:34 PM PDT 24
Peak memory 199884 kb
Host smart-c9ce0533-a227-4bc4-a2fe-ebbbb1c4c0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516580262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.516580262
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.2659039218
Short name T736
Test name
Test status
Simulation time 235126515760 ps
CPU time 39.29 seconds
Started Jun 28 04:41:30 PM PDT 24
Finished Jun 28 04:42:10 PM PDT 24
Peak memory 199876 kb
Host smart-e4b97d08-e369-4e83-8be6-3247804792e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659039218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2659039218
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.2931713328
Short name T172
Test name
Test status
Simulation time 18343947231 ps
CPU time 9.14 seconds
Started Jun 28 04:41:33 PM PDT 24
Finished Jun 28 04:41:43 PM PDT 24
Peak memory 199772 kb
Host smart-163fb9d5-66d6-45a7-b648-d0604e8e3a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931713328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2931713328
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.2684890029
Short name T781
Test name
Test status
Simulation time 206875222235 ps
CPU time 531.55 seconds
Started Jun 28 04:41:34 PM PDT 24
Finished Jun 28 04:50:26 PM PDT 24
Peak memory 199684 kb
Host smart-5f6ce324-3ae1-4605-b0ec-e9ef23a0af33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684890029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2684890029
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.2386273294
Short name T743
Test name
Test status
Simulation time 21139723980 ps
CPU time 29.32 seconds
Started Jun 28 04:41:42 PM PDT 24
Finished Jun 28 04:42:13 PM PDT 24
Peak memory 199460 kb
Host smart-bdbd8bcc-e91b-4fdd-8e80-aa462b261875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386273294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.2386273294
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.3843122839
Short name T523
Test name
Test status
Simulation time 5655793533 ps
CPU time 9.73 seconds
Started Jun 28 04:41:41 PM PDT 24
Finished Jun 28 04:41:52 PM PDT 24
Peak memory 199372 kb
Host smart-48925590-5e8d-470f-832f-5208581faa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843122839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3843122839
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2167225540
Short name T326
Test name
Test status
Simulation time 21250835 ps
CPU time 0.58 seconds
Started Jun 28 04:38:06 PM PDT 24
Finished Jun 28 04:38:08 PM PDT 24
Peak memory 194716 kb
Host smart-087948fd-6999-4a89-90b0-3fef9a440f67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167225540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2167225540
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.1680959660
Short name T369
Test name
Test status
Simulation time 147152801933 ps
CPU time 218.73 seconds
Started Jun 28 04:37:53 PM PDT 24
Finished Jun 28 04:41:33 PM PDT 24
Peak memory 199828 kb
Host smart-a01e26f3-3019-4459-9049-6d0f3f4c6e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680959660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1680959660
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.3189394689
Short name T643
Test name
Test status
Simulation time 88561641432 ps
CPU time 62.15 seconds
Started Jun 28 04:37:56 PM PDT 24
Finished Jun 28 04:38:59 PM PDT 24
Peak memory 199704 kb
Host smart-9a4d074c-22da-4c05-ba3e-73d1ebd1c0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189394689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.3189394689
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_intr.1425797743
Short name T544
Test name
Test status
Simulation time 58356930411 ps
CPU time 124.18 seconds
Started Jun 28 04:38:08 PM PDT 24
Finished Jun 28 04:40:14 PM PDT 24
Peak memory 199828 kb
Host smart-6b96ed15-48d1-4a70-8ff6-f69e8dd47c3b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425797743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1425797743
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.1019373474
Short name T274
Test name
Test status
Simulation time 98045231051 ps
CPU time 378.93 seconds
Started Jun 28 04:38:07 PM PDT 24
Finished Jun 28 04:44:27 PM PDT 24
Peak memory 199836 kb
Host smart-3eb489f8-17b9-4a0d-b92f-cb130315e31b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1019373474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.1019373474
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.3391205497
Short name T1070
Test name
Test status
Simulation time 8997953905 ps
CPU time 11.95 seconds
Started Jun 28 04:38:07 PM PDT 24
Finished Jun 28 04:38:21 PM PDT 24
Peak memory 199864 kb
Host smart-e6388d1a-da6f-4b71-9466-9e7abe882cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391205497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3391205497
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_perf.660079239
Short name T37
Test name
Test status
Simulation time 27301367057 ps
CPU time 213.97 seconds
Started Jun 28 04:38:08 PM PDT 24
Finished Jun 28 04:41:44 PM PDT 24
Peak memory 199796 kb
Host smart-506c27b7-213f-4b9e-94eb-9c34935f52ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=660079239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.660079239
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.3542421940
Short name T627
Test name
Test status
Simulation time 5449058225 ps
CPU time 3.79 seconds
Started Jun 28 04:37:54 PM PDT 24
Finished Jun 28 04:37:59 PM PDT 24
Peak memory 198584 kb
Host smart-c1f0ae20-9754-4e64-8384-bbc6b292df98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3542421940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3542421940
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.3060305851
Short name T560
Test name
Test status
Simulation time 8406446782 ps
CPU time 12.4 seconds
Started Jun 28 04:38:06 PM PDT 24
Finished Jun 28 04:38:19 PM PDT 24
Peak memory 199284 kb
Host smart-28373387-c9e0-4a19-87a8-dbeb67a95eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060305851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3060305851
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.2316062001
Short name T258
Test name
Test status
Simulation time 3955563937 ps
CPU time 6.32 seconds
Started Jun 28 04:38:06 PM PDT 24
Finished Jun 28 04:38:13 PM PDT 24
Peak memory 195836 kb
Host smart-e5e2d7b6-27af-4186-9bf0-3237bf6b848d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316062001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.2316062001
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.1082984345
Short name T570
Test name
Test status
Simulation time 5759336922 ps
CPU time 14.9 seconds
Started Jun 28 04:37:55 PM PDT 24
Finished Jun 28 04:38:10 PM PDT 24
Peak memory 199892 kb
Host smart-a595ac4f-038d-43c0-86b5-623e9821dd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082984345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1082984345
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.2397491642
Short name T890
Test name
Test status
Simulation time 55317990658 ps
CPU time 43.95 seconds
Started Jun 28 04:38:07 PM PDT 24
Finished Jun 28 04:38:53 PM PDT 24
Peak memory 199868 kb
Host smart-ff6bc7c7-71c8-42c2-8e57-1e70b242cd63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397491642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2397491642
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.3859034536
Short name T50
Test name
Test status
Simulation time 29775798667 ps
CPU time 687.13 seconds
Started Jun 28 04:38:05 PM PDT 24
Finished Jun 28 04:49:33 PM PDT 24
Peak memory 209236 kb
Host smart-edcc61db-9d29-4a83-941b-a9f89fd03c49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859034536 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.3859034536
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.3278735496
Short name T578
Test name
Test status
Simulation time 6576415011 ps
CPU time 20.6 seconds
Started Jun 28 04:38:06 PM PDT 24
Finished Jun 28 04:38:28 PM PDT 24
Peak memory 199352 kb
Host smart-a3ec0caf-d70d-4883-92d0-20bbe38da844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278735496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3278735496
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.3521023095
Short name T733
Test name
Test status
Simulation time 97804800205 ps
CPU time 47.38 seconds
Started Jun 28 04:37:56 PM PDT 24
Finished Jun 28 04:38:44 PM PDT 24
Peak memory 199860 kb
Host smart-331412c0-b7f3-4442-a624-065d3c52d37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521023095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.3521023095
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.1586693270
Short name T935
Test name
Test status
Simulation time 126852477804 ps
CPU time 38.22 seconds
Started Jun 28 04:41:41 PM PDT 24
Finished Jun 28 04:42:20 PM PDT 24
Peak memory 199916 kb
Host smart-6ada4c94-52f1-47ed-8c8d-c96cbd14e5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586693270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1586693270
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.3850884157
Short name T819
Test name
Test status
Simulation time 119067614630 ps
CPU time 227.84 seconds
Started Jun 28 04:41:42 PM PDT 24
Finished Jun 28 04:45:31 PM PDT 24
Peak memory 200108 kb
Host smart-d3b29cda-82d1-457f-82b0-44085a484767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850884157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.3850884157
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3839063461
Short name T477
Test name
Test status
Simulation time 11519547023 ps
CPU time 19.04 seconds
Started Jun 28 04:41:42 PM PDT 24
Finished Jun 28 04:42:03 PM PDT 24
Peak memory 199320 kb
Host smart-6d5f5f38-5a16-4da3-b349-d798915e64dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839063461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3839063461
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.3222970620
Short name T35
Test name
Test status
Simulation time 45820509348 ps
CPU time 19.5 seconds
Started Jun 28 04:41:42 PM PDT 24
Finished Jun 28 04:42:03 PM PDT 24
Peak memory 199836 kb
Host smart-7298fd43-7123-4191-9437-577e6dd7087a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222970620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3222970620
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.2163422377
Short name T474
Test name
Test status
Simulation time 12400724171 ps
CPU time 20.62 seconds
Started Jun 28 04:41:42 PM PDT 24
Finished Jun 28 04:42:04 PM PDT 24
Peak memory 199832 kb
Host smart-8a1e6f0b-015f-49fa-b6c9-b0dcbb06b1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163422377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2163422377
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.1838040325
Short name T428
Test name
Test status
Simulation time 144999907863 ps
CPU time 56.56 seconds
Started Jun 28 04:41:42 PM PDT 24
Finished Jun 28 04:42:40 PM PDT 24
Peak memory 199752 kb
Host smart-c4b10211-7193-4bb9-83f8-fbc28072550a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838040325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.1838040325
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2406878220
Short name T986
Test name
Test status
Simulation time 92177259667 ps
CPU time 53.02 seconds
Started Jun 28 04:41:41 PM PDT 24
Finished Jun 28 04:42:36 PM PDT 24
Peak memory 199916 kb
Host smart-d17bf398-532f-4a1d-a516-c84aa14e4e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406878220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2406878220
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.1232343116
Short name T700
Test name
Test status
Simulation time 40245455965 ps
CPU time 71.34 seconds
Started Jun 28 04:41:42 PM PDT 24
Finished Jun 28 04:42:55 PM PDT 24
Peak memory 199916 kb
Host smart-52afcc52-e430-4ac4-8b5f-1d9dcd100487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232343116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1232343116
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.126545583
Short name T465
Test name
Test status
Simulation time 10395725 ps
CPU time 0.56 seconds
Started Jun 28 04:36:36 PM PDT 24
Finished Jun 28 04:36:37 PM PDT 24
Peak memory 194116 kb
Host smart-9e6ebb9f-ef70-4ec2-9e9c-72a1830f028b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126545583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.126545583
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.1721381077
Short name T757
Test name
Test status
Simulation time 193291837435 ps
CPU time 70.17 seconds
Started Jun 28 04:36:32 PM PDT 24
Finished Jun 28 04:37:43 PM PDT 24
Peak memory 199904 kb
Host smart-b14c40e6-d7f8-4301-968f-c7fe03a715b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721381077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1721381077
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3362308186
Short name T572
Test name
Test status
Simulation time 123003972258 ps
CPU time 51.52 seconds
Started Jun 28 04:36:28 PM PDT 24
Finished Jun 28 04:37:20 PM PDT 24
Peak memory 199776 kb
Host smart-87ed482a-1b1a-4c18-8a69-e8ca95d986bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362308186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3362308186
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_intr.3423508280
Short name T671
Test name
Test status
Simulation time 40858398822 ps
CPU time 66.82 seconds
Started Jun 28 04:36:27 PM PDT 24
Finished Jun 28 04:37:35 PM PDT 24
Peak memory 199792 kb
Host smart-ea98c6b4-989c-4200-ad5a-365eafb14cfb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423508280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.3423508280
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.2388995191
Short name T448
Test name
Test status
Simulation time 119698089504 ps
CPU time 866.23 seconds
Started Jun 28 04:36:37 PM PDT 24
Finished Jun 28 04:51:05 PM PDT 24
Peak memory 199752 kb
Host smart-8ba2a3d3-ca78-4b06-9f95-9e1bb4274039
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2388995191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2388995191
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.1407237432
Short name T912
Test name
Test status
Simulation time 9543551547 ps
CPU time 6.54 seconds
Started Jun 28 04:36:39 PM PDT 24
Finished Jun 28 04:36:46 PM PDT 24
Peak memory 199372 kb
Host smart-8420eec4-c810-4ec3-9863-3d95b3ab798c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407237432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1407237432
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_perf.1039811002
Short name T951
Test name
Test status
Simulation time 4422592050 ps
CPU time 243.03 seconds
Started Jun 28 04:36:35 PM PDT 24
Finished Jun 28 04:40:39 PM PDT 24
Peak memory 199796 kb
Host smart-ef6f5b74-93c6-4de7-a76a-bde525e14879
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1039811002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.1039811002
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.2463785311
Short name T1021
Test name
Test status
Simulation time 2549422852 ps
CPU time 16.44 seconds
Started Jun 28 04:37:09 PM PDT 24
Finished Jun 28 04:37:26 PM PDT 24
Peak memory 197988 kb
Host smart-b92e4a1e-b09f-40ef-9c8a-dca8f129a8d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2463785311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2463785311
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1296133370
Short name T455
Test name
Test status
Simulation time 106448439527 ps
CPU time 13.2 seconds
Started Jun 28 04:36:37 PM PDT 24
Finished Jun 28 04:36:52 PM PDT 24
Peak memory 199836 kb
Host smart-1337b722-38e1-4e82-9c42-2b63a4bcce7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296133370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1296133370
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2951011231
Short name T1017
Test name
Test status
Simulation time 3188334832 ps
CPU time 5.84 seconds
Started Jun 28 04:36:35 PM PDT 24
Finished Jun 28 04:36:41 PM PDT 24
Peak memory 196628 kb
Host smart-82a86b8f-3188-48ae-850f-62cc603e1008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951011231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2951011231
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.3624129481
Short name T23
Test name
Test status
Simulation time 67948797 ps
CPU time 0.8 seconds
Started Jun 28 04:36:43 PM PDT 24
Finished Jun 28 04:36:44 PM PDT 24
Peak memory 217736 kb
Host smart-13810b9a-ed2c-4fc6-b8af-74f6187e5582
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624129481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.3624129481
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.4289023879
Short name T229
Test name
Test status
Simulation time 5850300484 ps
CPU time 3.89 seconds
Started Jun 28 04:36:32 PM PDT 24
Finished Jun 28 04:36:37 PM PDT 24
Peak memory 198924 kb
Host smart-61229087-b385-419f-8866-d00457bc87d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289023879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.4289023879
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.2852881238
Short name T193
Test name
Test status
Simulation time 150892079126 ps
CPU time 70.57 seconds
Started Jun 28 04:36:38 PM PDT 24
Finished Jun 28 04:37:50 PM PDT 24
Peak memory 199752 kb
Host smart-02ba0b5f-a1e1-422c-830b-5bc5b8b8648d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852881238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2852881238
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.2851542892
Short name T709
Test name
Test status
Simulation time 41335178098 ps
CPU time 477.44 seconds
Started Jun 28 04:36:37 PM PDT 24
Finished Jun 28 04:44:36 PM PDT 24
Peak memory 216272 kb
Host smart-535f1674-ced0-4db6-b845-f8b977af959e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851542892 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.2851542892
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1865422070
Short name T430
Test name
Test status
Simulation time 533600984 ps
CPU time 1.81 seconds
Started Jun 28 04:36:37 PM PDT 24
Finished Jun 28 04:36:40 PM PDT 24
Peak memory 198320 kb
Host smart-b3411d39-0399-4a98-8795-a2cfef354ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865422070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1865422070
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3528476360
Short name T683
Test name
Test status
Simulation time 167978780209 ps
CPU time 82.23 seconds
Started Jun 28 04:36:28 PM PDT 24
Finished Jun 28 04:37:51 PM PDT 24
Peak memory 200076 kb
Host smart-e8f99e49-ebf9-4110-ae0c-fb5cb4bf1f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528476360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3528476360
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.3548142319
Short name T327
Test name
Test status
Simulation time 11044036 ps
CPU time 0.55 seconds
Started Jun 28 04:38:05 PM PDT 24
Finished Jun 28 04:38:07 PM PDT 24
Peak memory 194104 kb
Host smart-11933d1a-6834-4a55-a637-09c26b42f8ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548142319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3548142319
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.2798967535
Short name T567
Test name
Test status
Simulation time 77157967288 ps
CPU time 14.14 seconds
Started Jun 28 04:38:07 PM PDT 24
Finished Jun 28 04:38:23 PM PDT 24
Peak memory 199848 kb
Host smart-329c2e8b-1cc7-4f36-a450-d198d36dc47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798967535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.2798967535
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.2112794154
Short name T1087
Test name
Test status
Simulation time 77947968369 ps
CPU time 33.8 seconds
Started Jun 28 04:38:07 PM PDT 24
Finished Jun 28 04:38:43 PM PDT 24
Peak memory 199880 kb
Host smart-7b0d1b56-a358-4e12-85eb-71f11b13f8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112794154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2112794154
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.709388259
Short name T767
Test name
Test status
Simulation time 77967055652 ps
CPU time 21.92 seconds
Started Jun 28 04:38:06 PM PDT 24
Finished Jun 28 04:38:29 PM PDT 24
Peak memory 199916 kb
Host smart-ba1b6567-a607-4a77-b432-0f195371f9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709388259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.709388259
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.3790289328
Short name T697
Test name
Test status
Simulation time 7059319008 ps
CPU time 15.96 seconds
Started Jun 28 04:38:07 PM PDT 24
Finished Jun 28 04:38:25 PM PDT 24
Peak memory 199900 kb
Host smart-285c1f9a-946b-4634-af83-e16c88b266d1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790289328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3790289328
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.1383742747
Short name T784
Test name
Test status
Simulation time 115575432287 ps
CPU time 418.85 seconds
Started Jun 28 04:38:05 PM PDT 24
Finished Jun 28 04:45:04 PM PDT 24
Peak memory 199880 kb
Host smart-dfd98dd0-11ce-4fdf-9b99-c13af1acd9e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1383742747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.1383742747
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2897712316
Short name T1002
Test name
Test status
Simulation time 3312691997 ps
CPU time 2.2 seconds
Started Jun 28 04:38:09 PM PDT 24
Finished Jun 28 04:38:12 PM PDT 24
Peak memory 196136 kb
Host smart-b67e3377-8300-42ba-b084-35fbe3b793c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897712316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2897712316
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_perf.2237816601
Short name T224
Test name
Test status
Simulation time 5479085885 ps
CPU time 296.01 seconds
Started Jun 28 04:38:07 PM PDT 24
Finished Jun 28 04:43:05 PM PDT 24
Peak memory 199952 kb
Host smart-ff5eef95-6e9d-4a77-999e-3369240c52e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2237816601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.2237816601
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.1087741708
Short name T876
Test name
Test status
Simulation time 4522095693 ps
CPU time 10.75 seconds
Started Jun 28 04:38:06 PM PDT 24
Finished Jun 28 04:38:18 PM PDT 24
Peak memory 198056 kb
Host smart-64afc79c-e8ce-4d10-89c9-28f9354ce0e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1087741708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1087741708
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3907602913
Short name T893
Test name
Test status
Simulation time 4765366305 ps
CPU time 2.25 seconds
Started Jun 28 04:38:06 PM PDT 24
Finished Jun 28 04:38:10 PM PDT 24
Peak memory 196148 kb
Host smart-eb38a1ef-cb11-4727-a623-5977f5c1d495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907602913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3907602913
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.842500931
Short name T533
Test name
Test status
Simulation time 5808545334 ps
CPU time 20.42 seconds
Started Jun 28 04:38:08 PM PDT 24
Finished Jun 28 04:38:30 PM PDT 24
Peak memory 199652 kb
Host smart-54056030-c87f-4720-b791-203b86ab66e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842500931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.842500931
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.1749287685
Short name T407
Test name
Test status
Simulation time 688613128748 ps
CPU time 635.72 seconds
Started Jun 28 04:38:07 PM PDT 24
Finished Jun 28 04:48:45 PM PDT 24
Peak memory 199872 kb
Host smart-9f5efd6f-8566-4d18-b72a-90c705b8c109
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749287685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1749287685
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.358942879
Short name T383
Test name
Test status
Simulation time 8321637661 ps
CPU time 15.1 seconds
Started Jun 28 04:38:08 PM PDT 24
Finished Jun 28 04:38:25 PM PDT 24
Peak memory 199892 kb
Host smart-4c5ac048-a38e-4cf1-acd2-de2c1fbfde20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358942879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.358942879
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.3253908077
Short name T754
Test name
Test status
Simulation time 38944935857 ps
CPU time 19.97 seconds
Started Jun 28 04:38:08 PM PDT 24
Finished Jun 28 04:38:30 PM PDT 24
Peak memory 199756 kb
Host smart-38800b11-c2a1-4a3f-b282-3b104786c02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253908077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3253908077
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.1447499773
Short name T243
Test name
Test status
Simulation time 180230708599 ps
CPU time 16.3 seconds
Started Jun 28 04:41:41 PM PDT 24
Finished Jun 28 04:41:59 PM PDT 24
Peak memory 199708 kb
Host smart-4cfb4fc2-5c19-40cc-8bf2-e5b896339bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447499773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1447499773
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.2563395923
Short name T885
Test name
Test status
Simulation time 254613307144 ps
CPU time 99.56 seconds
Started Jun 28 04:41:42 PM PDT 24
Finished Jun 28 04:43:24 PM PDT 24
Peak memory 199848 kb
Host smart-a4ffff35-8276-4cb7-aab0-16acdeb0b6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563395923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.2563395923
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.2736228258
Short name T687
Test name
Test status
Simulation time 40587925327 ps
CPU time 13.66 seconds
Started Jun 28 04:41:41 PM PDT 24
Finished Jun 28 04:41:56 PM PDT 24
Peak memory 199844 kb
Host smart-0553899d-4ebc-43ae-afc2-e37558fff228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736228258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2736228258
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.3277553780
Short name T141
Test name
Test status
Simulation time 77408030090 ps
CPU time 65.69 seconds
Started Jun 28 04:41:45 PM PDT 24
Finished Jun 28 04:42:51 PM PDT 24
Peak memory 199764 kb
Host smart-01f6d4ea-f6af-408c-a5d1-3984c4457fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277553780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3277553780
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.464314919
Short name T827
Test name
Test status
Simulation time 147079458265 ps
CPU time 34.86 seconds
Started Jun 28 04:41:41 PM PDT 24
Finished Jun 28 04:42:17 PM PDT 24
Peak memory 199916 kb
Host smart-1e3783db-5135-4874-82da-5263bba82651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464314919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.464314919
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.2573325878
Short name T186
Test name
Test status
Simulation time 13093993244 ps
CPU time 12.21 seconds
Started Jun 28 04:41:43 PM PDT 24
Finished Jun 28 04:41:57 PM PDT 24
Peak memory 199856 kb
Host smart-ea534a2e-09eb-456a-996f-8628d6121778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573325878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2573325878
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.686296282
Short name T732
Test name
Test status
Simulation time 47883451715 ps
CPU time 71.29 seconds
Started Jun 28 04:41:41 PM PDT 24
Finished Jun 28 04:42:53 PM PDT 24
Peak memory 199908 kb
Host smart-f22b6453-93b6-4d22-88a8-d00bd36a4aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686296282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.686296282
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.2036097740
Short name T1060
Test name
Test status
Simulation time 151894280447 ps
CPU time 56.85 seconds
Started Jun 28 04:41:41 PM PDT 24
Finished Jun 28 04:42:38 PM PDT 24
Peak memory 199804 kb
Host smart-61e3fe58-9c35-4f74-b3cc-d22edc7e7810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036097740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2036097740
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.2610528003
Short name T855
Test name
Test status
Simulation time 228956332504 ps
CPU time 78.09 seconds
Started Jun 28 04:41:42 PM PDT 24
Finished Jun 28 04:43:02 PM PDT 24
Peak memory 199856 kb
Host smart-bdf1fe0c-6221-470a-a1da-5f7240a4b2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610528003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2610528003
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.230942321
Short name T871
Test name
Test status
Simulation time 56515547326 ps
CPU time 159 seconds
Started Jun 28 04:41:42 PM PDT 24
Finished Jun 28 04:44:23 PM PDT 24
Peak memory 199796 kb
Host smart-d410c953-f510-43ac-a8df-9df5e32dab35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230942321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.230942321
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.1788931203
Short name T759
Test name
Test status
Simulation time 13908969 ps
CPU time 0.55 seconds
Started Jun 28 04:38:20 PM PDT 24
Finished Jun 28 04:38:21 PM PDT 24
Peak memory 195128 kb
Host smart-90789ad3-11ff-45f8-916f-6df1c199966c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788931203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1788931203
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.4056938304
Short name T775
Test name
Test status
Simulation time 93507830426 ps
CPU time 178 seconds
Started Jun 28 04:38:07 PM PDT 24
Finished Jun 28 04:41:07 PM PDT 24
Peak memory 199912 kb
Host smart-4c200a1a-1971-4880-b39b-248c9eb6a787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056938304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.4056938304
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.3584372528
Short name T937
Test name
Test status
Simulation time 53354451374 ps
CPU time 18.15 seconds
Started Jun 28 04:38:07 PM PDT 24
Finished Jun 28 04:38:27 PM PDT 24
Peak memory 199768 kb
Host smart-bd3a26c3-4160-4373-83b1-bc680466d9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584372528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3584372528
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.3039912611
Short name T1020
Test name
Test status
Simulation time 30655024092 ps
CPU time 49.73 seconds
Started Jun 28 04:38:06 PM PDT 24
Finished Jun 28 04:38:56 PM PDT 24
Peak memory 200012 kb
Host smart-6f6af826-8ebc-4417-adaa-9d474f217640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039912611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.3039912611
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.2212334367
Short name T941
Test name
Test status
Simulation time 19370246027 ps
CPU time 5.83 seconds
Started Jun 28 04:38:07 PM PDT 24
Finished Jun 28 04:38:14 PM PDT 24
Peak memory 198844 kb
Host smart-a76f9e2c-c1d7-4b83-a704-6da2d76c402c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212334367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2212334367
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.3339865005
Short name T765
Test name
Test status
Simulation time 36269181349 ps
CPU time 208.31 seconds
Started Jun 28 04:38:08 PM PDT 24
Finished Jun 28 04:41:38 PM PDT 24
Peak memory 199900 kb
Host smart-290346c8-03bb-4a4a-95bf-358723ec9ca6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3339865005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3339865005
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.1105040906
Short name T972
Test name
Test status
Simulation time 6490856542 ps
CPU time 7.31 seconds
Started Jun 28 04:38:07 PM PDT 24
Finished Jun 28 04:38:16 PM PDT 24
Peak memory 199920 kb
Host smart-155ba085-0678-4def-a33f-83c0b2aa3e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105040906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1105040906
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_perf.499987691
Short name T604
Test name
Test status
Simulation time 4631195638 ps
CPU time 246 seconds
Started Jun 28 04:38:06 PM PDT 24
Finished Jun 28 04:42:13 PM PDT 24
Peak memory 199956 kb
Host smart-e364daf1-2220-453d-87df-4bb09c85d179
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=499987691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.499987691
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3457104181
Short name T997
Test name
Test status
Simulation time 1775516113 ps
CPU time 8.61 seconds
Started Jun 28 04:38:06 PM PDT 24
Finished Jun 28 04:38:15 PM PDT 24
Peak memory 198036 kb
Host smart-cd98378f-2858-451e-834e-a8f3f53c3581
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3457104181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3457104181
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.2793338593
Short name T1
Test name
Test status
Simulation time 11649658791 ps
CPU time 11.32 seconds
Started Jun 28 04:38:07 PM PDT 24
Finished Jun 28 04:38:20 PM PDT 24
Peak memory 199744 kb
Host smart-f67e1e50-2b1c-4938-a6c0-29b3041854bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793338593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2793338593
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.3888569833
Short name T549
Test name
Test status
Simulation time 4974007574 ps
CPU time 1.46 seconds
Started Jun 28 04:38:09 PM PDT 24
Finished Jun 28 04:38:12 PM PDT 24
Peak memory 196064 kb
Host smart-d5889866-c27a-41a9-9194-a28ea6fdb15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888569833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.3888569833
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.3185070572
Short name T621
Test name
Test status
Simulation time 509851568 ps
CPU time 2.01 seconds
Started Jun 28 04:38:05 PM PDT 24
Finished Jun 28 04:38:08 PM PDT 24
Peak memory 198684 kb
Host smart-4c1dc21f-06cb-4d48-a184-8d468e73d209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185070572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3185070572
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.4234835246
Short name T311
Test name
Test status
Simulation time 132616190465 ps
CPU time 127.26 seconds
Started Jun 28 04:38:07 PM PDT 24
Finished Jun 28 04:40:16 PM PDT 24
Peak memory 199944 kb
Host smart-2a74bad4-26c2-426f-9a68-d684e74fefcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234835246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.4234835246
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2353287855
Short name T968
Test name
Test status
Simulation time 856902918 ps
CPU time 4.81 seconds
Started Jun 28 04:38:07 PM PDT 24
Finished Jun 28 04:38:13 PM PDT 24
Peak memory 198968 kb
Host smart-74e424d5-b32d-4f54-9fc4-77fdb5785f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353287855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2353287855
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.3720362586
Short name T310
Test name
Test status
Simulation time 44044904298 ps
CPU time 35.79 seconds
Started Jun 28 04:38:06 PM PDT 24
Finished Jun 28 04:38:44 PM PDT 24
Peak memory 199932 kb
Host smart-85fea8f3-65d3-4585-8f19-0ec284705931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720362586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3720362586
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.4241158273
Short name T174
Test name
Test status
Simulation time 113059646687 ps
CPU time 194.96 seconds
Started Jun 28 04:41:43 PM PDT 24
Finished Jun 28 04:44:59 PM PDT 24
Peak memory 199916 kb
Host smart-6b2906bb-0462-44fa-b162-1752af4f6df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241158273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.4241158273
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.2816295911
Short name T261
Test name
Test status
Simulation time 56805974123 ps
CPU time 12.36 seconds
Started Jun 28 04:41:41 PM PDT 24
Finished Jun 28 04:41:55 PM PDT 24
Peak memory 198392 kb
Host smart-6e1954d7-6c93-42ad-ba84-c4c1c0dfba61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816295911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2816295911
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.2330979680
Short name T1062
Test name
Test status
Simulation time 207466378738 ps
CPU time 241.06 seconds
Started Jun 28 04:41:45 PM PDT 24
Finished Jun 28 04:45:47 PM PDT 24
Peak memory 199800 kb
Host smart-a4bd22a3-dbec-436c-a092-2ac3262f171d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330979680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2330979680
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.1145392383
Short name T257
Test name
Test status
Simulation time 73528337671 ps
CPU time 56.14 seconds
Started Jun 28 04:41:51 PM PDT 24
Finished Jun 28 04:42:49 PM PDT 24
Peak memory 199668 kb
Host smart-8fb56273-14de-46b0-b11e-f096f88c2d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145392383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.1145392383
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.743864377
Short name T441
Test name
Test status
Simulation time 80216675175 ps
CPU time 210.87 seconds
Started Jun 28 04:41:50 PM PDT 24
Finished Jun 28 04:45:22 PM PDT 24
Peak memory 199912 kb
Host smart-2f49cae8-36e0-433f-88b0-9b06ba649656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743864377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.743864377
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.402368795
Short name T96
Test name
Test status
Simulation time 42616991357 ps
CPU time 37.1 seconds
Started Jun 28 04:41:52 PM PDT 24
Finished Jun 28 04:42:30 PM PDT 24
Peak memory 199860 kb
Host smart-623030d4-0e52-4ca5-800e-7a5c869cdb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402368795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.402368795
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.3540915528
Short name T865
Test name
Test status
Simulation time 150630765126 ps
CPU time 436.66 seconds
Started Jun 28 04:41:52 PM PDT 24
Finished Jun 28 04:49:10 PM PDT 24
Peak memory 199916 kb
Host smart-b64bc093-ab11-44d4-a804-e6f31f370acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540915528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3540915528
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.2523701086
Short name T880
Test name
Test status
Simulation time 127503145822 ps
CPU time 250.89 seconds
Started Jun 28 04:41:50 PM PDT 24
Finished Jun 28 04:46:02 PM PDT 24
Peak memory 199840 kb
Host smart-777130f6-d491-42fa-9279-da59ac29464b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523701086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.2523701086
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.2792474552
Short name T1092
Test name
Test status
Simulation time 49099258605 ps
CPU time 79.76 seconds
Started Jun 28 04:41:52 PM PDT 24
Finished Jun 28 04:43:12 PM PDT 24
Peak memory 199640 kb
Host smart-66097415-70a3-4dcf-870c-3bb50411ede4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792474552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2792474552
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1900490630
Short name T1081
Test name
Test status
Simulation time 73918224731 ps
CPU time 99.18 seconds
Started Jun 28 04:41:53 PM PDT 24
Finished Jun 28 04:43:33 PM PDT 24
Peak memory 199896 kb
Host smart-100cb95e-c3dc-480c-88f3-16fd0ba8ddef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900490630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1900490630
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.3408135570
Short name T341
Test name
Test status
Simulation time 48677765 ps
CPU time 0.55 seconds
Started Jun 28 04:38:19 PM PDT 24
Finished Jun 28 04:38:21 PM PDT 24
Peak memory 195432 kb
Host smart-58bd6a62-4011-42d4-b566-ae616195b312
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408135570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.3408135570
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.3299345291
Short name T503
Test name
Test status
Simulation time 88721430195 ps
CPU time 67.84 seconds
Started Jun 28 04:38:24 PM PDT 24
Finished Jun 28 04:39:32 PM PDT 24
Peak memory 200048 kb
Host smart-535dd066-589e-4751-881e-b5ae130784db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299345291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3299345291
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2583105120
Short name T548
Test name
Test status
Simulation time 29006386210 ps
CPU time 28.16 seconds
Started Jun 28 04:38:22 PM PDT 24
Finished Jun 28 04:38:52 PM PDT 24
Peak memory 199796 kb
Host smart-6974ff04-b8a3-480a-ae30-efd0b51acf65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583105120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2583105120
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.3347962360
Short name T793
Test name
Test status
Simulation time 135090424973 ps
CPU time 97.86 seconds
Started Jun 28 04:38:22 PM PDT 24
Finished Jun 28 04:40:02 PM PDT 24
Peak memory 199760 kb
Host smart-10243ff0-ef07-4f4c-b6aa-14774002b56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347962360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3347962360
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.4236219104
Short name T1089
Test name
Test status
Simulation time 3824955374 ps
CPU time 1.16 seconds
Started Jun 28 04:38:22 PM PDT 24
Finished Jun 28 04:38:25 PM PDT 24
Peak memory 196636 kb
Host smart-6501d1c2-5007-44df-8af3-a8be25645f48
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236219104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.4236219104
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.1724132657
Short name T711
Test name
Test status
Simulation time 99110336900 ps
CPU time 190.7 seconds
Started Jun 28 04:38:19 PM PDT 24
Finished Jun 28 04:41:30 PM PDT 24
Peak memory 199836 kb
Host smart-7a652a52-b6bf-4146-9320-b9dd26ba21ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1724132657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1724132657
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.835228292
Short name T790
Test name
Test status
Simulation time 10659051262 ps
CPU time 20.07 seconds
Started Jun 28 04:38:22 PM PDT 24
Finished Jun 28 04:38:44 PM PDT 24
Peak memory 199528 kb
Host smart-8e306617-4283-42ef-85ed-adbf5b59ebe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835228292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.835228292
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_perf.2520286311
Short name T887
Test name
Test status
Simulation time 4389462165 ps
CPU time 239.82 seconds
Started Jun 28 04:38:20 PM PDT 24
Finished Jun 28 04:42:20 PM PDT 24
Peak memory 199832 kb
Host smart-f9ee9d23-ca50-4433-98a4-a58e71715a16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2520286311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2520286311
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.1012327662
Short name T956
Test name
Test status
Simulation time 2336859356 ps
CPU time 14.71 seconds
Started Jun 28 04:38:19 PM PDT 24
Finished Jun 28 04:38:35 PM PDT 24
Peak memory 198460 kb
Host smart-be555c0a-0975-4c31-9132-bdb216a9777d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1012327662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1012327662
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.2814960171
Short name T491
Test name
Test status
Simulation time 30547802946 ps
CPU time 43.05 seconds
Started Jun 28 04:38:20 PM PDT 24
Finished Jun 28 04:39:05 PM PDT 24
Peak memory 199892 kb
Host smart-2e1ba66e-adc1-4670-9374-74c6ec89d400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814960171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2814960171
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.43882493
Short name T824
Test name
Test status
Simulation time 2085469653 ps
CPU time 1.44 seconds
Started Jun 28 04:38:20 PM PDT 24
Finished Jun 28 04:38:22 PM PDT 24
Peak memory 195340 kb
Host smart-dc16217e-ce29-4876-a9a0-df96d8a75649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43882493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.43882493
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1741927862
Short name T371
Test name
Test status
Simulation time 899983517 ps
CPU time 3.9 seconds
Started Jun 28 04:38:22 PM PDT 24
Finished Jun 28 04:38:28 PM PDT 24
Peak memory 199832 kb
Host smart-0c6fb77b-fb76-415e-a874-55932794bd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741927862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1741927862
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.1251154116
Short name T433
Test name
Test status
Simulation time 25142063931 ps
CPU time 27.79 seconds
Started Jun 28 04:38:22 PM PDT 24
Finished Jun 28 04:38:51 PM PDT 24
Peak memory 199824 kb
Host smart-a093e5ce-1130-4a93-aae0-6fc8042bb02f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251154116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1251154116
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.3861502917
Short name T269
Test name
Test status
Simulation time 780969018 ps
CPU time 1.24 seconds
Started Jun 28 04:38:23 PM PDT 24
Finished Jun 28 04:38:25 PM PDT 24
Peak memory 198608 kb
Host smart-124a4144-7dc0-4f2e-b4a5-eb10bc094476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861502917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.3861502917
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3518000741
Short name T439
Test name
Test status
Simulation time 12142278701 ps
CPU time 31.22 seconds
Started Jun 28 04:38:19 PM PDT 24
Finished Jun 28 04:38:51 PM PDT 24
Peak memory 199884 kb
Host smart-c3570cef-fd7a-496f-ac9e-b02b0447e825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518000741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3518000741
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.2807677065
Short name T792
Test name
Test status
Simulation time 52329957193 ps
CPU time 25.4 seconds
Started Jun 28 04:41:50 PM PDT 24
Finished Jun 28 04:42:16 PM PDT 24
Peak memory 199916 kb
Host smart-86a4c400-21b4-4a05-821e-dfaa729fc848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807677065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2807677065
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.4151089564
Short name T453
Test name
Test status
Simulation time 20808300173 ps
CPU time 33.25 seconds
Started Jun 28 04:41:51 PM PDT 24
Finished Jun 28 04:42:25 PM PDT 24
Peak memory 199784 kb
Host smart-baf1dc2f-9ac9-409e-99f6-733f07720912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151089564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.4151089564
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1408233283
Short name T219
Test name
Test status
Simulation time 22608189437 ps
CPU time 9.24 seconds
Started Jun 28 04:41:52 PM PDT 24
Finished Jun 28 04:42:02 PM PDT 24
Peak memory 199800 kb
Host smart-a53139ce-b644-46a9-bc82-7f49af94408e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408233283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1408233283
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3075410673
Short name T205
Test name
Test status
Simulation time 3588237467 ps
CPU time 10.58 seconds
Started Jun 28 04:41:52 PM PDT 24
Finished Jun 28 04:42:04 PM PDT 24
Peak memory 199852 kb
Host smart-92bbdb52-32f3-4ec3-9326-cd5140c4126d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075410673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3075410673
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.1235560334
Short name T1030
Test name
Test status
Simulation time 63323987227 ps
CPU time 27.11 seconds
Started Jun 28 04:41:50 PM PDT 24
Finished Jun 28 04:42:17 PM PDT 24
Peak memory 199580 kb
Host smart-825dd0d1-b0ed-4574-907c-fcb83daef6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235560334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1235560334
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3575463016
Short name T902
Test name
Test status
Simulation time 20538613435 ps
CPU time 59.29 seconds
Started Jun 28 04:41:53 PM PDT 24
Finished Jun 28 04:42:53 PM PDT 24
Peak memory 199940 kb
Host smart-9294f6ed-0f2e-4bb5-a681-dbe62cf34de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575463016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3575463016
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1616381626
Short name T158
Test name
Test status
Simulation time 31433105894 ps
CPU time 18.07 seconds
Started Jun 28 04:41:50 PM PDT 24
Finished Jun 28 04:42:09 PM PDT 24
Peak memory 199832 kb
Host smart-89e13379-162a-4d14-b556-17b38468dc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616381626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1616381626
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.1983335133
Short name T980
Test name
Test status
Simulation time 28295991 ps
CPU time 0.57 seconds
Started Jun 28 04:38:20 PM PDT 24
Finished Jun 28 04:38:22 PM PDT 24
Peak memory 195084 kb
Host smart-07db39b8-ed7c-4c1c-b02b-c5c7ff681b9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983335133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1983335133
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.1538031335
Short name T910
Test name
Test status
Simulation time 44743297787 ps
CPU time 70.3 seconds
Started Jun 28 04:38:21 PM PDT 24
Finished Jun 28 04:39:33 PM PDT 24
Peak memory 199832 kb
Host smart-64dd6b7d-1596-4164-a011-16733dc8f1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538031335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1538031335
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.674267081
Short name T281
Test name
Test status
Simulation time 64842284059 ps
CPU time 49 seconds
Started Jun 28 04:38:25 PM PDT 24
Finished Jun 28 04:39:15 PM PDT 24
Peak memory 199504 kb
Host smart-0d43c2d3-cdee-4f51-ac44-b7d7d35a9394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674267081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.674267081
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_intr.2074735870
Short name T403
Test name
Test status
Simulation time 15024454210 ps
CPU time 6.97 seconds
Started Jun 28 04:38:22 PM PDT 24
Finished Jun 28 04:38:30 PM PDT 24
Peak memory 196492 kb
Host smart-c691e205-c860-40d6-be52-e9a6cb12431b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074735870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2074735870
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.3031108995
Short name T356
Test name
Test status
Simulation time 36256699118 ps
CPU time 185.19 seconds
Started Jun 28 04:38:20 PM PDT 24
Finished Jun 28 04:41:26 PM PDT 24
Peak memory 199840 kb
Host smart-6f071a95-3826-41c5-99e8-e93b5e2c0f1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3031108995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.3031108995
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.2900748018
Short name T674
Test name
Test status
Simulation time 4984070528 ps
CPU time 7.49 seconds
Started Jun 28 04:38:23 PM PDT 24
Finished Jun 28 04:38:31 PM PDT 24
Peak memory 198672 kb
Host smart-8fa9b30d-7c8a-4989-bf51-ebd4a34534f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900748018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.2900748018
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_perf.470168116
Short name T389
Test name
Test status
Simulation time 18789102219 ps
CPU time 277.13 seconds
Started Jun 28 04:38:21 PM PDT 24
Finished Jun 28 04:43:00 PM PDT 24
Peak memory 199720 kb
Host smart-b3b8c105-c39d-415c-8354-e9a2776089fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=470168116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.470168116
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.4234860221
Short name T519
Test name
Test status
Simulation time 3348170248 ps
CPU time 22.51 seconds
Started Jun 28 04:38:20 PM PDT 24
Finished Jun 28 04:38:44 PM PDT 24
Peak memory 198032 kb
Host smart-75bdb988-83dc-45b0-81ff-dc76dae1003a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4234860221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.4234860221
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.3335095729
Short name T816
Test name
Test status
Simulation time 126585015038 ps
CPU time 96.9 seconds
Started Jun 28 04:38:25 PM PDT 24
Finished Jun 28 04:40:03 PM PDT 24
Peak memory 199704 kb
Host smart-1f01153d-f3ef-4c60-a059-5221152aedd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335095729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3335095729
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.3296107119
Short name T328
Test name
Test status
Simulation time 622710032 ps
CPU time 1.72 seconds
Started Jun 28 04:38:20 PM PDT 24
Finished Jun 28 04:38:23 PM PDT 24
Peak memory 195320 kb
Host smart-bead22bc-8bbc-44a1-bfef-e8bea4abbb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296107119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.3296107119
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.160566976
Short name T571
Test name
Test status
Simulation time 697723300 ps
CPU time 2.92 seconds
Started Jun 28 04:38:20 PM PDT 24
Finished Jun 28 04:38:24 PM PDT 24
Peak memory 199564 kb
Host smart-653ef63a-568e-493d-9e12-b71541244a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160566976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.160566976
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.1581188794
Short name T385
Test name
Test status
Simulation time 652583908 ps
CPU time 2.57 seconds
Started Jun 28 04:38:25 PM PDT 24
Finished Jun 28 04:38:28 PM PDT 24
Peak memory 199624 kb
Host smart-9b724497-5ba6-4f80-a044-8c263f3d21c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581188794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1581188794
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.890854679
Short name T913
Test name
Test status
Simulation time 43167605479 ps
CPU time 14.02 seconds
Started Jun 28 04:38:22 PM PDT 24
Finished Jun 28 04:38:37 PM PDT 24
Peak memory 199756 kb
Host smart-fef43a49-72bd-48ee-955e-a53b15eb9d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890854679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.890854679
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.4124517930
Short name T462
Test name
Test status
Simulation time 57455035950 ps
CPU time 25.62 seconds
Started Jun 28 04:41:53 PM PDT 24
Finished Jun 28 04:42:19 PM PDT 24
Peak memory 199916 kb
Host smart-bcb65596-6353-4751-b843-25f2c91e2cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124517930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.4124517930
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3942701748
Short name T388
Test name
Test status
Simulation time 112963921905 ps
CPU time 40.59 seconds
Started Jun 28 04:41:51 PM PDT 24
Finished Jun 28 04:42:33 PM PDT 24
Peak memory 199708 kb
Host smart-25ff516d-48b8-4607-a7df-1850f404fa34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942701748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3942701748
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.2751376732
Short name T291
Test name
Test status
Simulation time 40476231359 ps
CPU time 33.09 seconds
Started Jun 28 04:41:50 PM PDT 24
Finished Jun 28 04:42:24 PM PDT 24
Peak memory 199832 kb
Host smart-a8de64fe-5c96-479a-90fa-c4e7e428647f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751376732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2751376732
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.4083549907
Short name T857
Test name
Test status
Simulation time 29294541108 ps
CPU time 28.4 seconds
Started Jun 28 04:41:51 PM PDT 24
Finished Jun 28 04:42:20 PM PDT 24
Peak memory 199796 kb
Host smart-494ac309-6f39-4a5e-850c-530feb32f8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083549907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.4083549907
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.141477931
Short name T1086
Test name
Test status
Simulation time 169486462086 ps
CPU time 58.33 seconds
Started Jun 28 04:41:57 PM PDT 24
Finished Jun 28 04:42:56 PM PDT 24
Peak memory 199836 kb
Host smart-3b3ac0bb-b7a9-4a37-ab08-05abdce3e6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141477931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.141477931
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.428247948
Short name T127
Test name
Test status
Simulation time 142422336130 ps
CPU time 122.55 seconds
Started Jun 28 04:41:52 PM PDT 24
Finished Jun 28 04:43:55 PM PDT 24
Peak memory 200016 kb
Host smart-dee4f625-5b58-4e62-8d39-5aa8f32e7ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428247948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.428247948
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.1635501149
Short name T1014
Test name
Test status
Simulation time 11947004837 ps
CPU time 10.85 seconds
Started Jun 28 04:41:51 PM PDT 24
Finished Jun 28 04:42:03 PM PDT 24
Peak memory 199936 kb
Host smart-7ecb0066-bee6-4182-bc20-1efb79edaa5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635501149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1635501149
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.786005502
Short name T233
Test name
Test status
Simulation time 125275122381 ps
CPU time 119.31 seconds
Started Jun 28 04:41:51 PM PDT 24
Finished Jun 28 04:43:52 PM PDT 24
Peak memory 199916 kb
Host smart-4b43b04c-9e9a-4139-9517-664ab2fab275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786005502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.786005502
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.3913226705
Short name T741
Test name
Test status
Simulation time 23031416424 ps
CPU time 38.08 seconds
Started Jun 28 04:41:52 PM PDT 24
Finished Jun 28 04:42:31 PM PDT 24
Peak memory 199832 kb
Host smart-fd059687-0f10-4766-a94d-6f7fc6cb4a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913226705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3913226705
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.4072222951
Short name T858
Test name
Test status
Simulation time 10640041108 ps
CPU time 16.32 seconds
Started Jun 28 04:41:52 PM PDT 24
Finished Jun 28 04:42:09 PM PDT 24
Peak memory 199812 kb
Host smart-eeebfd8c-ced8-4246-97a7-34dba85a774a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072222951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.4072222951
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.355214858
Short name T337
Test name
Test status
Simulation time 82486272 ps
CPU time 0.55 seconds
Started Jun 28 04:38:36 PM PDT 24
Finished Jun 28 04:38:37 PM PDT 24
Peak memory 195232 kb
Host smart-57e949dd-7049-4ee5-817c-9af7851eece3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355214858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.355214858
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.2886535861
Short name T699
Test name
Test status
Simulation time 43435264992 ps
CPU time 22.4 seconds
Started Jun 28 04:38:20 PM PDT 24
Finished Jun 28 04:38:43 PM PDT 24
Peak memory 199852 kb
Host smart-d80c5a31-db8e-4472-8cc0-f1312468c69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886535861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2886535861
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.2507760951
Short name T863
Test name
Test status
Simulation time 149816183015 ps
CPU time 158.38 seconds
Started Jun 28 04:38:22 PM PDT 24
Finished Jun 28 04:41:02 PM PDT 24
Peak memory 199776 kb
Host smart-d0739e62-ff04-4613-8200-7d515d698368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507760951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2507760951
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_intr.3834905473
Short name T593
Test name
Test status
Simulation time 32636345927 ps
CPU time 13.18 seconds
Started Jun 28 04:38:21 PM PDT 24
Finished Jun 28 04:38:36 PM PDT 24
Peak memory 199884 kb
Host smart-ae39e6f2-8d23-4f8a-b697-f45176a90d74
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834905473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3834905473
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.223155364
Short name T557
Test name
Test status
Simulation time 154815486449 ps
CPU time 940.38 seconds
Started Jun 28 04:38:41 PM PDT 24
Finished Jun 28 04:54:22 PM PDT 24
Peak memory 199812 kb
Host smart-89f6562c-66c7-43c7-ad0c-ea5a872a4c58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=223155364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.223155364
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.659281861
Short name T727
Test name
Test status
Simulation time 4547046462 ps
CPU time 2.99 seconds
Started Jun 28 04:38:31 PM PDT 24
Finished Jun 28 04:38:36 PM PDT 24
Peak memory 197736 kb
Host smart-4c07e7dc-7cc8-49af-96a2-07ee26cc6096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659281861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.659281861
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_perf.2986617642
Short name T923
Test name
Test status
Simulation time 14027588897 ps
CPU time 174.15 seconds
Started Jun 28 04:38:37 PM PDT 24
Finished Jun 28 04:41:31 PM PDT 24
Peak memory 199812 kb
Host smart-db917176-599b-4878-bd28-07ce463cd1ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2986617642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2986617642
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1003587184
Short name T343
Test name
Test status
Simulation time 5979497479 ps
CPU time 57.05 seconds
Started Jun 28 04:38:26 PM PDT 24
Finished Jun 28 04:39:23 PM PDT 24
Peak memory 198784 kb
Host smart-76419e94-a60b-43e5-8d92-a7ba575477cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1003587184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1003587184
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.3120404650
Short name T1064
Test name
Test status
Simulation time 121347456153 ps
CPU time 174.86 seconds
Started Jun 28 04:38:21 PM PDT 24
Finished Jun 28 04:41:17 PM PDT 24
Peak memory 199832 kb
Host smart-0559070b-0976-48bb-bc67-85dd51e0bdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120404650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3120404650
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1909672060
Short name T563
Test name
Test status
Simulation time 5579260381 ps
CPU time 2.68 seconds
Started Jun 28 04:38:22 PM PDT 24
Finished Jun 28 04:38:26 PM PDT 24
Peak memory 195900 kb
Host smart-f0655675-94ff-43d4-bd0f-e9819c53c7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909672060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1909672060
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.4155629718
Short name T394
Test name
Test status
Simulation time 5466777504 ps
CPU time 22.53 seconds
Started Jun 28 04:38:24 PM PDT 24
Finished Jun 28 04:38:48 PM PDT 24
Peak memory 199740 kb
Host smart-34146800-e3c6-46b0-946a-90115805743d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155629718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.4155629718
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.1355193480
Short name T242
Test name
Test status
Simulation time 134967847893 ps
CPU time 320.51 seconds
Started Jun 28 04:38:31 PM PDT 24
Finished Jun 28 04:43:53 PM PDT 24
Peak memory 199784 kb
Host smart-f1a805a6-1428-4150-8b8b-57c1be685ea1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355193480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.1355193480
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.2239581357
Short name T6
Test name
Test status
Simulation time 16138970705 ps
CPU time 454.87 seconds
Started Jun 28 04:38:33 PM PDT 24
Finished Jun 28 04:46:10 PM PDT 24
Peak memory 215876 kb
Host smart-b7e96186-0624-4f00-8dad-e8e20cc8bf20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239581357 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.2239581357
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.1006810423
Short name T565
Test name
Test status
Simulation time 4266644291 ps
CPU time 2.24 seconds
Started Jun 28 04:38:25 PM PDT 24
Finished Jun 28 04:38:28 PM PDT 24
Peak memory 199304 kb
Host smart-289bf6aa-68e5-4364-9557-de570066169e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006810423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1006810423
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.248641395
Short name T112
Test name
Test status
Simulation time 69367136534 ps
CPU time 79.48 seconds
Started Jun 28 04:38:20 PM PDT 24
Finished Jun 28 04:39:40 PM PDT 24
Peak memory 199904 kb
Host smart-35fc1309-94a8-4103-888b-c0544867c05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248641395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.248641395
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1030512268
Short name T1063
Test name
Test status
Simulation time 126875787805 ps
CPU time 58.94 seconds
Started Jun 28 04:42:01 PM PDT 24
Finished Jun 28 04:43:01 PM PDT 24
Peak memory 199880 kb
Host smart-9cff9303-c1d6-4277-bc0b-f4a4600c39cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030512268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1030512268
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.502036962
Short name T438
Test name
Test status
Simulation time 30124793283 ps
CPU time 11.77 seconds
Started Jun 28 04:42:03 PM PDT 24
Finished Jun 28 04:42:15 PM PDT 24
Peak memory 199816 kb
Host smart-86346e33-c6ed-4bdd-8c0f-dafdb9e1e111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502036962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.502036962
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.2826629206
Short name T180
Test name
Test status
Simulation time 16517280407 ps
CPU time 26.8 seconds
Started Jun 28 04:42:04 PM PDT 24
Finished Jun 28 04:42:32 PM PDT 24
Peak memory 199776 kb
Host smart-d0ab7ea5-3fc5-427e-b231-5346a523062f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826629206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2826629206
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.3362420415
Short name T396
Test name
Test status
Simulation time 182024890571 ps
CPU time 283.63 seconds
Started Jun 28 04:42:04 PM PDT 24
Finished Jun 28 04:46:48 PM PDT 24
Peak memory 199832 kb
Host smart-9cdde84a-aedb-4e82-ae43-d8114937586d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362420415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3362420415
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.2771947399
Short name T719
Test name
Test status
Simulation time 16734396916 ps
CPU time 24.27 seconds
Started Jun 28 04:42:02 PM PDT 24
Finished Jun 28 04:42:26 PM PDT 24
Peak memory 200036 kb
Host smart-8e082b0b-2266-4a9e-a725-77219b48bfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771947399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2771947399
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.4184274220
Short name T319
Test name
Test status
Simulation time 16604201070 ps
CPU time 26.34 seconds
Started Jun 28 04:42:03 PM PDT 24
Finished Jun 28 04:42:30 PM PDT 24
Peak memory 199784 kb
Host smart-5e46612f-f22e-48de-8b1d-aa1e02a90039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184274220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.4184274220
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.4074128736
Short name T836
Test name
Test status
Simulation time 149102904269 ps
CPU time 24.76 seconds
Started Jun 28 04:42:04 PM PDT 24
Finished Jun 28 04:42:29 PM PDT 24
Peak memory 199812 kb
Host smart-a73774c2-f601-43cc-875d-c577aefe4b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074128736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.4074128736
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.2115681671
Short name T652
Test name
Test status
Simulation time 15342242 ps
CPU time 0.55 seconds
Started Jun 28 04:38:33 PM PDT 24
Finished Jun 28 04:38:35 PM PDT 24
Peak memory 195228 kb
Host smart-54a8ea09-7d08-4e2b-81a9-79e63ab7ec89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115681671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2115681671
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.3463970593
Short name T103
Test name
Test status
Simulation time 79721979085 ps
CPU time 128.85 seconds
Started Jun 28 04:38:32 PM PDT 24
Finished Jun 28 04:40:42 PM PDT 24
Peak memory 199868 kb
Host smart-82a100d5-a3ae-4e27-9ed2-b3376eecaf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463970593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.3463970593
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.3389560855
Short name T633
Test name
Test status
Simulation time 78412146508 ps
CPU time 241.32 seconds
Started Jun 28 04:38:30 PM PDT 24
Finished Jun 28 04:42:33 PM PDT 24
Peak memory 199828 kb
Host smart-60efc906-71c4-49ce-9d39-9786d218f9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389560855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.3389560855
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.1955897723
Short name T588
Test name
Test status
Simulation time 69837566491 ps
CPU time 26.55 seconds
Started Jun 28 04:38:30 PM PDT 24
Finished Jun 28 04:38:58 PM PDT 24
Peak memory 199828 kb
Host smart-fadfe3b9-1f2d-4d6a-9ad8-49046e56ae12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955897723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1955897723
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.2670452305
Short name T662
Test name
Test status
Simulation time 43161372173 ps
CPU time 11.65 seconds
Started Jun 28 04:38:32 PM PDT 24
Finished Jun 28 04:38:45 PM PDT 24
Peak memory 199900 kb
Host smart-7e3ce4a7-f0e3-43b6-b132-ff1a501bb19f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670452305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2670452305
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.955097638
Short name T559
Test name
Test status
Simulation time 214972898318 ps
CPU time 302.69 seconds
Started Jun 28 04:38:30 PM PDT 24
Finished Jun 28 04:43:34 PM PDT 24
Peak memory 199748 kb
Host smart-319551d4-016f-45ff-bd7d-0b9848f246fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=955097638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.955097638
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.4286765917
Short name T606
Test name
Test status
Simulation time 5639962678 ps
CPU time 9.72 seconds
Started Jun 28 04:38:32 PM PDT 24
Finished Jun 28 04:38:43 PM PDT 24
Peak memory 198676 kb
Host smart-c6e5a1de-73a0-4874-82c8-7a8965a3f472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286765917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.4286765917
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.915266071
Short name T964
Test name
Test status
Simulation time 10457763182 ps
CPU time 14.25 seconds
Started Jun 28 04:38:34 PM PDT 24
Finished Jun 28 04:38:49 PM PDT 24
Peak memory 197216 kb
Host smart-129b3509-501e-40c5-8dd9-facfc3d6f46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915266071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.915266071
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.4252942037
Short name T686
Test name
Test status
Simulation time 5778867975 ps
CPU time 312.58 seconds
Started Jun 28 04:38:36 PM PDT 24
Finished Jun 28 04:43:50 PM PDT 24
Peak memory 199800 kb
Host smart-682d1872-d0c4-4482-9806-c0c7b3ae8be0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4252942037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.4252942037
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.1840814980
Short name T484
Test name
Test status
Simulation time 2210814185 ps
CPU time 12.49 seconds
Started Jun 28 04:38:29 PM PDT 24
Finished Jun 28 04:38:42 PM PDT 24
Peak memory 198636 kb
Host smart-dab755df-c1e8-40dd-8311-ffb1501067d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1840814980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1840814980
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.3796292164
Short name T734
Test name
Test status
Simulation time 94145203243 ps
CPU time 117.73 seconds
Started Jun 28 04:38:30 PM PDT 24
Finished Jun 28 04:40:29 PM PDT 24
Peak memory 199768 kb
Host smart-c8658bed-14a0-4800-b3fd-523eec03a499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796292164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3796292164
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.2773652848
Short name T289
Test name
Test status
Simulation time 3861967248 ps
CPU time 6.29 seconds
Started Jun 28 04:38:37 PM PDT 24
Finished Jun 28 04:38:43 PM PDT 24
Peak memory 196068 kb
Host smart-c46652d7-1852-403c-8619-3165cc98c95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773652848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.2773652848
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.204385689
Short name T626
Test name
Test status
Simulation time 272826290 ps
CPU time 1.2 seconds
Started Jun 28 04:38:29 PM PDT 24
Finished Jun 28 04:38:31 PM PDT 24
Peak memory 199388 kb
Host smart-e451f0c0-638d-4f57-8a6e-1c9e91b05e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204385689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.204385689
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.2141240017
Short name T576
Test name
Test status
Simulation time 2733538550 ps
CPU time 2.37 seconds
Started Jun 28 04:38:35 PM PDT 24
Finished Jun 28 04:38:38 PM PDT 24
Peak memory 198452 kb
Host smart-b2e337ca-eb98-489c-94a6-a691e681b8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141240017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2141240017
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.917780440
Short name T253
Test name
Test status
Simulation time 25745588598 ps
CPU time 20.85 seconds
Started Jun 28 04:38:36 PM PDT 24
Finished Jun 28 04:38:57 PM PDT 24
Peak memory 199412 kb
Host smart-4f607e95-b1c0-49b4-b89c-e1d0a774e071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917780440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.917780440
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.1930134222
Short name T378
Test name
Test status
Simulation time 15907182673 ps
CPU time 32.67 seconds
Started Jun 28 04:42:02 PM PDT 24
Finished Jun 28 04:42:35 PM PDT 24
Peak memory 199760 kb
Host smart-6625a74d-9f30-4ad9-9f65-2f1c6f6a7971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930134222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1930134222
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.4239784482
Short name T284
Test name
Test status
Simulation time 126133417839 ps
CPU time 187.98 seconds
Started Jun 28 04:42:03 PM PDT 24
Finished Jun 28 04:45:12 PM PDT 24
Peak memory 199904 kb
Host smart-464d1046-c07e-4044-aacb-9e79f63fb6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239784482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.4239784482
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2985847959
Short name T640
Test name
Test status
Simulation time 16713492167 ps
CPU time 18.59 seconds
Started Jun 28 04:42:02 PM PDT 24
Finished Jun 28 04:42:21 PM PDT 24
Peak memory 199684 kb
Host smart-bfd97dc0-e71e-4760-92fa-2e0d6753e6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985847959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2985847959
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.3301159072
Short name T1048
Test name
Test status
Simulation time 219755766052 ps
CPU time 166.02 seconds
Started Jun 28 04:42:03 PM PDT 24
Finished Jun 28 04:44:49 PM PDT 24
Peak memory 199912 kb
Host smart-6c3477af-ab56-4c2b-a6f9-3b7d252e7eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301159072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3301159072
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.221824425
Short name T471
Test name
Test status
Simulation time 57103900136 ps
CPU time 21.24 seconds
Started Jun 28 04:42:03 PM PDT 24
Finished Jun 28 04:42:24 PM PDT 24
Peak memory 199848 kb
Host smart-5891d7c6-4f2c-4ab8-8eea-25cddeda7d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221824425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.221824425
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.3292848463
Short name T825
Test name
Test status
Simulation time 81145496789 ps
CPU time 103.59 seconds
Started Jun 28 04:42:03 PM PDT 24
Finished Jun 28 04:43:47 PM PDT 24
Peak memory 199840 kb
Host smart-49cbb8d2-11ce-4daf-8bdf-d7cda42a70ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292848463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.3292848463
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.3910472731
Short name T1056
Test name
Test status
Simulation time 104003458299 ps
CPU time 841.72 seconds
Started Jun 28 04:42:02 PM PDT 24
Finished Jun 28 04:56:04 PM PDT 24
Peak memory 199860 kb
Host smart-ccc77bb5-088e-4029-80b2-c37b1e81f26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910472731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.3910472731
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.3070478465
Short name T798
Test name
Test status
Simulation time 90754634332 ps
CPU time 65.03 seconds
Started Jun 28 04:42:02 PM PDT 24
Finished Jun 28 04:43:08 PM PDT 24
Peak memory 199876 kb
Host smart-457b70f3-bf3c-41b9-ae29-ab025f13a995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070478465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3070478465
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.2002846524
Short name T135
Test name
Test status
Simulation time 44801808525 ps
CPU time 17.01 seconds
Started Jun 28 04:42:15 PM PDT 24
Finished Jun 28 04:42:33 PM PDT 24
Peak memory 199916 kb
Host smart-c2a98770-3c1b-4a6f-af10-72d817c08b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002846524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2002846524
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.698865101
Short name T1093
Test name
Test status
Simulation time 23350260394 ps
CPU time 37.38 seconds
Started Jun 28 04:42:15 PM PDT 24
Finished Jun 28 04:42:53 PM PDT 24
Peak memory 199832 kb
Host smart-866bd195-8668-4926-bacd-c27898c3ad5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698865101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.698865101
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.2223050227
Short name T458
Test name
Test status
Simulation time 14864736 ps
CPU time 0.57 seconds
Started Jun 28 04:38:32 PM PDT 24
Finished Jun 28 04:38:34 PM PDT 24
Peak memory 195144 kb
Host smart-0d7197ba-7b2b-4293-9bda-b4efca284db0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223050227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.2223050227
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1582733204
Short name T446
Test name
Test status
Simulation time 56700388815 ps
CPU time 101.84 seconds
Started Jun 28 04:38:30 PM PDT 24
Finished Jun 28 04:40:14 PM PDT 24
Peak memory 199912 kb
Host smart-13747344-49a3-4758-b288-124b5e11594a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582733204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1582733204
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.2722657149
Short name T122
Test name
Test status
Simulation time 31512904640 ps
CPU time 25.2 seconds
Started Jun 28 04:38:33 PM PDT 24
Finished Jun 28 04:39:00 PM PDT 24
Peak memory 199848 kb
Host smart-b9a871e5-a987-4f2a-9735-a26cbd01e58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722657149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2722657149
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.1188933241
Short name T217
Test name
Test status
Simulation time 157513652217 ps
CPU time 57.65 seconds
Started Jun 28 04:38:34 PM PDT 24
Finished Jun 28 04:39:33 PM PDT 24
Peak memory 199760 kb
Host smart-736a922d-4d92-4db6-9e7d-46be5433e8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188933241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1188933241
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.3059203581
Short name T296
Test name
Test status
Simulation time 237204055153 ps
CPU time 311.91 seconds
Started Jun 28 04:38:33 PM PDT 24
Finished Jun 28 04:43:46 PM PDT 24
Peak memory 197620 kb
Host smart-80ecb8e3-c7f9-409e-bf8a-dd5c16a3c4e7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059203581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3059203581
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1612925179
Short name T232
Test name
Test status
Simulation time 79848465210 ps
CPU time 288.51 seconds
Started Jun 28 04:38:30 PM PDT 24
Finished Jun 28 04:43:20 PM PDT 24
Peak memory 199892 kb
Host smart-439250ae-2bb1-4094-b343-248bd35684bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1612925179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1612925179
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.1938298383
Short name T803
Test name
Test status
Simulation time 12587832412 ps
CPU time 24.15 seconds
Started Jun 28 04:38:31 PM PDT 24
Finished Jun 28 04:38:57 PM PDT 24
Peak memory 198684 kb
Host smart-a4edf166-4fbb-41ee-aa64-9127ba200b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938298383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1938298383
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_perf.1202755954
Short name T38
Test name
Test status
Simulation time 16611149058 ps
CPU time 192.23 seconds
Started Jun 28 04:38:36 PM PDT 24
Finished Jun 28 04:41:49 PM PDT 24
Peak memory 199812 kb
Host smart-96b6c455-31b3-4863-b8c1-e98cf3d35e08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1202755954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.1202755954
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.4221882839
Short name T354
Test name
Test status
Simulation time 4587104219 ps
CPU time 36.27 seconds
Started Jun 28 04:38:33 PM PDT 24
Finished Jun 28 04:39:11 PM PDT 24
Peak memory 199588 kb
Host smart-ef4b58e6-efab-4e83-9822-eedbb4d41453
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4221882839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.4221882839
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.588658086
Short name T163
Test name
Test status
Simulation time 94974467815 ps
CPU time 156.3 seconds
Started Jun 28 04:38:37 PM PDT 24
Finished Jun 28 04:41:14 PM PDT 24
Peak memory 199848 kb
Host smart-bd42403b-f758-46f1-9baa-8cc4c19c4201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588658086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.588658086
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.2994477377
Short name T351
Test name
Test status
Simulation time 50689440631 ps
CPU time 68.39 seconds
Started Jun 28 04:38:32 PM PDT 24
Finished Jun 28 04:39:42 PM PDT 24
Peak memory 195668 kb
Host smart-5da53f9a-61fb-4e2d-9107-ea74fbd0a7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994477377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.2994477377
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.2902472436
Short name T364
Test name
Test status
Simulation time 457358740 ps
CPU time 1.18 seconds
Started Jun 28 04:38:33 PM PDT 24
Finished Jun 28 04:38:36 PM PDT 24
Peak memory 198588 kb
Host smart-e66a563c-0219-4bde-b84a-cd3d535eb2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902472436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2902472436
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.3056235685
Short name T971
Test name
Test status
Simulation time 1714953244 ps
CPU time 4.37 seconds
Started Jun 28 04:38:30 PM PDT 24
Finished Jun 28 04:38:37 PM PDT 24
Peak memory 199340 kb
Host smart-6d90efdb-ee2a-427e-bcee-361b34cca17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056235685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3056235685
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2131550736
Short name T485
Test name
Test status
Simulation time 2207405337 ps
CPU time 3.73 seconds
Started Jun 28 04:38:30 PM PDT 24
Finished Jun 28 04:38:35 PM PDT 24
Peak memory 196568 kb
Host smart-a7fc03ee-3229-49e4-a962-1d2cfcf810e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131550736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2131550736
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.811946580
Short name T456
Test name
Test status
Simulation time 36299047468 ps
CPU time 56.35 seconds
Started Jun 28 04:42:16 PM PDT 24
Finished Jun 28 04:43:13 PM PDT 24
Peak memory 199816 kb
Host smart-99c4aff9-3f20-45dc-aef0-ff8e7026200b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811946580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.811946580
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.584197707
Short name T76
Test name
Test status
Simulation time 88694258842 ps
CPU time 54.34 seconds
Started Jun 28 04:42:16 PM PDT 24
Finished Jun 28 04:43:11 PM PDT 24
Peak memory 199900 kb
Host smart-e48662d9-de57-4813-9ce2-43f6a0bf9a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584197707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.584197707
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.2234264995
Short name T276
Test name
Test status
Simulation time 270792915823 ps
CPU time 83.41 seconds
Started Jun 28 04:42:15 PM PDT 24
Finished Jun 28 04:43:39 PM PDT 24
Peak memory 199800 kb
Host smart-2866a848-8054-4417-b019-99da906e4500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234264995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2234264995
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.696036830
Short name T1018
Test name
Test status
Simulation time 35825335466 ps
CPU time 14.51 seconds
Started Jun 28 04:42:15 PM PDT 24
Finished Jun 28 04:42:30 PM PDT 24
Peak memory 198620 kb
Host smart-cfb1c8a0-e257-45b2-8163-97adb23f250e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696036830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.696036830
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.1164776584
Short name T666
Test name
Test status
Simulation time 136979784165 ps
CPU time 24.62 seconds
Started Jun 28 04:42:15 PM PDT 24
Finished Jun 28 04:42:40 PM PDT 24
Peak memory 199752 kb
Host smart-0cd319ca-7274-48fd-bad4-9c6b915a38db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164776584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1164776584
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.2280291525
Short name T916
Test name
Test status
Simulation time 47530634652 ps
CPU time 53.31 seconds
Started Jun 28 04:42:14 PM PDT 24
Finished Jun 28 04:43:09 PM PDT 24
Peak memory 199856 kb
Host smart-c04b0ec4-e7f4-468a-ab0d-c8da6de8d588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280291525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2280291525
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.744276274
Short name T444
Test name
Test status
Simulation time 27173876710 ps
CPU time 30.16 seconds
Started Jun 28 04:42:13 PM PDT 24
Finished Jun 28 04:42:43 PM PDT 24
Peak memory 199816 kb
Host smart-a91afe50-7d48-4885-8bff-b699751fce85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744276274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.744276274
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3714752022
Short name T763
Test name
Test status
Simulation time 124291004877 ps
CPU time 90.03 seconds
Started Jun 28 04:42:14 PM PDT 24
Finished Jun 28 04:43:46 PM PDT 24
Peak memory 199960 kb
Host smart-e24efbe0-05d9-4bb7-aca2-09a86b5bf697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714752022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3714752022
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.196140442
Short name T555
Test name
Test status
Simulation time 43600079 ps
CPU time 0.6 seconds
Started Jun 28 04:38:42 PM PDT 24
Finished Jun 28 04:38:43 PM PDT 24
Peak memory 195512 kb
Host smart-008c2714-0ea5-491a-822e-d0fcedd748fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196140442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.196140442
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.2789326814
Short name T90
Test name
Test status
Simulation time 38939751086 ps
CPU time 63.2 seconds
Started Jun 28 04:38:33 PM PDT 24
Finished Jun 28 04:39:38 PM PDT 24
Peak memory 199624 kb
Host smart-7861503a-4924-4cc2-a883-563c98afab5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789326814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.2789326814
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.2790088609
Short name T401
Test name
Test status
Simulation time 18338219675 ps
CPU time 28.03 seconds
Started Jun 28 04:38:32 PM PDT 24
Finished Jun 28 04:39:02 PM PDT 24
Peak memory 199900 kb
Host smart-d5f3987c-84e0-4266-9452-d0d4968e083c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790088609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.2790088609
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.700558104
Short name T758
Test name
Test status
Simulation time 42707226245 ps
CPU time 46.82 seconds
Started Jun 28 04:38:43 PM PDT 24
Finished Jun 28 04:39:31 PM PDT 24
Peak memory 199844 kb
Host smart-a2a7114d-445d-4cfa-8324-e48638853156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700558104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.700558104
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.553040386
Short name T721
Test name
Test status
Simulation time 152841101860 ps
CPU time 211.31 seconds
Started Jun 28 04:38:44 PM PDT 24
Finished Jun 28 04:42:16 PM PDT 24
Peak memory 198300 kb
Host smart-6d63a248-904d-4755-9079-91d66b5be867
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553040386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.553040386
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.2780359167
Short name T392
Test name
Test status
Simulation time 103353442120 ps
CPU time 468 seconds
Started Jun 28 04:38:46 PM PDT 24
Finished Jun 28 04:46:34 PM PDT 24
Peak memory 199824 kb
Host smart-993a301c-1bb6-4a89-92fe-73d6d9981cfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2780359167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2780359167
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.3636614191
Short name T345
Test name
Test status
Simulation time 13849286339 ps
CPU time 25.16 seconds
Started Jun 28 04:38:42 PM PDT 24
Finished Jun 28 04:39:08 PM PDT 24
Peak memory 199784 kb
Host smart-4e4751b0-223a-43d8-81ef-59a893d957e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636614191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3636614191
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_perf.1180289988
Short name T714
Test name
Test status
Simulation time 26856180262 ps
CPU time 1205.48 seconds
Started Jun 28 04:38:43 PM PDT 24
Finished Jun 28 04:58:50 PM PDT 24
Peak memory 199792 kb
Host smart-db921fff-aea3-4945-8b0d-dcdbb4ed810f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1180289988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1180289988
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.786287404
Short name T953
Test name
Test status
Simulation time 4515356631 ps
CPU time 22.86 seconds
Started Jun 28 04:38:42 PM PDT 24
Finished Jun 28 04:39:05 PM PDT 24
Peak memory 199076 kb
Host smart-4a357428-41b1-49b8-b01d-53d92176db75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=786287404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.786287404
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.344383079
Short name T631
Test name
Test status
Simulation time 17719339132 ps
CPU time 6.52 seconds
Started Jun 28 04:38:45 PM PDT 24
Finished Jun 28 04:38:52 PM PDT 24
Peak memory 198236 kb
Host smart-a13eaea2-2537-49ce-9ca7-834efb401459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344383079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.344383079
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.1488149791
Short name T266
Test name
Test status
Simulation time 37331939221 ps
CPU time 30.28 seconds
Started Jun 28 04:38:44 PM PDT 24
Finished Jun 28 04:39:15 PM PDT 24
Peak memory 196368 kb
Host smart-b3419fae-d06f-44d5-9102-2bd2add6fd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488149791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1488149791
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.2293433709
Short name T655
Test name
Test status
Simulation time 604517741 ps
CPU time 2.74 seconds
Started Jun 28 04:38:30 PM PDT 24
Finished Jun 28 04:38:34 PM PDT 24
Peak memory 199956 kb
Host smart-75d6f5d4-f733-41cc-a573-ecfc6659f6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293433709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2293433709
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.889566916
Short name T690
Test name
Test status
Simulation time 265019661296 ps
CPU time 104.59 seconds
Started Jun 28 04:38:43 PM PDT 24
Finished Jun 28 04:40:29 PM PDT 24
Peak memory 199812 kb
Host smart-f359914f-6271-4b54-9666-c2552c50884a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889566916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.889566916
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.2814899149
Short name T51
Test name
Test status
Simulation time 187831133441 ps
CPU time 1055.2 seconds
Started Jun 28 04:38:44 PM PDT 24
Finished Jun 28 04:56:20 PM PDT 24
Peak memory 209428 kb
Host smart-72814d50-5f31-4ca7-ae05-fe3ec12c7e3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814899149 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.2814899149
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.949629094
Short name T264
Test name
Test status
Simulation time 6651789604 ps
CPU time 15.6 seconds
Started Jun 28 04:38:43 PM PDT 24
Finished Jun 28 04:39:00 PM PDT 24
Peak memory 199764 kb
Host smart-866a39a0-46e8-4875-bb53-ce10fe71f47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949629094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.949629094
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.1614872695
Short name T280
Test name
Test status
Simulation time 20572123348 ps
CPU time 10.88 seconds
Started Jun 28 04:38:30 PM PDT 24
Finished Jun 28 04:38:42 PM PDT 24
Peak memory 199820 kb
Host smart-ecf9f565-01d0-4048-953c-67a68ee167b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614872695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1614872695
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.2689469473
Short name T1012
Test name
Test status
Simulation time 18450804379 ps
CPU time 12.76 seconds
Started Jun 28 04:42:15 PM PDT 24
Finished Jun 28 04:42:29 PM PDT 24
Peak memory 199344 kb
Host smart-d5b7b521-e742-44bd-8994-02511705e852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689469473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.2689469473
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.1869007890
Short name T104
Test name
Test status
Simulation time 102549605775 ps
CPU time 20.61 seconds
Started Jun 28 04:42:14 PM PDT 24
Finished Jun 28 04:42:35 PM PDT 24
Peak memory 199852 kb
Host smart-2b376e69-de34-46be-8cb6-b8cf015115f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869007890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1869007890
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.1767006090
Short name T1059
Test name
Test status
Simulation time 14805471990 ps
CPU time 19.37 seconds
Started Jun 28 04:42:13 PM PDT 24
Finished Jun 28 04:42:34 PM PDT 24
Peak memory 199776 kb
Host smart-70796daf-2961-4642-b3bf-a92ced2b905b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767006090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1767006090
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.3788111101
Short name T706
Test name
Test status
Simulation time 179434062111 ps
CPU time 87.03 seconds
Started Jun 28 04:42:12 PM PDT 24
Finished Jun 28 04:43:39 PM PDT 24
Peak memory 199904 kb
Host smart-b54220a8-e9bd-4b5c-ac7d-9d7e4f1ad3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788111101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3788111101
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.598067089
Short name T196
Test name
Test status
Simulation time 65076404305 ps
CPU time 112.68 seconds
Started Jun 28 04:42:14 PM PDT 24
Finished Jun 28 04:44:08 PM PDT 24
Peak memory 199904 kb
Host smart-8a7ab2d3-e549-4d0a-945a-aaeff53e406e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598067089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.598067089
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.3069678930
Short name T210
Test name
Test status
Simulation time 268087125260 ps
CPU time 42.62 seconds
Started Jun 28 04:42:14 PM PDT 24
Finished Jun 28 04:42:58 PM PDT 24
Peak memory 199744 kb
Host smart-85c9225c-bc6c-47e8-8ae9-3560f2c56ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069678930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3069678930
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.2987502097
Short name T904
Test name
Test status
Simulation time 56215873828 ps
CPU time 22.48 seconds
Started Jun 28 04:42:14 PM PDT 24
Finished Jun 28 04:42:38 PM PDT 24
Peak memory 199724 kb
Host smart-a04218ee-77cf-4c43-a692-f491e8d1a3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987502097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2987502097
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.3378070394
Short name T979
Test name
Test status
Simulation time 103203164411 ps
CPU time 42.32 seconds
Started Jun 28 04:42:14 PM PDT 24
Finished Jun 28 04:42:57 PM PDT 24
Peak memory 199900 kb
Host smart-5c77778f-cab7-4e2e-b2c5-d5c6885f0fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378070394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3378070394
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.3353489721
Short name T584
Test name
Test status
Simulation time 79674910047 ps
CPU time 30.62 seconds
Started Jun 28 04:42:15 PM PDT 24
Finished Jun 28 04:42:46 PM PDT 24
Peak memory 199828 kb
Host smart-795e717c-a031-4112-b12a-dfe02695d2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353489721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.3353489721
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.88059361
Short name T928
Test name
Test status
Simulation time 18869831 ps
CPU time 0.57 seconds
Started Jun 28 04:38:51 PM PDT 24
Finished Jun 28 04:38:53 PM PDT 24
Peak memory 195188 kb
Host smart-978bbca6-0117-45d0-a9f7-f79bbdafac41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88059361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.88059361
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.2529544842
Short name T126
Test name
Test status
Simulation time 57530302469 ps
CPU time 15.64 seconds
Started Jun 28 04:38:42 PM PDT 24
Finished Jun 28 04:38:58 PM PDT 24
Peak memory 199848 kb
Host smart-820fb9e8-7048-4e8a-98e9-573b89ff5d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529544842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2529544842
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.1310419024
Short name T1041
Test name
Test status
Simulation time 120508085402 ps
CPU time 74.98 seconds
Started Jun 28 04:38:43 PM PDT 24
Finished Jun 28 04:39:59 PM PDT 24
Peak memory 199824 kb
Host smart-fc9a9cad-5994-4dae-86cb-c15f694e5d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310419024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.1310419024
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.2427727953
Short name T917
Test name
Test status
Simulation time 30971185678 ps
CPU time 50.84 seconds
Started Jun 28 04:38:53 PM PDT 24
Finished Jun 28 04:39:45 PM PDT 24
Peak memory 199764 kb
Host smart-5d742d89-20b2-4b69-8caa-ded01d48f387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427727953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2427727953
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.1015682031
Short name T963
Test name
Test status
Simulation time 31866604639 ps
CPU time 28.08 seconds
Started Jun 28 04:38:44 PM PDT 24
Finished Jun 28 04:39:13 PM PDT 24
Peak memory 199608 kb
Host smart-f03477f3-3835-4836-9e63-9efd4f2e3687
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015682031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1015682031
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.445948677
Short name T272
Test name
Test status
Simulation time 78158035384 ps
CPU time 134.97 seconds
Started Jun 28 04:38:44 PM PDT 24
Finished Jun 28 04:41:00 PM PDT 24
Peak memory 199860 kb
Host smart-129e7a6d-d3d9-434d-a112-875e9ad03845
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=445948677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.445948677
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.2720238575
Short name T558
Test name
Test status
Simulation time 3835126823 ps
CPU time 2.68 seconds
Started Jun 28 04:38:44 PM PDT 24
Finished Jun 28 04:38:48 PM PDT 24
Peak memory 197984 kb
Host smart-341a2e7e-d4df-4f61-9818-a8f3135a7bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720238575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2720238575
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_perf.209117994
Short name T877
Test name
Test status
Simulation time 14851148348 ps
CPU time 683.14 seconds
Started Jun 28 04:38:42 PM PDT 24
Finished Jun 28 04:50:05 PM PDT 24
Peak memory 199812 kb
Host smart-e8ce97d1-9d2f-4ace-b96d-66017c070dc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=209117994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.209117994
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.2423521861
Short name T380
Test name
Test status
Simulation time 6688358995 ps
CPU time 27.31 seconds
Started Jun 28 04:38:45 PM PDT 24
Finished Jun 28 04:39:13 PM PDT 24
Peak memory 198708 kb
Host smart-252059ba-ee0a-4eb5-a252-bdee499446c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2423521861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2423521861
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.324094315
Short name T838
Test name
Test status
Simulation time 154992446517 ps
CPU time 78.47 seconds
Started Jun 28 04:38:46 PM PDT 24
Finished Jun 28 04:40:05 PM PDT 24
Peak memory 199820 kb
Host smart-27f597a8-010a-4eaf-a70c-aefc79ee3b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324094315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.324094315
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.22019013
Short name T292
Test name
Test status
Simulation time 4251468171 ps
CPU time 4.24 seconds
Started Jun 28 04:38:43 PM PDT 24
Finished Jun 28 04:38:49 PM PDT 24
Peak memory 196152 kb
Host smart-dd1195a8-9111-49de-9cc5-0322e203b092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22019013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.22019013
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.927082996
Short name T352
Test name
Test status
Simulation time 491527429 ps
CPU time 1.99 seconds
Started Jun 28 04:38:45 PM PDT 24
Finished Jun 28 04:38:48 PM PDT 24
Peak memory 199752 kb
Host smart-27767d7b-2f1f-4124-b6d5-f93a946bb3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927082996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.927082996
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.1362320985
Short name T442
Test name
Test status
Simulation time 46449357969 ps
CPU time 790.65 seconds
Started Jun 28 04:38:42 PM PDT 24
Finished Jun 28 04:51:54 PM PDT 24
Peak memory 214132 kb
Host smart-4a5b0553-b9ad-46d2-9df9-0b8948d740d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362320985 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.1362320985
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.775747740
Short name T340
Test name
Test status
Simulation time 1062120998 ps
CPU time 1.28 seconds
Started Jun 28 04:38:45 PM PDT 24
Finished Jun 28 04:38:47 PM PDT 24
Peak memory 198224 kb
Host smart-602813d6-d3be-46c7-9ca1-811b0f96fd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775747740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.775747740
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.2242123208
Short name T1061
Test name
Test status
Simulation time 54425014341 ps
CPU time 18.6 seconds
Started Jun 28 04:38:46 PM PDT 24
Finished Jun 28 04:39:05 PM PDT 24
Peak memory 199908 kb
Host smart-a8978521-0613-48b3-8c4a-cb583130d416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242123208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.2242123208
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.3233857844
Short name T230
Test name
Test status
Simulation time 25455732887 ps
CPU time 15.82 seconds
Started Jun 28 04:42:16 PM PDT 24
Finished Jun 28 04:42:33 PM PDT 24
Peak memory 199816 kb
Host smart-919cc4e3-9771-44c7-bdde-1dafbaa9e476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233857844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3233857844
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.74469166
Short name T689
Test name
Test status
Simulation time 35281900755 ps
CPU time 15.9 seconds
Started Jun 28 04:42:13 PM PDT 24
Finished Jun 28 04:42:30 PM PDT 24
Peak memory 199916 kb
Host smart-51989f9c-e05b-4ab9-a8f5-b8e108ab160b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74469166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.74469166
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.1360202683
Short name T678
Test name
Test status
Simulation time 147554617613 ps
CPU time 51.72 seconds
Started Jun 28 04:42:15 PM PDT 24
Finished Jun 28 04:43:08 PM PDT 24
Peak memory 199748 kb
Host smart-7755c449-3784-43f4-a9af-fb32c702c506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360202683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1360202683
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.3017127391
Short name T198
Test name
Test status
Simulation time 43265557808 ps
CPU time 31.26 seconds
Started Jun 28 04:42:13 PM PDT 24
Finished Jun 28 04:42:45 PM PDT 24
Peak memory 199824 kb
Host smart-d0d490f2-87a4-419e-8314-6152c0b84f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017127391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3017127391
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.3369335441
Short name T552
Test name
Test status
Simulation time 39826760303 ps
CPU time 36.2 seconds
Started Jun 28 04:42:14 PM PDT 24
Finished Jun 28 04:42:51 PM PDT 24
Peak memory 199912 kb
Host smart-9a26147b-2816-402c-8f2f-c5b3a838514c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369335441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3369335441
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.3872361957
Short name T848
Test name
Test status
Simulation time 24456170896 ps
CPU time 33.91 seconds
Started Jun 28 04:42:15 PM PDT 24
Finished Jun 28 04:42:50 PM PDT 24
Peak memory 199912 kb
Host smart-95be7d7e-99f7-4694-b2e3-b9188aa58578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872361957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3872361957
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3463149628
Short name T315
Test name
Test status
Simulation time 218416600154 ps
CPU time 86.4 seconds
Started Jun 28 04:42:13 PM PDT 24
Finished Jun 28 04:43:41 PM PDT 24
Peak memory 199832 kb
Host smart-5dbb654a-6f54-4be9-91f9-fdc3957f82df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463149628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3463149628
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.2912459363
Short name T995
Test name
Test status
Simulation time 12494633359 ps
CPU time 18.69 seconds
Started Jun 28 04:42:13 PM PDT 24
Finished Jun 28 04:42:33 PM PDT 24
Peak memory 199460 kb
Host smart-1c741aae-133c-4d92-83af-fd31ef7efbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912459363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2912459363
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.3254209426
Short name T859
Test name
Test status
Simulation time 19700864 ps
CPU time 0.55 seconds
Started Jun 28 04:38:53 PM PDT 24
Finished Jun 28 04:38:55 PM PDT 24
Peak memory 194404 kb
Host smart-36e86f90-802d-4302-b4cc-0a240e3f9275
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254209426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3254209426
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.2291966030
Short name T265
Test name
Test status
Simulation time 172366022766 ps
CPU time 420.63 seconds
Started Jun 28 04:38:45 PM PDT 24
Finished Jun 28 04:45:47 PM PDT 24
Peak memory 199772 kb
Host smart-4741dd5a-be6a-475e-9cb1-19810b107f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291966030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2291966030
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.1729945413
Short name T861
Test name
Test status
Simulation time 39235897124 ps
CPU time 11.47 seconds
Started Jun 28 04:38:53 PM PDT 24
Finished Jun 28 04:39:06 PM PDT 24
Peak memory 199668 kb
Host smart-d7048b1c-14b7-4762-883a-a4655ce56b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729945413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.1729945413
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.3235379513
Short name T241
Test name
Test status
Simulation time 19073639145 ps
CPU time 34.19 seconds
Started Jun 28 04:38:53 PM PDT 24
Finished Jun 28 04:39:29 PM PDT 24
Peak memory 199748 kb
Host smart-31dbad2c-1f25-49d0-a33d-fc4b33d661d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235379513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3235379513
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.2649317506
Short name T331
Test name
Test status
Simulation time 20162599259 ps
CPU time 16.75 seconds
Started Jun 28 04:38:42 PM PDT 24
Finished Jun 28 04:39:00 PM PDT 24
Peak memory 199756 kb
Host smart-ed5af7d6-9ac1-4c15-8a46-f9ddf56e7b43
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649317506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2649317506
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.1190094074
Short name T350
Test name
Test status
Simulation time 52522810365 ps
CPU time 109.16 seconds
Started Jun 28 04:38:52 PM PDT 24
Finished Jun 28 04:40:42 PM PDT 24
Peak memory 199760 kb
Host smart-7667a8c9-feca-40bd-a54b-dc8042e7a854
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1190094074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1190094074
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.2025505685
Short name T1008
Test name
Test status
Simulation time 10974910138 ps
CPU time 23.76 seconds
Started Jun 28 04:38:53 PM PDT 24
Finished Jun 28 04:39:18 PM PDT 24
Peak memory 199504 kb
Host smart-69d86d65-0f27-4e38-b564-2f866ee60692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025505685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2025505685
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_perf.1808440149
Short name T450
Test name
Test status
Simulation time 15867980594 ps
CPU time 835.62 seconds
Started Jun 28 04:38:52 PM PDT 24
Finished Jun 28 04:52:48 PM PDT 24
Peak memory 199752 kb
Host smart-e20f8bbd-251f-47d5-81e1-3c41830c34b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1808440149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.1808440149
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2143938375
Short name T589
Test name
Test status
Simulation time 6310389371 ps
CPU time 27.16 seconds
Started Jun 28 04:38:44 PM PDT 24
Finished Jun 28 04:39:12 PM PDT 24
Peak memory 199164 kb
Host smart-3c836e2b-0bdb-4fb5-a26b-15d802860eba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2143938375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2143938375
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1792441752
Short name T936
Test name
Test status
Simulation time 129417622391 ps
CPU time 43.65 seconds
Started Jun 28 04:38:54 PM PDT 24
Finished Jun 28 04:39:39 PM PDT 24
Peak memory 199836 kb
Host smart-508dafe1-2926-40f7-b079-b1dff98104c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792441752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1792441752
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2567338022
Short name T285
Test name
Test status
Simulation time 3593378866 ps
CPU time 2.15 seconds
Started Jun 28 04:38:51 PM PDT 24
Finished Jun 28 04:38:54 PM PDT 24
Peak memory 195892 kb
Host smart-a082def6-c4ee-420d-805c-aae829ab9f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567338022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2567338022
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.1060353896
Short name T288
Test name
Test status
Simulation time 346426353 ps
CPU time 1.1 seconds
Started Jun 28 04:38:53 PM PDT 24
Finished Jun 28 04:38:56 PM PDT 24
Peak memory 198384 kb
Host smart-a9fc2e30-c9d9-4226-bd46-e8cabb4aacdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060353896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1060353896
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.94647553
Short name T556
Test name
Test status
Simulation time 217895094758 ps
CPU time 912.43 seconds
Started Jun 28 04:38:52 PM PDT 24
Finished Jun 28 04:54:06 PM PDT 24
Peak memory 199632 kb
Host smart-6b37f3bc-7473-4281-ba76-c31c3b9f1dde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94647553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.94647553
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.4029306855
Short name T493
Test name
Test status
Simulation time 6774178519 ps
CPU time 8.56 seconds
Started Jun 28 04:38:54 PM PDT 24
Finished Jun 28 04:39:04 PM PDT 24
Peak memory 199608 kb
Host smart-89611387-9ff6-4b06-8fec-dab3abc65e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029306855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.4029306855
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.896169618
Short name T746
Test name
Test status
Simulation time 24732325165 ps
CPU time 37.36 seconds
Started Jun 28 04:38:53 PM PDT 24
Finished Jun 28 04:39:32 PM PDT 24
Peak memory 199868 kb
Host smart-4fa640e3-2d0f-489a-abd7-6a4e58cd6639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896169618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.896169618
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.3278424438
Short name T148
Test name
Test status
Simulation time 71428577664 ps
CPU time 29.3 seconds
Started Jun 28 04:42:15 PM PDT 24
Finished Jun 28 04:42:46 PM PDT 24
Peak memory 199824 kb
Host smart-c6b19eb0-ca71-4579-a588-30e444184ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278424438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.3278424438
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1283308202
Short name T673
Test name
Test status
Simulation time 14852371726 ps
CPU time 23.74 seconds
Started Jun 28 04:42:16 PM PDT 24
Finished Jun 28 04:42:40 PM PDT 24
Peak memory 200000 kb
Host smart-d212b152-1265-4fd9-b160-7651be7525da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283308202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1283308202
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.3784161471
Short name T273
Test name
Test status
Simulation time 12605068225 ps
CPU time 5.71 seconds
Started Jun 28 04:42:27 PM PDT 24
Finished Jun 28 04:42:34 PM PDT 24
Peak memory 200072 kb
Host smart-9f475d12-8c21-4046-9ff4-0355ec675bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784161471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.3784161471
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.954519463
Short name T945
Test name
Test status
Simulation time 16209996660 ps
CPU time 25.64 seconds
Started Jun 28 04:42:26 PM PDT 24
Finished Jun 28 04:42:53 PM PDT 24
Peak memory 199812 kb
Host smart-bf28fb27-326d-485f-b146-a4c72d23e876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954519463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.954519463
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.1029014022
Short name T787
Test name
Test status
Simulation time 29182627301 ps
CPU time 10.69 seconds
Started Jun 28 04:42:29 PM PDT 24
Finished Jun 28 04:42:41 PM PDT 24
Peak memory 198948 kb
Host smart-fa49d209-bd37-4bcd-8b74-4dfe371a1d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029014022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.1029014022
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.1056091288
Short name T870
Test name
Test status
Simulation time 20056338143 ps
CPU time 36.12 seconds
Started Jun 28 04:42:27 PM PDT 24
Finished Jun 28 04:43:05 PM PDT 24
Peak memory 199792 kb
Host smart-034c16f2-ebb9-46d9-8c1a-c7591b217149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056091288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1056091288
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.880474611
Short name T251
Test name
Test status
Simulation time 18242372512 ps
CPU time 29.34 seconds
Started Jun 28 04:42:26 PM PDT 24
Finished Jun 28 04:42:56 PM PDT 24
Peak memory 199688 kb
Host smart-a19298e0-0a0b-48c1-b143-9daa80e81b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880474611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.880474611
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.4208787037
Short name T619
Test name
Test status
Simulation time 15282341297 ps
CPU time 21.07 seconds
Started Jun 28 04:42:36 PM PDT 24
Finished Jun 28 04:42:57 PM PDT 24
Peak memory 199900 kb
Host smart-498ba01e-7157-494b-9f56-5c98a7451643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208787037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.4208787037
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.77369636
Short name T881
Test name
Test status
Simulation time 21493713606 ps
CPU time 31.58 seconds
Started Jun 28 04:42:26 PM PDT 24
Finished Jun 28 04:42:58 PM PDT 24
Peak memory 199708 kb
Host smart-e2bc9f9b-0b09-40a1-9bc2-8ba4de91a960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77369636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.77369636
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.2715002418
Short name T566
Test name
Test status
Simulation time 19189284594 ps
CPU time 33.18 seconds
Started Jun 28 04:42:29 PM PDT 24
Finished Jun 28 04:43:04 PM PDT 24
Peak memory 199836 kb
Host smart-6d5b8a28-fb8b-4989-a300-8dbd2322ae4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715002418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.2715002418
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.430520631
Short name T460
Test name
Test status
Simulation time 13976615 ps
CPU time 0.57 seconds
Started Jun 28 04:36:38 PM PDT 24
Finished Jun 28 04:36:40 PM PDT 24
Peak memory 194324 kb
Host smart-68464c62-6e56-4371-9b3c-a5fdd78777ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430520631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.430520631
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.695480119
Short name T1050
Test name
Test status
Simulation time 209891122189 ps
CPU time 142.55 seconds
Started Jun 28 04:36:38 PM PDT 24
Finished Jun 28 04:39:02 PM PDT 24
Peak memory 199856 kb
Host smart-f5b91910-1cd8-4b68-b0f0-59c3f89cdeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695480119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.695480119
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.2709932045
Short name T1052
Test name
Test status
Simulation time 106425073409 ps
CPU time 81.52 seconds
Started Jun 28 04:36:36 PM PDT 24
Finished Jun 28 04:37:58 PM PDT 24
Peak memory 199764 kb
Host smart-64915d9b-8e5e-4b95-822b-c255f413ad0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709932045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2709932045
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.3648993419
Short name T115
Test name
Test status
Simulation time 29207643654 ps
CPU time 13.55 seconds
Started Jun 28 04:36:36 PM PDT 24
Finished Jun 28 04:36:50 PM PDT 24
Peak memory 199140 kb
Host smart-b39ab88d-4a8a-4159-b854-ac300b606c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648993419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.3648993419
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.1173393956
Short name T940
Test name
Test status
Simulation time 22236593651 ps
CPU time 4.26 seconds
Started Jun 28 04:36:37 PM PDT 24
Finished Jun 28 04:36:43 PM PDT 24
Peak memory 198352 kb
Host smart-931af247-1ee1-43ae-90d7-b8a7b8c7ae27
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173393956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1173393956
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.2582759699
Short name T771
Test name
Test status
Simulation time 150555847175 ps
CPU time 480.05 seconds
Started Jun 28 04:36:37 PM PDT 24
Finished Jun 28 04:44:39 PM PDT 24
Peak memory 199796 kb
Host smart-ef238da2-87f1-455d-9c14-ea211a661074
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2582759699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.2582759699
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.2380028160
Short name T349
Test name
Test status
Simulation time 3201798354 ps
CPU time 2.25 seconds
Started Jun 28 04:36:36 PM PDT 24
Finished Jun 28 04:36:40 PM PDT 24
Peak memory 198668 kb
Host smart-3ef1d695-f908-4452-892f-91628a351882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380028160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2380028160
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_perf.171836603
Short name T361
Test name
Test status
Simulation time 8875947502 ps
CPU time 108.58 seconds
Started Jun 28 04:36:36 PM PDT 24
Finished Jun 28 04:38:26 PM PDT 24
Peak memory 199820 kb
Host smart-3b70ae27-0211-47ed-8982-650b1533741d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=171836603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.171836603
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.2544317742
Short name T886
Test name
Test status
Simulation time 4240717300 ps
CPU time 8.41 seconds
Started Jun 28 04:36:38 PM PDT 24
Finished Jun 28 04:36:48 PM PDT 24
Peak memory 198788 kb
Host smart-2a4b1f4f-a529-40b3-96f2-b9b03cb6aeb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2544317742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.2544317742
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.4097547842
Short name T398
Test name
Test status
Simulation time 67268822123 ps
CPU time 24.62 seconds
Started Jun 28 04:36:36 PM PDT 24
Finished Jun 28 04:37:03 PM PDT 24
Peak memory 199836 kb
Host smart-2d056eec-36ee-48fd-94a7-876a8d23e5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097547842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.4097547842
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.1423278534
Short name T801
Test name
Test status
Simulation time 5617190891 ps
CPU time 8.31 seconds
Started Jun 28 04:36:36 PM PDT 24
Finished Jun 28 04:36:46 PM PDT 24
Peak memory 196152 kb
Host smart-eb970486-c82f-4309-a272-79c4262e4ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423278534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1423278534
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1560019130
Short name T25
Test name
Test status
Simulation time 117156801 ps
CPU time 0.77 seconds
Started Jun 28 04:36:42 PM PDT 24
Finished Jun 28 04:36:43 PM PDT 24
Peak memory 218240 kb
Host smart-7f44e51b-87f1-41af-907f-79bb00a8b44e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560019130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1560019130
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.3983833576
Short name T524
Test name
Test status
Simulation time 777626517 ps
CPU time 1.75 seconds
Started Jun 28 04:36:35 PM PDT 24
Finished Jun 28 04:36:38 PM PDT 24
Peak memory 198184 kb
Host smart-8c931b52-6fcb-4539-92f6-29fbfefeef8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983833576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.3983833576
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.4098692920
Short name T510
Test name
Test status
Simulation time 12489421213 ps
CPU time 5.6 seconds
Started Jun 28 04:36:35 PM PDT 24
Finished Jun 28 04:36:42 PM PDT 24
Peak memory 200112 kb
Host smart-21857563-a8dc-4361-be12-b1151a89d78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098692920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.4098692920
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.182173004
Short name T1026
Test name
Test status
Simulation time 133264272133 ps
CPU time 35.47 seconds
Started Jun 28 04:36:36 PM PDT 24
Finished Jun 28 04:37:13 PM PDT 24
Peak memory 199900 kb
Host smart-5019ee9c-d5c7-44b2-9bce-6ea645c560d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182173004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.182173004
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.463099366
Short name T805
Test name
Test status
Simulation time 27357174 ps
CPU time 0.52 seconds
Started Jun 28 04:38:54 PM PDT 24
Finished Jun 28 04:38:56 PM PDT 24
Peak memory 194072 kb
Host smart-735103d6-9690-4979-8670-a66d105c57b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463099366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.463099366
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.2823527504
Short name T1046
Test name
Test status
Simulation time 110640575179 ps
CPU time 222.66 seconds
Started Jun 28 04:38:53 PM PDT 24
Finished Jun 28 04:42:37 PM PDT 24
Peak memory 199828 kb
Host smart-97e07558-8ba7-4526-9be6-e11a55988a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823527504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.2823527504
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.1533301206
Short name T762
Test name
Test status
Simulation time 134263840892 ps
CPU time 208.42 seconds
Started Jun 28 04:38:54 PM PDT 24
Finished Jun 28 04:42:24 PM PDT 24
Peak memory 199768 kb
Host smart-296ba2ca-0f82-48a6-9aeb-84e90953a889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533301206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1533301206
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3969202995
Short name T190
Test name
Test status
Simulation time 198342262875 ps
CPU time 46.24 seconds
Started Jun 28 04:38:52 PM PDT 24
Finished Jun 28 04:39:39 PM PDT 24
Peak memory 199820 kb
Host smart-caec1f05-2af3-4a57-8653-982616a16289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969202995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3969202995
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.4084056308
Short name T12
Test name
Test status
Simulation time 75690956160 ps
CPU time 31.84 seconds
Started Jun 28 04:38:54 PM PDT 24
Finished Jun 28 04:39:27 PM PDT 24
Peak memory 200116 kb
Host smart-f5cecbdd-769e-47d8-a852-38c29061246f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084056308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.4084056308
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.1498325178
Short name T434
Test name
Test status
Simulation time 174726319378 ps
CPU time 1198.28 seconds
Started Jun 28 04:38:55 PM PDT 24
Finished Jun 28 04:58:54 PM PDT 24
Peak memory 199836 kb
Host smart-8a1b9fa3-1690-4398-8815-c202f4025e3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1498325178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1498325178
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.3356100496
Short name T804
Test name
Test status
Simulation time 2618218332 ps
CPU time 2.76 seconds
Started Jun 28 04:38:52 PM PDT 24
Finished Jun 28 04:38:56 PM PDT 24
Peak memory 198032 kb
Host smart-47bf0308-7757-4cc4-9b62-02eb0b052f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356100496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3356100496
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_perf.1470478845
Short name T938
Test name
Test status
Simulation time 31993769391 ps
CPU time 217.09 seconds
Started Jun 28 04:38:53 PM PDT 24
Finished Jun 28 04:42:32 PM PDT 24
Peak memory 199832 kb
Host smart-d0bba78c-5f52-44c3-a773-989e7b41f8fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1470478845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1470478845
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.704880902
Short name T322
Test name
Test status
Simulation time 3596376305 ps
CPU time 13.25 seconds
Started Jun 28 04:38:54 PM PDT 24
Finished Jun 28 04:39:09 PM PDT 24
Peak memory 197972 kb
Host smart-3daba338-c2e3-490d-b738-3a144351fc4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=704880902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.704880902
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1133514391
Short name T644
Test name
Test status
Simulation time 101318139267 ps
CPU time 75.11 seconds
Started Jun 28 04:38:52 PM PDT 24
Finished Jun 28 04:40:09 PM PDT 24
Peak memory 199660 kb
Host smart-22b6d514-3ab6-40a6-a96a-44f285b904b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133514391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1133514391
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.3898061666
Short name T667
Test name
Test status
Simulation time 680837235 ps
CPU time 0.87 seconds
Started Jun 28 04:38:54 PM PDT 24
Finished Jun 28 04:38:56 PM PDT 24
Peak memory 195328 kb
Host smart-09bfc947-5bbf-4180-b112-b5e43b4d8406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898061666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.3898061666
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.1624980051
Short name T278
Test name
Test status
Simulation time 642484805 ps
CPU time 1.64 seconds
Started Jun 28 04:38:53 PM PDT 24
Finished Jun 28 04:38:56 PM PDT 24
Peak memory 199628 kb
Host smart-ceea8982-d485-4235-8a83-0e1c0674cd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624980051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1624980051
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.2587202300
Short name T581
Test name
Test status
Simulation time 259549066723 ps
CPU time 385.05 seconds
Started Jun 28 04:38:53 PM PDT 24
Finished Jun 28 04:45:19 PM PDT 24
Peak memory 199844 kb
Host smart-2a93f111-3d9c-44f7-8020-aa62f63bf56f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587202300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.2587202300
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2708850639
Short name T587
Test name
Test status
Simulation time 226232742 ps
CPU time 1.06 seconds
Started Jun 28 04:38:54 PM PDT 24
Finished Jun 28 04:38:56 PM PDT 24
Peak memory 197092 kb
Host smart-a4ba55a0-3b4c-4641-8c06-c84c842e135d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708850639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2708850639
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.4282482414
Short name T978
Test name
Test status
Simulation time 97351908027 ps
CPU time 30.81 seconds
Started Jun 28 04:38:53 PM PDT 24
Finished Jun 28 04:39:26 PM PDT 24
Peak memory 199820 kb
Host smart-f98a6687-df28-4222-aee5-1c0fea88201c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282482414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.4282482414
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.230251312
Short name T898
Test name
Test status
Simulation time 12633238 ps
CPU time 0.53 seconds
Started Jun 28 04:39:06 PM PDT 24
Finished Jun 28 04:39:09 PM PDT 24
Peak memory 194188 kb
Host smart-e3af72fd-f193-40d0-a512-48d49db1322f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230251312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.230251312
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.1009945169
Short name T346
Test name
Test status
Simulation time 118090711692 ps
CPU time 51 seconds
Started Jun 28 04:38:53 PM PDT 24
Finished Jun 28 04:39:46 PM PDT 24
Peak memory 199752 kb
Host smart-8f8a833f-3275-4dff-a7ef-0ecf53dad5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009945169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1009945169
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1329653943
Short name T475
Test name
Test status
Simulation time 36692825387 ps
CPU time 31.43 seconds
Started Jun 28 04:39:03 PM PDT 24
Finished Jun 28 04:39:36 PM PDT 24
Peak memory 199752 kb
Host smart-ec4c39ea-164c-41e1-a091-b3a773a239b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329653943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1329653943
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.3480216870
Short name T1065
Test name
Test status
Simulation time 121142376080 ps
CPU time 216.11 seconds
Started Jun 28 04:39:06 PM PDT 24
Finished Jun 28 04:42:44 PM PDT 24
Peak memory 199828 kb
Host smart-51bcdd08-b531-4530-bd24-e62cf3dc6a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480216870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3480216870
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.2729602426
Short name T502
Test name
Test status
Simulation time 242908910261 ps
CPU time 210.11 seconds
Started Jun 28 04:39:06 PM PDT 24
Finished Jun 28 04:42:38 PM PDT 24
Peak memory 199700 kb
Host smart-85a364ee-d18c-4747-9881-c014138e7c89
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729602426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2729602426
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.4031707576
Short name T335
Test name
Test status
Simulation time 103901196180 ps
CPU time 429.56 seconds
Started Jun 28 04:39:02 PM PDT 24
Finished Jun 28 04:46:13 PM PDT 24
Peak memory 199688 kb
Host smart-6ef6b2a2-5035-4229-9cf0-46d7bcab4c1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4031707576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.4031707576
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.1331512454
Short name T384
Test name
Test status
Simulation time 2511230007 ps
CPU time 1.68 seconds
Started Jun 28 04:39:03 PM PDT 24
Finished Jun 28 04:39:07 PM PDT 24
Peak memory 195740 kb
Host smart-40882d41-0b7d-49e0-bf2a-4c2c8aa83f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331512454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1331512454
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_perf.580147642
Short name T651
Test name
Test status
Simulation time 7448636231 ps
CPU time 83.5 seconds
Started Jun 28 04:39:03 PM PDT 24
Finished Jun 28 04:40:29 PM PDT 24
Peak memory 199888 kb
Host smart-b5fdd53c-f686-4984-b712-b440b3290d66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=580147642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.580147642
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.2514822000
Short name T985
Test name
Test status
Simulation time 6535189683 ps
CPU time 65.01 seconds
Started Jun 28 04:39:02 PM PDT 24
Finished Jun 28 04:40:09 PM PDT 24
Peak memory 197952 kb
Host smart-bff45006-54e4-4445-848f-83e39e2743e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2514822000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2514822000
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.531578845
Short name T413
Test name
Test status
Simulation time 16382985703 ps
CPU time 23.83 seconds
Started Jun 28 04:39:05 PM PDT 24
Finished Jun 28 04:39:30 PM PDT 24
Peak memory 199832 kb
Host smart-1271c044-20e9-4c81-b417-70ae7a3f999e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531578845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.531578845
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.3751514290
Short name T411
Test name
Test status
Simulation time 564844479 ps
CPU time 1.06 seconds
Started Jun 28 04:39:07 PM PDT 24
Finished Jun 28 04:39:09 PM PDT 24
Peak memory 195472 kb
Host smart-25456771-4c06-4927-bae4-e75df3c2242b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751514290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3751514290
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.1415491546
Short name T501
Test name
Test status
Simulation time 117365006 ps
CPU time 1.03 seconds
Started Jun 28 04:38:52 PM PDT 24
Finished Jun 28 04:38:55 PM PDT 24
Peak memory 197952 kb
Host smart-0d9e84c6-8647-4908-8cea-4fcabd7bc98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415491546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1415491546
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.3106437549
Short name T497
Test name
Test status
Simulation time 481242563 ps
CPU time 1.44 seconds
Started Jun 28 04:39:04 PM PDT 24
Finished Jun 28 04:39:08 PM PDT 24
Peak memory 196752 kb
Host smart-1e28534e-e3d0-4dfa-8131-5ca00dbb64c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106437549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3106437549
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.1750154007
Short name T843
Test name
Test status
Simulation time 128060755165 ps
CPU time 106.75 seconds
Started Jun 28 04:38:53 PM PDT 24
Finished Jun 28 04:40:42 PM PDT 24
Peak memory 199872 kb
Host smart-95bcebf7-930b-426e-aa81-c60e937a6395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750154007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1750154007
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.3783496086
Short name T680
Test name
Test status
Simulation time 12815840 ps
CPU time 0.56 seconds
Started Jun 28 04:39:06 PM PDT 24
Finished Jun 28 04:39:08 PM PDT 24
Peak memory 195228 kb
Host smart-9928b25f-f990-4a74-a590-3f2c52484be9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783496086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.3783496086
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.1209167298
Short name T612
Test name
Test status
Simulation time 58178820075 ps
CPU time 57.55 seconds
Started Jun 28 04:39:03 PM PDT 24
Finished Jun 28 04:40:03 PM PDT 24
Peak memory 199912 kb
Host smart-9f245451-6d5d-4ce2-930c-ae816f4580d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209167298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1209167298
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.184809934
Short name T91
Test name
Test status
Simulation time 153081055136 ps
CPU time 49.43 seconds
Started Jun 28 04:39:04 PM PDT 24
Finished Jun 28 04:39:55 PM PDT 24
Peak memory 199840 kb
Host smart-105960b2-f28c-4d7a-ad11-e4f2f05ebe95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184809934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.184809934
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1054380028
Short name T201
Test name
Test status
Simulation time 63007307631 ps
CPU time 27.71 seconds
Started Jun 28 04:39:06 PM PDT 24
Finished Jun 28 04:39:36 PM PDT 24
Peak memory 199912 kb
Host smart-35ca088e-97d9-4c09-babe-6c4e88b657ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054380028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1054380028
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.1320074375
Short name T298
Test name
Test status
Simulation time 61368869454 ps
CPU time 45.31 seconds
Started Jun 28 04:39:03 PM PDT 24
Finished Jun 28 04:39:50 PM PDT 24
Peak memory 199872 kb
Host smart-5a85011c-27e3-432e-88b1-70b4546fcaeb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320074375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1320074375
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.697246128
Short name T586
Test name
Test status
Simulation time 159447710783 ps
CPU time 394.28 seconds
Started Jun 28 04:39:05 PM PDT 24
Finished Jun 28 04:45:41 PM PDT 24
Peak memory 199900 kb
Host smart-227f5915-d815-43c9-ab4f-2b1160502376
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=697246128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.697246128
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.2088331580
Short name T624
Test name
Test status
Simulation time 3088726007 ps
CPU time 6.04 seconds
Started Jun 28 04:39:05 PM PDT 24
Finished Jun 28 04:39:13 PM PDT 24
Peak memory 199768 kb
Host smart-42ece797-64a6-44e3-85c3-12e8947ad9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088331580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2088331580
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.2345611270
Short name T788
Test name
Test status
Simulation time 71679513093 ps
CPU time 144.01 seconds
Started Jun 28 04:39:04 PM PDT 24
Finished Jun 28 04:41:30 PM PDT 24
Peak memory 199972 kb
Host smart-faf9b285-5ab1-4ae3-8ef9-45e7d10e7ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345611270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.2345611270
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.735963844
Short name T479
Test name
Test status
Simulation time 9278913106 ps
CPU time 222.08 seconds
Started Jun 28 04:39:04 PM PDT 24
Finished Jun 28 04:42:48 PM PDT 24
Peak memory 199816 kb
Host smart-f41b61c2-47d6-45a0-a021-a54ea3134cb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=735963844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.735963844
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3457352314
Short name T333
Test name
Test status
Simulation time 6434018937 ps
CPU time 54.77 seconds
Started Jun 28 04:39:03 PM PDT 24
Finished Jun 28 04:39:59 PM PDT 24
Peak memory 198720 kb
Host smart-029254ef-31f6-4f3f-869a-94dee06df20f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3457352314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3457352314
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.135739919
Short name T1035
Test name
Test status
Simulation time 48245455184 ps
CPU time 55.36 seconds
Started Jun 28 04:39:04 PM PDT 24
Finished Jun 28 04:40:02 PM PDT 24
Peak memory 199856 kb
Host smart-4fcbd792-176b-44e8-ae8b-beb000a05aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135739919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.135739919
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.1002759973
Short name T649
Test name
Test status
Simulation time 38036336501 ps
CPU time 16.2 seconds
Started Jun 28 04:39:04 PM PDT 24
Finished Jun 28 04:39:22 PM PDT 24
Peak memory 196528 kb
Host smart-264e0caa-38af-4635-aadc-0cf6926f18f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002759973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1002759973
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.2238113361
Short name T1074
Test name
Test status
Simulation time 566656439 ps
CPU time 0.99 seconds
Started Jun 28 04:39:04 PM PDT 24
Finished Jun 28 04:39:07 PM PDT 24
Peak memory 198556 kb
Host smart-70b278d3-43d5-429f-898d-f8153257d90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238113361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.2238113361
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1939490282
Short name T1029
Test name
Test status
Simulation time 50766983953 ps
CPU time 388.22 seconds
Started Jun 28 04:39:05 PM PDT 24
Finished Jun 28 04:45:35 PM PDT 24
Peak memory 215792 kb
Host smart-a9af7ed4-21c2-4e6c-ae17-6121785ea4a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939490282 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1939490282
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.215045005
Short name T329
Test name
Test status
Simulation time 867461158 ps
CPU time 2.54 seconds
Started Jun 28 04:39:03 PM PDT 24
Finished Jun 28 04:39:07 PM PDT 24
Peak memory 198968 kb
Host smart-5f742be1-733b-4241-a0a0-c190373b00d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215045005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.215045005
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.3720931971
Short name T841
Test name
Test status
Simulation time 158857498857 ps
CPU time 56.83 seconds
Started Jun 28 04:39:03 PM PDT 24
Finished Jun 28 04:40:02 PM PDT 24
Peak memory 199920 kb
Host smart-4c287489-d365-4491-a189-7ca058a82496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720931971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3720931971
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.4142880606
Short name T404
Test name
Test status
Simulation time 42713691 ps
CPU time 0.55 seconds
Started Jun 28 04:39:15 PM PDT 24
Finished Jun 28 04:39:17 PM PDT 24
Peak memory 195228 kb
Host smart-d6744c87-fca1-4ccd-8519-68c44771886b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142880606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.4142880606
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.2029511715
Short name T665
Test name
Test status
Simulation time 55803312130 ps
CPU time 62.04 seconds
Started Jun 28 04:39:04 PM PDT 24
Finished Jun 28 04:40:09 PM PDT 24
Peak memory 199912 kb
Host smart-1950ee54-91d5-4301-ba69-f723ed145532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029511715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2029511715
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.4167679574
Short name T944
Test name
Test status
Simulation time 103798649042 ps
CPU time 17.1 seconds
Started Jun 28 04:39:06 PM PDT 24
Finished Jun 28 04:39:25 PM PDT 24
Peak memory 198296 kb
Host smart-f295b0c8-8869-4ade-b1e6-f1281b79eea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167679574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.4167679574
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.352142319
Short name T580
Test name
Test status
Simulation time 40532398410 ps
CPU time 27.28 seconds
Started Jun 28 04:39:02 PM PDT 24
Finished Jun 28 04:39:30 PM PDT 24
Peak memory 199648 kb
Host smart-f001dadd-486e-4c99-b18e-ccbd3facefd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352142319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.352142319
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.2068089196
Short name T676
Test name
Test status
Simulation time 47652834878 ps
CPU time 85.05 seconds
Started Jun 28 04:39:04 PM PDT 24
Finished Jun 28 04:40:31 PM PDT 24
Peak memory 199548 kb
Host smart-1de45609-d4ae-4a4d-ae1e-64372b311b57
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068089196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2068089196
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.324278235
Short name T1015
Test name
Test status
Simulation time 137476961590 ps
CPU time 318.46 seconds
Started Jun 28 04:39:23 PM PDT 24
Finished Jun 28 04:44:43 PM PDT 24
Peak memory 199892 kb
Host smart-32aa735e-b5e6-4618-be42-28bb9a7a1a67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=324278235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.324278235
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.3151782871
Short name T987
Test name
Test status
Simulation time 246189011 ps
CPU time 0.65 seconds
Started Jun 28 04:39:04 PM PDT 24
Finished Jun 28 04:39:07 PM PDT 24
Peak memory 195608 kb
Host smart-430b6d11-48cc-4d41-a825-fc49a2ccd703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151782871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3151782871
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_perf.3861345868
Short name T961
Test name
Test status
Simulation time 29624720388 ps
CPU time 309.8 seconds
Started Jun 28 04:39:03 PM PDT 24
Finished Jun 28 04:44:15 PM PDT 24
Peak memory 199848 kb
Host smart-ba438544-6154-4cb3-a967-58a7445bba4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3861345868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3861345868
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.2757688623
Short name T17
Test name
Test status
Simulation time 7236014928 ps
CPU time 32.43 seconds
Started Jun 28 04:39:02 PM PDT 24
Finished Jun 28 04:39:35 PM PDT 24
Peak memory 199752 kb
Host smart-9f6fb995-cb86-4998-8fb7-08e9350ac741
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2757688623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2757688623
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.2238702857
Short name T151
Test name
Test status
Simulation time 107188437143 ps
CPU time 45.6 seconds
Started Jun 28 04:39:07 PM PDT 24
Finished Jun 28 04:39:54 PM PDT 24
Peak memory 199852 kb
Host smart-fe1f1fc7-8711-4925-9e2e-b19b67cfe085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238702857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2238702857
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1545566189
Short name T11
Test name
Test status
Simulation time 5027622768 ps
CPU time 7.03 seconds
Started Jun 28 04:39:03 PM PDT 24
Finished Jun 28 04:39:13 PM PDT 24
Peak memory 195944 kb
Host smart-2721db74-4ded-49a2-b91e-8c63b7529a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545566189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1545566189
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3258163704
Short name T950
Test name
Test status
Simulation time 6250729701 ps
CPU time 7.5 seconds
Started Jun 28 04:39:05 PM PDT 24
Finished Jun 28 04:39:15 PM PDT 24
Peak memory 199880 kb
Host smart-7efd2d42-1dc2-402c-bb59-cf035931058d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258163704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3258163704
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.3151216421
Short name T247
Test name
Test status
Simulation time 6552942128 ps
CPU time 19.56 seconds
Started Jun 28 04:39:06 PM PDT 24
Finished Jun 28 04:39:28 PM PDT 24
Peak memory 199360 kb
Host smart-771ad880-1efa-41b1-99d2-6013449579e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151216421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.3151216421
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.253506955
Short name T1001
Test name
Test status
Simulation time 5567755983 ps
CPU time 1.41 seconds
Started Jun 28 04:39:04 PM PDT 24
Finished Jun 28 04:39:08 PM PDT 24
Peak memory 197608 kb
Host smart-1288e665-8a4f-49ad-9d18-49f5d586a4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253506955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.253506955
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.4010239459
Short name T959
Test name
Test status
Simulation time 18767115 ps
CPU time 0.6 seconds
Started Jun 28 04:39:23 PM PDT 24
Finished Jun 28 04:39:24 PM PDT 24
Peak memory 195168 kb
Host smart-a971a64f-171e-44ea-9deb-b5285bf31772
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010239459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.4010239459
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.3036956875
Short name T1031
Test name
Test status
Simulation time 34866265254 ps
CPU time 16.68 seconds
Started Jun 28 04:39:14 PM PDT 24
Finished Jun 28 04:39:32 PM PDT 24
Peak memory 199912 kb
Host smart-9b1ee3fb-d1c3-4976-af17-3ca4ed93e4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036956875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3036956875
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.2311243109
Short name T605
Test name
Test status
Simulation time 65626995454 ps
CPU time 52.68 seconds
Started Jun 28 04:39:13 PM PDT 24
Finished Jun 28 04:40:06 PM PDT 24
Peak memory 199792 kb
Host smart-8992e781-9510-4800-8dc2-9407b0e9bfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311243109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2311243109
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.1676335364
Short name T948
Test name
Test status
Simulation time 41744946070 ps
CPU time 18.69 seconds
Started Jun 28 04:39:16 PM PDT 24
Finished Jun 28 04:39:35 PM PDT 24
Peak memory 199952 kb
Host smart-67bc4635-01f0-4b73-9e80-005c50463826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676335364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.1676335364
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.734232124
Short name T543
Test name
Test status
Simulation time 165292065558 ps
CPU time 258.26 seconds
Started Jun 28 04:39:13 PM PDT 24
Finished Jun 28 04:43:33 PM PDT 24
Peak memory 199760 kb
Host smart-8b37e579-8b20-4096-8b46-21b4620bb85e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734232124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.734232124
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.3443394883
Short name T297
Test name
Test status
Simulation time 111593410508 ps
CPU time 198.56 seconds
Started Jun 28 04:39:14 PM PDT 24
Finished Jun 28 04:42:34 PM PDT 24
Peak memory 199896 kb
Host smart-715e6bba-4b6c-4b96-a282-335075fd82d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3443394883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3443394883
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.2753042240
Short name T637
Test name
Test status
Simulation time 6521272684 ps
CPU time 13.37 seconds
Started Jun 28 04:39:14 PM PDT 24
Finished Jun 28 04:39:29 PM PDT 24
Peak memory 198572 kb
Host smart-459dadc4-f171-423e-9c7f-0ee4789183c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753042240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2753042240
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_perf.3733393384
Short name T648
Test name
Test status
Simulation time 20502475030 ps
CPU time 186.68 seconds
Started Jun 28 04:39:15 PM PDT 24
Finished Jun 28 04:42:22 PM PDT 24
Peak memory 199892 kb
Host smart-50705f33-deac-4e04-b422-b8b48159b9b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3733393384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3733393384
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.2579858441
Short name T332
Test name
Test status
Simulation time 4420565662 ps
CPU time 29.68 seconds
Started Jun 28 04:39:16 PM PDT 24
Finished Jun 28 04:39:47 PM PDT 24
Peak memory 199280 kb
Host smart-a832fc83-bbe7-4d15-b8f7-d09ceb0510e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2579858441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2579858441
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.4270699749
Short name T512
Test name
Test status
Simulation time 30390113030 ps
CPU time 77.44 seconds
Started Jun 28 04:39:13 PM PDT 24
Finished Jun 28 04:40:31 PM PDT 24
Peak memory 199768 kb
Host smart-6d2c43f1-2fe2-4c58-8de9-99681747305d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270699749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.4270699749
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.2804209274
Short name T402
Test name
Test status
Simulation time 2285208457 ps
CPU time 1.1 seconds
Started Jun 28 04:39:15 PM PDT 24
Finished Jun 28 04:39:17 PM PDT 24
Peak memory 195556 kb
Host smart-0c877daa-a949-4e76-afe6-5f0d09200fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804209274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.2804209274
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3567625416
Short name T1016
Test name
Test status
Simulation time 10587529302 ps
CPU time 26.87 seconds
Started Jun 28 04:39:15 PM PDT 24
Finished Jun 28 04:39:43 PM PDT 24
Peak memory 199652 kb
Host smart-f7ad3155-17db-4d39-84ce-3247506f90c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567625416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3567625416
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.1441477325
Short name T854
Test name
Test status
Simulation time 34339668697 ps
CPU time 412.26 seconds
Started Jun 28 04:39:14 PM PDT 24
Finished Jun 28 04:46:08 PM PDT 24
Peak memory 215504 kb
Host smart-602794ec-6663-4ef8-969b-5c0b56917945
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441477325 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.1441477325
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.3305195722
Short name T866
Test name
Test status
Simulation time 1218556069 ps
CPU time 3.44 seconds
Started Jun 28 04:39:14 PM PDT 24
Finished Jun 28 04:39:18 PM PDT 24
Peak memory 198216 kb
Host smart-4d285afb-c689-4a6f-a10c-8302fe21ffa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305195722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3305195722
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.2619586695
Short name T999
Test name
Test status
Simulation time 18318489828 ps
CPU time 24.39 seconds
Started Jun 28 04:39:13 PM PDT 24
Finished Jun 28 04:39:39 PM PDT 24
Peak memory 199884 kb
Host smart-097dfd84-75f9-43fb-afd5-bf9ccec6d2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619586695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.2619586695
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.3862553611
Short name T22
Test name
Test status
Simulation time 14307003 ps
CPU time 0.58 seconds
Started Jun 28 04:39:13 PM PDT 24
Finished Jun 28 04:39:15 PM PDT 24
Peak memory 195344 kb
Host smart-82b9ffb5-59cf-4f12-bd08-2252017485a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862553611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3862553611
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.4262383882
Short name T650
Test name
Test status
Simulation time 76381438282 ps
CPU time 119.45 seconds
Started Jun 28 04:39:14 PM PDT 24
Finished Jun 28 04:41:14 PM PDT 24
Peak memory 199916 kb
Host smart-588d78eb-452f-49c7-acc9-befd4196b013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262383882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.4262383882
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.3814085876
Short name T547
Test name
Test status
Simulation time 26160538733 ps
CPU time 44.61 seconds
Started Jun 28 04:39:14 PM PDT 24
Finished Jun 28 04:39:59 PM PDT 24
Peak memory 199808 kb
Host smart-fba08850-4cdf-454f-bf0d-0f71f6c61918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814085876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3814085876
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2462297372
Short name T610
Test name
Test status
Simulation time 62156694838 ps
CPU time 24.08 seconds
Started Jun 28 04:39:15 PM PDT 24
Finished Jun 28 04:39:40 PM PDT 24
Peak memory 199856 kb
Host smart-e30f8b38-2007-49db-ab6e-1a56ea0f2abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462297372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2462297372
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.628282387
Short name T481
Test name
Test status
Simulation time 129313193980 ps
CPU time 42.77 seconds
Started Jun 28 04:39:15 PM PDT 24
Finished Jun 28 04:39:59 PM PDT 24
Peak memory 198016 kb
Host smart-c138b23d-2298-4db6-8496-9bd244946308
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628282387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.628282387
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3505660443
Short name T831
Test name
Test status
Simulation time 179398271711 ps
CPU time 939.63 seconds
Started Jun 28 04:39:23 PM PDT 24
Finished Jun 28 04:55:04 PM PDT 24
Peak memory 199808 kb
Host smart-a8a34102-756d-49c0-bf92-19f46ac4a0e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3505660443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3505660443
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.1336728947
Short name T745
Test name
Test status
Simulation time 12551175082 ps
CPU time 11.21 seconds
Started Jun 28 04:39:14 PM PDT 24
Finished Jun 28 04:39:26 PM PDT 24
Peak memory 199808 kb
Host smart-eb36d224-0456-48d2-b277-09f9a145259a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336728947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1336728947
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_perf.1317796128
Short name T546
Test name
Test status
Simulation time 19184080484 ps
CPU time 249.49 seconds
Started Jun 28 04:39:14 PM PDT 24
Finished Jun 28 04:43:25 PM PDT 24
Peak memory 199832 kb
Host smart-e4bafba6-6a28-4e8f-a047-5547ed498d83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1317796128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1317796128
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3684010181
Short name T1078
Test name
Test status
Simulation time 6310204720 ps
CPU time 64.45 seconds
Started Jun 28 04:39:23 PM PDT 24
Finished Jun 28 04:40:28 PM PDT 24
Peak memory 198284 kb
Host smart-a4f92280-4c29-441a-8825-5c37d1b556f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3684010181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3684010181
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.3475456529
Short name T488
Test name
Test status
Simulation time 86785826429 ps
CPU time 16.43 seconds
Started Jun 28 04:39:15 PM PDT 24
Finished Jun 28 04:39:32 PM PDT 24
Peak memory 199768 kb
Host smart-25c6c9d1-6ebb-4bba-9ab3-e98901a01266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475456529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.3475456529
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.2933586199
Short name T499
Test name
Test status
Simulation time 85316547573 ps
CPU time 39.29 seconds
Started Jun 28 04:39:14 PM PDT 24
Finished Jun 28 04:39:54 PM PDT 24
Peak memory 195688 kb
Host smart-df8b1483-b8a8-4932-91c9-50f4c425ed8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933586199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2933586199
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2122629073
Short name T750
Test name
Test status
Simulation time 5436393468 ps
CPU time 11.53 seconds
Started Jun 28 04:39:13 PM PDT 24
Finished Jun 28 04:39:26 PM PDT 24
Peak memory 199796 kb
Host smart-e53db376-48cf-43bd-9933-2a2fac44d0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122629073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2122629073
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.3588344057
Short name T300
Test name
Test status
Simulation time 48572430840 ps
CPU time 529.86 seconds
Started Jun 28 04:39:15 PM PDT 24
Finished Jun 28 04:48:06 PM PDT 24
Peak memory 216504 kb
Host smart-e9546faa-024a-44b4-a347-e4fe5214d736
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588344057 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.3588344057
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.4099354130
Short name T729
Test name
Test status
Simulation time 2066474042 ps
CPU time 2.21 seconds
Started Jun 28 04:39:13 PM PDT 24
Finished Jun 28 04:39:17 PM PDT 24
Peak memory 198856 kb
Host smart-ccd158ca-47da-494f-8805-f6db72b5859d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099354130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.4099354130
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.1880482119
Short name T424
Test name
Test status
Simulation time 4139532811 ps
CPU time 6.77 seconds
Started Jun 28 04:39:16 PM PDT 24
Finished Jun 28 04:39:24 PM PDT 24
Peak memory 197064 kb
Host smart-b850dd8d-2b91-4815-8fe5-f567129aa933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880482119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.1880482119
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.996143850
Short name T336
Test name
Test status
Simulation time 31539693 ps
CPU time 0.56 seconds
Started Jun 28 04:39:24 PM PDT 24
Finished Jun 28 04:39:26 PM PDT 24
Peak memory 194548 kb
Host smart-34ef5451-d2cf-49c8-b9c4-019026e6b293
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996143850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.996143850
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.1152040553
Short name T551
Test name
Test status
Simulation time 67230128256 ps
CPU time 29.44 seconds
Started Jun 28 04:39:22 PM PDT 24
Finished Jun 28 04:39:52 PM PDT 24
Peak memory 199848 kb
Host smart-757906a0-b85d-4b21-9c9c-7800be0100d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152040553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.1152040553
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3288753703
Short name T860
Test name
Test status
Simulation time 13903077702 ps
CPU time 23.48 seconds
Started Jun 28 04:39:34 PM PDT 24
Finished Jun 28 04:39:58 PM PDT 24
Peak memory 198976 kb
Host smart-3865e851-c738-46f2-b910-928e5b91eaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288753703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3288753703
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.220283888
Short name T1068
Test name
Test status
Simulation time 18531795363 ps
CPU time 44.15 seconds
Started Jun 28 04:39:23 PM PDT 24
Finished Jun 28 04:40:08 PM PDT 24
Peak memory 199844 kb
Host smart-c6f664ca-92b0-490f-9c42-c3071b8da0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220283888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.220283888
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.199957295
Short name T295
Test name
Test status
Simulation time 9219227457 ps
CPU time 2.02 seconds
Started Jun 28 04:39:25 PM PDT 24
Finished Jun 28 04:39:28 PM PDT 24
Peak memory 195984 kb
Host smart-eee9c513-ab20-4085-9584-ada90d5b39cd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199957295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.199957295
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.3652657339
Short name T755
Test name
Test status
Simulation time 41391170597 ps
CPU time 183.58 seconds
Started Jun 28 04:39:24 PM PDT 24
Finished Jun 28 04:42:29 PM PDT 24
Peak memory 199728 kb
Host smart-d5436770-314f-40e4-80f5-e84914ce0b38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3652657339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.3652657339
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.1008183444
Short name T483
Test name
Test status
Simulation time 7869950695 ps
CPU time 17.53 seconds
Started Jun 28 04:39:23 PM PDT 24
Finished Jun 28 04:39:42 PM PDT 24
Peak memory 199596 kb
Host smart-a8f8eb7b-0e2c-46bf-aa1e-8b10b85d4027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008183444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1008183444
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_perf.565443009
Short name T33
Test name
Test status
Simulation time 6264994764 ps
CPU time 364.21 seconds
Started Jun 28 04:39:33 PM PDT 24
Finished Jun 28 04:45:38 PM PDT 24
Peak memory 199824 kb
Host smart-4249eccc-9d1b-4329-a910-e328f1328eb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=565443009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.565443009
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.1772915206
Short name T305
Test name
Test status
Simulation time 3559619025 ps
CPU time 14.68 seconds
Started Jun 28 04:39:26 PM PDT 24
Finished Jun 28 04:39:42 PM PDT 24
Peak memory 199004 kb
Host smart-23edc318-5de3-49cd-9699-0671d76bb4cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1772915206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.1772915206
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.2578783714
Short name T1058
Test name
Test status
Simulation time 144137328264 ps
CPU time 237.38 seconds
Started Jun 28 04:39:24 PM PDT 24
Finished Jun 28 04:43:23 PM PDT 24
Peak memory 199708 kb
Host smart-88069a63-0788-423d-9edb-9c66cdc226a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578783714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2578783714
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.3809740304
Short name T993
Test name
Test status
Simulation time 37401517883 ps
CPU time 30.18 seconds
Started Jun 28 04:39:23 PM PDT 24
Finished Jun 28 04:39:55 PM PDT 24
Peak memory 195776 kb
Host smart-b8840927-8fa5-41e9-969b-87f42f8326a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809740304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3809740304
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.2100422488
Short name T814
Test name
Test status
Simulation time 5459600797 ps
CPU time 11.1 seconds
Started Jun 28 04:39:15 PM PDT 24
Finished Jun 28 04:39:27 PM PDT 24
Peak memory 199652 kb
Host smart-27a4d71e-cf76-42f8-803e-4ee227f21700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100422488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2100422488
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.4115670767
Short name T100
Test name
Test status
Simulation time 72659151230 ps
CPU time 277.98 seconds
Started Jun 28 04:39:24 PM PDT 24
Finished Jun 28 04:44:03 PM PDT 24
Peak memory 199860 kb
Host smart-4eb5d3f5-bb42-405b-842c-bd88b06ef67c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115670767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.4115670767
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1576656393
Short name T1044
Test name
Test status
Simulation time 39440524517 ps
CPU time 483.55 seconds
Started Jun 28 04:39:23 PM PDT 24
Finished Jun 28 04:47:28 PM PDT 24
Peak memory 216240 kb
Host smart-a038c738-d075-4e5a-8551-fbd56551fccf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576656393 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1576656393
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.2289274255
Short name T526
Test name
Test status
Simulation time 6683202888 ps
CPU time 14.98 seconds
Started Jun 28 04:39:34 PM PDT 24
Finished Jun 28 04:39:49 PM PDT 24
Peak memory 199328 kb
Host smart-78092ead-c7bc-4b67-ae95-3a6489f1d7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289274255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2289274255
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.212893183
Short name T783
Test name
Test status
Simulation time 92994484097 ps
CPU time 48.05 seconds
Started Jun 28 04:39:13 PM PDT 24
Finished Jun 28 04:40:02 PM PDT 24
Peak memory 199908 kb
Host smart-52b8eebb-85aa-4d02-b5bc-52d66354dcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212893183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.212893183
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1216603185
Short name T21
Test name
Test status
Simulation time 16563330 ps
CPU time 0.56 seconds
Started Jun 28 04:39:25 PM PDT 24
Finished Jun 28 04:39:27 PM PDT 24
Peak memory 195432 kb
Host smart-56f490c1-cf6f-45a0-b3d8-afd7bf8abbd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216603185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1216603185
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.1155754167
Short name T869
Test name
Test status
Simulation time 14873327592 ps
CPU time 7.53 seconds
Started Jun 28 04:39:25 PM PDT 24
Finished Jun 28 04:39:34 PM PDT 24
Peak memory 199852 kb
Host smart-5c865440-ede2-455a-8847-31beb63b6d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155754167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.1155754167
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.2793539347
Short name T535
Test name
Test status
Simulation time 151241770084 ps
CPU time 222.69 seconds
Started Jun 28 04:39:24 PM PDT 24
Finished Jun 28 04:43:08 PM PDT 24
Peak memory 199852 kb
Host smart-51bc4ddf-bc6b-4ace-af4e-088e4306c571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793539347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.2793539347
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.221312464
Short name T440
Test name
Test status
Simulation time 74420909483 ps
CPU time 33.38 seconds
Started Jun 28 04:39:25 PM PDT 24
Finished Jun 28 04:40:00 PM PDT 24
Peak memory 199756 kb
Host smart-84f673d8-5d66-4790-90f0-94be2df7c710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221312464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.221312464
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.1742985172
Short name T726
Test name
Test status
Simulation time 65595818809 ps
CPU time 53.99 seconds
Started Jun 28 04:39:26 PM PDT 24
Finished Jun 28 04:40:21 PM PDT 24
Peak memory 199832 kb
Host smart-544ca26f-88c9-4496-adfb-19d442824d66
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742985172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1742985172
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.616886845
Short name T663
Test name
Test status
Simulation time 201100838771 ps
CPU time 741.16 seconds
Started Jun 28 04:39:25 PM PDT 24
Finished Jun 28 04:51:48 PM PDT 24
Peak memory 199796 kb
Host smart-4cee5da1-43ea-49a1-b1ef-a8b77e5e420c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=616886845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.616886845
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2611791467
Short name T363
Test name
Test status
Simulation time 2587209995 ps
CPU time 2.39 seconds
Started Jun 28 04:39:25 PM PDT 24
Finished Jun 28 04:39:29 PM PDT 24
Peak memory 199180 kb
Host smart-7d14dfcd-7504-4c20-81b5-228d1682dc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611791467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2611791467
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_perf.1630794565
Short name T225
Test name
Test status
Simulation time 21153016301 ps
CPU time 506.01 seconds
Started Jun 28 04:39:34 PM PDT 24
Finished Jun 28 04:48:00 PM PDT 24
Peak memory 199436 kb
Host smart-1babf18b-d627-47c2-aea4-b2e5fab51161
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1630794565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1630794565
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.3625695864
Short name T568
Test name
Test status
Simulation time 5593549235 ps
CPU time 6.74 seconds
Started Jun 28 04:39:25 PM PDT 24
Finished Jun 28 04:39:33 PM PDT 24
Peak memory 198160 kb
Host smart-d2a51d3b-b553-4e11-988f-753c60a595c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3625695864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3625695864
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.2624884764
Short name T287
Test name
Test status
Simulation time 16660949081 ps
CPU time 25.08 seconds
Started Jun 28 04:39:24 PM PDT 24
Finished Jun 28 04:39:50 PM PDT 24
Peak memory 199132 kb
Host smart-eb057ba5-3f39-4c8e-994c-9714bdb60ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624884764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.2624884764
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.1255877267
Short name T1073
Test name
Test status
Simulation time 4900249769 ps
CPU time 8.01 seconds
Started Jun 28 04:39:25 PM PDT 24
Finished Jun 28 04:39:34 PM PDT 24
Peak memory 195844 kb
Host smart-f0f5c1e9-8139-46ac-a1dd-da48571a454e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255877267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1255877267
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.965242718
Short name T353
Test name
Test status
Simulation time 843551916 ps
CPU time 4.19 seconds
Started Jun 28 04:39:26 PM PDT 24
Finished Jun 28 04:39:31 PM PDT 24
Peak memory 199344 kb
Host smart-e8c28a2f-e82c-499b-acb4-91cedbca4fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965242718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.965242718
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.1137025263
Short name T873
Test name
Test status
Simulation time 336154578272 ps
CPU time 464.73 seconds
Started Jun 28 04:39:25 PM PDT 24
Finished Jun 28 04:47:11 PM PDT 24
Peak memory 199884 kb
Host smart-95cc0f4d-c23c-4539-896b-a55d2a66e2cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137025263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.1137025263
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.2702650907
Short name T445
Test name
Test status
Simulation time 6539438620 ps
CPU time 18.93 seconds
Started Jun 28 04:39:25 PM PDT 24
Finished Jun 28 04:39:46 PM PDT 24
Peak memory 199812 kb
Host smart-dd8723d0-a24c-4548-b6fe-d58e4b332cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702650907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.2702650907
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.342051762
Short name T382
Test name
Test status
Simulation time 85610367104 ps
CPU time 69.38 seconds
Started Jun 28 04:39:25 PM PDT 24
Finished Jun 28 04:40:36 PM PDT 24
Peak memory 199844 kb
Host smart-8e884c23-0a05-4fb3-93a9-e6fdee28c68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342051762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.342051762
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3332231777
Short name T915
Test name
Test status
Simulation time 36689549 ps
CPU time 0.59 seconds
Started Jun 28 04:39:39 PM PDT 24
Finished Jun 28 04:39:41 PM PDT 24
Peak memory 194680 kb
Host smart-2c7efb04-8eed-4c74-8920-f69d30d64656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332231777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3332231777
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.3838317071
Short name T260
Test name
Test status
Simulation time 131932513703 ps
CPU time 167.33 seconds
Started Jun 28 04:39:25 PM PDT 24
Finished Jun 28 04:42:14 PM PDT 24
Peak memory 199852 kb
Host smart-a7bea40d-609c-4096-8d2d-726802fb257d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838317071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3838317071
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1408740167
Short name T903
Test name
Test status
Simulation time 20903418118 ps
CPU time 27.02 seconds
Started Jun 28 04:39:24 PM PDT 24
Finished Jun 28 04:39:53 PM PDT 24
Peak memory 199808 kb
Host smart-81e82c18-8db2-4ce8-9b99-ab18d16554cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408740167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1408740167
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3552499556
Short name T505
Test name
Test status
Simulation time 19687013284 ps
CPU time 8.9 seconds
Started Jun 28 04:39:26 PM PDT 24
Finished Jun 28 04:39:36 PM PDT 24
Peak memory 199620 kb
Host smart-90783bc5-f8f8-4e37-a4ef-1a040a8591b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552499556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3552499556
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.2275649419
Short name T807
Test name
Test status
Simulation time 145429922454 ps
CPU time 73.62 seconds
Started Jun 28 04:39:39 PM PDT 24
Finished Jun 28 04:40:54 PM PDT 24
Peak memory 199820 kb
Host smart-5fcb1b79-3f8a-47d2-bebb-bdceb3d30fd9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275649419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2275649419
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.3261753587
Short name T735
Test name
Test status
Simulation time 173256376142 ps
CPU time 307.66 seconds
Started Jun 28 04:39:40 PM PDT 24
Finished Jun 28 04:44:48 PM PDT 24
Peak memory 199824 kb
Host smart-94f9d683-5b8e-43bc-8c08-b282d0765883
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3261753587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.3261753587
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.3342957043
Short name T492
Test name
Test status
Simulation time 2219920933 ps
CPU time 4.17 seconds
Started Jun 28 04:39:39 PM PDT 24
Finished Jun 28 04:39:44 PM PDT 24
Peak memory 195928 kb
Host smart-475187ac-b25f-4ec1-9c08-ce60c462dab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342957043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3342957043
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.1174139210
Short name T812
Test name
Test status
Simulation time 16391801042 ps
CPU time 30.68 seconds
Started Jun 28 04:39:39 PM PDT 24
Finished Jun 28 04:40:11 PM PDT 24
Peak memory 199964 kb
Host smart-d5e2686e-b5d7-4e97-8dfd-e78c26565dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174139210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.1174139210
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.1277658218
Short name T467
Test name
Test status
Simulation time 29407562454 ps
CPU time 1135.02 seconds
Started Jun 28 04:39:36 PM PDT 24
Finished Jun 28 04:58:32 PM PDT 24
Peak memory 199876 kb
Host smart-57fdc594-e4bb-49d0-a567-d0c67d9b727d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1277658218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1277658218
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.2371600357
Short name T638
Test name
Test status
Simulation time 2649154817 ps
CPU time 15.31 seconds
Started Jun 28 04:39:38 PM PDT 24
Finished Jun 28 04:39:55 PM PDT 24
Peak memory 198368 kb
Host smart-300c9204-1c81-4746-982d-b34c086e9727
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2371600357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2371600357
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2891437984
Short name T946
Test name
Test status
Simulation time 30639563710 ps
CPU time 53.77 seconds
Started Jun 28 04:39:36 PM PDT 24
Finished Jun 28 04:40:30 PM PDT 24
Peak memory 199848 kb
Host smart-41b21f00-9f6b-4d46-bef1-8f7ec65d437d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891437984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2891437984
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.567621631
Short name T582
Test name
Test status
Simulation time 31419646420 ps
CPU time 25.93 seconds
Started Jun 28 04:39:37 PM PDT 24
Finished Jun 28 04:40:04 PM PDT 24
Peak memory 195672 kb
Host smart-e2ccbe89-99de-4610-b072-b519bc5d8aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567621631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.567621631
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.1481095086
Short name T768
Test name
Test status
Simulation time 557092045 ps
CPU time 1.94 seconds
Started Jun 28 04:39:25 PM PDT 24
Finished Jun 28 04:39:29 PM PDT 24
Peak memory 199556 kb
Host smart-12f910b8-9692-44d2-87fd-b6211cf44f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481095086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.1481095086
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.2520207040
Short name T976
Test name
Test status
Simulation time 1061491335 ps
CPU time 1.97 seconds
Started Jun 28 04:39:38 PM PDT 24
Finished Jun 28 04:39:42 PM PDT 24
Peak memory 199748 kb
Host smart-57bce0d7-9a44-4543-bbe8-92ad2b423a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520207040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2520207040
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.538711065
Short name T583
Test name
Test status
Simulation time 85562989108 ps
CPU time 109.69 seconds
Started Jun 28 04:39:33 PM PDT 24
Finished Jun 28 04:41:23 PM PDT 24
Peak memory 199728 kb
Host smart-22a6dd42-ad93-4e56-81b4-8e55ec2852ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538711065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.538711065
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.1376018192
Short name T1023
Test name
Test status
Simulation time 15803190 ps
CPU time 0.55 seconds
Started Jun 28 04:39:37 PM PDT 24
Finished Jun 28 04:39:38 PM PDT 24
Peak memory 194596 kb
Host smart-76ba4565-cbb3-4e52-bbf3-92c3ce70aeaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376018192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1376018192
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.875393175
Short name T245
Test name
Test status
Simulation time 104022448840 ps
CPU time 183.51 seconds
Started Jun 28 04:39:37 PM PDT 24
Finished Jun 28 04:42:41 PM PDT 24
Peak memory 199916 kb
Host smart-8c00680a-651e-4cda-bef6-d47e69f3b750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875393175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.875393175
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.218922129
Short name T540
Test name
Test status
Simulation time 69654267169 ps
CPU time 36.46 seconds
Started Jun 28 04:39:39 PM PDT 24
Finished Jun 28 04:40:16 PM PDT 24
Peak memory 198176 kb
Host smart-46cf197d-f20a-4fdd-a477-ca62e6301730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218922129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.218922129
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.91109816
Short name T150
Test name
Test status
Simulation time 18787292118 ps
CPU time 15.78 seconds
Started Jun 28 04:39:38 PM PDT 24
Finished Jun 28 04:39:55 PM PDT 24
Peak memory 199708 kb
Host smart-c56b11ab-0989-4e1d-a8cc-2cd3f109bccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91109816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.91109816
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.2599261012
Short name T472
Test name
Test status
Simulation time 154709276284 ps
CPU time 123.86 seconds
Started Jun 28 04:39:37 PM PDT 24
Finished Jun 28 04:41:41 PM PDT 24
Peak memory 196608 kb
Host smart-606b127d-ccf0-4692-8542-89ea49ed500f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599261012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.2599261012
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.4159817016
Short name T949
Test name
Test status
Simulation time 129019939932 ps
CPU time 1174.16 seconds
Started Jun 28 04:39:38 PM PDT 24
Finished Jun 28 04:59:13 PM PDT 24
Peak memory 199908 kb
Host smart-f5a0d3c6-aabb-410a-8b0f-f6d6d5f12aee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4159817016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.4159817016
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.3611058871
Short name T742
Test name
Test status
Simulation time 616199925 ps
CPU time 1.41 seconds
Started Jun 28 04:39:36 PM PDT 24
Finished Jun 28 04:39:38 PM PDT 24
Peak memory 195228 kb
Host smart-49b1ee50-87bd-46f0-9731-90bec6611831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611058871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.3611058871
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_perf.3781332333
Short name T431
Test name
Test status
Simulation time 19503722614 ps
CPU time 206.74 seconds
Started Jun 28 04:39:37 PM PDT 24
Finished Jun 28 04:43:05 PM PDT 24
Peak memory 199896 kb
Host smart-4ec2d456-be7f-4747-a499-3edf41615572
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3781332333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3781332333
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.458144091
Short name T592
Test name
Test status
Simulation time 3783552805 ps
CPU time 7.76 seconds
Started Jun 28 04:39:39 PM PDT 24
Finished Jun 28 04:39:48 PM PDT 24
Peak memory 196320 kb
Host smart-611ddcfa-4a19-4175-b346-4eabd53d3117
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=458144091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.458144091
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.601620747
Short name T41
Test name
Test status
Simulation time 50172456536 ps
CPU time 12.8 seconds
Started Jun 28 04:39:38 PM PDT 24
Finished Jun 28 04:39:52 PM PDT 24
Peak memory 199828 kb
Host smart-b2c9508d-ba0b-4ee4-bcd6-5576e6212310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601620747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.601620747
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.2095143474
Short name T1038
Test name
Test status
Simulation time 38299837014 ps
CPU time 46.23 seconds
Started Jun 28 04:39:37 PM PDT 24
Finished Jun 28 04:40:25 PM PDT 24
Peak memory 195616 kb
Host smart-52494de9-a321-4d6a-a285-5b9a4eee9320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095143474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2095143474
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1414704634
Short name T629
Test name
Test status
Simulation time 278460248 ps
CPU time 1.02 seconds
Started Jun 28 04:39:39 PM PDT 24
Finished Jun 28 04:39:41 PM PDT 24
Peak memory 198440 kb
Host smart-5e322d20-02b4-4a9e-b30c-9d757f76ddb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414704634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1414704634
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.1748118270
Short name T703
Test name
Test status
Simulation time 205278600717 ps
CPU time 378.06 seconds
Started Jun 28 04:39:38 PM PDT 24
Finished Jun 28 04:45:57 PM PDT 24
Peak memory 199884 kb
Host smart-c3bd0bee-1a94-4bba-a98d-67276987dcd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748118270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.1748118270
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.718806960
Short name T888
Test name
Test status
Simulation time 37500998170 ps
CPU time 325.18 seconds
Started Jun 28 04:39:39 PM PDT 24
Finished Jun 28 04:45:05 PM PDT 24
Peak memory 216412 kb
Host smart-4f90062e-08e3-459e-8f12-986a62bc4e16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718806960 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.718806960
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.2053769752
Short name T420
Test name
Test status
Simulation time 1843672014 ps
CPU time 2.47 seconds
Started Jun 28 04:39:37 PM PDT 24
Finished Jun 28 04:39:40 PM PDT 24
Peak memory 198792 kb
Host smart-e7f32db4-8f4f-44aa-b136-d2b15c25b5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053769752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.2053769752
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.278555016
Short name T622
Test name
Test status
Simulation time 56959863032 ps
CPU time 46.22 seconds
Started Jun 28 04:39:35 PM PDT 24
Finished Jun 28 04:40:21 PM PDT 24
Peak memory 199844 kb
Host smart-9bca83e9-81b7-4d97-b1fb-a866e36d94b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278555016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.278555016
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.1616202202
Short name T377
Test name
Test status
Simulation time 19720529 ps
CPU time 0.57 seconds
Started Jun 28 04:36:47 PM PDT 24
Finished Jun 28 04:36:49 PM PDT 24
Peak memory 195060 kb
Host smart-f9ac07cf-410b-4014-9bd3-193d92902ffb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616202202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1616202202
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1105832810
Short name T677
Test name
Test status
Simulation time 169440522160 ps
CPU time 178.78 seconds
Started Jun 28 04:36:37 PM PDT 24
Finished Jun 28 04:39:38 PM PDT 24
Peak memory 199748 kb
Host smart-3eb914f4-8db0-4ac5-a0db-9517116c1b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105832810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1105832810
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.8703978
Short name T647
Test name
Test status
Simulation time 141699012374 ps
CPU time 19.29 seconds
Started Jun 28 04:36:43 PM PDT 24
Finished Jun 28 04:37:02 PM PDT 24
Peak memory 199488 kb
Host smart-bfe04dfd-f5a1-4bdb-beb1-b8f56ab45c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8703978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.8703978
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.1233209338
Short name T167
Test name
Test status
Simulation time 148937098174 ps
CPU time 212.9 seconds
Started Jun 28 04:36:35 PM PDT 24
Finished Jun 28 04:40:09 PM PDT 24
Peak memory 199788 kb
Host smart-b6fea2f0-8dfa-491f-9b6a-4d8b06e7c06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233209338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1233209338
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.1608968209
Short name T89
Test name
Test status
Simulation time 5235472115 ps
CPU time 8.41 seconds
Started Jun 28 04:36:47 PM PDT 24
Finished Jun 28 04:36:56 PM PDT 24
Peak memory 196636 kb
Host smart-b54d38b8-8243-4043-8285-6614efd5b127
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608968209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.1608968209
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.89250691
Short name T1069
Test name
Test status
Simulation time 155417221149 ps
CPU time 1079.32 seconds
Started Jun 28 04:36:47 PM PDT 24
Finished Jun 28 04:54:48 PM PDT 24
Peak memory 199752 kb
Host smart-62ddb7d4-a6cb-4ee9-a5ed-89822e58d861
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=89250691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.89250691
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.3107855098
Short name T496
Test name
Test status
Simulation time 1742877863 ps
CPU time 1.28 seconds
Started Jun 28 04:36:48 PM PDT 24
Finished Jun 28 04:36:51 PM PDT 24
Peak memory 195872 kb
Host smart-e0e20126-74ff-4c74-9e9b-88e198037980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107855098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3107855098
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_perf.446329878
Short name T1037
Test name
Test status
Simulation time 16818486218 ps
CPU time 235.57 seconds
Started Jun 28 04:36:46 PM PDT 24
Finished Jun 28 04:40:42 PM PDT 24
Peak memory 199760 kb
Host smart-44f976e9-d22d-4966-bf49-73579b7052dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=446329878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.446329878
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.940013932
Short name T981
Test name
Test status
Simulation time 3381980039 ps
CPU time 28.3 seconds
Started Jun 28 04:36:43 PM PDT 24
Finished Jun 28 04:37:12 PM PDT 24
Peak memory 198488 kb
Host smart-1605fc90-26a2-418a-9ce6-17fb37f7f8d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=940013932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.940013932
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2977603999
Short name T124
Test name
Test status
Simulation time 102238519467 ps
CPU time 17.7 seconds
Started Jun 28 04:36:47 PM PDT 24
Finished Jun 28 04:37:07 PM PDT 24
Peak memory 199436 kb
Host smart-966f8889-1311-4914-afe9-ec37540bd5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977603999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2977603999
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.3342417440
Short name T850
Test name
Test status
Simulation time 3750478531 ps
CPU time 5.26 seconds
Started Jun 28 04:36:48 PM PDT 24
Finished Jun 28 04:36:56 PM PDT 24
Peak memory 195864 kb
Host smart-54593a51-d555-4b7a-9401-3010b64a5beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342417440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.3342417440
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.1606705775
Short name T87
Test name
Test status
Simulation time 112688566 ps
CPU time 0.8 seconds
Started Jun 28 04:36:47 PM PDT 24
Finished Jun 28 04:36:49 PM PDT 24
Peak memory 218344 kb
Host smart-0eac2b89-8dee-4803-92fd-c5b21bf1cd3c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606705775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.1606705775
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.328811209
Short name T704
Test name
Test status
Simulation time 5297423193 ps
CPU time 12.69 seconds
Started Jun 28 04:36:36 PM PDT 24
Finished Jun 28 04:36:49 PM PDT 24
Peak memory 199644 kb
Host smart-da6df52b-6a18-4876-b0c5-d6a67e13b583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328811209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.328811209
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2790756126
Short name T636
Test name
Test status
Simulation time 131317736833 ps
CPU time 390.51 seconds
Started Jun 28 04:36:48 PM PDT 24
Finished Jun 28 04:43:21 PM PDT 24
Peak memory 199924 kb
Host smart-fa0f84b1-d3ca-4eb8-9e65-6050d110f966
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790756126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2790756126
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.3214678582
Short name T786
Test name
Test status
Simulation time 75907468237 ps
CPU time 633.45 seconds
Started Jun 28 04:36:48 PM PDT 24
Finished Jun 28 04:47:25 PM PDT 24
Peak memory 216272 kb
Host smart-5df2c59e-df75-4069-b9f4-e0757bf24b05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214678582 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.3214678582
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.2641603249
Short name T864
Test name
Test status
Simulation time 1230909279 ps
CPU time 1.38 seconds
Started Jun 28 04:36:48 PM PDT 24
Finished Jun 28 04:36:51 PM PDT 24
Peak memory 198568 kb
Host smart-6f4fc089-5dd3-436e-802f-2e54ee7a3198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641603249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2641603249
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3264000729
Short name T390
Test name
Test status
Simulation time 8384772387 ps
CPU time 12.99 seconds
Started Jun 28 04:36:35 PM PDT 24
Finished Jun 28 04:36:49 PM PDT 24
Peak memory 199596 kb
Host smart-985ab23b-7cef-4bfd-8e66-94c7414d969a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264000729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3264000729
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.3469022903
Short name T330
Test name
Test status
Simulation time 14158723 ps
CPU time 0.57 seconds
Started Jun 28 04:39:46 PM PDT 24
Finished Jun 28 04:39:48 PM PDT 24
Peak memory 195060 kb
Host smart-44e34644-f7b8-468b-bdbd-4c6eab70f084
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469022903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3469022903
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.37151398
Short name T255
Test name
Test status
Simulation time 300466017093 ps
CPU time 73.44 seconds
Started Jun 28 04:39:39 PM PDT 24
Finished Jun 28 04:40:54 PM PDT 24
Peak memory 199908 kb
Host smart-cb6db5d0-5679-4ae8-8980-780f9c67510c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37151398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.37151398
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2502631452
Short name T932
Test name
Test status
Simulation time 201590000963 ps
CPU time 495.76 seconds
Started Jun 28 04:39:37 PM PDT 24
Finished Jun 28 04:47:54 PM PDT 24
Peak memory 199768 kb
Host smart-b6c1f0ac-5160-4fdf-97b9-b59a9f38db2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502631452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2502631452
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.2446678275
Short name T579
Test name
Test status
Simulation time 111331252111 ps
CPU time 32.24 seconds
Started Jun 28 04:39:36 PM PDT 24
Finished Jun 28 04:40:09 PM PDT 24
Peak memory 199792 kb
Host smart-f6db2d80-e456-46e9-8826-d70510e35212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446678275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.2446678275
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.2496826652
Short name T518
Test name
Test status
Simulation time 29855062028 ps
CPU time 25.47 seconds
Started Jun 28 04:39:36 PM PDT 24
Finished Jun 28 04:40:02 PM PDT 24
Peak memory 199688 kb
Host smart-3f7deec5-4f4f-4030-8165-63f410d8a056
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496826652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.2496826652
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2705329329
Short name T654
Test name
Test status
Simulation time 108208378959 ps
CPU time 472.26 seconds
Started Jun 28 04:39:46 PM PDT 24
Finished Jun 28 04:47:40 PM PDT 24
Peak memory 199896 kb
Host smart-e126b530-0767-43a9-8731-4305ffe47582
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2705329329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2705329329
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.3106217461
Short name T324
Test name
Test status
Simulation time 9612604455 ps
CPU time 7.21 seconds
Started Jun 28 04:39:56 PM PDT 24
Finished Jun 28 04:40:04 PM PDT 24
Peak memory 198736 kb
Host smart-4e06cb01-1877-4298-a885-beefb7e9c53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106217461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3106217461
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_perf.423249608
Short name T393
Test name
Test status
Simulation time 5943894412 ps
CPU time 172.5 seconds
Started Jun 28 04:39:46 PM PDT 24
Finished Jun 28 04:42:39 PM PDT 24
Peak memory 199692 kb
Host smart-1f4e0a3a-4af7-463f-a586-032c0b785878
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=423249608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.423249608
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.3308908535
Short name T1033
Test name
Test status
Simulation time 1403929439 ps
CPU time 1.95 seconds
Started Jun 28 04:39:39 PM PDT 24
Finished Jun 28 04:39:42 PM PDT 24
Peak memory 198096 kb
Host smart-3cdfd61f-2930-45bc-a1c5-32f7ace7bf7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3308908535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3308908535
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.717574963
Short name T111
Test name
Test status
Simulation time 17207844778 ps
CPU time 126.87 seconds
Started Jun 28 04:39:45 PM PDT 24
Finished Jun 28 04:41:52 PM PDT 24
Peak memory 199820 kb
Host smart-d8ee4e5d-ff49-4b4f-bbe4-d3618ac81210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717574963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.717574963
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.374596845
Short name T1036
Test name
Test status
Simulation time 557461010 ps
CPU time 1.06 seconds
Started Jun 28 04:39:50 PM PDT 24
Finished Jun 28 04:39:51 PM PDT 24
Peak memory 195308 kb
Host smart-5649cdbf-e908-4575-8744-7648ebaae8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374596845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.374596845
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.565500020
Short name T694
Test name
Test status
Simulation time 463788628 ps
CPU time 3.24 seconds
Started Jun 28 04:39:38 PM PDT 24
Finished Jun 28 04:39:42 PM PDT 24
Peak memory 198656 kb
Host smart-be508c90-6d7b-437e-b3c0-4c542d5a79ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565500020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.565500020
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.2008464478
Short name T88
Test name
Test status
Simulation time 20061143907 ps
CPU time 165.71 seconds
Started Jun 28 04:39:46 PM PDT 24
Finished Jun 28 04:42:33 PM PDT 24
Peak memory 208144 kb
Host smart-f501682f-d19d-4e3d-a1a3-a714f6d9fc9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008464478 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.2008464478
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3750487639
Short name T590
Test name
Test status
Simulation time 7031628419 ps
CPU time 9.43 seconds
Started Jun 28 04:39:45 PM PDT 24
Finished Jun 28 04:39:56 PM PDT 24
Peak memory 199648 kb
Host smart-53af25cf-c700-4872-8507-072b9edb6725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750487639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3750487639
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.4041497605
Short name T899
Test name
Test status
Simulation time 11798732792 ps
CPU time 16.29 seconds
Started Jun 28 04:39:40 PM PDT 24
Finished Jun 28 04:39:57 PM PDT 24
Peak memory 198264 kb
Host smart-256dc7bb-7052-427b-bb15-4286f1f1998c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041497605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.4041497605
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.2067559811
Short name T810
Test name
Test status
Simulation time 17115442 ps
CPU time 0.58 seconds
Started Jun 28 04:39:45 PM PDT 24
Finished Jun 28 04:39:47 PM PDT 24
Peak memory 195144 kb
Host smart-d08575ae-dc72-4682-8641-06bc45729930
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067559811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2067559811
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3219176566
Short name T522
Test name
Test status
Simulation time 35411155264 ps
CPU time 29.89 seconds
Started Jun 28 04:39:45 PM PDT 24
Finished Jun 28 04:40:16 PM PDT 24
Peak memory 199612 kb
Host smart-a8eb0ff3-a053-44ec-a1ff-55584b881a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219176566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3219176566
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.3151290121
Short name T231
Test name
Test status
Simulation time 133418756869 ps
CPU time 60.45 seconds
Started Jun 28 04:39:56 PM PDT 24
Finished Jun 28 04:40:57 PM PDT 24
Peak memory 199736 kb
Host smart-0b033b1f-42d8-4e10-90a8-c5327d52f461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151290121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3151290121
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.2261401231
Short name T828
Test name
Test status
Simulation time 75952587873 ps
CPU time 67.81 seconds
Started Jun 28 04:39:49 PM PDT 24
Finished Jun 28 04:40:57 PM PDT 24
Peak memory 199848 kb
Host smart-33865a4e-35b5-493f-8ba2-80dd59c9d852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261401231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2261401231
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.4218875400
Short name T802
Test name
Test status
Simulation time 33705939651 ps
CPU time 28.16 seconds
Started Jun 28 04:39:46 PM PDT 24
Finished Jun 28 04:40:16 PM PDT 24
Peak memory 199080 kb
Host smart-c3bd7775-a864-473a-8565-055c71bbe392
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218875400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.4218875400
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.328607509
Short name T688
Test name
Test status
Simulation time 154383903485 ps
CPU time 321.26 seconds
Started Jun 28 04:39:45 PM PDT 24
Finished Jun 28 04:45:07 PM PDT 24
Peak memory 199832 kb
Host smart-89ed1cb9-5f4e-4e1f-be4f-b9b177059979
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=328607509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.328607509
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1024558893
Short name T381
Test name
Test status
Simulation time 6440041365 ps
CPU time 1.71 seconds
Started Jun 28 04:39:46 PM PDT 24
Finished Jun 28 04:39:49 PM PDT 24
Peak memory 199160 kb
Host smart-d1be87d7-4952-4187-b57e-039a82c64c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024558893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1024558893
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_perf.2745869032
Short name T585
Test name
Test status
Simulation time 8563970652 ps
CPU time 86.71 seconds
Started Jun 28 04:39:45 PM PDT 24
Finished Jun 28 04:41:13 PM PDT 24
Peak memory 199892 kb
Host smart-61eaa2ab-c566-424e-bcb0-66065c9686a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2745869032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2745869032
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.52678687
Short name T464
Test name
Test status
Simulation time 5071007419 ps
CPU time 43.52 seconds
Started Jun 28 04:39:46 PM PDT 24
Finished Jun 28 04:40:31 PM PDT 24
Peak memory 198932 kb
Host smart-fb9f0166-ac30-437d-9104-264997e8d96b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=52678687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.52678687
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.1127883561
Short name T991
Test name
Test status
Simulation time 109923799967 ps
CPU time 175.71 seconds
Started Jun 28 04:39:50 PM PDT 24
Finished Jun 28 04:42:46 PM PDT 24
Peak memory 199660 kb
Host smart-cee88b38-7fbb-42f1-a22e-7c05e6f82ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127883561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1127883561
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.3679601298
Short name T620
Test name
Test status
Simulation time 5728961147 ps
CPU time 4.75 seconds
Started Jun 28 04:39:48 PM PDT 24
Finished Jun 28 04:39:54 PM PDT 24
Peak memory 196148 kb
Host smart-eb484c0c-7bde-499c-9b46-941a37ef71b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679601298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3679601298
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.1645473667
Short name T263
Test name
Test status
Simulation time 718150459 ps
CPU time 3.15 seconds
Started Jun 28 04:39:49 PM PDT 24
Finished Jun 28 04:39:53 PM PDT 24
Peak memory 199852 kb
Host smart-86a6d4a9-a736-4d49-9b12-6972744ca83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645473667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.1645473667
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.2236385454
Short name T303
Test name
Test status
Simulation time 295803233291 ps
CPU time 1829.67 seconds
Started Jun 28 04:39:47 PM PDT 24
Finished Jun 28 05:10:18 PM PDT 24
Peak memory 224704 kb
Host smart-bac10245-dc1d-40ad-9fee-0be9b3a17443
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236385454 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.2236385454
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.2349152344
Short name T443
Test name
Test status
Simulation time 7502906640 ps
CPU time 13.3 seconds
Started Jun 28 04:39:49 PM PDT 24
Finished Jun 28 04:40:02 PM PDT 24
Peak memory 199812 kb
Host smart-76db295c-215c-438c-ade7-fc969de51904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349152344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2349152344
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.84868866
Short name T317
Test name
Test status
Simulation time 45241345525 ps
CPU time 13.05 seconds
Started Jun 28 04:39:54 PM PDT 24
Finished Jun 28 04:40:08 PM PDT 24
Peak memory 197552 kb
Host smart-fbb61d48-fe90-4fbf-b582-4502664da4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84868866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.84868866
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3657936412
Short name T92
Test name
Test status
Simulation time 18148463 ps
CPU time 0.57 seconds
Started Jun 28 04:39:59 PM PDT 24
Finished Jun 28 04:40:00 PM PDT 24
Peak memory 195228 kb
Host smart-33bc5e44-d72a-47dc-a35c-c9dbe04c16d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657936412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3657936412
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.152626043
Short name T575
Test name
Test status
Simulation time 128093087051 ps
CPU time 206.83 seconds
Started Jun 28 04:39:45 PM PDT 24
Finished Jun 28 04:43:12 PM PDT 24
Peak memory 199772 kb
Host smart-52cee607-d652-400c-8d97-bd3106db03eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152626043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.152626043
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.3113651324
Short name T713
Test name
Test status
Simulation time 144600974531 ps
CPU time 297.5 seconds
Started Jun 28 04:39:47 PM PDT 24
Finished Jun 28 04:44:46 PM PDT 24
Peak memory 199856 kb
Host smart-c6d73c7b-50eb-42d0-9c9c-c83299ed2455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113651324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3113651324
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.406182845
Short name T470
Test name
Test status
Simulation time 77401523597 ps
CPU time 61.24 seconds
Started Jun 28 04:39:45 PM PDT 24
Finished Jun 28 04:40:47 PM PDT 24
Peak memory 199748 kb
Host smart-c6253259-ae82-41ed-a3b6-9ec9e5be950f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406182845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.406182845
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.901649432
Short name T817
Test name
Test status
Simulation time 26599844684 ps
CPU time 16.41 seconds
Started Jun 28 04:40:02 PM PDT 24
Finished Jun 28 04:40:19 PM PDT 24
Peak memory 199732 kb
Host smart-8719f2ac-d6ac-4d11-9da8-8b4ed1dff082
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901649432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.901649432
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.2730774335
Short name T504
Test name
Test status
Simulation time 166457012830 ps
CPU time 389.5 seconds
Started Jun 28 04:39:56 PM PDT 24
Finished Jun 28 04:46:26 PM PDT 24
Peak memory 199840 kb
Host smart-938be84c-51e9-41b6-bb79-f04fad98584d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2730774335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2730774335
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.2695610469
Short name T728
Test name
Test status
Simulation time 12220738119 ps
CPU time 26.83 seconds
Started Jun 28 04:40:00 PM PDT 24
Finished Jun 28 04:40:27 PM PDT 24
Peak memory 200052 kb
Host smart-29b482b2-3d0c-40b2-a6dc-3be3c65b94cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695610469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.2695610469
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_perf.256318561
Short name T970
Test name
Test status
Simulation time 22069991750 ps
CPU time 1342.19 seconds
Started Jun 28 04:40:01 PM PDT 24
Finished Jun 28 05:02:24 PM PDT 24
Peak memory 199668 kb
Host smart-2b732daf-7c6c-4c27-960f-bf63a747838e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=256318561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.256318561
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.2348793973
Short name T795
Test name
Test status
Simulation time 7566996680 ps
CPU time 15.73 seconds
Started Jun 28 04:39:46 PM PDT 24
Finished Jun 28 04:40:04 PM PDT 24
Peak memory 198468 kb
Host smart-b2b36ff7-305f-4550-8c55-968f93955a36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2348793973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.2348793973
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.1392714761
Short name T525
Test name
Test status
Simulation time 21704260998 ps
CPU time 34.48 seconds
Started Jun 28 04:40:02 PM PDT 24
Finished Jun 28 04:40:37 PM PDT 24
Peak memory 199848 kb
Host smart-7d75bb90-b031-41f4-893c-d90af0012599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392714761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1392714761
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.757083569
Short name T387
Test name
Test status
Simulation time 3092465805 ps
CPU time 5.19 seconds
Started Jun 28 04:39:58 PM PDT 24
Finished Jun 28 04:40:04 PM PDT 24
Peak memory 195968 kb
Host smart-0170e0d1-5cb4-4d89-b47b-8ff11ff4dc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757083569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.757083569
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.4108555838
Short name T879
Test name
Test status
Simulation time 854868296 ps
CPU time 2.78 seconds
Started Jun 28 04:39:48 PM PDT 24
Finished Jun 28 04:39:51 PM PDT 24
Peak memory 199512 kb
Host smart-f69c4a88-457d-4afc-825a-ecb8511d0a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108555838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.4108555838
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.1168302380
Short name T716
Test name
Test status
Simulation time 1097432048 ps
CPU time 3.58 seconds
Started Jun 28 04:39:57 PM PDT 24
Finished Jun 28 04:40:01 PM PDT 24
Peak memory 198240 kb
Host smart-d0b8d5f8-2217-4ccd-a360-7a1219d7db9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168302380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1168302380
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.3522926504
Short name T437
Test name
Test status
Simulation time 24416087878 ps
CPU time 3.02 seconds
Started Jun 28 04:39:46 PM PDT 24
Finished Jun 28 04:39:50 PM PDT 24
Peak memory 199524 kb
Host smart-1fbd901b-e41a-4a37-8351-7f0c1b6fe53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522926504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.3522926504
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.801869693
Short name T722
Test name
Test status
Simulation time 43990633 ps
CPU time 0.59 seconds
Started Jun 28 04:40:03 PM PDT 24
Finished Jun 28 04:40:04 PM PDT 24
Peak memory 195512 kb
Host smart-5888166b-284c-45e3-86ef-9ff0afd4bbca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801869693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.801869693
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1294902823
Short name T692
Test name
Test status
Simulation time 75402313447 ps
CPU time 33.5 seconds
Started Jun 28 04:40:02 PM PDT 24
Finished Jun 28 04:40:36 PM PDT 24
Peak memory 199852 kb
Host smart-5efc0c30-53fb-4102-adf4-512b97800b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294902823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1294902823
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.1541881288
Short name T244
Test name
Test status
Simulation time 136494975729 ps
CPU time 213.33 seconds
Started Jun 28 04:40:02 PM PDT 24
Finished Jun 28 04:43:36 PM PDT 24
Peak memory 199812 kb
Host smart-74e48337-5f8c-4070-b3a0-a54fd9dff184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541881288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1541881288
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.223350686
Short name T368
Test name
Test status
Simulation time 73910574632 ps
CPU time 57.63 seconds
Started Jun 28 04:40:01 PM PDT 24
Finished Jun 28 04:41:00 PM PDT 24
Peak memory 199856 kb
Host smart-d8e8d42a-4a60-45f3-af2f-0f9d188e111e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223350686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.223350686
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.1251978470
Short name T718
Test name
Test status
Simulation time 22326845634 ps
CPU time 9.07 seconds
Started Jun 28 04:40:02 PM PDT 24
Finished Jun 28 04:40:12 PM PDT 24
Peak memory 197972 kb
Host smart-765e89a8-12af-47db-a626-e4eb8b2f2f66
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251978470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1251978470
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.919157383
Short name T737
Test name
Test status
Simulation time 160044399051 ps
CPU time 296.36 seconds
Started Jun 28 04:40:00 PM PDT 24
Finished Jun 28 04:44:57 PM PDT 24
Peak memory 199916 kb
Host smart-5f34b137-b1e3-4f74-8f1b-b65716e0e241
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=919157383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.919157383
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.4257379081
Short name T534
Test name
Test status
Simulation time 8857747746 ps
CPU time 14.68 seconds
Started Jun 28 04:40:02 PM PDT 24
Finished Jun 28 04:40:18 PM PDT 24
Peak memory 199888 kb
Host smart-69a5d0a0-0757-4152-8fa6-a07a77df3a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257379081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.4257379081
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_perf.1776449521
Short name T965
Test name
Test status
Simulation time 19676341590 ps
CPU time 1091.82 seconds
Started Jun 28 04:39:58 PM PDT 24
Finished Jun 28 04:58:10 PM PDT 24
Peak memory 199856 kb
Host smart-a09afa7a-2418-48b4-88cf-60ad6db49c8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1776449521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1776449521
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.706262337
Short name T400
Test name
Test status
Simulation time 5088649641 ps
CPU time 48.36 seconds
Started Jun 28 04:40:01 PM PDT 24
Finished Jun 28 04:40:50 PM PDT 24
Peak memory 199108 kb
Host smart-e60c3f0f-8c55-43cc-8177-2e17b971c2a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=706262337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.706262337
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.2139615073
Short name T234
Test name
Test status
Simulation time 100670275282 ps
CPU time 225.69 seconds
Started Jun 28 04:40:02 PM PDT 24
Finished Jun 28 04:43:48 PM PDT 24
Peak memory 199816 kb
Host smart-59e8caa6-e0e5-4478-abb1-ed83ddf222c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139615073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.2139615073
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.1712504124
Short name T1032
Test name
Test status
Simulation time 5440623196 ps
CPU time 2.84 seconds
Started Jun 28 04:39:58 PM PDT 24
Finished Jun 28 04:40:02 PM PDT 24
Peak memory 196292 kb
Host smart-1e24b818-08f1-4a60-a955-7f7d7b3cc773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712504124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.1712504124
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1659505142
Short name T355
Test name
Test status
Simulation time 511592917 ps
CPU time 1.6 seconds
Started Jun 28 04:39:56 PM PDT 24
Finished Jun 28 04:39:59 PM PDT 24
Peak memory 198528 kb
Host smart-0facb72e-484c-41ab-96a9-c2a861652f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659505142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1659505142
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.3431580235
Short name T911
Test name
Test status
Simulation time 53641339843 ps
CPU time 144.27 seconds
Started Jun 28 04:39:56 PM PDT 24
Finished Jun 28 04:42:21 PM PDT 24
Peak memory 216476 kb
Host smart-2ce8ce32-bf8f-4861-a5cf-2e060fbed3a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431580235 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.3431580235
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3621470455
Short name T617
Test name
Test status
Simulation time 802072174 ps
CPU time 3.21 seconds
Started Jun 28 04:39:57 PM PDT 24
Finished Jun 28 04:40:01 PM PDT 24
Peak memory 198944 kb
Host smart-6c451235-b314-4e29-bf42-b377c6380b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621470455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3621470455
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.86346747
Short name T731
Test name
Test status
Simulation time 7471792789 ps
CPU time 13.15 seconds
Started Jun 28 04:39:57 PM PDT 24
Finished Jun 28 04:40:11 PM PDT 24
Peak memory 197792 kb
Host smart-dee0802f-8987-4d27-b497-8315e69f9a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86346747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.86346747
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.1853260217
Short name T1042
Test name
Test status
Simulation time 28281770 ps
CPU time 0.53 seconds
Started Jun 28 04:40:08 PM PDT 24
Finished Jun 28 04:40:09 PM PDT 24
Peak memory 194268 kb
Host smart-52c0a331-5d33-4d37-8a0b-54d5c92f4246
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853260217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1853260217
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.3348116218
Short name T1083
Test name
Test status
Simulation time 118211531868 ps
CPU time 155.31 seconds
Started Jun 28 04:40:02 PM PDT 24
Finished Jun 28 04:42:39 PM PDT 24
Peak memory 199916 kb
Host smart-b968f642-0ca7-4677-b93e-19b29b5701e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348116218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3348116218
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3475997317
Short name T1076
Test name
Test status
Simulation time 20330955882 ps
CPU time 13.15 seconds
Started Jun 28 04:40:00 PM PDT 24
Finished Jun 28 04:40:14 PM PDT 24
Peak memory 199780 kb
Host smart-d6ba95a2-8efa-4488-81a4-25110fb69c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475997317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3475997317
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_intr.1376388822
Short name T954
Test name
Test status
Simulation time 245379318340 ps
CPU time 41.82 seconds
Started Jun 28 04:40:08 PM PDT 24
Finished Jun 28 04:40:51 PM PDT 24
Peak memory 197288 kb
Host smart-038c44c6-682f-4b6a-8709-d8a982b9fe0d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376388822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1376388822
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.2795588059
Short name T227
Test name
Test status
Simulation time 147233149578 ps
CPU time 479.68 seconds
Started Jun 28 04:40:08 PM PDT 24
Finished Jun 28 04:48:08 PM PDT 24
Peak memory 199836 kb
Host smart-dad31158-bbf4-45fe-9994-7c141f1fa817
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2795588059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2795588059
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.4127630682
Short name T773
Test name
Test status
Simulation time 13242832985 ps
CPU time 6.69 seconds
Started Jun 28 04:40:11 PM PDT 24
Finished Jun 28 04:40:18 PM PDT 24
Peak memory 199848 kb
Host smart-d0242575-ad6e-4872-a0f5-7d69ee0595f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127630682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.4127630682
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_perf.1271010191
Short name T905
Test name
Test status
Simulation time 14947640102 ps
CPU time 45.15 seconds
Started Jun 28 04:40:12 PM PDT 24
Finished Jun 28 04:40:57 PM PDT 24
Peak memory 199356 kb
Host smart-9cb37992-e854-41c0-ab93-4dec4286ddfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1271010191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.1271010191
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2092091883
Short name T1019
Test name
Test status
Simulation time 7388048647 ps
CPU time 15.86 seconds
Started Jun 28 04:40:10 PM PDT 24
Finished Jun 28 04:40:26 PM PDT 24
Peak memory 198036 kb
Host smart-793330dd-b9f2-420b-978b-e37c4a7f446c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2092091883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2092091883
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.365445788
Short name T842
Test name
Test status
Simulation time 47459784786 ps
CPU time 67.59 seconds
Started Jun 28 04:40:07 PM PDT 24
Finished Jun 28 04:41:16 PM PDT 24
Peak memory 199852 kb
Host smart-f28408db-a3d7-4b9f-9d4b-50d23c2a7afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365445788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.365445788
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.967225377
Short name T595
Test name
Test status
Simulation time 7361939026 ps
CPU time 5.55 seconds
Started Jun 28 04:40:11 PM PDT 24
Finished Jun 28 04:40:17 PM PDT 24
Peak memory 195948 kb
Host smart-7c22fd00-259c-4ecc-bac2-042167475989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967225377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.967225377
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.2386029619
Short name T1067
Test name
Test status
Simulation time 1074162927 ps
CPU time 0.99 seconds
Started Jun 28 04:39:58 PM PDT 24
Finished Jun 28 04:40:00 PM PDT 24
Peak memory 198468 kb
Host smart-e0b02bcd-c174-4c61-a0fb-539d76146eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386029619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2386029619
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2077691605
Short name T998
Test name
Test status
Simulation time 277432297304 ps
CPU time 530.09 seconds
Started Jun 28 04:40:10 PM PDT 24
Finished Jun 28 04:49:01 PM PDT 24
Peak memory 199796 kb
Host smart-3595a0c6-022b-4e43-a44d-9f368f1bd2dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077691605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2077691605
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.873987061
Short name T974
Test name
Test status
Simulation time 82326272905 ps
CPU time 166.36 seconds
Started Jun 28 04:40:09 PM PDT 24
Finished Jun 28 04:42:56 PM PDT 24
Peak memory 216132 kb
Host smart-e672ec0c-94df-4550-a633-34d7ad597dc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873987061 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.873987061
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.3759608430
Short name T46
Test name
Test status
Simulation time 1998145131 ps
CPU time 1.72 seconds
Started Jun 28 04:40:07 PM PDT 24
Finished Jun 28 04:40:09 PM PDT 24
Peak memory 198156 kb
Host smart-26d18bfe-afc0-44a7-8b6a-38bcc76b25dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759608430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.3759608430
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.3667756385
Short name T1004
Test name
Test status
Simulation time 52185937305 ps
CPU time 100.44 seconds
Started Jun 28 04:39:57 PM PDT 24
Finished Jun 28 04:41:39 PM PDT 24
Peak memory 199884 kb
Host smart-ded18165-e86d-4879-97b3-5d58f2ff2c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667756385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3667756385
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.1686588713
Short name T892
Test name
Test status
Simulation time 37804714 ps
CPU time 0.55 seconds
Started Jun 28 04:40:17 PM PDT 24
Finished Jun 28 04:40:18 PM PDT 24
Peak memory 195380 kb
Host smart-4589be7e-0d1f-40d7-8d2f-8ffd927a517a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686588713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1686588713
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.1418698910
Short name T837
Test name
Test status
Simulation time 130108205218 ps
CPU time 94.11 seconds
Started Jun 28 04:40:07 PM PDT 24
Finished Jun 28 04:41:41 PM PDT 24
Peak memory 199684 kb
Host smart-3ed683fa-bb2d-45c5-8f61-05c639689b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418698910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1418698910
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.35746848
Short name T835
Test name
Test status
Simulation time 20001722869 ps
CPU time 38.57 seconds
Started Jun 28 04:40:11 PM PDT 24
Finished Jun 28 04:40:50 PM PDT 24
Peak memory 199816 kb
Host smart-236e3d2a-af82-477b-95b0-9b1ae5ffbaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35746848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.35746848
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.3878193486
Short name T1022
Test name
Test status
Simulation time 65826329602 ps
CPU time 23.27 seconds
Started Jun 28 04:40:11 PM PDT 24
Finished Jun 28 04:40:34 PM PDT 24
Peak memory 199812 kb
Host smart-e35421bd-1b99-4ef7-9e8e-33be9f9ae474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878193486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3878193486
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.3149383634
Short name T309
Test name
Test status
Simulation time 242048237899 ps
CPU time 49.56 seconds
Started Jun 28 04:40:06 PM PDT 24
Finished Jun 28 04:40:56 PM PDT 24
Peak memory 199760 kb
Host smart-0ad5ff9d-eb9e-467f-badb-a014502e4711
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149383634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3149383634
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.1909921640
Short name T237
Test name
Test status
Simulation time 148718608878 ps
CPU time 194.53 seconds
Started Jun 28 04:40:11 PM PDT 24
Finished Jun 28 04:43:26 PM PDT 24
Peak memory 199800 kb
Host smart-9b25b990-b6da-4f8a-a2e2-9da966d2aa57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1909921640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1909921640
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.718275145
Short name T44
Test name
Test status
Simulation time 2777343650 ps
CPU time 5.24 seconds
Started Jun 28 04:40:12 PM PDT 24
Finished Jun 28 04:40:17 PM PDT 24
Peak memory 195792 kb
Host smart-54ae84ee-3302-4d2f-a52b-7f8ab5f0d408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718275145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.718275145
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_perf.3314290990
Short name T813
Test name
Test status
Simulation time 15388739920 ps
CPU time 355.35 seconds
Started Jun 28 04:40:09 PM PDT 24
Finished Jun 28 04:46:05 PM PDT 24
Peak memory 199808 kb
Host smart-adb008d2-6a46-441c-bea4-99e976bc29d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3314290990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3314290990
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.1603005783
Short name T323
Test name
Test status
Simulation time 4610175296 ps
CPU time 3.92 seconds
Started Jun 28 04:40:07 PM PDT 24
Finished Jun 28 04:40:11 PM PDT 24
Peak memory 198996 kb
Host smart-39d0204b-c3ab-41aa-b89e-23a55952a831
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1603005783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.1603005783
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.2504016717
Short name T256
Test name
Test status
Simulation time 234526155871 ps
CPU time 51.19 seconds
Started Jun 28 04:40:08 PM PDT 24
Finished Jun 28 04:41:00 PM PDT 24
Peak memory 199416 kb
Host smart-4cf845a1-50e1-4d18-a53d-c8e3c4f815b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504016717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2504016717
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.971257246
Short name T797
Test name
Test status
Simulation time 3180335240 ps
CPU time 2.07 seconds
Started Jun 28 04:40:08 PM PDT 24
Finished Jun 28 04:40:10 PM PDT 24
Peak memory 196324 kb
Host smart-e6d74dc4-44ae-4907-8b9d-efafb6ab2ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971257246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.971257246
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2932369886
Short name T357
Test name
Test status
Simulation time 5388835148 ps
CPU time 9.17 seconds
Started Jun 28 04:40:10 PM PDT 24
Finished Jun 28 04:40:19 PM PDT 24
Peak memory 199796 kb
Host smart-566ab219-35fb-4b39-879d-78bd0c13cd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932369886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2932369886
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.2169813080
Short name T206
Test name
Test status
Simulation time 156375879945 ps
CPU time 76.24 seconds
Started Jun 28 04:40:20 PM PDT 24
Finished Jun 28 04:41:37 PM PDT 24
Peak memory 200008 kb
Host smart-80dde7c8-5dee-4645-8b13-03699352963e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169813080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2169813080
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.3179530471
Short name T208
Test name
Test status
Simulation time 220376079721 ps
CPU time 541.78 seconds
Started Jun 28 04:40:16 PM PDT 24
Finished Jun 28 04:49:19 PM PDT 24
Peak memory 216412 kb
Host smart-4c282619-08f9-4384-b252-87ba58771be9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179530471 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.3179530471
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.1689169310
Short name T705
Test name
Test status
Simulation time 2001954810 ps
CPU time 1.84 seconds
Started Jun 28 04:40:14 PM PDT 24
Finished Jun 28 04:40:16 PM PDT 24
Peak memory 198564 kb
Host smart-4160ef03-4995-4087-8282-7b1fe9586818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689169310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.1689169310
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.1409192327
Short name T613
Test name
Test status
Simulation time 114760835112 ps
CPU time 86.94 seconds
Started Jun 28 04:40:07 PM PDT 24
Finished Jun 28 04:41:35 PM PDT 24
Peak memory 199804 kb
Host smart-c097d62f-6304-466d-b5d1-631cf23b8e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409192327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1409192327
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.2401564786
Short name T1013
Test name
Test status
Simulation time 14167979 ps
CPU time 0.56 seconds
Started Jun 28 04:40:17 PM PDT 24
Finished Jun 28 04:40:18 PM PDT 24
Peak memory 195428 kb
Host smart-78656492-fa81-4c1b-b133-a034399f0c9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401564786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2401564786
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.3338077178
Short name T409
Test name
Test status
Simulation time 72465718589 ps
CPU time 31.34 seconds
Started Jun 28 04:40:18 PM PDT 24
Finished Jun 28 04:40:50 PM PDT 24
Peak memory 199900 kb
Host smart-027b25ed-a05b-4ce7-b15c-2dbb5a080fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338077178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.3338077178
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.1545730386
Short name T822
Test name
Test status
Simulation time 49984256809 ps
CPU time 71.1 seconds
Started Jun 28 04:40:17 PM PDT 24
Finished Jun 28 04:41:29 PM PDT 24
Peak memory 199772 kb
Host smart-88e166c6-a008-49db-9b09-0f6bef4d789b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545730386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1545730386
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.1964835080
Short name T1051
Test name
Test status
Simulation time 121678584010 ps
CPU time 43.77 seconds
Started Jun 28 04:40:21 PM PDT 24
Finished Jun 28 04:41:05 PM PDT 24
Peak memory 199772 kb
Host smart-725c5777-3e53-4467-a9da-91852e197a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964835080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.1964835080
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.986254747
Short name T856
Test name
Test status
Simulation time 62394346244 ps
CPU time 98.69 seconds
Started Jun 28 04:40:19 PM PDT 24
Finished Jun 28 04:41:59 PM PDT 24
Peak memory 199828 kb
Host smart-e9104ea5-4bc0-40c1-87f9-6ff81e215c19
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986254747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.986254747
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3105998414
Short name T1040
Test name
Test status
Simulation time 98165816415 ps
CPU time 361.17 seconds
Started Jun 28 04:40:18 PM PDT 24
Finished Jun 28 04:46:20 PM PDT 24
Peak memory 199896 kb
Host smart-d70977fe-6626-4cd4-a26b-181402801ffd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3105998414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3105998414
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2557641640
Short name T883
Test name
Test status
Simulation time 9278604950 ps
CPU time 14.29 seconds
Started Jun 28 04:40:16 PM PDT 24
Finished Jun 28 04:40:31 PM PDT 24
Peak memory 199828 kb
Host smart-be73f999-fe40-4ee8-aed8-10659112bc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557641640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2557641640
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_perf.3369754842
Short name T362
Test name
Test status
Simulation time 10803916766 ps
CPU time 610.07 seconds
Started Jun 28 04:40:17 PM PDT 24
Finished Jun 28 04:50:28 PM PDT 24
Peak memory 199892 kb
Host smart-036d429f-cfae-44d2-9177-26c43080a820
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3369754842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3369754842
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.3701766834
Short name T366
Test name
Test status
Simulation time 4640623990 ps
CPU time 13.94 seconds
Started Jun 28 04:40:17 PM PDT 24
Finished Jun 28 04:40:31 PM PDT 24
Peak memory 199012 kb
Host smart-985efa78-70c0-4739-9acd-aa0127729eb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3701766834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3701766834
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.3725541155
Short name T573
Test name
Test status
Simulation time 105345500158 ps
CPU time 86.04 seconds
Started Jun 28 04:40:19 PM PDT 24
Finished Jun 28 04:41:45 PM PDT 24
Peak memory 199896 kb
Host smart-a9a20953-6c20-40dc-81b5-710b10d5bcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725541155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.3725541155
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.4158364007
Short name T889
Test name
Test status
Simulation time 2601754223 ps
CPU time 2.69 seconds
Started Jun 28 04:40:19 PM PDT 24
Finished Jun 28 04:40:22 PM PDT 24
Peak memory 195860 kb
Host smart-624a9cf1-84d0-4e58-9c11-13d6196aaa25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158364007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.4158364007
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.150615960
Short name T715
Test name
Test status
Simulation time 312291588 ps
CPU time 1.12 seconds
Started Jun 28 04:40:18 PM PDT 24
Finished Jun 28 04:40:19 PM PDT 24
Peak memory 198664 kb
Host smart-bda1dbac-b194-48e1-8a24-fcaeda36f184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150615960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.150615960
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.959322146
Short name T359
Test name
Test status
Simulation time 7950872171 ps
CPU time 14.69 seconds
Started Jun 28 04:40:21 PM PDT 24
Finished Jun 28 04:40:36 PM PDT 24
Peak memory 198712 kb
Host smart-927bb9e8-5949-4dec-8f89-b8da31efea98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959322146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.959322146
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.891075620
Short name T511
Test name
Test status
Simulation time 64430673068 ps
CPU time 51.99 seconds
Started Jun 28 04:40:16 PM PDT 24
Finished Jun 28 04:41:09 PM PDT 24
Peak memory 199844 kb
Host smart-e4877076-06cc-4525-891e-d312e5a43a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891075620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.891075620
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.3028488714
Short name T358
Test name
Test status
Simulation time 10909050 ps
CPU time 0.55 seconds
Started Jun 28 04:40:35 PM PDT 24
Finished Jun 28 04:40:36 PM PDT 24
Peak memory 194204 kb
Host smart-15a39e83-4ddf-4165-bf97-0618a15fd785
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028488714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3028488714
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.3905296799
Short name T545
Test name
Test status
Simulation time 58858476769 ps
CPU time 92.47 seconds
Started Jun 28 04:40:20 PM PDT 24
Finished Jun 28 04:41:53 PM PDT 24
Peak memory 200048 kb
Host smart-c2248a75-5afd-41cd-8b4b-a556ad40e214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905296799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3905296799
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1104934975
Short name T966
Test name
Test status
Simulation time 25960155021 ps
CPU time 59.12 seconds
Started Jun 28 04:40:16 PM PDT 24
Finished Jun 28 04:41:15 PM PDT 24
Peak memory 199644 kb
Host smart-9d20019f-5deb-485d-9f7b-fd2dcb238251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104934975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1104934975
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.2538166843
Short name T187
Test name
Test status
Simulation time 53830932000 ps
CPU time 50.7 seconds
Started Jun 28 04:40:21 PM PDT 24
Finished Jun 28 04:41:12 PM PDT 24
Peak memory 198736 kb
Host smart-db0906ea-f02f-4a84-aafd-871224f5a22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538166843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.2538166843
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.3065871533
Short name T308
Test name
Test status
Simulation time 22345801522 ps
CPU time 7.72 seconds
Started Jun 28 04:40:17 PM PDT 24
Finished Jun 28 04:40:25 PM PDT 24
Peak memory 198604 kb
Host smart-e4db2ce7-0215-4262-aca5-a366d636f68d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065871533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.3065871533
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.3750450742
Short name T482
Test name
Test status
Simulation time 37573826512 ps
CPU time 110.9 seconds
Started Jun 28 04:40:20 PM PDT 24
Finished Jun 28 04:42:12 PM PDT 24
Peak memory 199900 kb
Host smart-159cafd6-5cfb-43c7-85b0-c4b07ac41c3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3750450742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.3750450742
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.3431067240
Short name T776
Test name
Test status
Simulation time 5058343447 ps
CPU time 5.11 seconds
Started Jun 28 04:40:18 PM PDT 24
Finished Jun 28 04:40:24 PM PDT 24
Peak memory 198264 kb
Host smart-c95d0b0b-708a-4e59-826a-3db824da7176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431067240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3431067240
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_perf.2179528948
Short name T829
Test name
Test status
Simulation time 19562077848 ps
CPU time 898.46 seconds
Started Jun 28 04:40:19 PM PDT 24
Finished Jun 28 04:55:18 PM PDT 24
Peak memory 200076 kb
Host smart-73cb6e6e-ee50-42cc-9e90-bba386863036
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2179528948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2179528948
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.1035463852
Short name T820
Test name
Test status
Simulation time 3893148721 ps
CPU time 13.89 seconds
Started Jun 28 04:40:17 PM PDT 24
Finished Jun 28 04:40:32 PM PDT 24
Peak memory 198976 kb
Host smart-82c591d4-45c3-45dd-8269-911c6c5cadcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1035463852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1035463852
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3050598615
Short name T596
Test name
Test status
Simulation time 19112050584 ps
CPU time 26.94 seconds
Started Jun 28 04:40:18 PM PDT 24
Finished Jun 28 04:40:45 PM PDT 24
Peak memory 199752 kb
Host smart-de5faf02-75fb-4b85-ac0e-1aa205d306fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050598615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3050598615
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.3210613899
Short name T500
Test name
Test status
Simulation time 750559320 ps
CPU time 1.65 seconds
Started Jun 28 04:40:17 PM PDT 24
Finished Jun 28 04:40:19 PM PDT 24
Peak memory 195348 kb
Host smart-a57846cd-226b-42f1-be2e-6f0869b49af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210613899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3210613899
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.4239987544
Short name T849
Test name
Test status
Simulation time 6062699248 ps
CPU time 8.34 seconds
Started Jun 28 04:40:17 PM PDT 24
Finished Jun 28 04:40:26 PM PDT 24
Peak memory 199420 kb
Host smart-39ffe79e-d10d-4d89-b72d-7abc136b9215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239987544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.4239987544
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.3965768806
Short name T884
Test name
Test status
Simulation time 662763069641 ps
CPU time 333.03 seconds
Started Jun 28 04:40:36 PM PDT 24
Finished Jun 28 04:46:10 PM PDT 24
Peak memory 199880 kb
Host smart-d00182ec-8666-498f-8268-219750c5dd4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965768806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.3965768806
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.3931994259
Short name T28
Test name
Test status
Simulation time 11050344675 ps
CPU time 169.84 seconds
Started Jun 28 04:40:17 PM PDT 24
Finished Jun 28 04:43:08 PM PDT 24
Peak memory 215384 kb
Host smart-a8f832e5-2c84-43f3-80f0-54af24f112b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931994259 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.3931994259
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.4059317037
Short name T248
Test name
Test status
Simulation time 6011916638 ps
CPU time 18.05 seconds
Started Jun 28 04:40:18 PM PDT 24
Finished Jun 28 04:40:37 PM PDT 24
Peak memory 199896 kb
Host smart-382b98d7-1272-45a2-a969-2f60efa17bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059317037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.4059317037
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.2130597762
Short name T43
Test name
Test status
Simulation time 88469162589 ps
CPU time 155.13 seconds
Started Jun 28 04:40:20 PM PDT 24
Finished Jun 28 04:42:55 PM PDT 24
Peak memory 200024 kb
Host smart-ab177502-a2ae-4d13-bbe4-4c99ddcc9014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130597762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2130597762
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3438282285
Short name T1075
Test name
Test status
Simulation time 92857083 ps
CPU time 0.55 seconds
Started Jun 28 04:40:36 PM PDT 24
Finished Jun 28 04:40:38 PM PDT 24
Peak memory 195128 kb
Host smart-dd1fe613-b52f-48b3-8733-65028a0d01bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438282285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3438282285
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.840578435
Short name T1085
Test name
Test status
Simulation time 43511242655 ps
CPU time 72.76 seconds
Started Jun 28 04:40:36 PM PDT 24
Finished Jun 28 04:41:50 PM PDT 24
Peak memory 199836 kb
Host smart-bc791470-d8a2-4e5e-89b5-55853c678ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840578435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.840578435
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.3040204888
Short name T1047
Test name
Test status
Simulation time 22721585258 ps
CPU time 7.81 seconds
Started Jun 28 04:40:36 PM PDT 24
Finished Jun 28 04:40:45 PM PDT 24
Peak memory 197880 kb
Host smart-6eb47d55-4b54-4023-8179-bf915295130b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040204888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.3040204888
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.2006606877
Short name T1005
Test name
Test status
Simulation time 40327680680 ps
CPU time 65 seconds
Started Jun 28 04:40:37 PM PDT 24
Finished Jun 28 04:41:43 PM PDT 24
Peak memory 199768 kb
Host smart-7a616e5e-8e96-47dd-b4cc-b350fa9fffb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006606877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.2006606877
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.45174190
Short name T94
Test name
Test status
Simulation time 219207136718 ps
CPU time 83.66 seconds
Started Jun 28 04:40:36 PM PDT 24
Finished Jun 28 04:42:01 PM PDT 24
Peak memory 197196 kb
Host smart-0f9cfc8e-9494-4717-9d73-2bdb9a5246f2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45174190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.45174190
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.160647180
Short name T1024
Test name
Test status
Simulation time 149655810470 ps
CPU time 866.3 seconds
Started Jun 28 04:40:37 PM PDT 24
Finished Jun 28 04:55:05 PM PDT 24
Peak memory 199748 kb
Host smart-ed4c8b99-bd5f-47e0-8668-9b69a39b6ee9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=160647180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.160647180
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.2886510525
Short name T920
Test name
Test status
Simulation time 734689879 ps
CPU time 1.2 seconds
Started Jun 28 04:40:36 PM PDT 24
Finished Jun 28 04:40:38 PM PDT 24
Peak memory 195452 kb
Host smart-7b9b3b9b-9e13-4b10-9525-116d56896639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886510525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.2886510525
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.3122096927
Short name T290
Test name
Test status
Simulation time 77270006832 ps
CPU time 18.66 seconds
Started Jun 28 04:40:36 PM PDT 24
Finished Jun 28 04:40:56 PM PDT 24
Peak memory 199852 kb
Host smart-1e5f60c5-5766-48f4-b9c3-e29270992f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122096927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.3122096927
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.359098408
Short name T918
Test name
Test status
Simulation time 18317795490 ps
CPU time 241.31 seconds
Started Jun 28 04:40:37 PM PDT 24
Finished Jun 28 04:44:39 PM PDT 24
Peak memory 199928 kb
Host smart-d03dcaa1-c583-4400-abf3-7ea1f4444434
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=359098408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.359098408
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2706775700
Short name T360
Test name
Test status
Simulation time 4567108850 ps
CPU time 17.07 seconds
Started Jun 28 04:40:38 PM PDT 24
Finished Jun 28 04:40:56 PM PDT 24
Peak memory 198676 kb
Host smart-8afc3208-5288-46fa-8cd9-ede346b0e9b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2706775700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2706775700
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.3184605888
Short name T977
Test name
Test status
Simulation time 76890186088 ps
CPU time 64.89 seconds
Started Jun 28 04:40:39 PM PDT 24
Finished Jun 28 04:41:45 PM PDT 24
Peak memory 199676 kb
Host smart-682dec82-c1e5-4095-be7a-2b0ac2505a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184605888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3184605888
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.834465084
Short name T921
Test name
Test status
Simulation time 28805580414 ps
CPU time 24.23 seconds
Started Jun 28 04:40:37 PM PDT 24
Finished Jun 28 04:41:02 PM PDT 24
Peak memory 195880 kb
Host smart-8f54132e-dc89-4ae9-bf51-a521dfec4a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834465084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.834465084
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.4245298434
Short name T639
Test name
Test status
Simulation time 6157886196 ps
CPU time 10.5 seconds
Started Jun 28 04:40:36 PM PDT 24
Finished Jun 28 04:40:48 PM PDT 24
Peak memory 199808 kb
Host smart-b44b2d7a-2d20-4703-a711-3e82de988b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245298434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.4245298434
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.4206699519
Short name T901
Test name
Test status
Simulation time 498565571740 ps
CPU time 213.31 seconds
Started Jun 28 04:40:36 PM PDT 24
Finished Jun 28 04:44:10 PM PDT 24
Peak memory 199804 kb
Host smart-0ea051f2-1c03-471c-afde-d3d777c555b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206699519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.4206699519
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.3868142665
Short name T561
Test name
Test status
Simulation time 65193049659 ps
CPU time 858.15 seconds
Started Jun 28 04:40:37 PM PDT 24
Finished Jun 28 04:54:56 PM PDT 24
Peak memory 215552 kb
Host smart-cac2bbeb-dc1d-4dee-b2f3-b247fe7cd698
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868142665 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.3868142665
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.3288347
Short name T252
Test name
Test status
Simulation time 809168778 ps
CPU time 2.23 seconds
Started Jun 28 04:40:36 PM PDT 24
Finished Jun 28 04:40:39 PM PDT 24
Peak memory 199024 kb
Host smart-476b86a0-73f5-4ef6-ad5a-847f27eab575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3288347
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.3643989482
Short name T973
Test name
Test status
Simulation time 58892529224 ps
CPU time 90.29 seconds
Started Jun 28 04:40:35 PM PDT 24
Finished Jun 28 04:42:06 PM PDT 24
Peak memory 199908 kb
Host smart-70ddbd2c-467f-4fd2-a9cd-f8098a5261f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643989482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3643989482
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.3059336608
Short name T321
Test name
Test status
Simulation time 11696863 ps
CPU time 0.55 seconds
Started Jun 28 04:40:49 PM PDT 24
Finished Jun 28 04:40:51 PM PDT 24
Peak memory 195228 kb
Host smart-e17e1df4-a0e3-475b-931d-a343b065ca00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059336608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.3059336608
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.2523356571
Short name T939
Test name
Test status
Simulation time 80611694815 ps
CPU time 34.04 seconds
Started Jun 28 04:40:35 PM PDT 24
Finished Jun 28 04:41:09 PM PDT 24
Peak memory 199852 kb
Host smart-57f601b8-13e8-455b-a621-dcfd9fd160ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523356571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.2523356571
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.79951797
Short name T520
Test name
Test status
Simulation time 39380414501 ps
CPU time 33.4 seconds
Started Jun 28 04:40:36 PM PDT 24
Finished Jun 28 04:41:10 PM PDT 24
Peak memory 199852 kb
Host smart-da80396d-947a-4bcb-8efc-2bb06bc0b9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79951797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.79951797
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.3446980555
Short name T7
Test name
Test status
Simulation time 150195699478 ps
CPU time 114.21 seconds
Started Jun 28 04:40:36 PM PDT 24
Finished Jun 28 04:42:31 PM PDT 24
Peak memory 199780 kb
Host smart-f6b64d91-f1ef-4b4c-823a-aab7f1c079c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446980555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3446980555
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3034776991
Short name T778
Test name
Test status
Simulation time 16239752826 ps
CPU time 3.72 seconds
Started Jun 28 04:40:40 PM PDT 24
Finished Jun 28 04:40:44 PM PDT 24
Peak memory 196820 kb
Host smart-57a11895-819a-4eaf-b416-e28ee1c1367c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034776991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3034776991
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.205252748
Short name T293
Test name
Test status
Simulation time 240605058807 ps
CPU time 117.64 seconds
Started Jun 28 04:40:47 PM PDT 24
Finished Jun 28 04:42:46 PM PDT 24
Peak memory 199892 kb
Host smart-7b456c89-5546-4903-9dd7-015c969ff262
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=205252748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.205252748
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1428405076
Short name T609
Test name
Test status
Simulation time 951079452 ps
CPU time 1.01 seconds
Started Jun 28 04:40:49 PM PDT 24
Finished Jun 28 04:40:52 PM PDT 24
Peak memory 195912 kb
Host smart-15673885-d21d-4c0a-aae8-857d9efdb0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428405076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1428405076
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_perf.1183705895
Short name T277
Test name
Test status
Simulation time 14426625547 ps
CPU time 183.76 seconds
Started Jun 28 04:40:48 PM PDT 24
Finished Jun 28 04:43:53 PM PDT 24
Peak memory 199816 kb
Host smart-2a0c6e57-f86a-4081-b314-fe45a43dfa1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1183705895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1183705895
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.2852646935
Short name T320
Test name
Test status
Simulation time 3279994962 ps
CPU time 9.77 seconds
Started Jun 28 04:40:38 PM PDT 24
Finished Jun 28 04:40:48 PM PDT 24
Peak memory 198048 kb
Host smart-fdc57d75-39bc-4b5b-a8ae-49b5b64cec98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2852646935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.2852646935
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.568119155
Short name T564
Test name
Test status
Simulation time 215195887624 ps
CPU time 67.15 seconds
Started Jun 28 04:40:38 PM PDT 24
Finished Jun 28 04:41:46 PM PDT 24
Peak memory 199896 kb
Host smart-4ff72929-0a07-4de5-87d2-f00e1870006a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568119155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.568119155
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.603897812
Short name T429
Test name
Test status
Simulation time 3074941493 ps
CPU time 3.1 seconds
Started Jun 28 04:40:35 PM PDT 24
Finished Jun 28 04:40:39 PM PDT 24
Peak memory 196400 kb
Host smart-843a70c0-686d-4304-bc54-3cbff062ac68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603897812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.603897812
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.164463321
Short name T562
Test name
Test status
Simulation time 516550862 ps
CPU time 2.32 seconds
Started Jun 28 04:40:36 PM PDT 24
Finished Jun 28 04:40:40 PM PDT 24
Peak memory 198796 kb
Host smart-cb6e6851-df4b-4d40-81f6-b62a632e7560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164463321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.164463321
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.2954894526
Short name T159
Test name
Test status
Simulation time 82434794651 ps
CPU time 37.62 seconds
Started Jun 28 04:40:45 PM PDT 24
Finished Jun 28 04:41:23 PM PDT 24
Peak memory 199804 kb
Host smart-a7d2d991-42b5-4d1e-b189-6c8314756648
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954894526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2954894526
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.731564110
Short name T15
Test name
Test status
Simulation time 1005543492 ps
CPU time 3.04 seconds
Started Jun 28 04:40:47 PM PDT 24
Finished Jun 28 04:40:52 PM PDT 24
Peak memory 198592 kb
Host smart-78d551b1-a476-4b60-9dff-1bdaa0245f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731564110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.731564110
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.3115025972
Short name T314
Test name
Test status
Simulation time 120895924706 ps
CPU time 35.67 seconds
Started Jun 28 04:40:35 PM PDT 24
Finished Jun 28 04:41:11 PM PDT 24
Peak memory 199780 kb
Host smart-6b080aad-ab45-4591-88fc-5650daba568b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115025972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.3115025972
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.3563016265
Short name T960
Test name
Test status
Simulation time 16102191 ps
CPU time 0.56 seconds
Started Jun 28 04:36:47 PM PDT 24
Finished Jun 28 04:36:49 PM PDT 24
Peak memory 195208 kb
Host smart-83a41678-8434-48e8-adda-e4f984f4f477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563016265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3563016265
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.3671608272
Short name T147
Test name
Test status
Simulation time 73173680077 ps
CPU time 36.97 seconds
Started Jun 28 04:36:48 PM PDT 24
Finished Jun 28 04:37:27 PM PDT 24
Peak memory 199916 kb
Host smart-439bcc0d-c3a3-493b-b463-fb16e25536c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671608272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.3671608272
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.1374611377
Short name T684
Test name
Test status
Simulation time 163371090819 ps
CPU time 63.13 seconds
Started Jun 28 04:36:48 PM PDT 24
Finished Jun 28 04:37:54 PM PDT 24
Peak memory 199836 kb
Host smart-6857168f-1638-4869-bfbe-3a0f8c8105b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374611377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.1374611377
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.722408319
Short name T161
Test name
Test status
Simulation time 103501954889 ps
CPU time 43.48 seconds
Started Jun 28 04:36:47 PM PDT 24
Finished Jun 28 04:37:32 PM PDT 24
Peak memory 200052 kb
Host smart-507ffb3e-c945-4ee4-b2e5-607736e71e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722408319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.722408319
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.398300873
Short name T418
Test name
Test status
Simulation time 31212832804 ps
CPU time 8.48 seconds
Started Jun 28 04:36:47 PM PDT 24
Finished Jun 28 04:36:57 PM PDT 24
Peak memory 199036 kb
Host smart-bbcc588a-6c63-496e-b212-6b39f152be16
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398300873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.398300873
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.1878961470
Short name T39
Test name
Test status
Simulation time 74454358451 ps
CPU time 409.45 seconds
Started Jun 28 04:36:46 PM PDT 24
Finished Jun 28 04:43:37 PM PDT 24
Peak memory 199856 kb
Host smart-b6bbe848-4c81-417b-901b-1ab9ef740244
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1878961470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1878961470
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.1824855325
Short name T867
Test name
Test status
Simulation time 2504309007 ps
CPU time 4.65 seconds
Started Jun 28 04:36:46 PM PDT 24
Finished Jun 28 04:36:52 PM PDT 24
Peak memory 198752 kb
Host smart-e1c99fec-60fe-48df-9074-0a2929b759a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824855325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.1824855325
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_perf.1829140138
Short name T414
Test name
Test status
Simulation time 18911816766 ps
CPU time 734.51 seconds
Started Jun 28 04:36:47 PM PDT 24
Finished Jun 28 04:49:04 PM PDT 24
Peak memory 199728 kb
Host smart-fe889521-89fd-425f-9b41-412f1ae4af43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1829140138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.1829140138
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1947338593
Short name T906
Test name
Test status
Simulation time 1503864811 ps
CPU time 1.77 seconds
Started Jun 28 04:36:48 PM PDT 24
Finished Jun 28 04:36:53 PM PDT 24
Peak memory 198624 kb
Host smart-d430018f-84cf-4d4d-b07a-12c698c86b32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1947338593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1947338593
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.3722872792
Short name T931
Test name
Test status
Simulation time 25438880121 ps
CPU time 42.66 seconds
Started Jun 28 04:36:47 PM PDT 24
Finished Jun 28 04:37:32 PM PDT 24
Peak memory 199772 kb
Host smart-bfa89954-b744-4d56-a8f4-ce180e3b6c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722872792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3722872792
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1783752107
Short name T962
Test name
Test status
Simulation time 2997653718 ps
CPU time 3.06 seconds
Started Jun 28 04:36:48 PM PDT 24
Finished Jun 28 04:36:53 PM PDT 24
Peak memory 196608 kb
Host smart-bc7140c0-dde4-4e68-a2d2-0f0e2527b74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783752107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1783752107
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1465033789
Short name T761
Test name
Test status
Simulation time 865365388 ps
CPU time 2.09 seconds
Started Jun 28 04:36:46 PM PDT 24
Finished Jun 28 04:36:49 PM PDT 24
Peak memory 198572 kb
Host smart-a41f2a15-d151-405c-8802-cc62ec58fb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465033789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1465033789
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.518165377
Short name T785
Test name
Test status
Simulation time 297000352877 ps
CPU time 589.69 seconds
Started Jun 28 04:36:47 PM PDT 24
Finished Jun 28 04:46:38 PM PDT 24
Peak memory 199816 kb
Host smart-1cca96ca-9f57-471a-9ccd-8c1d351a3c44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518165377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.518165377
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.677416376
Short name T397
Test name
Test status
Simulation time 1849807907 ps
CPU time 2.2 seconds
Started Jun 28 04:36:49 PM PDT 24
Finished Jun 28 04:36:54 PM PDT 24
Peak memory 199100 kb
Host smart-3b46dbe5-a6f5-47c1-bc99-7ccec1816e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677416376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.677416376
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.1630777685
Short name T895
Test name
Test status
Simulation time 103133549803 ps
CPU time 39.65 seconds
Started Jun 28 04:36:47 PM PDT 24
Finished Jun 28 04:37:28 PM PDT 24
Peak memory 199736 kb
Host smart-e0e98af7-da36-4ea4-9222-ea74ba367bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630777685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1630777685
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.919943834
Short name T110
Test name
Test status
Simulation time 102080572999 ps
CPU time 81.24 seconds
Started Jun 28 04:40:47 PM PDT 24
Finished Jun 28 04:42:09 PM PDT 24
Peak memory 199772 kb
Host smart-b65f1c11-2b7a-4110-b628-e2c815180c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919943834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.919943834
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.3610630043
Short name T623
Test name
Test status
Simulation time 19804976480 ps
CPU time 188.22 seconds
Started Jun 28 04:40:48 PM PDT 24
Finished Jun 28 04:43:57 PM PDT 24
Peak memory 212084 kb
Host smart-543614c6-b647-49fe-b571-f9e42b26aa07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610630043 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.3610630043
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.2047256347
Short name T698
Test name
Test status
Simulation time 71807351746 ps
CPU time 117.17 seconds
Started Jun 28 04:40:47 PM PDT 24
Finished Jun 28 04:42:46 PM PDT 24
Peak memory 200048 kb
Host smart-1ca05375-9a0a-450e-8a12-01bbffd2341c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047256347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2047256347
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.659096309
Short name T770
Test name
Test status
Simulation time 12720047388 ps
CPU time 13.89 seconds
Started Jun 28 04:40:48 PM PDT 24
Finished Jun 28 04:41:03 PM PDT 24
Peak memory 199832 kb
Host smart-2df6e5f2-c2ff-4e5a-a5dc-c823ad8858c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659096309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.659096309
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.303366758
Short name T507
Test name
Test status
Simulation time 35059779181 ps
CPU time 15.7 seconds
Started Jun 28 04:40:48 PM PDT 24
Finished Jun 28 04:41:05 PM PDT 24
Peak memory 199856 kb
Host smart-b42741b7-c81d-4d63-9f49-55c72a315281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303366758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.303366758
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.1053186783
Short name T1049
Test name
Test status
Simulation time 114297084079 ps
CPU time 101.51 seconds
Started Jun 28 04:40:47 PM PDT 24
Finished Jun 28 04:42:30 PM PDT 24
Peak memory 199876 kb
Host smart-6cb783fb-ab57-4c97-992b-9b5ee7c12f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053186783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1053186783
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.242585402
Short name T29
Test name
Test status
Simulation time 23601365424 ps
CPU time 269.44 seconds
Started Jun 28 04:40:50 PM PDT 24
Finished Jun 28 04:45:21 PM PDT 24
Peak memory 215836 kb
Host smart-fc76f151-85c7-4a47-a5ac-b1cb9dc3f214
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242585402 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.242585402
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.1881031268
Short name T599
Test name
Test status
Simulation time 245447148474 ps
CPU time 105.79 seconds
Started Jun 28 04:40:46 PM PDT 24
Finished Jun 28 04:42:33 PM PDT 24
Peak memory 199916 kb
Host smart-2deb40c2-5fa1-4213-a1d6-113bdb0be729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881031268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1881031268
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1468761847
Short name T228
Test name
Test status
Simulation time 164931154141 ps
CPU time 216.38 seconds
Started Jun 28 04:40:48 PM PDT 24
Finished Jun 28 04:44:26 PM PDT 24
Peak memory 199772 kb
Host smart-ed007202-cf5d-4210-b5c1-57e67d5d0fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468761847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1468761847
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.2387127608
Short name T634
Test name
Test status
Simulation time 27754976037 ps
CPU time 47.36 seconds
Started Jun 28 04:40:49 PM PDT 24
Finished Jun 28 04:41:38 PM PDT 24
Peak memory 199912 kb
Host smart-aff1cfe4-3d71-4e5b-8d41-5fea4aae870d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387127608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2387127608
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.3049204394
Short name T49
Test name
Test status
Simulation time 79886837816 ps
CPU time 788.54 seconds
Started Jun 28 04:40:48 PM PDT 24
Finished Jun 28 04:53:58 PM PDT 24
Peak memory 216480 kb
Host smart-9ef7a6f7-b895-49f5-a045-60e21341c1dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049204394 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.3049204394
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1367359608
Short name T254
Test name
Test status
Simulation time 115374621925 ps
CPU time 61.73 seconds
Started Jun 28 04:40:47 PM PDT 24
Finished Jun 28 04:41:50 PM PDT 24
Peak memory 199720 kb
Host smart-1de35aeb-07da-4b30-9b2a-799a2fff3e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367359608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1367359608
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.2588837277
Short name T367
Test name
Test status
Simulation time 30838168701 ps
CPU time 25.46 seconds
Started Jun 28 04:40:47 PM PDT 24
Finished Jun 28 04:41:13 PM PDT 24
Peak memory 199928 kb
Host smart-ebaca481-318d-4dbb-8c0a-f978826eadfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588837277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.2588837277
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.1062560749
Short name T600
Test name
Test status
Simulation time 584057419710 ps
CPU time 531.54 seconds
Started Jun 28 04:40:50 PM PDT 24
Finished Jun 28 04:49:43 PM PDT 24
Peak memory 216444 kb
Host smart-61aa9a66-073d-4216-99e8-493638e33b18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062560749 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1062560749
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3883659629
Short name T325
Test name
Test status
Simulation time 40829896 ps
CPU time 0.54 seconds
Started Jun 28 04:36:59 PM PDT 24
Finished Jun 28 04:37:01 PM PDT 24
Peak memory 194884 kb
Host smart-15dd775f-8d59-4805-bf72-5d0c443e67c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883659629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3883659629
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.1128322874
Short name T929
Test name
Test status
Simulation time 203745284672 ps
CPU time 398.93 seconds
Started Jun 28 04:36:47 PM PDT 24
Finished Jun 28 04:43:28 PM PDT 24
Peak memory 199916 kb
Host smart-2209fbe3-3bbe-432e-9504-2a050bb0df3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128322874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1128322874
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.3639846198
Short name T155
Test name
Test status
Simulation time 109151053729 ps
CPU time 23.44 seconds
Started Jun 28 04:36:59 PM PDT 24
Finished Jun 28 04:37:23 PM PDT 24
Peak memory 199900 kb
Host smart-e5ccc7c1-d688-422e-b8e5-58b320a3b0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639846198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.3639846198
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.735309002
Short name T882
Test name
Test status
Simulation time 31468386602 ps
CPU time 47.88 seconds
Started Jun 28 04:37:03 PM PDT 24
Finished Jun 28 04:37:52 PM PDT 24
Peak memory 199740 kb
Host smart-7bf779cf-3876-4e31-adbd-28ddb59d8f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735309002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.735309002
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.2774757793
Short name T659
Test name
Test status
Simulation time 155027962464 ps
CPU time 101.81 seconds
Started Jun 28 04:37:01 PM PDT 24
Finished Jun 28 04:38:44 PM PDT 24
Peak memory 199816 kb
Host smart-d1d9c4d8-9684-47b7-9673-2c555f41984d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774757793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2774757793
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.1698050346
Short name T707
Test name
Test status
Simulation time 115286299578 ps
CPU time 198.66 seconds
Started Jun 28 04:37:02 PM PDT 24
Finished Jun 28 04:40:21 PM PDT 24
Peak memory 199820 kb
Host smart-5f4124a8-9127-45fc-b18b-4bb2f57e7366
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1698050346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1698050346
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.1139593888
Short name T930
Test name
Test status
Simulation time 2957364921 ps
CPU time 1.49 seconds
Started Jun 28 04:37:01 PM PDT 24
Finished Jun 28 04:37:04 PM PDT 24
Peak memory 196548 kb
Host smart-2abe9452-03aa-4a57-b4bb-1222df37e001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139593888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1139593888
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_perf.1985252591
Short name T574
Test name
Test status
Simulation time 15468336703 ps
CPU time 187.38 seconds
Started Jun 28 04:37:00 PM PDT 24
Finished Jun 28 04:40:08 PM PDT 24
Peak memory 199760 kb
Host smart-09ccdc4c-1fec-4f19-8117-dc897a3a813d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1985252591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1985252591
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.518604980
Short name T1025
Test name
Test status
Simulation time 1693270164 ps
CPU time 4.94 seconds
Started Jun 28 04:36:59 PM PDT 24
Finished Jun 28 04:37:05 PM PDT 24
Peak memory 197852 kb
Host smart-6750f221-294a-4082-9225-fa8f45b16a79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=518604980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.518604980
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.2050752277
Short name T833
Test name
Test status
Simulation time 83182124711 ps
CPU time 29.34 seconds
Started Jun 28 04:37:00 PM PDT 24
Finished Jun 28 04:37:30 PM PDT 24
Peak memory 199748 kb
Host smart-382c1a14-1e16-4160-8b46-834677e03147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050752277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2050752277
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.3801094204
Short name T642
Test name
Test status
Simulation time 5127891067 ps
CPU time 8.35 seconds
Started Jun 28 04:37:02 PM PDT 24
Finished Jun 28 04:37:11 PM PDT 24
Peak memory 196140 kb
Host smart-675ae02c-eb8b-4da6-b93f-4641aff820ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801094204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.3801094204
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.1200370779
Short name T262
Test name
Test status
Simulation time 453211846 ps
CPU time 2.29 seconds
Started Jun 28 04:36:48 PM PDT 24
Finished Jun 28 04:36:53 PM PDT 24
Peak memory 198236 kb
Host smart-9e5958d2-3b40-4783-ab41-c506780d3299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200370779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.1200370779
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.2400036733
Short name T747
Test name
Test status
Simulation time 36696099843 ps
CPU time 30.5 seconds
Started Jun 28 04:37:00 PM PDT 24
Finished Jun 28 04:37:31 PM PDT 24
Peak memory 200104 kb
Host smart-880d2771-9119-421e-8d95-adfc8be172b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400036733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2400036733
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.1193372031
Short name T99
Test name
Test status
Simulation time 85006225644 ps
CPU time 418.26 seconds
Started Jun 28 04:37:02 PM PDT 24
Finished Jun 28 04:44:01 PM PDT 24
Peak memory 212232 kb
Host smart-06d25bd4-d724-412a-862f-bcb79130aaac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193372031 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.1193372031
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.911688362
Short name T1088
Test name
Test status
Simulation time 6509315276 ps
CPU time 22.76 seconds
Started Jun 28 04:37:02 PM PDT 24
Finished Jun 28 04:37:25 PM PDT 24
Peak memory 199220 kb
Host smart-c8689716-f3fc-415d-a8ea-7cc2f444c0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911688362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.911688362
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.746405843
Short name T679
Test name
Test status
Simulation time 37830723849 ps
CPU time 68.12 seconds
Started Jun 28 04:36:49 PM PDT 24
Finished Jun 28 04:38:00 PM PDT 24
Peak memory 199764 kb
Host smart-71a2e489-d073-4713-bc07-b4c9f97c8245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746405843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.746405843
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.729242181
Short name T823
Test name
Test status
Simulation time 45159232213 ps
CPU time 15.97 seconds
Started Jun 28 04:40:50 PM PDT 24
Finished Jun 28 04:41:07 PM PDT 24
Peak memory 199784 kb
Host smart-9f2a1149-87e3-49c2-849a-01b4e6a410c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729242181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.729242181
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.1817093226
Short name T701
Test name
Test status
Simulation time 136384878433 ps
CPU time 12.91 seconds
Started Jun 28 04:40:48 PM PDT 24
Finished Jun 28 04:41:02 PM PDT 24
Peak memory 199828 kb
Host smart-af74c522-0a8b-4af2-9bd8-5b3d18189e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817093226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1817093226
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2522757318
Short name T302
Test name
Test status
Simulation time 104492864189 ps
CPU time 2022.32 seconds
Started Jun 28 04:40:51 PM PDT 24
Finished Jun 28 05:14:35 PM PDT 24
Peak memory 224416 kb
Host smart-0ee4fc25-813d-49e0-a2f7-2f7754b09d63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522757318 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2522757318
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.3227731304
Short name T246
Test name
Test status
Simulation time 26979168656 ps
CPU time 45.78 seconds
Started Jun 28 04:40:51 PM PDT 24
Finished Jun 28 04:41:38 PM PDT 24
Peak memory 199852 kb
Host smart-09c36083-6781-4c36-9e7e-328ee40d244f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227731304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3227731304
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1985195027
Short name T304
Test name
Test status
Simulation time 90453473152 ps
CPU time 3327 seconds
Started Jun 28 04:40:51 PM PDT 24
Finished Jun 28 05:36:19 PM PDT 24
Peak memory 224500 kb
Host smart-8548ec54-aa10-4584-a9a2-73f1aa9f28df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985195027 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1985195027
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.4159575261
Short name T618
Test name
Test status
Simulation time 82251319461 ps
CPU time 32.15 seconds
Started Jun 28 04:40:51 PM PDT 24
Finished Jun 28 04:41:24 PM PDT 24
Peak memory 199820 kb
Host smart-1f877465-9585-4e6b-b332-903716f1f0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159575261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.4159575261
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.1023424355
Short name T97
Test name
Test status
Simulation time 70474038693 ps
CPU time 592.19 seconds
Started Jun 28 04:40:48 PM PDT 24
Finished Jun 28 04:50:42 PM PDT 24
Peak memory 216100 kb
Host smart-1d6ce493-1589-4726-8db6-10018adce1d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023424355 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.1023424355
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.2225042457
Short name T943
Test name
Test status
Simulation time 275401926707 ps
CPU time 135.09 seconds
Started Jun 28 04:40:48 PM PDT 24
Finished Jun 28 04:43:04 PM PDT 24
Peak memory 199916 kb
Host smart-16fc9c7e-4f89-4002-ac5c-f0f018548845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225042457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2225042457
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.3973248376
Short name T927
Test name
Test status
Simulation time 776115723738 ps
CPU time 1012.56 seconds
Started Jun 28 04:40:50 PM PDT 24
Finished Jun 28 04:57:44 PM PDT 24
Peak memory 224668 kb
Host smart-dfb7d5bc-1a79-432e-af31-0439b7a6baa7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973248376 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.3973248376
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.2811972801
Short name T436
Test name
Test status
Simulation time 16827348345 ps
CPU time 25.11 seconds
Started Jun 28 04:40:51 PM PDT 24
Finished Jun 28 04:41:17 PM PDT 24
Peak memory 199848 kb
Host smart-386601c3-1f31-44eb-ab23-7e6ed087a86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811972801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2811972801
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.3343199647
Short name T539
Test name
Test status
Simulation time 266978769875 ps
CPU time 1024.06 seconds
Started Jun 28 04:40:49 PM PDT 24
Finished Jun 28 04:57:55 PM PDT 24
Peak memory 216408 kb
Host smart-8d0645eb-d8df-4b4b-af04-aab16819f07c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343199647 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.3343199647
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.2356228229
Short name T238
Test name
Test status
Simulation time 3490589519 ps
CPU time 7.2 seconds
Started Jun 28 04:40:50 PM PDT 24
Finished Jun 28 04:40:58 PM PDT 24
Peak memory 199900 kb
Host smart-76d4305a-f89e-43d9-a34b-3b67cf59e13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356228229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.2356228229
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.1847828310
Short name T27
Test name
Test status
Simulation time 58757234243 ps
CPU time 716.79 seconds
Started Jun 28 04:40:49 PM PDT 24
Finished Jun 28 04:52:48 PM PDT 24
Peak memory 225472 kb
Host smart-26521962-94fc-4802-897e-f76d80ff8b95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847828310 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.1847828310
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.2413876715
Short name T815
Test name
Test status
Simulation time 18657095609 ps
CPU time 14.91 seconds
Started Jun 28 04:40:54 PM PDT 24
Finished Jun 28 04:41:09 PM PDT 24
Peak memory 199564 kb
Host smart-5fcce93d-d759-4eda-803f-9fe8a051cf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413876715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.2413876715
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.910127730
Short name T176
Test name
Test status
Simulation time 79087423303 ps
CPU time 121.39 seconds
Started Jun 28 04:40:54 PM PDT 24
Finished Jun 28 04:42:56 PM PDT 24
Peak memory 199780 kb
Host smart-5024bb21-ec68-48a2-af3c-880cd130a315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910127730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.910127730
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.3439720872
Short name T47
Test name
Test status
Simulation time 48025445866 ps
CPU time 48.61 seconds
Started Jun 28 04:40:54 PM PDT 24
Finished Jun 28 04:41:43 PM PDT 24
Peak memory 199812 kb
Host smart-f2fc742d-f7a2-47d9-b17a-691f746c9397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439720872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3439720872
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.3181996214
Short name T646
Test name
Test status
Simulation time 16935457 ps
CPU time 0.55 seconds
Started Jun 28 04:36:59 PM PDT 24
Finished Jun 28 04:37:00 PM PDT 24
Peak memory 195152 kb
Host smart-d2f8402d-f01b-4965-a3b8-0f0e059abcf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181996214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.3181996214
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.1499607494
Short name T538
Test name
Test status
Simulation time 46882679676 ps
CPU time 36.98 seconds
Started Jun 28 04:37:00 PM PDT 24
Finished Jun 28 04:37:38 PM PDT 24
Peak memory 199780 kb
Host smart-4cd4694e-0b28-4bd5-8f03-89b40ed1f695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499607494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.1499607494
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.1322295732
Short name T527
Test name
Test status
Simulation time 82711718979 ps
CPU time 108.55 seconds
Started Jun 28 04:37:00 PM PDT 24
Finished Jun 28 04:38:49 PM PDT 24
Peak memory 199912 kb
Host smart-4f144046-5390-435b-8406-14e15af7fcb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322295732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1322295732
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.2842229449
Short name T468
Test name
Test status
Simulation time 17117628721 ps
CPU time 24.14 seconds
Started Jun 28 04:37:04 PM PDT 24
Finished Jun 28 04:37:29 PM PDT 24
Peak memory 199852 kb
Host smart-aaa20ff1-4536-4b62-ac64-fc0465775b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842229449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2842229449
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.2000669092
Short name T528
Test name
Test status
Simulation time 14104570245 ps
CPU time 8.01 seconds
Started Jun 28 04:37:00 PM PDT 24
Finished Jun 28 04:37:09 PM PDT 24
Peak memory 199400 kb
Host smart-ddaebdae-b2b4-4910-9619-5a4742b6a26c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000669092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.2000669092
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_loopback.3797754286
Short name T334
Test name
Test status
Simulation time 1104240525 ps
CPU time 3.26 seconds
Started Jun 28 04:37:01 PM PDT 24
Finished Jun 28 04:37:05 PM PDT 24
Peak memory 198764 kb
Host smart-ac14e0c8-9011-4570-ae67-93499627417b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797754286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.3797754286
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_perf.3472529769
Short name T682
Test name
Test status
Simulation time 10307665509 ps
CPU time 144.9 seconds
Started Jun 28 04:37:03 PM PDT 24
Finished Jun 28 04:39:29 PM PDT 24
Peak memory 199752 kb
Host smart-ba2f5cc8-4953-46f4-9f0e-ab49b17c21ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3472529769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3472529769
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.1962235386
Short name T601
Test name
Test status
Simulation time 7156398318 ps
CPU time 65.33 seconds
Started Jun 28 04:37:01 PM PDT 24
Finished Jun 28 04:38:07 PM PDT 24
Peak memory 198680 kb
Host smart-90abefc1-d5c7-48fc-ae31-b17f06f4c213
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1962235386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1962235386
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.3634660898
Short name T794
Test name
Test status
Simulation time 18882930562 ps
CPU time 33 seconds
Started Jun 28 04:37:00 PM PDT 24
Finished Jun 28 04:37:34 PM PDT 24
Peak memory 199760 kb
Host smart-81fe9e8b-e0a2-47fc-a584-1a278fccec64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634660898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3634660898
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.2025358338
Short name T339
Test name
Test status
Simulation time 3103510203 ps
CPU time 3.23 seconds
Started Jun 28 04:37:02 PM PDT 24
Finished Jun 28 04:37:06 PM PDT 24
Peak memory 195896 kb
Host smart-e94a640e-736e-429c-b0d3-faae1622459d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025358338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.2025358338
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.3638437377
Short name T809
Test name
Test status
Simulation time 507754376 ps
CPU time 3.22 seconds
Started Jun 28 04:36:59 PM PDT 24
Finished Jun 28 04:37:03 PM PDT 24
Peak memory 199804 kb
Host smart-7e8f4b90-51bc-41f8-bdd8-2185262d4d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638437377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3638437377
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.2141716011
Short name T312
Test name
Test status
Simulation time 47269391276 ps
CPU time 104.29 seconds
Started Jun 28 04:37:01 PM PDT 24
Finished Jun 28 04:38:46 PM PDT 24
Peak memory 199828 kb
Host smart-24f14786-ead0-48de-b167-96f54aad0df3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141716011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.2141716011
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.1652154382
Short name T1091
Test name
Test status
Simulation time 11852609938 ps
CPU time 144.11 seconds
Started Jun 28 04:37:02 PM PDT 24
Finished Jun 28 04:39:27 PM PDT 24
Peak memory 216280 kb
Host smart-68f70eb7-91f1-4948-b412-f965585aa599
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652154382 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.1652154382
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.4279127371
Short name T675
Test name
Test status
Simulation time 6568804306 ps
CPU time 20.6 seconds
Started Jun 28 04:37:00 PM PDT 24
Finished Jun 28 04:37:22 PM PDT 24
Peak memory 199624 kb
Host smart-8a11ce05-4f56-4471-b596-5d7b18c545af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279127371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.4279127371
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.3292518505
Short name T48
Test name
Test status
Simulation time 117873462084 ps
CPU time 78.68 seconds
Started Jun 28 04:37:00 PM PDT 24
Finished Jun 28 04:38:20 PM PDT 24
Peak memory 199840 kb
Host smart-d7c555c9-dbd6-4c51-ae11-77669a88ef2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292518505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.3292518505
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.1269752292
Short name T221
Test name
Test status
Simulation time 108520540656 ps
CPU time 87.93 seconds
Started Jun 28 04:40:54 PM PDT 24
Finished Jun 28 04:42:23 PM PDT 24
Peak memory 199684 kb
Host smart-6479ae1c-d182-4356-b081-c5dea6cf1df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269752292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1269752292
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.379554
Short name T1054
Test name
Test status
Simulation time 34665721341 ps
CPU time 28.47 seconds
Started Jun 28 04:40:49 PM PDT 24
Finished Jun 28 04:41:19 PM PDT 24
Peak memory 199856 kb
Host smart-49ff7360-13ec-46e6-8aa6-48004f937740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.379554
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2535846030
Short name T919
Test name
Test status
Simulation time 53570753095 ps
CPU time 619.71 seconds
Started Jun 28 04:40:54 PM PDT 24
Finished Jun 28 04:51:14 PM PDT 24
Peak memory 214236 kb
Host smart-4ea7f1bc-130d-46cc-8981-79da8c6d919e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535846030 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2535846030
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.2171524174
Short name T554
Test name
Test status
Simulation time 68057549138 ps
CPU time 111.89 seconds
Started Jun 28 04:40:54 PM PDT 24
Finished Jun 28 04:42:47 PM PDT 24
Peak memory 199684 kb
Host smart-10d843bf-87c7-411e-9911-0f3a07d9ba3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171524174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2171524174
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.962762500
Short name T658
Test name
Test status
Simulation time 12578460340 ps
CPU time 24.78 seconds
Started Jun 28 04:40:53 PM PDT 24
Finished Jun 28 04:41:19 PM PDT 24
Peak memory 199772 kb
Host smart-a10825e1-eb97-43a9-841d-6633e8b73bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962762500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.962762500
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.466775842
Short name T830
Test name
Test status
Simulation time 8159824062 ps
CPU time 12 seconds
Started Jun 28 04:40:53 PM PDT 24
Finished Jun 28 04:41:07 PM PDT 24
Peak memory 199852 kb
Host smart-7888e7e1-d5e9-4d64-be83-409bc5375178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466775842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.466775842
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3107227261
Short name T457
Test name
Test status
Simulation time 88379087112 ps
CPU time 665.62 seconds
Started Jun 28 04:40:48 PM PDT 24
Finished Jun 28 04:51:55 PM PDT 24
Peak memory 216224 kb
Host smart-d76f45c9-fc0f-4b1a-93b7-1f2c8147ea4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107227261 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3107227261
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.4183875067
Short name T42
Test name
Test status
Simulation time 12899311326 ps
CPU time 20.31 seconds
Started Jun 28 04:40:50 PM PDT 24
Finished Jun 28 04:41:12 PM PDT 24
Peak memory 199700 kb
Host smart-37f468e2-44a1-4b90-97db-369bad3a6877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183875067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.4183875067
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.1666988263
Short name T214
Test name
Test status
Simulation time 41992979437 ps
CPU time 64.31 seconds
Started Jun 28 04:40:49 PM PDT 24
Finished Jun 28 04:41:55 PM PDT 24
Peak memory 199852 kb
Host smart-3c424853-6b80-445a-bdc2-884d872e617a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666988263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1666988263
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.2616233071
Short name T653
Test name
Test status
Simulation time 224798636093 ps
CPU time 1890.36 seconds
Started Jun 28 04:40:53 PM PDT 24
Finished Jun 28 05:12:25 PM PDT 24
Peak memory 216424 kb
Host smart-607b914a-6554-4b47-9b71-4e4ccacd8382
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616233071 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.2616233071
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.894963666
Short name T990
Test name
Test status
Simulation time 62480516252 ps
CPU time 33.78 seconds
Started Jun 28 04:40:53 PM PDT 24
Finished Jun 28 04:41:27 PM PDT 24
Peak memory 199916 kb
Host smart-7c577d7e-03bc-453b-abbc-92822030bfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894963666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.894963666
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.1352552446
Short name T128
Test name
Test status
Simulation time 46366100783 ps
CPU time 31.14 seconds
Started Jun 28 04:41:02 PM PDT 24
Finished Jun 28 04:41:34 PM PDT 24
Peak memory 199808 kb
Host smart-cb4e7c31-a20a-4ecb-a6ec-377a77d23ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352552446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1352552446
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.2128619965
Short name T54
Test name
Test status
Simulation time 241972051036 ps
CPU time 1011.98 seconds
Started Jun 28 04:40:59 PM PDT 24
Finished Jun 28 04:57:53 PM PDT 24
Peak memory 224588 kb
Host smart-7982e794-05e7-4449-a1a5-9fce005d2ad4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128619965 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.2128619965
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.3153005014
Short name T693
Test name
Test status
Simulation time 34323748292 ps
CPU time 12.1 seconds
Started Jun 28 04:41:03 PM PDT 24
Finished Jun 28 04:41:16 PM PDT 24
Peak memory 199828 kb
Host smart-d6b9a80a-af44-42be-96e3-629069f0a791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153005014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.3153005014
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.2578229186
Short name T774
Test name
Test status
Simulation time 69538485813 ps
CPU time 370.51 seconds
Started Jun 28 04:40:57 PM PDT 24
Finished Jun 28 04:47:09 PM PDT 24
Peak memory 216380 kb
Host smart-97c93ac4-f9c6-4005-98e6-45872993a025
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578229186 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.2578229186
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.444370030
Short name T777
Test name
Test status
Simulation time 33411880 ps
CPU time 0.56 seconds
Started Jun 28 04:37:11 PM PDT 24
Finished Jun 28 04:37:13 PM PDT 24
Peak memory 194716 kb
Host smart-6b2ff21c-4698-45a8-8c1a-182bd26366bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444370030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.444370030
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.840224908
Short name T996
Test name
Test status
Simulation time 115084509555 ps
CPU time 49.84 seconds
Started Jun 28 04:37:03 PM PDT 24
Finished Jun 28 04:37:54 PM PDT 24
Peak memory 199840 kb
Host smart-945ec534-5f80-4b48-b9a8-151868a8cc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840224908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.840224908
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.2850475306
Short name T725
Test name
Test status
Simulation time 107162303452 ps
CPU time 59.45 seconds
Started Jun 28 04:37:02 PM PDT 24
Finished Jun 28 04:38:02 PM PDT 24
Peak memory 199880 kb
Host smart-f2e253c2-ac1c-486c-9cbb-eab42b6b8898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850475306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2850475306
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3542141496
Short name T517
Test name
Test status
Simulation time 5467607824 ps
CPU time 9.59 seconds
Started Jun 28 04:37:01 PM PDT 24
Finished Jun 28 04:37:12 PM PDT 24
Peak memory 199536 kb
Host smart-294b5efa-6d58-459c-9075-40a846f666c5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542141496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3542141496
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.3561332939
Short name T240
Test name
Test status
Simulation time 167991366358 ps
CPU time 1219.09 seconds
Started Jun 28 04:37:13 PM PDT 24
Finished Jun 28 04:57:33 PM PDT 24
Peak memory 199892 kb
Host smart-00f38a5c-51c5-4715-944c-adee623d915a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3561332939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3561332939
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1588183990
Short name T406
Test name
Test status
Simulation time 8191236124 ps
CPU time 8.34 seconds
Started Jun 28 04:37:14 PM PDT 24
Finished Jun 28 04:37:24 PM PDT 24
Peak memory 199332 kb
Host smart-7ef8ad28-d17a-48d1-b2f0-69135a59bdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588183990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1588183990
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.2642287149
Short name T423
Test name
Test status
Simulation time 13122489887 ps
CPU time 5.48 seconds
Started Jun 28 04:37:12 PM PDT 24
Finished Jun 28 04:37:19 PM PDT 24
Peak memory 197240 kb
Host smart-111b7cd7-252a-42ca-ae42-d07c3c93fff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642287149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2642287149
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.2586375066
Short name T933
Test name
Test status
Simulation time 10448555097 ps
CPU time 154.31 seconds
Started Jun 28 04:37:12 PM PDT 24
Finished Jun 28 04:39:47 PM PDT 24
Peak memory 199752 kb
Host smart-9cd7e3de-3026-446e-8b3e-4f2aac6e11b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2586375066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2586375066
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.1085703492
Short name T760
Test name
Test status
Simulation time 6549968639 ps
CPU time 61.91 seconds
Started Jun 28 04:37:00 PM PDT 24
Finished Jun 28 04:38:03 PM PDT 24
Peak memory 198084 kb
Host smart-cc6e2fd4-5377-4a9b-803b-c869b8b5b4c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1085703492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1085703492
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.2845286344
Short name T1057
Test name
Test status
Simulation time 174266468958 ps
CPU time 15.92 seconds
Started Jun 28 04:37:14 PM PDT 24
Finished Jun 28 04:37:31 PM PDT 24
Peak memory 199904 kb
Host smart-282ef0c3-4011-4973-b543-0ed705932865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845286344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2845286344
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.1562372020
Short name T739
Test name
Test status
Simulation time 4169282665 ps
CPU time 5.52 seconds
Started Jun 28 04:37:12 PM PDT 24
Finished Jun 28 04:37:19 PM PDT 24
Peak memory 196368 kb
Host smart-22e37a61-2610-4b65-9f11-1aa710e5d8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562372020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1562372020
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.4149651934
Short name T942
Test name
Test status
Simulation time 724706244 ps
CPU time 1.72 seconds
Started Jun 28 04:36:59 PM PDT 24
Finished Jun 28 04:37:01 PM PDT 24
Peak memory 198708 kb
Host smart-1c754d47-4548-4ff3-a362-042702e917e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149651934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.4149651934
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.2266966927
Short name T19
Test name
Test status
Simulation time 211301685066 ps
CPU time 206.37 seconds
Started Jun 28 04:37:12 PM PDT 24
Finished Jun 28 04:40:39 PM PDT 24
Peak memory 199856 kb
Host smart-1993800c-c53d-4f78-9845-3d7c56e52a87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266966927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2266966927
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.3899670542
Short name T1082
Test name
Test status
Simulation time 236467101922 ps
CPU time 1009.12 seconds
Started Jun 28 04:37:11 PM PDT 24
Finished Jun 28 04:54:02 PM PDT 24
Peak memory 216328 kb
Host smart-f2a6c2a7-ab45-49a7-bfe0-86a3b5c8cec0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899670542 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.3899670542
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.4066496539
Short name T691
Test name
Test status
Simulation time 5672181039 ps
CPU time 1.89 seconds
Started Jun 28 04:37:11 PM PDT 24
Finished Jun 28 04:37:14 PM PDT 24
Peak memory 199596 kb
Host smart-13e81ca5-1e25-415c-8402-8faca4e9dcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066496539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.4066496539
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.253830440
Short name T984
Test name
Test status
Simulation time 186281401097 ps
CPU time 25.2 seconds
Started Jun 28 04:37:01 PM PDT 24
Finished Jun 28 04:37:27 PM PDT 24
Peak memory 199760 kb
Host smart-a713ef30-ba42-4dfb-8852-613509ffc05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253830440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.253830440
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.1087951066
Short name T832
Test name
Test status
Simulation time 91082642429 ps
CPU time 38.43 seconds
Started Jun 28 04:41:00 PM PDT 24
Finished Jun 28 04:41:39 PM PDT 24
Peak memory 199732 kb
Host smart-a7c1cee6-388b-4dc7-8755-383f45b25456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087951066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.1087951066
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.3933913835
Short name T53
Test name
Test status
Simulation time 281209203116 ps
CPU time 483.07 seconds
Started Jun 28 04:41:03 PM PDT 24
Finished Jun 28 04:49:07 PM PDT 24
Peak memory 216420 kb
Host smart-7f8f5a7a-e552-43ee-acaa-524f8f4dc56e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933913835 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.3933913835
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.4241618089
Short name T513
Test name
Test status
Simulation time 17583567918 ps
CPU time 28.85 seconds
Started Jun 28 04:41:02 PM PDT 24
Finished Jun 28 04:41:32 PM PDT 24
Peak memory 199808 kb
Host smart-a2ca74ff-bb98-4846-9cb6-36ee432a25c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241618089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.4241618089
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.1499288493
Short name T1011
Test name
Test status
Simulation time 87487780533 ps
CPU time 159.74 seconds
Started Jun 28 04:40:57 PM PDT 24
Finished Jun 28 04:43:38 PM PDT 24
Peak memory 216464 kb
Host smart-5858c903-2dfe-4bd4-b1d8-632a568292b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499288493 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.1499288493
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.2909796839
Short name T840
Test name
Test status
Simulation time 243423699197 ps
CPU time 96.78 seconds
Started Jun 28 04:40:58 PM PDT 24
Finished Jun 28 04:42:36 PM PDT 24
Peak memory 199828 kb
Host smart-7ac137bd-9c06-4401-9a01-79684e326dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909796839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.2909796839
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.1912616032
Short name T1080
Test name
Test status
Simulation time 21791535791 ps
CPU time 63.47 seconds
Started Jun 28 04:40:59 PM PDT 24
Finished Jun 28 04:42:04 PM PDT 24
Peak memory 216356 kb
Host smart-cce13846-5709-45a3-8850-1ea1dae006a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912616032 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.1912616032
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.51109058
Short name T908
Test name
Test status
Simulation time 64082430660 ps
CPU time 12.77 seconds
Started Jun 28 04:41:00 PM PDT 24
Finished Jun 28 04:41:14 PM PDT 24
Peak memory 199836 kb
Host smart-5fd484ec-1867-48e9-800a-8044b64fff20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51109058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.51109058
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.271710560
Short name T852
Test name
Test status
Simulation time 67358655086 ps
CPU time 415.24 seconds
Started Jun 28 04:41:01 PM PDT 24
Finished Jun 28 04:47:58 PM PDT 24
Peak memory 216328 kb
Host smart-5c643d44-ec29-4704-881a-389c47db5a46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271710560 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.271710560
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.3509581366
Short name T144
Test name
Test status
Simulation time 49929358807 ps
CPU time 37.64 seconds
Started Jun 28 04:40:59 PM PDT 24
Finished Jun 28 04:41:38 PM PDT 24
Peak memory 199744 kb
Host smart-6f2d6e48-da9f-42a1-b024-c45ee27ff1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509581366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3509581366
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.1806676437
Short name T156
Test name
Test status
Simulation time 193901918514 ps
CPU time 106.12 seconds
Started Jun 28 04:41:03 PM PDT 24
Finished Jun 28 04:42:50 PM PDT 24
Peak memory 199920 kb
Host smart-6d64e2c9-cfd9-4f05-b5d6-104ce6ba547e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806676437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1806676437
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.4031640774
Short name T989
Test name
Test status
Simulation time 26475546060 ps
CPU time 54.8 seconds
Started Jun 28 04:41:02 PM PDT 24
Finished Jun 28 04:41:58 PM PDT 24
Peak memory 199912 kb
Host smart-32c29726-e79d-4a91-b73b-0cc7ac62ebb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031640774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.4031640774
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.3711350390
Short name T983
Test name
Test status
Simulation time 147513694377 ps
CPU time 507.41 seconds
Started Jun 28 04:41:03 PM PDT 24
Finished Jun 28 04:49:31 PM PDT 24
Peak memory 216340 kb
Host smart-03cc89d8-04a5-41cc-b717-6fed695cd2cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711350390 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.3711350390
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2630526390
Short name T789
Test name
Test status
Simulation time 71537730683 ps
CPU time 34.04 seconds
Started Jun 28 04:40:57 PM PDT 24
Finished Jun 28 04:41:32 PM PDT 24
Peak memory 199900 kb
Host smart-257fdc9f-4ce4-4c95-9916-9134f2e66c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630526390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2630526390
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.2273626411
Short name T139
Test name
Test status
Simulation time 17974821517 ps
CPU time 14.88 seconds
Started Jun 28 04:41:02 PM PDT 24
Finished Jun 28 04:41:18 PM PDT 24
Peak memory 199920 kb
Host smart-aa63d343-dc40-46d2-b7eb-f2907021bcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273626411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.2273626411
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.1829825817
Short name T30
Test name
Test status
Simulation time 105885540312 ps
CPU time 935.63 seconds
Started Jun 28 04:40:58 PM PDT 24
Finished Jun 28 04:56:34 PM PDT 24
Peak memory 216500 kb
Host smart-81c88241-31dc-48a0-9453-a784bc9d8597
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829825817 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.1829825817
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.723078267
Short name T844
Test name
Test status
Simulation time 32491870 ps
CPU time 0.55 seconds
Started Jun 28 04:37:14 PM PDT 24
Finished Jun 28 04:37:15 PM PDT 24
Peak memory 195296 kb
Host smart-dc3ce27a-cbef-4c1c-aa65-1963ffc3c76f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723078267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.723078267
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.3536516711
Short name T952
Test name
Test status
Simulation time 26732979079 ps
CPU time 45.64 seconds
Started Jun 28 04:37:15 PM PDT 24
Finished Jun 28 04:38:01 PM PDT 24
Peak memory 199720 kb
Host smart-9fdfbfa6-4e1b-4aac-aa5f-313e1ecb8826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536516711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3536516711
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.881518415
Short name T435
Test name
Test status
Simulation time 44383275132 ps
CPU time 71.67 seconds
Started Jun 28 04:37:10 PM PDT 24
Finished Jun 28 04:38:22 PM PDT 24
Peak memory 199892 kb
Host smart-584c50b1-0102-4ca5-a03e-098c86c0a964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881518415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.881518415
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.3016918477
Short name T702
Test name
Test status
Simulation time 103924524865 ps
CPU time 44.07 seconds
Started Jun 28 04:37:12 PM PDT 24
Finished Jun 28 04:37:57 PM PDT 24
Peak memory 199904 kb
Host smart-abba2e9b-9a27-4830-a003-4f02391c4ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016918477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.3016918477
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.1985675154
Short name T780
Test name
Test status
Simulation time 48144789382 ps
CPU time 23.55 seconds
Started Jun 28 04:37:10 PM PDT 24
Finished Jun 28 04:37:35 PM PDT 24
Peak memory 199816 kb
Host smart-5981af2c-dc68-4624-927b-e4b46bd4ea4a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985675154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.1985675154
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.1343663260
Short name T373
Test name
Test status
Simulation time 75183312926 ps
CPU time 601.42 seconds
Started Jun 28 04:37:12 PM PDT 24
Finished Jun 28 04:47:15 PM PDT 24
Peak memory 199808 kb
Host smart-057962a4-acff-4701-8028-eb5164dffb0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1343663260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1343663260
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.2815065469
Short name T753
Test name
Test status
Simulation time 10209714642 ps
CPU time 5.47 seconds
Started Jun 28 04:37:14 PM PDT 24
Finished Jun 28 04:37:21 PM PDT 24
Peak memory 199680 kb
Host smart-9476a6e6-5aa1-48f7-a492-4d535e1f0b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815065469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2815065469
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_perf.805133840
Short name T632
Test name
Test status
Simulation time 20854767227 ps
CPU time 269.43 seconds
Started Jun 28 04:37:13 PM PDT 24
Finished Jun 28 04:41:43 PM PDT 24
Peak memory 199788 kb
Host smart-b378599c-6247-4e6f-a418-6dbb6f0546d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=805133840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.805133840
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.3626314313
Short name T3
Test name
Test status
Simulation time 5448052906 ps
CPU time 21.75 seconds
Started Jun 28 04:37:12 PM PDT 24
Finished Jun 28 04:37:34 PM PDT 24
Peak memory 199816 kb
Host smart-0a77ab41-3bff-492d-9d17-53423dba487a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3626314313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.3626314313
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.2261104523
Short name T152
Test name
Test status
Simulation time 70773777333 ps
CPU time 28.84 seconds
Started Jun 28 04:37:12 PM PDT 24
Finished Jun 28 04:37:42 PM PDT 24
Peak memory 199852 kb
Host smart-15ef9867-fe43-44fe-a830-b985200dad46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261104523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2261104523
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1063259430
Short name T1045
Test name
Test status
Simulation time 6447010973 ps
CPU time 1.96 seconds
Started Jun 28 04:37:16 PM PDT 24
Finished Jun 28 04:37:18 PM PDT 24
Peak memory 196000 kb
Host smart-d78b14a9-ae07-4426-b339-8f44db9f53d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063259430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1063259430
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.686588488
Short name T685
Test name
Test status
Simulation time 624101448 ps
CPU time 2.43 seconds
Started Jun 28 04:37:14 PM PDT 24
Finished Jun 28 04:37:18 PM PDT 24
Peak memory 198136 kb
Host smart-794e7a70-ae6e-4c3f-b95c-61ba3b82636c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686588488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.686588488
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.2602531268
Short name T542
Test name
Test status
Simulation time 2339105628 ps
CPU time 2.18 seconds
Started Jun 28 04:37:11 PM PDT 24
Finished Jun 28 04:37:14 PM PDT 24
Peak memory 198288 kb
Host smart-25429697-54f5-4b1e-957c-fefeef6e5583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602531268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2602531268
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3167410376
Short name T318
Test name
Test status
Simulation time 44858000270 ps
CPU time 72.45 seconds
Started Jun 28 04:37:11 PM PDT 24
Finished Jun 28 04:38:24 PM PDT 24
Peak memory 199840 kb
Host smart-74b3d21c-a0b9-4525-b12e-9eccb4811329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167410376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3167410376
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.1482676784
Short name T1028
Test name
Test status
Simulation time 95095303073 ps
CPU time 146.74 seconds
Started Jun 28 04:41:01 PM PDT 24
Finished Jun 28 04:43:29 PM PDT 24
Peak memory 199808 kb
Host smart-c9dc60cd-f596-4f0d-a5c4-deeb20ccc8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482676784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1482676784
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.239430614
Short name T1006
Test name
Test status
Simulation time 206706837387 ps
CPU time 664.39 seconds
Started Jun 28 04:41:00 PM PDT 24
Finished Jun 28 04:52:06 PM PDT 24
Peak memory 225664 kb
Host smart-77c29e61-0ad6-4abc-b836-25c173767994
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239430614 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.239430614
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.4252783801
Short name T847
Test name
Test status
Simulation time 37209978695 ps
CPU time 14.13 seconds
Started Jun 28 04:41:03 PM PDT 24
Finished Jun 28 04:41:18 PM PDT 24
Peak memory 198772 kb
Host smart-531c413e-1f71-4339-a341-100455ee66a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252783801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.4252783801
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.622056442
Short name T168
Test name
Test status
Simulation time 17401256662 ps
CPU time 31.54 seconds
Started Jun 28 04:40:58 PM PDT 24
Finished Jun 28 04:41:30 PM PDT 24
Peak memory 199912 kb
Host smart-a79a704b-f599-4101-8976-7ddb82543d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622056442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.622056442
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.2722245641
Short name T603
Test name
Test status
Simulation time 47202535906 ps
CPU time 269.28 seconds
Started Jun 28 04:41:00 PM PDT 24
Finished Jun 28 04:45:30 PM PDT 24
Peak memory 210968 kb
Host smart-ba93770e-7b59-40a0-a01a-4148975e9caa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722245641 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.2722245641
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3980876577
Short name T490
Test name
Test status
Simulation time 41276479499 ps
CPU time 30.28 seconds
Started Jun 28 04:41:00 PM PDT 24
Finished Jun 28 04:41:31 PM PDT 24
Peak memory 199720 kb
Host smart-78282474-f571-41b7-9209-8134435ec5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980876577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3980876577
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.2517060303
Short name T476
Test name
Test status
Simulation time 29065980444 ps
CPU time 25.1 seconds
Started Jun 28 04:41:03 PM PDT 24
Finished Jun 28 04:41:29 PM PDT 24
Peak memory 199912 kb
Host smart-ed4b95d3-3829-4fe7-993a-b714213be472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517060303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2517060303
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.1235778140
Short name T1043
Test name
Test status
Simulation time 54999997477 ps
CPU time 581.1 seconds
Started Jun 28 04:40:59 PM PDT 24
Finished Jun 28 04:50:41 PM PDT 24
Peak memory 216336 kb
Host smart-a05d1eda-9ee1-4a91-b9e5-b4556afb0290
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235778140 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.1235778140
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.71799814
Short name T988
Test name
Test status
Simulation time 48821322242 ps
CPU time 107.96 seconds
Started Jun 28 04:41:01 PM PDT 24
Finished Jun 28 04:42:51 PM PDT 24
Peak memory 199752 kb
Host smart-495124ec-f2a6-4beb-a2dd-9af5b2313476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71799814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.71799814
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.2804075412
Short name T415
Test name
Test status
Simulation time 47426597858 ps
CPU time 537.49 seconds
Started Jun 28 04:41:03 PM PDT 24
Finished Jun 28 04:50:01 PM PDT 24
Peak memory 213224 kb
Host smart-ca0cadbb-9165-4768-bf39-6ec23517feec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804075412 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.2804075412
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.2898876434
Short name T220
Test name
Test status
Simulation time 286539681069 ps
CPU time 74.44 seconds
Started Jun 28 04:41:01 PM PDT 24
Finished Jun 28 04:42:17 PM PDT 24
Peak memory 199776 kb
Host smart-3e632aae-000d-4b4e-afc4-7118a8024045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898876434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.2898876434
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.974879914
Short name T635
Test name
Test status
Simulation time 49778193746 ps
CPU time 682.91 seconds
Started Jun 28 04:40:59 PM PDT 24
Finished Jun 28 04:52:23 PM PDT 24
Peak memory 216244 kb
Host smart-1fe7fc1f-d8cc-4aca-9e0f-e7ab6ef6d438
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974879914 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.974879914
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2235940904
Short name T668
Test name
Test status
Simulation time 21160868318 ps
CPU time 33.74 seconds
Started Jun 28 04:40:58 PM PDT 24
Finished Jun 28 04:41:33 PM PDT 24
Peak memory 199912 kb
Host smart-3dc22745-b108-41e5-9909-e8fadd77633e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235940904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2235940904
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.3376976158
Short name T98
Test name
Test status
Simulation time 25769400936 ps
CPU time 240.38 seconds
Started Jun 28 04:41:02 PM PDT 24
Finished Jun 28 04:45:03 PM PDT 24
Peak memory 216320 kb
Host smart-2d08c945-512a-4d33-845f-92cf00d6fd92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376976158 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.3376976158
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.4113603195
Short name T171
Test name
Test status
Simulation time 56634272590 ps
CPU time 28.76 seconds
Started Jun 28 04:41:00 PM PDT 24
Finished Jun 28 04:41:29 PM PDT 24
Peak memory 199916 kb
Host smart-9a44dd8b-0feb-422a-97dc-55650d4fe771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113603195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.4113603195
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.4011204815
Short name T553
Test name
Test status
Simulation time 105000642674 ps
CPU time 370.69 seconds
Started Jun 28 04:41:10 PM PDT 24
Finished Jun 28 04:47:22 PM PDT 24
Peak memory 209884 kb
Host smart-42dfe219-35db-4562-a465-898f57ddc675
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011204815 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.4011204815
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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