Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	104403	1			T1	2		T2	28		T3	78
all_values[1]	104403	1			T1	2		T2	28		T3	78
all_values[2]	104403	1			T1	2		T2	28		T3	78
all_values[3]	104403	1			T1	2		T2	28		T3	78
all_values[4]	104403	1			T1	2		T2	28		T3	78
all_values[5]	104403	1			T1	2		T2	28		T3	78
all_values[6]	104403	1			T1	2		T2	28		T3	78
all_values[7]	104403	1			T1	2		T2	28		T3	78
all_values[8]	104403	1			T1	2		T2	28		T3	78

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

477326

1

T1

18

T2

140

T3

405

auto[1]

462301

1

T2

112

T3

297

T4

246

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

856597

1

T1

13

T2

240

T3

510

auto[1]

83030

1

T1

5

T2

12

T3

192

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	31554	1			T2	7		T4	8		T5	39
all_values[0]	auto[0]	auto[1]	21988	1			T1	2		T2	5		T3	78
all_values[0]	auto[1]	auto[0]	31959	1			T2	16		T5	17		T7	4
all_values[0]	auto[1]	auto[1]	18902	1			T5	7		T6	2		T7	7
all_values[1]	auto[0]	auto[0]	53789	1			T1	2		T2	16		T3	47
all_values[1]	auto[0]	auto[1]	1484	1			T3	31		T4	12		T43	2
all_values[1]	auto[1]	auto[0]	47724	1			T2	12		T5	53		T6	2
all_values[1]	auto[1]	auto[1]	1406	1			T5	5		T8	4		T11	8
all_values[2]	auto[0]	auto[0]	51383	1			T1	1		T2	16		T3	54
all_values[2]	auto[0]	auto[1]	2203	1			T1	1		T5	2		T7	6
all_values[2]	auto[1]	auto[0]	48771	1			T2	9		T3	24		T4	24
all_values[2]	auto[1]	auto[1]	2046	1			T2	3		T5	8		T6	1
all_values[3]	auto[0]	auto[0]	51445	1			T1	2		T2	28		T3	45
all_values[3]	auto[0]	auto[1]	241	1			T3	2		T11	1		T15	1
all_values[3]	auto[1]	auto[0]	52431	1			T3	31		T4	64		T5	53
all_values[3]	auto[1]	auto[1]	286	1			T4	2		T13	2		T84	1
all_values[4]	auto[0]	auto[0]	48196	1			T1	2		T2	12		T3	21
all_values[4]	auto[0]	auto[1]	438	1			T3	2		T4	15		T11	5
all_values[4]	auto[1]	auto[0]	55444	1			T2	16		T3	51		T4	16
all_values[4]	auto[1]	auto[1]	325	1			T3	4		T4	8		T39	4
all_values[5]	auto[0]	auto[0]	52010	1			T1	2		T4	42		T5	54
all_values[5]	auto[0]	auto[1]	148	1			T111	8		T29	2		T122	6
all_values[5]	auto[1]	auto[0]	52103	1			T2	28		T3	78		T4	24
all_values[5]	auto[1]	auto[1]	142	1			T13	3		T22	1		T111	4
all_values[6]	auto[0]	auto[0]	54432	1			T1	2		T2	16		T3	47
all_values[6]	auto[0]	auto[1]	142	1			T17	3		T111	6		T29	5
all_values[6]	auto[1]	auto[0]	49680	1			T2	12		T3	31		T4	42
all_values[6]	auto[1]	auto[1]	149	1			T22	3		T17	2		T111	2
all_values[7]	auto[0]	auto[0]	52163	1			T1	2		T2	28		T3	54
all_values[7]	auto[0]	auto[1]	333	1			T11	4		T12	6		T13	6
all_values[7]	auto[1]	auto[0]	51627	1			T3	24		T4	24		T5	35
all_values[7]	auto[1]	auto[1]	280	1			T12	1		T15	1		T39	4
all_values[8]	auto[0]	auto[0]	37593	1			T2	8		T4	4		T5	41
all_values[8]	auto[0]	auto[1]	17784	1			T1	2		T2	4		T3	24
all_values[8]	auto[1]	auto[0]	34293	1			T2	16		T3	3		T4	6
all_values[8]	auto[1]	auto[1]	14733	1			T3	51		T4	36		T5	7