Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1940	1			T1	1		T2	2		T8	2
auto[BaudRate115200]	1596	1			T1	1		T3	3		T6	1
auto[BaudRate230400]	1742	1			T2	1		T4	1		T7	2
auto[BaudRate128Kbps]	1527	1			T4	1		T6	2		T7	2
auto[BaudRate256Kbps]	1820	1			T2	3		T5	3		T6	1
auto[BaudRate1Mbps]	1513	1			T2	2		T5	5		T6	2
auto[BaudRate1p5Mbps]	1148	1			T5	2		T6	1		T7	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1217	1			T10	24		T20	2		T259	7
freqs[25]	1312	1			T6	7		T12	42		T15	1
freqs[48]	410	1			T7	10		T21	2		T278	2
freqs[50]	322	1			T44	2		T128	12		T84	8
freqs[100]	1059	1			T1	2		T5	10		T16	3

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	184	1			T10	9		T58	3		T142	1
auto[BaudRate9600]	freqs[25]	200	1			T12	7		T49	6		T160	1
auto[BaudRate9600]	freqs[48]	57	1			T278	1		T281	3		T145	1
auto[BaudRate9600]	freqs[50]	54	1			T44	1		T84	1		T131	1
auto[BaudRate9600]	freqs[100]	253	1			T1	1		T43	3		T38	2
auto[BaudRate115200]	freqs[24]	139	1			T10	3		T308	1		T120	1
auto[BaudRate115200]	freqs[25]	210	1			T6	1		T12	9		T304	1
auto[BaudRate115200]	freqs[48]	57	1			T21	1		T260	1		T321	1
auto[BaudRate115200]	freqs[50]	46	1			T128	2		T84	1		T131	1
auto[BaudRate115200]	freqs[100]	130	1			T1	1		T43	2		T38	1
auto[BaudRate230400]	freqs[24]	201	1			T20	2		T308	1		T58	2
auto[BaudRate230400]	freqs[25]	217	1			T12	3		T15	1		T40	1
auto[BaudRate230400]	freqs[48]	58	1			T7	2		T21	1		T260	3
auto[BaudRate230400]	freqs[50]	48	1			T44	1		T128	4		T84	1
auto[BaudRate230400]	freqs[100]	132	1			T16	1		T18	4		T43	1
auto[BaudRate128Kbps]	freqs[24]	180	1			T10	6		T120	3		T58	2
auto[BaudRate128Kbps]	freqs[25]	183	1			T6	2		T12	4		T40	2
auto[BaudRate128Kbps]	freqs[48]	46	1			T7	2		T281	3		T158	2
auto[BaudRate128Kbps]	freqs[50]	40	1			T128	1		T84	3		T131	2
auto[BaudRate128Kbps]	freqs[100]	123	1			T43	1		T129	2		T13	2
auto[BaudRate256Kbps]	freqs[24]	206	1			T10	6		T259	2		T262	3
auto[BaudRate256Kbps]	freqs[25]	221	1			T6	1		T12	2		T40	1
auto[BaudRate256Kbps]	freqs[48]	58	1			T7	2		T321	1		T281	2
auto[BaudRate256Kbps]	freqs[50]	51	1			T128	3		T84	1		T31	1
auto[BaudRate256Kbps]	freqs[100]	116	1			T5	3		T16	1		T18	2
auto[BaudRate1Mbps]	freqs[24]	207	1			T259	3		T262	3		T56	1
auto[BaudRate1Mbps]	freqs[25]	181	1			T6	2		T12	13		T40	1
auto[BaudRate1Mbps]	freqs[48]	54	1			T7	2		T278	1		T260	2
auto[BaudRate1Mbps]	freqs[50]	42	1			T128	1		T131	1		T31	1
auto[BaudRate1Mbps]	freqs[100]	139	1			T5	5		T18	1		T38	3
auto[BaudRate1p5Mbps]	freqs[25]	100	1			T6	1		T12	4		T40	1
auto[BaudRate1p5Mbps]	freqs[48]	80	1			T7	2		T260	2		T281	3
auto[BaudRate1p5Mbps]	freqs[50]	41	1			T128	1		T84	1		T31	1
auto[BaudRate1p5Mbps]	freqs[100]	166	1			T5	2		T16	1		T18	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded