Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.91	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	12	118	90.77

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	12	118	90.77	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	29230494	1			T2	85		T3	878		T4	5498
all_levels[1]	170497	1			T2	15		T5	2812		T8	23
all_levels[2]	1834	1			T6	1		T7	2		T43	2
all_levels[3]	863	1			T2	3		T41	1		T127	5
all_levels[4]	589	1			T43	1		T37	12		T40	2
all_levels[5]	439	1			T7	2		T8	2		T36	2
all_levels[6]	346	1			T8	1		T42	1		T43	1
all_levels[7]	304	1			T6	3		T41	2		T42	1
all_levels[8]	227	1			T41	1		T43	1		T127	1
all_levels[9]	225	1			T41	1		T43	1		T37	1
all_levels[10]	213	1			T2	2		T12	2		T128	1
all_levels[11]	148	1			T36	1		T129	1		T119	1
all_levels[12]	131	1			T36	1		T37	1		T119	4
all_levels[13]	110	1			T40	1		T112	3		T29	1
all_levels[14]	111	1			T43	1		T36	1		T40	2
all_levels[15]	95	1			T36	1		T130	1		T84	1
all_levels[16]	91	1			T36	1		T131	1		T132	1
all_levels[17]	90	1			T6	2		T12	1		T36	1
all_levels[18]	76	1			T43	2		T46	2		T48	1
all_levels[19]	69	1			T40	1		T29	1		T133	1
all_levels[20]	61	1			T130	1		T29	1		T133	1
all_levels[21]	71	1			T129	1		T134	1		T84	1
all_levels[22]	47	1			T131	1		T112	1		T135	2
all_levels[23]	70	1			T6	1		T36	1		T46	3
all_levels[24]	50	1			T56	1		T136	1		T137	3
all_levels[25]	54	1			T2	2		T111	1		T135	1
all_levels[26]	52	1			T36	1		T40	2		T138	1
all_levels[27]	42	1			T131	1		T112	1		T54	1
all_levels[28]	36	1			T133	1		T139	1		T140	1
all_levels[29]	43	1			T6	1		T134	1		T119	1
all_levels[30]	29	1			T54	1		T141	1		T121	1
all_levels[31]	29	1			T46	1		T48	1		T142	1
all_levels[32]	31	1			T134	1		T131	1		T143	1
all_levels[33]	14	1			T144	1		T145	1		T146	1
all_levels[34]	22	1			T51	2		T52	1		T105	1
all_levels[35]	29	1			T7	3		T17	1		T136	1
all_levels[36]	27	1			T84	1		T51	1		T52	2
all_levels[37]	21	1			T17	1		T58	2		T147	1
all_levels[38]	14	1			T48	1		T60	1		T148	1
all_levels[39]	10	1			T149	2		T150	1		T151	1
all_levels[40]	13	1			T12	1		T152	2		T153	2
all_levels[41]	22	1			T12	1		T54	2		T146	1
all_levels[42]	22	1			T29	1		T154	1		T155	3
all_levels[43]	14	1			T156	1		T157	1		T117	1
all_levels[44]	13	1			T131	1		T158	1		T159	1
all_levels[45]	14	1			T160	1		T60	1		T161	2
all_levels[46]	8	1			T60	1		T162	1		T154	1
all_levels[47]	18	1			T48	1		T17	1		T163	1
all_levels[48]	16	1			T121	1		T163	1		T164	3
all_levels[49]	9	1			T104	2		T165	1		T164	1
all_levels[50]	6	1			T52	1		T166	1		T167	1
all_levels[51]	17	1			T38	1		T160	1		T162	1
all_levels[52]	11	1			T164	1		T168	1		T169	1
all_levels[53]	4	1			T170	1		T171	1		T172	1
all_levels[54]	9	1			T47	1		T29	1		T155	1
all_levels[55]	6	1			T173	2		T174	1		T175	1
all_levels[56]	11	1			T148	1		T176	1		T177	3
all_levels[57]	15	1			T12	1		T60	1		T165	2
all_levels[58]	7	1			T141	2		T158	1		T178	1
all_levels[59]	1	1			T179	1		-	-		-	-
all_levels[60]	3	1			T84	1		T104	1		T180	1
all_levels[61]	5	1			T157	1		T181	1		T182	1
all_levels[62]	7	1			T176	1		T183	1		T184	1
all_levels[63]	8	1			T173	1		T185	1		T186	2
all_levels[64]	86	1			T12	1		T84	5		T17	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29403624

1

T2

99

T3

849

T4

5476

auto[1]

4425

1

T2

8

T3

29

T4

22

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	12	118	90.77	12

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[27]]	[auto[1]]	0	1	1
[all_levels[33]]	[auto[1]]	0	1	1
[all_levels[38]]	[auto[1]]	0	1	1
[all_levels[46]]	[auto[1]]	0	1	1
[all_levels[50]]	[auto[1]]	0	1	1
[all_levels[53] , all_levels[54] , all_levels[55]]	[auto[1]]	--	--	3
[all_levels[59] , all_levels[60] , all_levels[61]]	[auto[1]]	--	--	3
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	29226495	1			T2	84		T3	849		T4	5476
all_levels[0]	auto[1]	3999	1			T2	1		T3	29		T4	22
all_levels[1]	auto[0]	170424	1			T2	10		T5	2812		T8	23
all_levels[1]	auto[1]	73	1			T2	5		T43	1		T38	1
all_levels[2]	auto[0]	1811	1			T6	1		T7	1		T43	2
all_levels[2]	auto[1]	23	1			T7	1		T135	1		T161	4
all_levels[3]	auto[0]	839	1			T2	3		T41	1		T127	5
all_levels[3]	auto[1]	24	1			T138	2		T135	1		T187	1
all_levels[4]	auto[0]	575	1			T43	1		T37	12		T40	2
all_levels[4]	auto[1]	14	1			T142	1		T188	1		T100	1
all_levels[5]	auto[0]	418	1			T7	1		T8	1		T36	2
all_levels[5]	auto[1]	21	1			T7	1		T8	1		T131	1
all_levels[6]	auto[0]	325	1			T8	1		T42	1		T43	1
all_levels[6]	auto[1]	21	1			T149	1		T141	2		T104	3
all_levels[7]	auto[0]	285	1			T6	1		T41	1		T42	1
all_levels[7]	auto[1]	19	1			T6	2		T41	1		T135	1
all_levels[8]	auto[0]	215	1			T41	1		T43	1		T127	1
all_levels[8]	auto[1]	12	1			T189	1		T190	1		T188	3
all_levels[9]	auto[0]	210	1			T41	1		T43	1		T37	1
all_levels[9]	auto[1]	15	1			T191	1		T192	5		T193	1
all_levels[10]	auto[0]	203	1			T2	1		T12	2		T128	1
all_levels[10]	auto[1]	10	1			T2	1		T190	2		T150	1
all_levels[11]	auto[0]	140	1			T36	1		T129	1		T119	1
all_levels[11]	auto[1]	8	1			T194	3		T195	1		T196	1
all_levels[12]	auto[0]	123	1			T36	1		T37	1		T119	2
all_levels[12]	auto[1]	8	1			T119	2		T197	1		T198	1
all_levels[13]	auto[0]	105	1			T40	1		T112	3		T29	1
all_levels[13]	auto[1]	5	1			T199	1		T200	2		T201	1
all_levels[14]	auto[0]	105	1			T43	1		T36	1		T40	2
all_levels[14]	auto[1]	6	1			T202	2		T184	1		T203	1
all_levels[15]	auto[0]	92	1			T36	1		T130	1		T84	1
all_levels[15]	auto[1]	3	1			T204	1		T205	1		T206	1
all_levels[16]	auto[0]	85	1			T36	1		T131	1		T132	1
all_levels[16]	auto[1]	6	1			T207	1		T155	1		T208	1
all_levels[17]	auto[0]	78	1			T6	1		T12	1		T36	1
all_levels[17]	auto[1]	12	1			T6	1		T113	1		T209	4
all_levels[18]	auto[0]	68	1			T43	1		T46	1		T48	1
all_levels[18]	auto[1]	8	1			T43	1		T46	1		T210	3
all_levels[19]	auto[0]	65	1			T40	1		T29	1		T133	1
all_levels[19]	auto[1]	4	1			T186	1		T211	1		T212	1
all_levels[20]	auto[0]	58	1			T130	1		T29	1		T133	1
all_levels[20]	auto[1]	3	1			T143	1		T213	1		T214	1
all_levels[21]	auto[0]	63	1			T129	1		T134	1		T84	1
all_levels[21]	auto[1]	8	1			T144	2		T215	2		T168	1
all_levels[22]	auto[0]	43	1			T131	1		T112	1		T135	1
all_levels[22]	auto[1]	4	1			T135	1		T216	1		T217	2
all_levels[23]	auto[0]	59	1			T6	1		T36	1		T46	1
all_levels[23]	auto[1]	11	1			T46	2		T54	1		T218	1
all_levels[24]	auto[0]	47	1			T56	1		T136	1		T137	3
all_levels[24]	auto[1]	3	1			T219	1		T220	2		-	-
all_levels[25]	auto[0]	50	1			T2	1		T111	1		T135	1
all_levels[25]	auto[1]	4	1			T2	1		T56	1		T221	2
all_levels[26]	auto[0]	45	1			T36	1		T40	2		T138	1
all_levels[26]	auto[1]	7	1			T56	1		T149	1		T222	1
all_levels[27]	auto[0]	42	1			T131	1		T112	1		T54	1
all_levels[28]	auto[0]	30	1			T133	1		T139	1		T140	1
all_levels[28]	auto[1]	6	1			T162	1		T210	3		T223	2
all_levels[29]	auto[0]	38	1			T6	1		T134	1		T119	1
all_levels[29]	auto[1]	5	1			T224	1		T206	1		T225	2
all_levels[30]	auto[0]	28	1			T54	1		T141	1		T121	1
all_levels[30]	auto[1]	1	1			T226	1		-	-		-	-
all_levels[31]	auto[0]	27	1			T46	1		T48	1		T142	1
all_levels[31]	auto[1]	2	1			T227	2		-	-		-	-
all_levels[32]	auto[0]	29	1			T134	1		T131	1		T143	1
all_levels[32]	auto[1]	2	1			T228	1		T229	1		-	-
all_levels[33]	auto[0]	14	1			T144	1		T145	1		T146	1
all_levels[34]	auto[0]	19	1			T51	1		T52	1		T105	1
all_levels[34]	auto[1]	3	1			T51	1		T230	2		-	-
all_levels[35]	auto[0]	24	1			T7	1		T17	1		T136	1
all_levels[35]	auto[1]	5	1			T7	2		T231	1		T232	1
all_levels[36]	auto[0]	19	1			T84	1		T51	1		T52	1
all_levels[36]	auto[1]	8	1			T52	1		T172	1		T233	4
all_levels[37]	auto[0]	17	1			T17	1		T58	1		T147	1
all_levels[37]	auto[1]	4	1			T58	1		T234	2		T235	1
all_levels[38]	auto[0]	14	1			T48	1		T60	1		T148	1
all_levels[39]	auto[0]	9	1			T149	1		T150	1		T151	1
all_levels[39]	auto[1]	1	1			T149	1		-	-		-	-
all_levels[40]	auto[0]	10	1			T12	1		T152	1		T153	1
all_levels[40]	auto[1]	3	1			T152	1		T153	1		T236	1
all_levels[41]	auto[0]	18	1			T12	1		T54	1		T146	1
all_levels[41]	auto[1]	4	1			T54	1		T237	3		-	-
all_levels[42]	auto[0]	17	1			T29	1		T154	1		T155	2
all_levels[42]	auto[1]	5	1			T155	1		T238	2		T239	2
all_levels[43]	auto[0]	12	1			T156	1		T157	1		T117	1
all_levels[43]	auto[1]	2	1			T240	2		-	-		-	-
all_levels[44]	auto[0]	10	1			T131	1		T158	1		T159	1
all_levels[44]	auto[1]	3	1			T241	2		T242	1		-	-
all_levels[45]	auto[0]	11	1			T160	1		T60	1		T161	1
all_levels[45]	auto[1]	3	1			T161	1		T243	2		-	-
all_levels[46]	auto[0]	8	1			T60	1		T162	1		T154	1
all_levels[47]	auto[0]	16	1			T48	1		T17	1		T163	1
all_levels[47]	auto[1]	2	1			T244	2		-	-		-	-
all_levels[48]	auto[0]	13	1			T121	1		T163	1		T164	3
all_levels[48]	auto[1]	3	1			T245	1		T101	1		T246	1
all_levels[49]	auto[0]	7	1			T104	1		T165	1		T164	1
all_levels[49]	auto[1]	2	1			T104	1		T184	1		-	-
all_levels[50]	auto[0]	6	1			T52	1		T166	1		T167	1
all_levels[51]	auto[0]	12	1			T38	1		T160	1		T162	1
all_levels[51]	auto[1]	5	1			T168	1		T247	4		-	-
all_levels[52]	auto[0]	10	1			T164	1		T168	1		T169	1
all_levels[52]	auto[1]	1	1			T248	1		-	-		-	-
all_levels[53]	auto[0]	4	1			T170	1		T171	1		T172	1
all_levels[54]	auto[0]	9	1			T47	1		T29	1		T155	1
all_levels[55]	auto[0]	6	1			T173	2		T174	1		T175	1
all_levels[56]	auto[0]	8	1			T148	1		T176	1		T177	1
all_levels[56]	auto[1]	3	1			T177	2		T249	1		-	-
all_levels[57]	auto[0]	10	1			T12	1		T60	1		T165	1
all_levels[57]	auto[1]	5	1			T165	1		T250	1		T251	3
all_levels[58]	auto[0]	6	1			T141	1		T158	1		T178	1
all_levels[58]	auto[1]	1	1			T141	1		-	-		-	-
all_levels[59]	auto[0]	1	1			T179	1		-	-		-	-
all_levels[60]	auto[0]	3	1			T84	1		T104	1		T180	1
all_levels[61]	auto[0]	5	1			T157	1		T181	1		T182	1
all_levels[62]	auto[0]	6	1			T176	1		T183	1		T184	1
all_levels[62]	auto[1]	1	1			T252	1		-	-		-	-
all_levels[63]	auto[0]	8	1			T173	1		T185	1		T186	2
all_levels[64]	auto[0]	72	1			T12	1		T84	2		T17	1
all_levels[64]	auto[1]	14	1			T84	3		T113	3		T253	1