Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	104403	1			T1	2		T2	28		T3	78
all_pins[1]	104403	1			T1	2		T2	28		T3	78
all_pins[2]	104403	1			T1	2		T2	28		T3	78
all_pins[3]	104403	1			T1	2		T2	28		T3	78
all_pins[4]	104403	1			T1	2		T2	28		T3	78
all_pins[5]	104403	1			T1	2		T2	28		T3	78
all_pins[6]	104403	1			T1	2		T2	28		T3	78
all_pins[7]	104403	1			T1	2		T2	28		T3	78
all_pins[8]	104403	1			T1	2		T2	28		T3	78

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	900558	1			T1	18		T2	247		T3	645
values[0x1]	39069	1			T2	5		T3	57		T4	50
transitions[0x0=>0x1]	31792	1			T2	5		T3	55		T4	49
transitions[0x1=>0x0]	31561	1			T2	5		T3	56		T4	49

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	85432	1			T1	2		T2	28		T3	78
all_pins[0]	values[0x1]	18971	1			T5	7		T6	2		T7	7
all_pins[0]	transitions[0x0=>0x1]	18534	1			T5	5		T6	2		T7	7
all_pins[0]	transitions[0x1=>0x0]	969	1			T5	3		T11	8		T36	14
all_pins[1]	values[0x0]	102997	1			T1	2		T2	28		T3	78
all_pins[1]	values[0x1]	1406	1			T5	5		T8	4		T11	8
all_pins[1]	transitions[0x0=>0x1]	1312	1			T5	3		T8	1		T11	8
all_pins[1]	transitions[0x1=>0x0]	2025	1			T2	3		T4	1		T5	6
all_pins[2]	values[0x0]	102284	1			T1	2		T2	25		T3	78
all_pins[2]	values[0x1]	2119	1			T2	3		T4	1		T5	8
all_pins[2]	transitions[0x0=>0x1]	2054	1			T2	3		T4	1		T5	8
all_pins[2]	transitions[0x1=>0x0]	221	1			T4	2		T84	1		T22	1
all_pins[3]	values[0x0]	104117	1			T1	2		T2	28		T3	78
all_pins[3]	values[0x1]	286	1			T4	2		T13	2		T84	1
all_pins[3]	transitions[0x0=>0x1]	254	1			T4	2		T13	2		T84	1
all_pins[3]	transitions[0x1=>0x0]	293	1			T3	4		T4	8		T39	4
all_pins[4]	values[0x0]	104078	1			T1	2		T2	28		T3	74
all_pins[4]	values[0x1]	325	1			T3	4		T4	8		T39	4
all_pins[4]	transitions[0x0=>0x1]	273	1			T3	3		T4	7		T39	3
all_pins[4]	transitions[0x1=>0x0]	139	1			T12	1		T118	2		T13	8
all_pins[5]	values[0x0]	104212	1			T1	2		T2	28		T3	77
all_pins[5]	values[0x1]	191	1			T3	1		T4	1		T12	1
all_pins[5]	transitions[0x0=>0x1]	148	1			T3	1		T4	1		T12	1
all_pins[5]	transitions[0x1=>0x0]	657	1			T2	2		T4	2		T43	1
all_pins[6]	values[0x0]	103703	1			T1	2		T2	26		T3	78
all_pins[6]	values[0x1]	700	1			T2	2		T4	2		T43	1
all_pins[6]	transitions[0x0=>0x1]	656	1			T2	2		T4	2		T43	1
all_pins[6]	transitions[0x1=>0x0]	236	1			T12	1		T15	1		T39	4
all_pins[7]	values[0x0]	104123	1			T1	2		T2	28		T3	78
all_pins[7]	values[0x1]	280	1			T12	1		T15	1		T39	4
all_pins[7]	transitions[0x0=>0x1]	156	1			T40	1		T118	2		T13	1
all_pins[7]	transitions[0x1=>0x0]	14667	1			T3	52		T4	36		T5	7
all_pins[8]	values[0x0]	89612	1			T1	2		T2	28		T3	26
all_pins[8]	values[0x1]	14791	1			T3	52		T4	36		T5	7
all_pins[8]	transitions[0x0=>0x1]	8405	1			T3	51		T4	36		T5	3
all_pins[8]	transitions[0x1=>0x0]	12354	1			T5	3		T6	1		T8	34