Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7625558	1			T2	8		T3	28		T4	12
all_levels[1]	1480091	1			T2	11		T3	848		T4	3512
all_levels[2]	375269	1			T5	211		T7	3		T18	4715
all_levels[3]	207254	1			T2	3		T5	225		T7	2
all_levels[4]	215561	1			T2	1		T5	230		T18	4705
all_levels[5]	197637	1			T5	197		T18	4690		T43	6
all_levels[6]	239149	1			T2	1		T5	218		T18	4709
all_levels[7]	342400	1			T2	3		T4	8		T5	200
all_levels[8]	293605	1			T2	2		T4	1962		T5	237
all_levels[9]	245617	1			T2	7		T5	207		T16	1
all_levels[10]	202959	1			T2	3		T5	242		T18	4699
all_levels[11]	226416	1			T2	3		T5	213		T16	9
all_levels[12]	653768	1			T2	3		T5	215		T42	3
all_levels[13]	627623	1			T2	2		T5	223		T8	3
all_levels[14]	193464	1			T2	1		T5	235		T42	1
all_levels[15]	175715	1			T2	1		T5	193		T18	4774
all_levels[16]	279734	1			T2	6		T5	233		T41	3
all_levels[17]	168994	1			T2	4		T5	224		T18	5844
all_levels[18]	167065	1			T2	6		T5	216		T42	1
all_levels[19]	265406	1			T2	4		T5	227		T42	2
all_levels[20]	165233	1			T2	4		T5	233		T7	2
all_levels[21]	161971	1			T2	3		T5	229		T42	2
all_levels[22]	169147	1			T2	3		T5	232		T18	5783
all_levels[23]	322332	1			T2	2		T5	210		T18	5758
all_levels[24]	255462	1			T2	1		T5	230		T18	5798
all_levels[25]	385005	1			T2	7		T5	186		T18	5795
all_levels[26]	198600	1			T2	4		T5	254		T7	2
all_levels[27]	270434	1			T2	3		T5	228		T42	1
all_levels[28]	164324	1			T5	231		T18	5821		T19	7031
all_levels[29]	170742	1			T2	1		T5	218		T18	5775
all_levels[30]	321403	1			T2	2		T5	202		T18	5808
all_levels[31]	538379	1			T2	4		T5	5217		T18	16480
all_levels[32]	12101385	1			T2	4		T5	129097		T6	3

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29403624

1

T2

99

T3

849

T4

5476

auto[1]

4078

1

T2

8

T3

27

T4

18

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7623199	1			T2	7		T3	1		T4	1
all_levels[0]	auto[1]	2359	1			T2	1		T3	27		T4	11
all_levels[1]	auto[0]	1479833	1			T2	9		T3	848		T4	3512
all_levels[1]	auto[1]	258	1			T2	2		T38	4		T22	3
all_levels[2]	auto[0]	375218	1			T5	211		T7	1		T18	4715
all_levels[2]	auto[1]	51	1			T7	2		T265	1		T132	2
all_levels[3]	auto[0]	207154	1			T2	3		T5	225		T7	1
all_levels[3]	auto[1]	100	1			T7	1		T13	5		T48	1
all_levels[4]	auto[0]	215533	1			T2	1		T5	230		T18	4705
all_levels[4]	auto[1]	28	1			T146	2		T141	1		T338	1
all_levels[5]	auto[0]	197609	1			T5	197		T18	4690		T43	6
all_levels[5]	auto[1]	28	1			T38	1		T144	1		T54	2
all_levels[6]	auto[0]	239124	1			T2	1		T5	218		T18	4709
all_levels[6]	auto[1]	25	1			T202	1		T189	1		T269	1
all_levels[7]	auto[0]	342302	1			T2	3		T4	1		T5	200
all_levels[7]	auto[1]	98	1			T4	7		T12	11		T39	18
all_levels[8]	auto[0]	293571	1			T2	2		T4	1962		T5	237
all_levels[8]	auto[1]	34	1			T45	1		T113	1		T135	2
all_levels[9]	auto[0]	245586	1			T2	2		T5	207		T16	1
all_levels[9]	auto[1]	31	1			T2	5		T104	3		T332	1
all_levels[10]	auto[0]	202928	1			T2	3		T5	242		T18	4699
all_levels[10]	auto[1]	31	1			T48	3		T116	3		T54	1
all_levels[11]	auto[0]	226375	1			T2	3		T5	213		T16	9
all_levels[11]	auto[1]	41	1			T131	1		T283	2		T304	1
all_levels[12]	auto[0]	653745	1			T2	3		T5	215		T42	3
all_levels[12]	auto[1]	23	1			T304	1		T339	1		T205	1
all_levels[13]	auto[0]	627596	1			T2	2		T5	223		T8	3
all_levels[13]	auto[1]	27	1			T36	1		T111	1		T271	1
all_levels[14]	auto[0]	193428	1			T2	1		T5	235		T42	1
all_levels[14]	auto[1]	36	1			T197	2		T274	2		T190	2
all_levels[15]	auto[0]	175588	1			T2	1		T5	193		T18	4774
all_levels[15]	auto[1]	127	1			T118	2		T121	5		T340	1
all_levels[16]	auto[0]	279722	1			T2	6		T5	233		T41	2
all_levels[16]	auto[1]	12	1			T41	1		T341	1		T342	1
all_levels[17]	auto[0]	168973	1			T2	4		T5	224		T18	5844
all_levels[17]	auto[1]	21	1			T128	1		T46	1		T132	1
all_levels[18]	auto[0]	167034	1			T2	6		T5	216		T42	1
all_levels[18]	auto[1]	31	1			T52	1		T60	1		T218	1
all_levels[19]	auto[0]	265383	1			T2	4		T5	227		T42	2
all_levels[19]	auto[1]	23	1			T306	2		T101	3		T343	3
all_levels[20]	auto[0]	165216	1			T2	4		T5	233		T7	1
all_levels[20]	auto[1]	17	1			T7	1		T8	1		T131	1
all_levels[21]	auto[0]	161961	1			T2	3		T5	229		T42	2
all_levels[21]	auto[1]	10	1			T119	2		T51	1		T105	2
all_levels[22]	auto[0]	169135	1			T2	3		T5	232		T18	5783
all_levels[22]	auto[1]	12	1			T162	1		T344	2		T345	1
all_levels[23]	auto[0]	322318	1			T2	2		T5	210		T18	5758
all_levels[23]	auto[1]	14	1			T346	1		T347	1		T348	1
all_levels[24]	auto[0]	255425	1			T2	1		T5	230		T18	5798
all_levels[24]	auto[1]	37	1			T46	2		T116	1		T202	2
all_levels[25]	auto[0]	384980	1			T2	7		T5	186		T18	5795
all_levels[25]	auto[1]	25	1			T149	1		T197	2		T332	1
all_levels[26]	auto[0]	198577	1			T2	4		T5	254		T7	2
all_levels[26]	auto[1]	23	1			T119	2		T45	5		T111	1
all_levels[27]	auto[0]	270415	1			T2	3		T5	228		T42	1
all_levels[27]	auto[1]	19	1			T133	1		T54	1		T349	2
all_levels[28]	auto[0]	164309	1			T5	231		T18	5821		T19	7031
all_levels[28]	auto[1]	15	1			T152	1		T316	1		T322	2
all_levels[29]	auto[0]	170731	1			T2	1		T5	218		T18	5775
all_levels[29]	auto[1]	11	1			T144	1		T164	1		T350	3
all_levels[30]	auto[0]	321382	1			T2	2		T5	202		T18	5808
all_levels[30]	auto[1]	21	1			T43	1		T22	1		T50	1
all_levels[31]	auto[0]	538366	1			T2	4		T5	5217		T18	16480
all_levels[31]	auto[1]	13	1			T351	4		T161	1		T352	1
all_levels[32]	auto[0]	12100908	1			T2	4		T5	129097		T6	2
all_levels[32]	auto[1]	477	1			T6	1		T8	3		T41	2