Group : uart_env_pkg::uart_env_cov::tx_watermark_cg
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Group : uart_env_pkg::uart_env_cov::tx_watermark_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
71.43 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::tx_watermark_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 2 5 71.43


Variables for Group uart_env_pkg::uart_env_cov::tx_watermark_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_watermark_lvl 7 2 5 71.43 100 1 1 0


Summary for Variable cp_watermark_lvl

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 7 2 5 71.43


User Defined Bins for cp_watermark_lvl

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
all_levels[5] 0 1 1
all_levels[6] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 6645 1 T1 2 T3 23 T4 21
all_levels[1] 9015 1 T2 5 T5 2 T8 1
all_levels[2] 6626 1 T7 7 T10 1 T42 1
all_levels[3] 10469 1 T4 39 T5 33 T6 2
all_levels[4] 8268 1 T3 55 T41 3 T42 3

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