Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	614	1			T13	7		T22	4		T17	7
all_values[1]	614	1			T13	7		T22	4		T17	7
all_values[2]	614	1			T13	7		T22	4		T17	7
all_values[3]	614	1			T13	7		T22	4		T17	7
all_values[4]	614	1			T13	7		T22	4		T17	7
all_values[5]	614	1			T13	7		T22	4		T17	7
all_values[6]	614	1			T13	7		T22	4		T17	7
all_values[7]	614	1			T13	7		T22	4		T17	7
all_values[8]	614	1			T13	7		T22	4		T17	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2945

1

T13

38

T22

20

T17

28

auto[1]

2581

1

T13

25

T22

16

T17

35

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1768

1

T13

24

T22

12

T17

14

auto[1]

3758

1

T13

39

T22

24

T17

49

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3289

1

T13

39

T22

24

T17

35

auto[1]

2237

1

T13

24

T22

12

T17

28

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	195	1			T13	1		T22	3		T17	2
all_values[0]	auto[0]	auto[1]	auto[1]	172	1			T13	3		T17	2		T111	5
all_values[0]	auto[1]	auto[0]	auto[1]	130	1			T22	1		T17	1		T111	1
all_values[0]	auto[1]	auto[1]	auto[1]	117	1			T13	3		T17	2		T111	5
all_values[1]	auto[0]	auto[0]	auto[0]	205	1			T13	2		T22	3		T111	6
all_values[1]	auto[0]	auto[1]	auto[0]	175	1			T13	1		T17	3		T111	3
all_values[1]	auto[1]	auto[0]	auto[1]	123	1			T13	4		T22	1		T17	1
all_values[1]	auto[1]	auto[1]	auto[1]	111	1			T17	3		T111	2		T29	4
all_values[2]	auto[0]	auto[0]	auto[0]	134	1			T13	3		T22	1		T111	2
all_values[2]	auto[0]	auto[0]	auto[1]	70	1			T22	2		T17	1		T111	3
all_values[2]	auto[0]	auto[1]	auto[0]	86	1			T17	2		T111	2		T29	4
all_values[2]	auto[0]	auto[1]	auto[1]	64	1			T13	2		T29	1		T122	1
all_values[2]	auto[1]	auto[0]	auto[1]	159	1			T13	1		T22	1		T17	4
all_values[2]	auto[1]	auto[1]	auto[1]	101	1			T13	1		T111	4		T29	1
all_values[3]	auto[0]	auto[0]	auto[0]	130	1			T13	1		T22	2		T111	3
all_values[3]	auto[0]	auto[0]	auto[1]	56	1			T13	1		T17	1		T29	4
all_values[3]	auto[0]	auto[1]	auto[0]	97	1			T17	3		T111	5		T122	5
all_values[3]	auto[0]	auto[1]	auto[1]	78	1			T13	1		T17	1		T111	1
all_values[3]	auto[1]	auto[0]	auto[1]	122	1			T13	3		T22	1		T111	2
all_values[3]	auto[1]	auto[1]	auto[1]	131	1			T13	1		T22	1		T17	2
all_values[4]	auto[0]	auto[0]	auto[0]	135	1			T13	4		T17	1		T111	1
all_values[4]	auto[0]	auto[0]	auto[1]	67	1			T22	1		T17	1		T111	1
all_values[4]	auto[0]	auto[1]	auto[0]	101	1			T13	1		T111	1		T122	1
all_values[4]	auto[0]	auto[1]	auto[1]	61	1			T22	1		T17	2		T111	3
all_values[4]	auto[1]	auto[0]	auto[1]	140	1			T13	1		T22	1		T111	5
all_values[4]	auto[1]	auto[1]	auto[1]	110	1			T13	1		T22	1		T17	3
all_values[5]	auto[0]	auto[0]	auto[0]	117	1			T13	3		T17	2		T29	4
all_values[5]	auto[0]	auto[0]	auto[1]	58	1			T111	2		T29	1		T122	5
all_values[5]	auto[0]	auto[1]	auto[0]	116	1			T22	3		T17	2		T111	1
all_values[5]	auto[0]	auto[1]	auto[1]	58	1			T13	2		T111	3		T29	1
all_values[5]	auto[1]	auto[0]	auto[1]	142	1			T13	1		T17	2		T111	7
all_values[5]	auto[1]	auto[1]	auto[1]	123	1			T13	1		T22	1		T17	1
all_values[6]	auto[0]	auto[0]	auto[0]	99	1			T13	3		T17	1		T111	4
all_values[6]	auto[0]	auto[0]	auto[1]	65	1			T17	2		T111	3		T29	3
all_values[6]	auto[0]	auto[1]	auto[0]	131	1			T13	3		T22	1		T111	2
all_values[6]	auto[0]	auto[1]	auto[1]	61	1			T22	1		T17	1		T29	1
all_values[6]	auto[1]	auto[0]	auto[1]	136	1			T17	2		T111	5		T29	6
all_values[6]	auto[1]	auto[1]	auto[1]	122	1			T13	1		T22	2		T17	1
all_values[7]	auto[0]	auto[0]	auto[0]	131	1			T13	2		T22	1		T111	4
all_values[7]	auto[0]	auto[0]	auto[1]	58	1			T13	1		T17	2		T111	1
all_values[7]	auto[0]	auto[1]	auto[0]	111	1			T13	1		T22	1		T111	1
all_values[7]	auto[0]	auto[1]	auto[1]	73	1			T13	1		T22	1		T17	2
all_values[7]	auto[1]	auto[0]	auto[1]	140	1			T13	2		T17	1		T111	4
all_values[7]	auto[1]	auto[1]	auto[1]	101	1			T22	1		T17	2		T111	2
all_values[8]	auto[0]	auto[0]	auto[1]	209	1			T13	2		T22	2		T17	3
all_values[8]	auto[0]	auto[1]	auto[1]	176	1			T13	1		T22	1		T17	1
all_values[8]	auto[1]	auto[0]	auto[1]	124	1			T13	3		T17	1		T111	5
all_values[8]	auto[1]	auto[1]	auto[1]	105	1			T13	1		T22	1		T17	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal