Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.10 99.10 97.65 100.00 98.38 100.00 99.50


Total test records in report: 1232
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T1035 /workspace/coverage/default/10.uart_long_xfer_wo_dly.3161884375 Jun 29 04:48:11 PM PDT 24 Jun 29 04:49:31 PM PDT 24 45339884600 ps
T1036 /workspace/coverage/default/16.uart_fifo_full.1585473806 Jun 29 04:48:24 PM PDT 24 Jun 29 04:51:36 PM PDT 24 126426022401 ps
T180 /workspace/coverage/default/194.uart_fifo_reset.2712777391 Jun 29 04:51:21 PM PDT 24 Jun 29 04:51:34 PM PDT 24 31420874263 ps
T1037 /workspace/coverage/default/35.uart_tx_ovrd.3281436121 Jun 29 04:49:33 PM PDT 24 Jun 29 04:49:36 PM PDT 24 1738140535 ps
T94 /workspace/coverage/default/4.uart_sec_cm.1025355431 Jun 29 04:48:04 PM PDT 24 Jun 29 04:48:06 PM PDT 24 55573913 ps
T1038 /workspace/coverage/default/29.uart_fifo_overflow.2857159364 Jun 29 04:49:05 PM PDT 24 Jun 29 04:50:51 PM PDT 24 73335964330 ps
T1039 /workspace/coverage/default/47.uart_loopback.3707479201 Jun 29 04:50:14 PM PDT 24 Jun 29 04:50:26 PM PDT 24 5430734895 ps
T1040 /workspace/coverage/default/141.uart_fifo_reset.1450080316 Jun 29 04:51:02 PM PDT 24 Jun 29 04:52:13 PM PDT 24 42059225727 ps
T1041 /workspace/coverage/default/44.uart_long_xfer_wo_dly.4146402097 Jun 29 04:50:07 PM PDT 24 Jun 29 05:00:56 PM PDT 24 92339388957 ps
T1042 /workspace/coverage/default/8.uart_long_xfer_wo_dly.45516777 Jun 29 04:48:02 PM PDT 24 Jun 29 04:53:47 PM PDT 24 140700419702 ps
T1043 /workspace/coverage/default/103.uart_fifo_reset.3911396944 Jun 29 04:50:51 PM PDT 24 Jun 29 04:51:14 PM PDT 24 134257709450 ps
T1044 /workspace/coverage/default/31.uart_rx_start_bit_filter.2152242699 Jun 29 04:49:13 PM PDT 24 Jun 29 04:49:16 PM PDT 24 2687745067 ps
T1045 /workspace/coverage/default/20.uart_rx_oversample.2498767081 Jun 29 04:48:27 PM PDT 24 Jun 29 04:48:29 PM PDT 24 1295326363 ps
T1046 /workspace/coverage/default/29.uart_smoke.2198812380 Jun 29 04:49:09 PM PDT 24 Jun 29 04:49:11 PM PDT 24 544664446 ps
T1047 /workspace/coverage/default/29.uart_stress_all.451951778 Jun 29 04:49:05 PM PDT 24 Jun 29 04:49:41 PM PDT 24 75530099056 ps
T1048 /workspace/coverage/default/21.uart_alert_test.253140725 Jun 29 04:48:39 PM PDT 24 Jun 29 04:48:40 PM PDT 24 93993844 ps
T1049 /workspace/coverage/default/120.uart_fifo_reset.2181886260 Jun 29 04:50:58 PM PDT 24 Jun 29 04:51:11 PM PDT 24 17391825380 ps
T1050 /workspace/coverage/default/40.uart_long_xfer_wo_dly.2254173720 Jun 29 04:49:49 PM PDT 24 Jun 29 05:03:46 PM PDT 24 188886876505 ps
T1051 /workspace/coverage/default/17.uart_fifo_full.2568885548 Jun 29 04:48:34 PM PDT 24 Jun 29 04:51:50 PM PDT 24 137146423608 ps
T1052 /workspace/coverage/default/184.uart_fifo_reset.658903755 Jun 29 04:51:20 PM PDT 24 Jun 29 04:52:04 PM PDT 24 27279810351 ps
T1053 /workspace/coverage/default/40.uart_fifo_overflow.1074918343 Jun 29 04:49:43 PM PDT 24 Jun 29 04:50:27 PM PDT 24 25971497131 ps
T1054 /workspace/coverage/default/84.uart_stress_all_with_rand_reset.2822633751 Jun 29 04:50:43 PM PDT 24 Jun 29 05:07:14 PM PDT 24 53883632894 ps
T1055 /workspace/coverage/default/2.uart_perf.708480723 Jun 29 04:48:01 PM PDT 24 Jun 29 05:05:09 PM PDT 24 17963525658 ps
T1056 /workspace/coverage/default/11.uart_smoke.4098505088 Jun 29 04:48:09 PM PDT 24 Jun 29 04:48:12 PM PDT 24 914711707 ps
T1057 /workspace/coverage/default/2.uart_alert_test.1728997650 Jun 29 04:47:54 PM PDT 24 Jun 29 04:47:55 PM PDT 24 82102138 ps
T1058 /workspace/coverage/default/38.uart_intr.2992537629 Jun 29 04:49:35 PM PDT 24 Jun 29 04:49:40 PM PDT 24 7889673186 ps
T1059 /workspace/coverage/default/21.uart_rx_oversample.3955360748 Jun 29 04:48:35 PM PDT 24 Jun 29 04:49:39 PM PDT 24 7281271500 ps
T1060 /workspace/coverage/default/267.uart_fifo_reset.724372024 Jun 29 04:51:52 PM PDT 24 Jun 29 04:52:37 PM PDT 24 20468266236 ps
T1061 /workspace/coverage/default/173.uart_fifo_reset.3035979149 Jun 29 04:51:13 PM PDT 24 Jun 29 04:51:31 PM PDT 24 41802983654 ps
T1062 /workspace/coverage/default/34.uart_long_xfer_wo_dly.821409404 Jun 29 04:49:30 PM PDT 24 Jun 29 04:59:52 PM PDT 24 80411744388 ps
T1063 /workspace/coverage/default/45.uart_smoke.4050723442 Jun 29 04:50:05 PM PDT 24 Jun 29 04:50:08 PM PDT 24 488306702 ps
T1064 /workspace/coverage/default/46.uart_alert_test.3085935342 Jun 29 04:50:17 PM PDT 24 Jun 29 04:50:18 PM PDT 24 23951306 ps
T1065 /workspace/coverage/default/45.uart_loopback.429481707 Jun 29 04:50:06 PM PDT 24 Jun 29 04:50:22 PM PDT 24 12424932759 ps
T1066 /workspace/coverage/default/28.uart_alert_test.291925367 Jun 29 04:49:03 PM PDT 24 Jun 29 04:49:04 PM PDT 24 29996651 ps
T1067 /workspace/coverage/default/31.uart_perf.3830776493 Jun 29 04:49:14 PM PDT 24 Jun 29 04:54:33 PM PDT 24 12096351183 ps
T1068 /workspace/coverage/default/5.uart_rx_parity_err.3892057245 Jun 29 04:47:54 PM PDT 24 Jun 29 04:48:23 PM PDT 24 119025483574 ps
T1069 /workspace/coverage/default/229.uart_fifo_reset.2122107161 Jun 29 04:51:35 PM PDT 24 Jun 29 04:51:56 PM PDT 24 9220966936 ps
T1070 /workspace/coverage/default/31.uart_smoke.1625161873 Jun 29 04:49:10 PM PDT 24 Jun 29 04:49:41 PM PDT 24 10570594715 ps
T1071 /workspace/coverage/default/22.uart_intr.1375258121 Jun 29 04:48:45 PM PDT 24 Jun 29 04:49:35 PM PDT 24 69268214847 ps
T1072 /workspace/coverage/default/7.uart_stress_all.51750033 Jun 29 04:48:08 PM PDT 24 Jun 29 04:53:45 PM PDT 24 19180442692 ps
T1073 /workspace/coverage/default/221.uart_fifo_reset.1179241226 Jun 29 04:51:36 PM PDT 24 Jun 29 04:52:30 PM PDT 24 121770352971 ps
T1074 /workspace/coverage/default/47.uart_fifo_overflow.4124840810 Jun 29 04:50:15 PM PDT 24 Jun 29 04:51:05 PM PDT 24 155203723121 ps
T1075 /workspace/coverage/default/142.uart_fifo_reset.880810200 Jun 29 04:50:58 PM PDT 24 Jun 29 04:54:42 PM PDT 24 77965565402 ps
T246 /workspace/coverage/default/185.uart_fifo_reset.2688484538 Jun 29 04:51:22 PM PDT 24 Jun 29 04:51:51 PM PDT 24 20273107624 ps
T1076 /workspace/coverage/default/93.uart_stress_all_with_rand_reset.3149139903 Jun 29 04:50:52 PM PDT 24 Jun 29 04:56:15 PM PDT 24 120917256305 ps
T1077 /workspace/coverage/default/80.uart_fifo_reset.854569443 Jun 29 04:50:49 PM PDT 24 Jun 29 04:52:23 PM PDT 24 86889697364 ps
T179 /workspace/coverage/default/30.uart_rx_parity_err.1759425829 Jun 29 04:49:12 PM PDT 24 Jun 29 04:49:26 PM PDT 24 46697535090 ps
T1078 /workspace/coverage/default/94.uart_fifo_reset.2701947021 Jun 29 04:50:51 PM PDT 24 Jun 29 04:51:36 PM PDT 24 109539587009 ps
T1079 /workspace/coverage/default/28.uart_fifo_full.2699283140 Jun 29 04:49:02 PM PDT 24 Jun 29 04:49:25 PM PDT 24 103809922062 ps
T1080 /workspace/coverage/default/40.uart_rx_parity_err.846510862 Jun 29 04:49:50 PM PDT 24 Jun 29 04:51:04 PM PDT 24 60129374563 ps
T1081 /workspace/coverage/default/13.uart_stress_all.1265602355 Jun 29 04:48:22 PM PDT 24 Jun 29 04:55:27 PM PDT 24 48462671297 ps
T1082 /workspace/coverage/default/294.uart_fifo_reset.2520775486 Jun 29 04:51:58 PM PDT 24 Jun 29 04:52:29 PM PDT 24 17874031559 ps
T1083 /workspace/coverage/default/25.uart_alert_test.256316021 Jun 29 04:48:49 PM PDT 24 Jun 29 04:48:50 PM PDT 24 12529254 ps
T1084 /workspace/coverage/default/46.uart_fifo_full.2253061532 Jun 29 04:50:15 PM PDT 24 Jun 29 04:50:52 PM PDT 24 81559631250 ps
T1085 /workspace/coverage/default/32.uart_intr.3874666373 Jun 29 04:49:24 PM PDT 24 Jun 29 04:49:28 PM PDT 24 13531601314 ps
T1086 /workspace/coverage/default/40.uart_tx_rx.4218038187 Jun 29 04:49:47 PM PDT 24 Jun 29 04:51:18 PM PDT 24 52708074377 ps
T1087 /workspace/coverage/default/215.uart_fifo_reset.141978893 Jun 29 04:51:28 PM PDT 24 Jun 29 04:54:25 PM PDT 24 144454285100 ps
T1088 /workspace/coverage/default/22.uart_noise_filter.1619115988 Jun 29 04:48:43 PM PDT 24 Jun 29 04:49:08 PM PDT 24 74674648514 ps
T1089 /workspace/coverage/default/23.uart_rx_oversample.4007781239 Jun 29 04:48:54 PM PDT 24 Jun 29 04:48:59 PM PDT 24 2686162599 ps
T1090 /workspace/coverage/default/2.uart_loopback.2723773533 Jun 29 04:48:00 PM PDT 24 Jun 29 04:48:10 PM PDT 24 8821145584 ps
T1091 /workspace/coverage/default/15.uart_loopback.696928517 Jun 29 04:48:15 PM PDT 24 Jun 29 04:48:21 PM PDT 24 5875674401 ps
T1092 /workspace/coverage/default/7.uart_noise_filter.4246102148 Jun 29 04:48:00 PM PDT 24 Jun 29 04:48:21 PM PDT 24 23620113629 ps
T1093 /workspace/coverage/default/0.uart_fifo_reset.38842018 Jun 29 04:47:54 PM PDT 24 Jun 29 04:48:55 PM PDT 24 43395495566 ps
T1094 /workspace/coverage/default/46.uart_fifo_reset.4227536733 Jun 29 04:50:14 PM PDT 24 Jun 29 04:51:20 PM PDT 24 137115765179 ps
T1095 /workspace/coverage/default/30.uart_smoke.3527867980 Jun 29 04:49:05 PM PDT 24 Jun 29 04:49:08 PM PDT 24 649453667 ps
T1096 /workspace/coverage/default/21.uart_tx_rx.4212046271 Jun 29 04:48:39 PM PDT 24 Jun 29 04:48:58 PM PDT 24 18248314837 ps
T1097 /workspace/coverage/default/11.uart_rx_start_bit_filter.1986284291 Jun 29 04:48:09 PM PDT 24 Jun 29 04:48:11 PM PDT 24 2119941392 ps
T1098 /workspace/coverage/cover_reg_top/32.uart_intr_test.110943430 Jun 29 05:34:54 PM PDT 24 Jun 29 05:34:57 PM PDT 24 17510873 ps
T1099 /workspace/coverage/cover_reg_top/40.uart_intr_test.3519417911 Jun 29 05:35:05 PM PDT 24 Jun 29 05:35:06 PM PDT 24 17600563 ps
T74 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2617466469 Jun 29 05:34:44 PM PDT 24 Jun 29 05:34:45 PM PDT 24 59717204 ps
T85 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1438041099 Jun 29 05:34:59 PM PDT 24 Jun 29 05:35:02 PM PDT 24 841722868 ps
T86 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1302931141 Jun 29 05:34:29 PM PDT 24 Jun 29 05:34:32 PM PDT 24 524936167 ps
T87 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3259358811 Jun 29 05:34:54 PM PDT 24 Jun 29 05:34:57 PM PDT 24 1251925576 ps
T1100 /workspace/coverage/cover_reg_top/7.uart_intr_test.3621390340 Jun 29 05:34:55 PM PDT 24 Jun 29 05:34:58 PM PDT 24 43512159 ps
T75 /workspace/coverage/cover_reg_top/17.uart_csr_rw.3461594164 Jun 29 05:34:51 PM PDT 24 Jun 29 05:34:54 PM PDT 24 108422775 ps
T123 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2536826381 Jun 29 05:34:49 PM PDT 24 Jun 29 05:34:52 PM PDT 24 266192210 ps
T1101 /workspace/coverage/cover_reg_top/11.uart_tl_errors.1883109778 Jun 29 05:34:48 PM PDT 24 Jun 29 05:34:51 PM PDT 24 53872359 ps
T1102 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2726308382 Jun 29 05:34:43 PM PDT 24 Jun 29 05:34:44 PM PDT 24 23895190 ps
T1103 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1808489519 Jun 29 05:34:43 PM PDT 24 Jun 29 05:34:45 PM PDT 24 19184475 ps
T1104 /workspace/coverage/cover_reg_top/0.uart_intr_test.1330236371 Jun 29 05:34:28 PM PDT 24 Jun 29 05:34:30 PM PDT 24 23961043 ps
T1105 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3008512812 Jun 29 05:34:40 PM PDT 24 Jun 29 05:34:41 PM PDT 24 34266311 ps
T1106 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3493518752 Jun 29 05:34:45 PM PDT 24 Jun 29 05:34:47 PM PDT 24 58727324 ps
T66 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1007545233 Jun 29 05:34:29 PM PDT 24 Jun 29 05:34:31 PM PDT 24 30454187 ps
T1107 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1145706533 Jun 29 05:34:37 PM PDT 24 Jun 29 05:34:39 PM PDT 24 134354091 ps
T76 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.826402152 Jun 29 05:34:54 PM PDT 24 Jun 29 05:34:57 PM PDT 24 32280446 ps
T1108 /workspace/coverage/cover_reg_top/45.uart_intr_test.3082590874 Jun 29 05:35:03 PM PDT 24 Jun 29 05:35:05 PM PDT 24 56177765 ps
T77 /workspace/coverage/cover_reg_top/10.uart_csr_rw.82602616 Jun 29 05:34:45 PM PDT 24 Jun 29 05:34:46 PM PDT 24 26918771 ps
T78 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1977332738 Jun 29 05:34:51 PM PDT 24 Jun 29 05:34:54 PM PDT 24 15256793 ps
T1109 /workspace/coverage/cover_reg_top/37.uart_intr_test.3082370134 Jun 29 05:34:56 PM PDT 24 Jun 29 05:34:58 PM PDT 24 14614020 ps
T79 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.306606760 Jun 29 05:34:37 PM PDT 24 Jun 29 05:34:39 PM PDT 24 300073073 ps
T80 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2475355877 Jun 29 05:34:51 PM PDT 24 Jun 29 05:34:54 PM PDT 24 53641039 ps
T1110 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2256317707 Jun 29 05:34:54 PM PDT 24 Jun 29 05:34:57 PM PDT 24 43842461 ps
T1111 /workspace/coverage/cover_reg_top/2.uart_tl_errors.2531572600 Jun 29 05:34:26 PM PDT 24 Jun 29 05:34:29 PM PDT 24 210125473 ps
T1112 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.7729654 Jun 29 05:34:51 PM PDT 24 Jun 29 05:34:55 PM PDT 24 31168442 ps
T1113 /workspace/coverage/cover_reg_top/18.uart_tl_errors.225834285 Jun 29 05:34:51 PM PDT 24 Jun 29 05:34:55 PM PDT 24 105743765 ps
T1114 /workspace/coverage/cover_reg_top/2.uart_intr_test.3257246451 Jun 29 05:34:33 PM PDT 24 Jun 29 05:34:35 PM PDT 24 12580967 ps
T81 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.4264895876 Jun 29 05:34:34 PM PDT 24 Jun 29 05:34:36 PM PDT 24 176156572 ps
T82 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3049519033 Jun 29 05:34:51 PM PDT 24 Jun 29 05:34:54 PM PDT 24 35596093 ps
T1115 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1509182333 Jun 29 05:35:01 PM PDT 24 Jun 29 05:35:04 PM PDT 24 358041748 ps
T83 /workspace/coverage/cover_reg_top/11.uart_csr_rw.2786288416 Jun 29 05:34:41 PM PDT 24 Jun 29 05:34:42 PM PDT 24 40584019 ps
T1116 /workspace/coverage/cover_reg_top/13.uart_csr_rw.4022428634 Jun 29 05:34:42 PM PDT 24 Jun 29 05:34:43 PM PDT 24 52272643 ps
T1117 /workspace/coverage/cover_reg_top/24.uart_intr_test.1486676624 Jun 29 05:34:51 PM PDT 24 Jun 29 05:34:54 PM PDT 24 13080372 ps
T1118 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.99100792 Jun 29 05:34:28 PM PDT 24 Jun 29 05:34:31 PM PDT 24 342817484 ps
T1119 /workspace/coverage/cover_reg_top/0.uart_csr_rw.266728302 Jun 29 05:34:34 PM PDT 24 Jun 29 05:34:36 PM PDT 24 12359014 ps
T1120 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4068213142 Jun 29 05:34:32 PM PDT 24 Jun 29 05:34:34 PM PDT 24 1029820378 ps
T1121 /workspace/coverage/cover_reg_top/39.uart_intr_test.2149174298 Jun 29 05:34:48 PM PDT 24 Jun 29 05:34:50 PM PDT 24 44401237 ps
T1122 /workspace/coverage/cover_reg_top/47.uart_intr_test.3785465581 Jun 29 05:34:56 PM PDT 24 Jun 29 05:34:58 PM PDT 24 43271848 ps
T1123 /workspace/coverage/cover_reg_top/16.uart_intr_test.210676718 Jun 29 05:34:49 PM PDT 24 Jun 29 05:34:52 PM PDT 24 77013554 ps
T124 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3208392869 Jun 29 05:34:37 PM PDT 24 Jun 29 05:34:39 PM PDT 24 143133047 ps
T1124 /workspace/coverage/cover_reg_top/14.uart_csr_rw.2320150698 Jun 29 05:34:50 PM PDT 24 Jun 29 05:34:53 PM PDT 24 17851913 ps
T1125 /workspace/coverage/cover_reg_top/3.uart_intr_test.544898348 Jun 29 05:34:34 PM PDT 24 Jun 29 05:34:36 PM PDT 24 14466616 ps
T88 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.4092319092 Jun 29 05:34:52 PM PDT 24 Jun 29 05:34:55 PM PDT 24 181530757 ps
T1126 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.119494948 Jun 29 05:34:53 PM PDT 24 Jun 29 05:34:55 PM PDT 24 23789254 ps
T1127 /workspace/coverage/cover_reg_top/43.uart_intr_test.3338598748 Jun 29 05:34:53 PM PDT 24 Jun 29 05:34:55 PM PDT 24 11349475 ps
T92 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.730788467 Jun 29 05:34:37 PM PDT 24 Jun 29 05:34:39 PM PDT 24 151442039 ps
T1128 /workspace/coverage/cover_reg_top/26.uart_intr_test.3692611708 Jun 29 05:35:04 PM PDT 24 Jun 29 05:35:05 PM PDT 24 11814338 ps
T67 /workspace/coverage/cover_reg_top/9.uart_csr_rw.1488682918 Jun 29 05:34:42 PM PDT 24 Jun 29 05:34:43 PM PDT 24 40424612 ps
T68 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.402329442 Jun 29 05:34:35 PM PDT 24 Jun 29 05:34:37 PM PDT 24 27850857 ps
T1129 /workspace/coverage/cover_reg_top/19.uart_intr_test.619345562 Jun 29 05:34:52 PM PDT 24 Jun 29 05:34:55 PM PDT 24 13454044 ps
T1130 /workspace/coverage/cover_reg_top/5.uart_csr_rw.1298329120 Jun 29 05:34:55 PM PDT 24 Jun 29 05:34:57 PM PDT 24 33249932 ps
T89 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2281173977 Jun 29 05:34:36 PM PDT 24 Jun 29 05:34:39 PM PDT 24 220011553 ps
T1131 /workspace/coverage/cover_reg_top/7.uart_tl_errors.2114004206 Jun 29 05:34:40 PM PDT 24 Jun 29 05:34:41 PM PDT 24 145648482 ps
T1132 /workspace/coverage/cover_reg_top/22.uart_intr_test.1946060792 Jun 29 05:35:00 PM PDT 24 Jun 29 05:35:01 PM PDT 24 79374094 ps
T1133 /workspace/coverage/cover_reg_top/20.uart_intr_test.3652248387 Jun 29 05:34:55 PM PDT 24 Jun 29 05:34:57 PM PDT 24 39485479 ps
T1134 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1267022511 Jun 29 05:34:34 PM PDT 24 Jun 29 05:34:36 PM PDT 24 28701485 ps
T1135 /workspace/coverage/cover_reg_top/1.uart_csr_rw.3008652236 Jun 29 05:34:28 PM PDT 24 Jun 29 05:34:29 PM PDT 24 14190630 ps
T1136 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3618997635 Jun 29 05:34:49 PM PDT 24 Jun 29 05:34:51 PM PDT 24 212708812 ps
T1137 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1130614208 Jun 29 05:34:49 PM PDT 24 Jun 29 05:34:52 PM PDT 24 66782180 ps
T1138 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1140630233 Jun 29 05:34:41 PM PDT 24 Jun 29 05:34:43 PM PDT 24 16361029 ps
T1139 /workspace/coverage/cover_reg_top/21.uart_intr_test.44178113 Jun 29 05:34:54 PM PDT 24 Jun 29 05:34:57 PM PDT 24 14332761 ps
T1140 /workspace/coverage/cover_reg_top/48.uart_intr_test.1938211577 Jun 29 05:35:01 PM PDT 24 Jun 29 05:35:02 PM PDT 24 15019725 ps
T1141 /workspace/coverage/cover_reg_top/35.uart_intr_test.1850149843 Jun 29 05:34:54 PM PDT 24 Jun 29 05:34:57 PM PDT 24 50023984 ps
T1142 /workspace/coverage/cover_reg_top/12.uart_intr_test.1701608963 Jun 29 05:34:48 PM PDT 24 Jun 29 05:34:50 PM PDT 24 123461904 ps
T1143 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1520930789 Jun 29 05:34:49 PM PDT 24 Jun 29 05:34:52 PM PDT 24 323861288 ps
T1144 /workspace/coverage/cover_reg_top/13.uart_tl_errors.319915362 Jun 29 05:34:45 PM PDT 24 Jun 29 05:34:47 PM PDT 24 221971563 ps
T1145 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2613702341 Jun 29 05:34:55 PM PDT 24 Jun 29 05:34:58 PM PDT 24 110343097 ps
T1146 /workspace/coverage/cover_reg_top/23.uart_intr_test.2971197228 Jun 29 05:34:55 PM PDT 24 Jun 29 05:34:57 PM PDT 24 55365596 ps
T1147 /workspace/coverage/cover_reg_top/28.uart_intr_test.4264969381 Jun 29 05:35:03 PM PDT 24 Jun 29 05:35:05 PM PDT 24 45717328 ps
T1148 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2663768659 Jun 29 05:34:51 PM PDT 24 Jun 29 05:34:54 PM PDT 24 30522671 ps
T1149 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3335059308 Jun 29 05:34:50 PM PDT 24 Jun 29 05:34:54 PM PDT 24 66686919 ps
T1150 /workspace/coverage/cover_reg_top/4.uart_intr_test.875930316 Jun 29 05:34:40 PM PDT 24 Jun 29 05:34:41 PM PDT 24 52584387 ps
T1151 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3251564373 Jun 29 05:34:47 PM PDT 24 Jun 29 05:34:49 PM PDT 24 34184967 ps
T1152 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.4253096424 Jun 29 05:34:37 PM PDT 24 Jun 29 05:34:38 PM PDT 24 59659807 ps
T1153 /workspace/coverage/cover_reg_top/1.uart_intr_test.3444287781 Jun 29 05:34:51 PM PDT 24 Jun 29 05:34:54 PM PDT 24 19142850 ps
T1154 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3745450972 Jun 29 05:34:44 PM PDT 24 Jun 29 05:34:45 PM PDT 24 54521607 ps
T1155 /workspace/coverage/cover_reg_top/5.uart_tl_errors.391331872 Jun 29 05:34:44 PM PDT 24 Jun 29 05:34:46 PM PDT 24 317559231 ps
T125 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.4200101900 Jun 29 05:34:55 PM PDT 24 Jun 29 05:34:58 PM PDT 24 46907747 ps
T1156 /workspace/coverage/cover_reg_top/41.uart_intr_test.1347863088 Jun 29 05:34:51 PM PDT 24 Jun 29 05:34:54 PM PDT 24 23004369 ps
T1157 /workspace/coverage/cover_reg_top/0.uart_tl_errors.3478698018 Jun 29 05:34:28 PM PDT 24 Jun 29 05:34:31 PM PDT 24 77875332 ps
T1158 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2102850577 Jun 29 05:34:48 PM PDT 24 Jun 29 05:34:51 PM PDT 24 20007320 ps
T1159 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1498439031 Jun 29 05:34:47 PM PDT 24 Jun 29 05:34:49 PM PDT 24 23790989 ps
T1160 /workspace/coverage/cover_reg_top/12.uart_csr_rw.4135376435 Jun 29 05:34:48 PM PDT 24 Jun 29 05:34:50 PM PDT 24 34561651 ps
T71 /workspace/coverage/cover_reg_top/6.uart_csr_rw.589303088 Jun 29 05:34:34 PM PDT 24 Jun 29 05:34:36 PM PDT 24 27102412 ps
T126 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2929069628 Jun 29 05:34:38 PM PDT 24 Jun 29 05:34:40 PM PDT 24 219713722 ps
T1161 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1523680559 Jun 29 05:34:46 PM PDT 24 Jun 29 05:34:48 PM PDT 24 97853065 ps
T1162 /workspace/coverage/cover_reg_top/4.uart_tl_errors.1484835442 Jun 29 05:34:33 PM PDT 24 Jun 29 05:34:36 PM PDT 24 215034117 ps
T1163 /workspace/coverage/cover_reg_top/33.uart_intr_test.838265159 Jun 29 05:34:56 PM PDT 24 Jun 29 05:34:58 PM PDT 24 24984027 ps
T1164 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.604275907 Jun 29 05:34:52 PM PDT 24 Jun 29 05:34:54 PM PDT 24 21768869 ps
T90 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2496972453 Jun 29 05:35:05 PM PDT 24 Jun 29 05:35:06 PM PDT 24 81322110 ps
T1165 /workspace/coverage/cover_reg_top/31.uart_intr_test.1736935924 Jun 29 05:34:48 PM PDT 24 Jun 29 05:34:50 PM PDT 24 114541078 ps
T72 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3063159270 Jun 29 05:34:33 PM PDT 24 Jun 29 05:34:35 PM PDT 24 66987265 ps
T1166 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.672141540 Jun 29 05:34:49 PM PDT 24 Jun 29 05:34:53 PM PDT 24 70893878 ps
T1167 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.145060133 Jun 29 05:34:40 PM PDT 24 Jun 29 05:34:42 PM PDT 24 273220770 ps
T1168 /workspace/coverage/cover_reg_top/17.uart_tl_errors.4087455601 Jun 29 05:34:56 PM PDT 24 Jun 29 05:34:59 PM PDT 24 24963953 ps
T1169 /workspace/coverage/cover_reg_top/46.uart_intr_test.511096631 Jun 29 05:34:54 PM PDT 24 Jun 29 05:34:56 PM PDT 24 59539324 ps
T1170 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.567062378 Jun 29 05:34:53 PM PDT 24 Jun 29 05:34:56 PM PDT 24 33266940 ps
T69 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1121977100 Jun 29 05:34:47 PM PDT 24 Jun 29 05:34:50 PM PDT 24 36482076 ps
T1171 /workspace/coverage/cover_reg_top/17.uart_intr_test.1809147070 Jun 29 05:34:50 PM PDT 24 Jun 29 05:34:53 PM PDT 24 21527506 ps
T1172 /workspace/coverage/cover_reg_top/7.uart_csr_rw.3842840921 Jun 29 05:34:35 PM PDT 24 Jun 29 05:34:37 PM PDT 24 34466014 ps
T1173 /workspace/coverage/cover_reg_top/36.uart_intr_test.2507663902 Jun 29 05:34:53 PM PDT 24 Jun 29 05:34:56 PM PDT 24 36950661 ps
T1174 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.341830555 Jun 29 05:34:48 PM PDT 24 Jun 29 05:34:51 PM PDT 24 79333814 ps
T1175 /workspace/coverage/cover_reg_top/3.uart_tl_errors.1622965152 Jun 29 05:34:42 PM PDT 24 Jun 29 05:34:45 PM PDT 24 30222411 ps
T1176 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.36737361 Jun 29 05:34:38 PM PDT 24 Jun 29 05:34:39 PM PDT 24 19013758 ps
T1177 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2327938197 Jun 29 05:34:43 PM PDT 24 Jun 29 05:34:45 PM PDT 24 174299454 ps
T1178 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.744793383 Jun 29 05:34:49 PM PDT 24 Jun 29 05:34:51 PM PDT 24 85291767 ps
T1179 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1179735564 Jun 29 05:34:33 PM PDT 24 Jun 29 05:34:35 PM PDT 24 83475966 ps
T1180 /workspace/coverage/cover_reg_top/1.uart_tl_errors.2733995770 Jun 29 05:34:35 PM PDT 24 Jun 29 05:34:38 PM PDT 24 121149181 ps
T1181 /workspace/coverage/cover_reg_top/16.uart_tl_errors.4273797823 Jun 29 05:34:54 PM PDT 24 Jun 29 05:34:58 PM PDT 24 125625036 ps
T1182 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.680983464 Jun 29 05:34:35 PM PDT 24 Jun 29 05:34:37 PM PDT 24 80168260 ps
T1183 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3143572805 Jun 29 05:34:48 PM PDT 24 Jun 29 05:34:50 PM PDT 24 136673015 ps
T1184 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2040047908 Jun 29 05:34:52 PM PDT 24 Jun 29 05:34:55 PM PDT 24 31734934 ps
T1185 /workspace/coverage/cover_reg_top/2.uart_csr_rw.2013572397 Jun 29 05:34:33 PM PDT 24 Jun 29 05:34:35 PM PDT 24 31714575 ps
T1186 /workspace/coverage/cover_reg_top/12.uart_tl_errors.924756924 Jun 29 05:34:44 PM PDT 24 Jun 29 05:34:47 PM PDT 24 160129907 ps
T1187 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.973433951 Jun 29 05:34:50 PM PDT 24 Jun 29 05:34:53 PM PDT 24 16230701 ps
T1188 /workspace/coverage/cover_reg_top/10.uart_intr_test.2363488993 Jun 29 05:34:51 PM PDT 24 Jun 29 05:34:54 PM PDT 24 41680756 ps
T1189 /workspace/coverage/cover_reg_top/8.uart_csr_rw.2012130732 Jun 29 05:34:35 PM PDT 24 Jun 29 05:34:37 PM PDT 24 14026091 ps
T1190 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2588116202 Jun 29 05:34:43 PM PDT 24 Jun 29 05:34:45 PM PDT 24 23023670 ps
T1191 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2063253696 Jun 29 05:34:47 PM PDT 24 Jun 29 05:34:49 PM PDT 24 16565470 ps
T1192 /workspace/coverage/cover_reg_top/38.uart_intr_test.1699875063 Jun 29 05:34:52 PM PDT 24 Jun 29 05:34:55 PM PDT 24 77352887 ps
T1193 /workspace/coverage/cover_reg_top/16.uart_csr_rw.3942825772 Jun 29 05:34:53 PM PDT 24 Jun 29 05:34:55 PM PDT 24 39236091 ps
T1194 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2259040799 Jun 29 05:34:30 PM PDT 24 Jun 29 05:34:32 PM PDT 24 13645638 ps
T1195 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3606773609 Jun 29 05:34:47 PM PDT 24 Jun 29 05:34:49 PM PDT 24 36543900 ps
T1196 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3824986187 Jun 29 05:34:50 PM PDT 24 Jun 29 05:34:53 PM PDT 24 181449908 ps
T1197 /workspace/coverage/cover_reg_top/9.uart_intr_test.3621144469 Jun 29 05:34:46 PM PDT 24 Jun 29 05:34:48 PM PDT 24 21996438 ps
T1198 /workspace/coverage/cover_reg_top/15.uart_csr_rw.4008020022 Jun 29 05:34:54 PM PDT 24 Jun 29 05:34:56 PM PDT 24 13364323 ps
T1199 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2324690746 Jun 29 05:34:47 PM PDT 24 Jun 29 05:34:50 PM PDT 24 42946710 ps
T1200 /workspace/coverage/cover_reg_top/19.uart_tl_errors.2895746379 Jun 29 05:34:49 PM PDT 24 Jun 29 05:34:52 PM PDT 24 75344891 ps
T1201 /workspace/coverage/cover_reg_top/6.uart_intr_test.4076068512 Jun 29 05:34:48 PM PDT 24 Jun 29 05:34:50 PM PDT 24 16032996 ps
T1202 /workspace/coverage/cover_reg_top/29.uart_intr_test.3603273871 Jun 29 05:34:55 PM PDT 24 Jun 29 05:34:58 PM PDT 24 52773632 ps
T1203 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1210310762 Jun 29 05:34:37 PM PDT 24 Jun 29 05:34:39 PM PDT 24 865705768 ps
T1204 /workspace/coverage/cover_reg_top/49.uart_intr_test.241574518 Jun 29 05:35:03 PM PDT 24 Jun 29 05:35:05 PM PDT 24 21589025 ps
T1205 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.819853807 Jun 29 05:34:41 PM PDT 24 Jun 29 05:34:42 PM PDT 24 50773991 ps
T1206 /workspace/coverage/cover_reg_top/18.uart_csr_rw.2573271214 Jun 29 05:34:54 PM PDT 24 Jun 29 05:34:57 PM PDT 24 36412518 ps
T1207 /workspace/coverage/cover_reg_top/15.uart_intr_test.2404649501 Jun 29 05:34:50 PM PDT 24 Jun 29 05:34:54 PM PDT 24 27656337 ps
T1208 /workspace/coverage/cover_reg_top/8.uart_intr_test.1348318398 Jun 29 05:34:50 PM PDT 24 Jun 29 05:34:53 PM PDT 24 34843799 ps
T1209 /workspace/coverage/cover_reg_top/11.uart_intr_test.3039943843 Jun 29 05:34:50 PM PDT 24 Jun 29 05:34:53 PM PDT 24 15704958 ps
T1210 /workspace/coverage/cover_reg_top/14.uart_tl_errors.855837819 Jun 29 05:34:52 PM PDT 24 Jun 29 05:34:55 PM PDT 24 139665435 ps
T1211 /workspace/coverage/cover_reg_top/5.uart_intr_test.1803958828 Jun 29 05:34:46 PM PDT 24 Jun 29 05:34:48 PM PDT 24 200067675 ps
T1212 /workspace/coverage/cover_reg_top/27.uart_intr_test.2825613973 Jun 29 05:34:50 PM PDT 24 Jun 29 05:34:53 PM PDT 24 30920934 ps
T1213 /workspace/coverage/cover_reg_top/14.uart_intr_test.2624665215 Jun 29 05:34:53 PM PDT 24 Jun 29 05:34:56 PM PDT 24 15165628 ps
T1214 /workspace/coverage/cover_reg_top/9.uart_tl_errors.1886855760 Jun 29 05:34:45 PM PDT 24 Jun 29 05:34:47 PM PDT 24 143609521 ps
T73 /workspace/coverage/cover_reg_top/3.uart_csr_rw.1535325317 Jun 29 05:34:33 PM PDT 24 Jun 29 05:34:35 PM PDT 24 34442400 ps
T1215 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1595832636 Jun 29 05:34:50 PM PDT 24 Jun 29 05:34:54 PM PDT 24 314825579 ps
T1216 /workspace/coverage/cover_reg_top/25.uart_intr_test.1914741608 Jun 29 05:34:49 PM PDT 24 Jun 29 05:34:51 PM PDT 24 243666096 ps
T1217 /workspace/coverage/cover_reg_top/19.uart_csr_rw.3243469007 Jun 29 05:34:55 PM PDT 24 Jun 29 05:34:57 PM PDT 24 75992672 ps
T1218 /workspace/coverage/cover_reg_top/6.uart_tl_errors.3225658201 Jun 29 05:34:44 PM PDT 24 Jun 29 05:34:47 PM PDT 24 212237815 ps
T1219 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1121659114 Jun 29 05:34:44 PM PDT 24 Jun 29 05:34:46 PM PDT 24 61937969 ps
T1220 /workspace/coverage/cover_reg_top/34.uart_intr_test.2576149548 Jun 29 05:34:54 PM PDT 24 Jun 29 05:34:56 PM PDT 24 13193030 ps
T1221 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2962226939 Jun 29 05:34:35 PM PDT 24 Jun 29 05:34:37 PM PDT 24 151645200 ps
T1222 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1367238616 Jun 29 05:34:50 PM PDT 24 Jun 29 05:34:53 PM PDT 24 27838758 ps
T1223 /workspace/coverage/cover_reg_top/8.uart_tl_errors.2391111216 Jun 29 05:34:41 PM PDT 24 Jun 29 05:34:45 PM PDT 24 182851680 ps
T91 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.438933903 Jun 29 05:34:45 PM PDT 24 Jun 29 05:34:47 PM PDT 24 419347140 ps
T1224 /workspace/coverage/cover_reg_top/18.uart_intr_test.3114318878 Jun 29 05:34:54 PM PDT 24 Jun 29 05:34:56 PM PDT 24 46987265 ps
T70 /workspace/coverage/cover_reg_top/4.uart_csr_rw.2854430711 Jun 29 05:34:32 PM PDT 24 Jun 29 05:34:33 PM PDT 24 14768980 ps
T1225 /workspace/coverage/cover_reg_top/15.uart_tl_errors.2463186486 Jun 29 05:35:03 PM PDT 24 Jun 29 05:35:06 PM PDT 24 43045053 ps
T1226 /workspace/coverage/cover_reg_top/13.uart_intr_test.3362467519 Jun 29 05:34:41 PM PDT 24 Jun 29 05:34:42 PM PDT 24 13855413 ps
T1227 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3891944331 Jun 29 05:34:39 PM PDT 24 Jun 29 05:34:40 PM PDT 24 24434891 ps
T1228 /workspace/coverage/cover_reg_top/42.uart_intr_test.457026918 Jun 29 05:35:05 PM PDT 24 Jun 29 05:35:06 PM PDT 24 18328366 ps
T1229 /workspace/coverage/cover_reg_top/30.uart_intr_test.1387350330 Jun 29 05:34:49 PM PDT 24 Jun 29 05:34:51 PM PDT 24 14460555 ps
T1230 /workspace/coverage/cover_reg_top/10.uart_tl_errors.2341883590 Jun 29 05:34:50 PM PDT 24 Jun 29 05:34:55 PM PDT 24 143094429 ps
T1231 /workspace/coverage/cover_reg_top/44.uart_intr_test.2140697048 Jun 29 05:34:58 PM PDT 24 Jun 29 05:34:59 PM PDT 24 16305908 ps
T1232 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2753340598 Jun 29 05:34:38 PM PDT 24 Jun 29 05:34:39 PM PDT 24 29859221 ps

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.1406734957
Short name T5
Test name
Test status
Simulation time 118033457259 ps
CPU time 787.57 seconds
Started Jun 29 04:48:25 PM PDT 24
Finished Jun 29 05:01:34 PM PDT 24
Peak memory 199912 kb
Host smart-eeb013db-7b10-4654-aef9-2b8d2f343c75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1406734957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1406734957
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.851937003
Short name T29
Test name
Test status
Simulation time 228058479728 ps
CPU time 544.07 seconds
Started Jun 29 04:48:23 PM PDT 24
Finished Jun 29 04:57:28 PM PDT 24
Peak memory 216556 kb
Host smart-3966d8a4-c5cd-47af-8872-28a822a849bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851937003 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.851937003
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.203823817
Short name T104
Test name
Test status
Simulation time 702221113152 ps
CPU time 509.22 seconds
Started Jun 29 04:50:45 PM PDT 24
Finished Jun 29 04:59:15 PM PDT 24
Peak memory 216516 kb
Host smart-a40bdf64-28c6-4fdb-b569-68a7569871ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203823817 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.203823817
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.1488320820
Short name T12
Test name
Test status
Simulation time 111613310083 ps
CPU time 336.71 seconds
Started Jun 29 04:50:44 PM PDT 24
Finished Jun 29 04:56:21 PM PDT 24
Peak memory 216492 kb
Host smart-371dd4d0-3f03-440f-9bf0-2b43cce8414c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488320820 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.1488320820
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all.807395118
Short name T54
Test name
Test status
Simulation time 302993986962 ps
CPU time 513.8 seconds
Started Jun 29 04:48:16 PM PDT 24
Finished Jun 29 04:56:51 PM PDT 24
Peak memory 200116 kb
Host smart-8e542a8c-84e6-4044-b6a4-8efd67006b5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807395118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.807395118
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_intr.2599788198
Short name T11
Test name
Test status
Simulation time 104652574892 ps
CPU time 211.21 seconds
Started Jun 29 04:48:56 PM PDT 24
Finished Jun 29 04:52:28 PM PDT 24
Peak memory 199920 kb
Host smart-84f749e1-17fa-41f6-9c1a-148a7ada1c76
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599788198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.2599788198
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.1421361428
Short name T30
Test name
Test status
Simulation time 90253756708 ps
CPU time 646.05 seconds
Started Jun 29 04:49:40 PM PDT 24
Finished Jun 29 05:00:27 PM PDT 24
Peak memory 215124 kb
Host smart-8cf9b101-855d-4999-80ff-3d2359dd12e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421361428 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1421361428
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.1631018488
Short name T32
Test name
Test status
Simulation time 83560196821 ps
CPU time 1138.39 seconds
Started Jun 29 04:50:42 PM PDT 24
Finished Jun 29 05:09:41 PM PDT 24
Peak memory 227452 kb
Host smart-19ac14d7-c3e5-4ca0-97fa-f3f37a75869c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631018488 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.1631018488
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_fifo_full.2357118100
Short name T130
Test name
Test status
Simulation time 224452381990 ps
CPU time 638.92 seconds
Started Jun 29 04:49:29 PM PDT 24
Finished Jun 29 05:00:09 PM PDT 24
Peak memory 199848 kb
Host smart-81047b36-5eed-4426-8750-c87399d7db34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357118100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2357118100
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_alert_test.1682224230
Short name T24
Test name
Test status
Simulation time 36504688 ps
CPU time 0.57 seconds
Started Jun 29 04:48:26 PM PDT 24
Finished Jun 29 04:48:27 PM PDT 24
Peak memory 194252 kb
Host smart-8fa615dd-fbee-402b-a1aa-44a1e6a3f5dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682224230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.1682224230
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_sec_cm.892366737
Short name T28
Test name
Test status
Simulation time 395118362 ps
CPU time 0.89 seconds
Started Jun 29 04:48:01 PM PDT 24
Finished Jun 29 04:48:03 PM PDT 24
Peak memory 218268 kb
Host smart-1deb6302-cfde-45ac-a4ae-fc9ffb05c6cc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892366737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.892366737
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.3059238769
Short name T17
Test name
Test status
Simulation time 92334855376 ps
CPU time 180.85 seconds
Started Jun 29 04:50:31 PM PDT 24
Finished Jun 29 04:53:32 PM PDT 24
Peak memory 216488 kb
Host smart-db006e48-ad9a-4676-9d75-cdeab860aa72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059238769 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.3059238769
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.2080893401
Short name T58
Test name
Test status
Simulation time 134207796189 ps
CPU time 79.78 seconds
Started Jun 29 04:51:30 PM PDT 24
Finished Jun 29 04:52:50 PM PDT 24
Peak memory 199928 kb
Host smart-6a8af60e-6d7b-48d0-8c40-7c9410551b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080893401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2080893401
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.895991411
Short name T47
Test name
Test status
Simulation time 117026076096 ps
CPU time 204.4 seconds
Started Jun 29 04:49:56 PM PDT 24
Finished Jun 29 04:53:20 PM PDT 24
Peak memory 199948 kb
Host smart-6ec7453f-bb7a-4acc-b75a-f67caf87be3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895991411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.895991411
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.463915759
Short name T144
Test name
Test status
Simulation time 88137750026 ps
CPU time 204.7 seconds
Started Jun 29 04:50:42 PM PDT 24
Finished Jun 29 04:54:08 PM PDT 24
Peak memory 199908 kb
Host smart-e1d15b5c-4fe5-4ead-9244-e2c4d73b6499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463915759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.463915759
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1704995730
Short name T140
Test name
Test status
Simulation time 206138437074 ps
CPU time 223.05 seconds
Started Jun 29 04:50:21 PM PDT 24
Finished Jun 29 04:54:04 PM PDT 24
Peak memory 200012 kb
Host smart-e59b1511-a0f4-4013-b4fe-be7b5f1526ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704995730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1704995730
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2160192926
Short name T133
Test name
Test status
Simulation time 114983024793 ps
CPU time 173.91 seconds
Started Jun 29 04:49:28 PM PDT 24
Finished Jun 29 04:52:23 PM PDT 24
Peak memory 199932 kb
Host smart-aa6c57d4-7acc-4dcb-a944-5cae35166ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160192926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2160192926
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3259358811
Short name T87
Test name
Test status
Simulation time 1251925576 ps
CPU time 1.33 seconds
Started Jun 29 05:34:54 PM PDT 24
Finished Jun 29 05:34:57 PM PDT 24
Peak memory 199880 kb
Host smart-2d5d6539-bcec-4c24-b355-cbf4e17c7ddb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259358811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3259358811
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.1932448446
Short name T121
Test name
Test status
Simulation time 91521446585 ps
CPU time 1357.26 seconds
Started Jun 29 04:50:31 PM PDT 24
Finished Jun 29 05:13:09 PM PDT 24
Peak memory 224692 kb
Host smart-3ed957e0-c736-4db1-bbc8-ea7692d15cdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932448446 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.1932448446
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_stress_all.212916403
Short name T318
Test name
Test status
Simulation time 310885610796 ps
CPU time 140.93 seconds
Started Jun 29 04:48:39 PM PDT 24
Finished Jun 29 04:51:01 PM PDT 24
Peak memory 199896 kb
Host smart-e97c7b9a-bcf1-4896-8e4a-2316a8b02702
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212916403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.212916403
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.3642757654
Short name T299
Test name
Test status
Simulation time 107467895708 ps
CPU time 163.23 seconds
Started Jun 29 04:48:03 PM PDT 24
Finished Jun 29 04:50:48 PM PDT 24
Peak memory 199988 kb
Host smart-3a70e801-f4e9-45ed-9461-263098ba6e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642757654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3642757654
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_stress_all.96010662
Short name T154
Test name
Test status
Simulation time 285768872082 ps
CPU time 999.05 seconds
Started Jun 29 04:48:56 PM PDT 24
Finished Jun 29 05:05:37 PM PDT 24
Peak memory 199916 kb
Host smart-aa0ece67-d5d4-4f71-8fac-1d31409bf141
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96010662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.96010662
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.2491178011
Short name T160
Test name
Test status
Simulation time 234489637120 ps
CPU time 105.67 seconds
Started Jun 29 04:49:03 PM PDT 24
Finished Jun 29 04:50:49 PM PDT 24
Peak memory 199808 kb
Host smart-35306dda-6cc2-4fdb-afbb-b011a3cb0960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491178011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2491178011
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.3657964743
Short name T43
Test name
Test status
Simulation time 61041746646 ps
CPU time 101.95 seconds
Started Jun 29 04:50:29 PM PDT 24
Finished Jun 29 04:52:12 PM PDT 24
Peak memory 199896 kb
Host smart-85acdadf-c94e-4ad1-bdbf-343c6afa24a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657964743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3657964743
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_stress_all.3767201046
Short name T151
Test name
Test status
Simulation time 278470191247 ps
CPU time 434.42 seconds
Started Jun 29 04:50:22 PM PDT 24
Finished Jun 29 04:57:37 PM PDT 24
Peak memory 199952 kb
Host smart-e0501143-84da-4e14-9be4-27ef300df5d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767201046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3767201046
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1007545233
Short name T66
Test name
Test status
Simulation time 30454187 ps
CPU time 0.79 seconds
Started Jun 29 05:34:29 PM PDT 24
Finished Jun 29 05:34:31 PM PDT 24
Peak memory 196872 kb
Host smart-f52ac5d2-f7d8-439e-8200-7cb4b1b17f24
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007545233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1007545233
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.82602616
Short name T77
Test name
Test status
Simulation time 26918771 ps
CPU time 0.6 seconds
Started Jun 29 05:34:45 PM PDT 24
Finished Jun 29 05:34:46 PM PDT 24
Peak memory 195900 kb
Host smart-c619faa0-b74a-4099-80ff-4ac857b3005a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82602616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.82602616
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.2552508058
Short name T495
Test name
Test status
Simulation time 116445298289 ps
CPU time 792.21 seconds
Started Jun 29 04:48:00 PM PDT 24
Finished Jun 29 05:01:13 PM PDT 24
Peak memory 216332 kb
Host smart-8064178a-d95f-4f89-94e9-095fa9070ecf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552508058 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.2552508058
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.4203809560
Short name T84
Test name
Test status
Simulation time 23038360403 ps
CPU time 18.83 seconds
Started Jun 29 04:51:53 PM PDT 24
Finished Jun 29 04:52:12 PM PDT 24
Peak memory 199904 kb
Host smart-a3b724f7-9dc1-4d7a-803d-e3020a2c7b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203809560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.4203809560
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.2306984539
Short name T7
Test name
Test status
Simulation time 27407848009 ps
CPU time 23.4 seconds
Started Jun 29 04:51:06 PM PDT 24
Finished Jun 29 04:51:30 PM PDT 24
Peak memory 199720 kb
Host smart-cd0812c4-811b-447b-9ee9-ed3395c46878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306984539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2306984539
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.3131946468
Short name T272
Test name
Test status
Simulation time 137422827514 ps
CPU time 86.94 seconds
Started Jun 29 04:49:37 PM PDT 24
Finished Jun 29 04:51:04 PM PDT 24
Peak memory 199852 kb
Host smart-70d2c817-b6c1-4ff9-b6d4-761350570513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131946468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3131946468
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2177981188
Short name T274
Test name
Test status
Simulation time 118122035119 ps
CPU time 180.02 seconds
Started Jun 29 04:51:35 PM PDT 24
Finished Jun 29 04:54:36 PM PDT 24
Peak memory 199900 kb
Host smart-85c9c461-a1a3-4a24-9ff7-8b4fe806d250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177981188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2177981188
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.694597277
Short name T290
Test name
Test status
Simulation time 161185040479 ps
CPU time 64.59 seconds
Started Jun 29 04:48:16 PM PDT 24
Finished Jun 29 04:49:22 PM PDT 24
Peak memory 199892 kb
Host smart-84bfcdd8-9081-4b64-8c03-d02dfb0aacd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694597277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.694597277
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.508968460
Short name T52
Test name
Test status
Simulation time 67051178114 ps
CPU time 25.5 seconds
Started Jun 29 04:51:58 PM PDT 24
Finished Jun 29 04:52:24 PM PDT 24
Peak memory 199836 kb
Host smart-5b48afa7-1038-4741-a1cb-6bd95ce376db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508968460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.508968460
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.438933903
Short name T91
Test name
Test status
Simulation time 419347140 ps
CPU time 1.43 seconds
Started Jun 29 05:34:45 PM PDT 24
Finished Jun 29 05:34:47 PM PDT 24
Peak memory 199664 kb
Host smart-028d3703-9e6b-4edb-9401-9d6f71439ec2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438933903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.438933903
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.3552211866
Short name T328
Test name
Test status
Simulation time 327990656121 ps
CPU time 963.81 seconds
Started Jun 29 04:50:08 PM PDT 24
Finished Jun 29 05:06:12 PM PDT 24
Peak memory 224756 kb
Host smart-87d9343a-63c8-4890-a77d-0c4d29c60a76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552211866 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.3552211866
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.399844713
Short name T184
Test name
Test status
Simulation time 117514632690 ps
CPU time 19.76 seconds
Started Jun 29 04:50:31 PM PDT 24
Finished Jun 29 04:50:51 PM PDT 24
Peak memory 199956 kb
Host smart-f1fcee0e-ae3e-48bd-b6db-eb93c4922948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399844713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.399844713
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_stress_all.1520734964
Short name T158
Test name
Test status
Simulation time 174698937084 ps
CPU time 144.85 seconds
Started Jun 29 04:48:06 PM PDT 24
Finished Jun 29 04:50:31 PM PDT 24
Peak memory 199968 kb
Host smart-94cb28ba-fae9-42db-a6d4-9f93c3dc067c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520734964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1520734964
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2783852881
Short name T101
Test name
Test status
Simulation time 224652080701 ps
CPU time 432.05 seconds
Started Jun 29 04:50:41 PM PDT 24
Finished Jun 29 04:57:54 PM PDT 24
Peak memory 216400 kb
Host smart-3a1077e8-b8eb-4783-b60e-cb66ed401c17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783852881 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2783852881
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2496972453
Short name T90
Test name
Test status
Simulation time 81322110 ps
CPU time 0.97 seconds
Started Jun 29 05:35:05 PM PDT 24
Finished Jun 29 05:35:06 PM PDT 24
Peak memory 199528 kb
Host smart-cf6a0567-b876-41af-b3ce-d768b13ae04b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496972453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2496972453
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.1022430664
Short name T163
Test name
Test status
Simulation time 53833363178 ps
CPU time 26.5 seconds
Started Jun 29 04:48:09 PM PDT 24
Finished Jun 29 04:48:36 PM PDT 24
Peak memory 199904 kb
Host smart-15045211-9d0d-46f1-89fd-a81e89774a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022430664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.1022430664
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.2174660550
Short name T132
Test name
Test status
Simulation time 207777748342 ps
CPU time 50.59 seconds
Started Jun 29 04:50:57 PM PDT 24
Finished Jun 29 04:51:48 PM PDT 24
Peak memory 199816 kb
Host smart-a973ed63-27be-4614-a46b-801d7f78e533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174660550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2174660550
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_stress_all.4254598384
Short name T173
Test name
Test status
Simulation time 641892950101 ps
CPU time 217.78 seconds
Started Jun 29 04:49:52 PM PDT 24
Finished Jun 29 04:53:30 PM PDT 24
Peak memory 199972 kb
Host smart-005a2560-1b67-4bdc-bbc0-b136350915ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254598384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.4254598384
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.2792748513
Short name T119
Test name
Test status
Simulation time 33300782670 ps
CPU time 54.67 seconds
Started Jun 29 04:50:57 PM PDT 24
Finished Jun 29 04:51:52 PM PDT 24
Peak memory 199928 kb
Host smart-8ae94db5-50ca-463a-9662-66fa5239d88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792748513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2792748513
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_stress_all.622315207
Short name T171
Test name
Test status
Simulation time 132386030869 ps
CPU time 76.56 seconds
Started Jun 29 04:48:57 PM PDT 24
Finished Jun 29 04:50:14 PM PDT 24
Peak memory 199960 kb
Host smart-c5369214-c126-4f8f-a20d-0c431287b5f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622315207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.622315207
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3561024320
Short name T316
Test name
Test status
Simulation time 83368499399 ps
CPU time 55.03 seconds
Started Jun 29 04:50:42 PM PDT 24
Finished Jun 29 04:51:38 PM PDT 24
Peak memory 199988 kb
Host smart-ff4d3b4a-6929-41e1-9ce6-4ffbe766fe5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561024320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3561024320
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.1850097516
Short name T202
Test name
Test status
Simulation time 34899792735 ps
CPU time 28.44 seconds
Started Jun 29 04:50:45 PM PDT 24
Finished Jun 29 04:51:14 PM PDT 24
Peak memory 199928 kb
Host smart-76ab1cfb-2e83-4e4b-84a5-dfe9ccf931ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850097516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1850097516
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.1871310932
Short name T135
Test name
Test status
Simulation time 100679873783 ps
CPU time 293.44 seconds
Started Jun 29 04:48:12 PM PDT 24
Finished Jun 29 04:53:07 PM PDT 24
Peak memory 199860 kb
Host smart-2dee9a86-b659-4aec-812b-481aa8635383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871310932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1871310932
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.545028161
Short name T176
Test name
Test status
Simulation time 123469802889 ps
CPU time 46 seconds
Started Jun 29 04:51:15 PM PDT 24
Finished Jun 29 04:52:01 PM PDT 24
Peak memory 199988 kb
Host smart-836ff913-0b23-407e-8118-26f24c036d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545028161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.545028161
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.45304834
Short name T149
Test name
Test status
Simulation time 25255788202 ps
CPU time 59.93 seconds
Started Jun 29 04:48:33 PM PDT 24
Finished Jun 29 04:49:33 PM PDT 24
Peak memory 199988 kb
Host smart-a035c42f-1d0f-40c3-be40-37d92793bcd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45304834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.45304834
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.2646613328
Short name T231
Test name
Test status
Simulation time 36576785613 ps
CPU time 51.99 seconds
Started Jun 29 04:50:56 PM PDT 24
Finished Jun 29 04:51:48 PM PDT 24
Peak memory 199988 kb
Host smart-6578d2f9-0b55-48d0-8ec0-f9a1f5a7ed4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646613328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.2646613328
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.409824873
Short name T210
Test name
Test status
Simulation time 113668596705 ps
CPU time 46.82 seconds
Started Jun 29 04:50:56 PM PDT 24
Finished Jun 29 04:51:44 PM PDT 24
Peak memory 199924 kb
Host smart-911daa53-a34d-418b-a5cd-84f29cb620d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409824873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.409824873
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.3128073112
Short name T206
Test name
Test status
Simulation time 86970620704 ps
CPU time 43.48 seconds
Started Jun 29 04:50:58 PM PDT 24
Finished Jun 29 04:51:42 PM PDT 24
Peak memory 199964 kb
Host smart-cdf82a19-fc46-4d64-a4a1-e1cc5bcccb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128073112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.3128073112
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2311799748
Short name T628
Test name
Test status
Simulation time 142811305395 ps
CPU time 55.07 seconds
Started Jun 29 04:48:17 PM PDT 24
Finished Jun 29 04:49:13 PM PDT 24
Peak memory 199996 kb
Host smart-7772f876-2796-4c80-bbfc-6ef1f5582825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311799748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2311799748
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2398332070
Short name T155
Test name
Test status
Simulation time 102963320477 ps
CPU time 25.39 seconds
Started Jun 29 04:51:07 PM PDT 24
Finished Jun 29 04:51:33 PM PDT 24
Peak memory 199268 kb
Host smart-e41b4548-5e71-4941-8236-e77df3e10b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398332070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2398332070
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_stress_all.1725162170
Short name T282
Test name
Test status
Simulation time 162175551878 ps
CPU time 243.51 seconds
Started Jun 29 04:48:40 PM PDT 24
Finished Jun 29 04:52:44 PM PDT 24
Peak memory 199912 kb
Host smart-4e12ccd6-2b53-4e50-bc6b-16ccdf9369ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725162170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1725162170
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1586723437
Short name T220
Test name
Test status
Simulation time 164580106424 ps
CPU time 35.12 seconds
Started Jun 29 04:51:45 PM PDT 24
Finished Jun 29 04:52:21 PM PDT 24
Peak memory 199992 kb
Host smart-7bf52496-ee04-4bb8-95ff-fdef071790f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586723437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1586723437
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1759425829
Short name T179
Test name
Test status
Simulation time 46697535090 ps
CPU time 13.85 seconds
Started Jun 29 04:49:12 PM PDT 24
Finished Jun 29 04:49:26 PM PDT 24
Peak memory 199924 kb
Host smart-d19eaeee-3a0c-43e7-8986-29e7188cc470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759425829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1759425829
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.1116855893
Short name T213
Test name
Test status
Simulation time 36605323948 ps
CPU time 58.44 seconds
Started Jun 29 04:50:38 PM PDT 24
Finished Jun 29 04:51:36 PM PDT 24
Peak memory 199988 kb
Host smart-49ca36d3-cc8e-4f8f-9a0e-b66f0118154f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116855893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1116855893
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.2869114486
Short name T165
Test name
Test status
Simulation time 9925784045 ps
CPU time 16.75 seconds
Started Jun 29 04:50:52 PM PDT 24
Finished Jun 29 04:51:09 PM PDT 24
Peak memory 199876 kb
Host smart-58bbe6ec-6222-44f3-8d96-07523acedc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869114486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2869114486
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.4091947998
Short name T240
Test name
Test status
Simulation time 21757002983 ps
CPU time 30.46 seconds
Started Jun 29 04:50:51 PM PDT 24
Finished Jun 29 04:51:22 PM PDT 24
Peak memory 199920 kb
Host smart-0cad023b-eb9e-4a31-bbf9-0c71a56c956e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091947998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.4091947998
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.2328626775
Short name T209
Test name
Test status
Simulation time 107544730571 ps
CPU time 42.09 seconds
Started Jun 29 04:50:51 PM PDT 24
Finished Jun 29 04:51:33 PM PDT 24
Peak memory 199692 kb
Host smart-be941ca5-625a-43a4-92b4-db99eda0ca03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328626775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2328626775
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.163951155
Short name T230
Test name
Test status
Simulation time 63455563727 ps
CPU time 106.26 seconds
Started Jun 29 04:51:02 PM PDT 24
Finished Jun 29 04:52:49 PM PDT 24
Peak memory 199376 kb
Host smart-7229fab7-a2a0-4629-9bc1-44307e9611cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163951155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.163951155
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3049587916
Short name T201
Test name
Test status
Simulation time 11975922817 ps
CPU time 20.41 seconds
Started Jun 29 04:51:02 PM PDT 24
Finished Jun 29 04:51:23 PM PDT 24
Peak memory 199988 kb
Host smart-09afd584-415e-43da-8718-c5f351f8219a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049587916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3049587916
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.1407118192
Short name T161
Test name
Test status
Simulation time 11299438590 ps
CPU time 21.04 seconds
Started Jun 29 04:50:58 PM PDT 24
Finished Jun 29 04:51:20 PM PDT 24
Peak memory 199928 kb
Host smart-6030477f-3781-4e74-88ab-68daf4276abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407118192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1407118192
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_stress_all.1061842325
Short name T508
Test name
Test status
Simulation time 124914982390 ps
CPU time 258.91 seconds
Started Jun 29 04:48:16 PM PDT 24
Finished Jun 29 04:52:36 PM PDT 24
Peak memory 199840 kb
Host smart-a7a1307b-c193-4b61-88ee-68edf0c2c515
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061842325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1061842325
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.360312474
Short name T56
Test name
Test status
Simulation time 41134382917 ps
CPU time 20.93 seconds
Started Jun 29 04:51:04 PM PDT 24
Finished Jun 29 04:51:26 PM PDT 24
Peak memory 199904 kb
Host smart-f53f881a-bf36-4b2c-a88b-a8354be2e8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360312474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.360312474
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1748780867
Short name T247
Test name
Test status
Simulation time 157047816030 ps
CPU time 54.77 seconds
Started Jun 29 04:51:04 PM PDT 24
Finished Jun 29 04:52:00 PM PDT 24
Peak memory 199928 kb
Host smart-90dca878-5360-4efe-9f27-507851941b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748780867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1748780867
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2523576068
Short name T195
Test name
Test status
Simulation time 22518205005 ps
CPU time 48.04 seconds
Started Jun 29 04:48:22 PM PDT 24
Finished Jun 29 04:49:11 PM PDT 24
Peak memory 199904 kb
Host smart-e5184f0e-7ae9-49ab-ac40-87b0ebdecec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523576068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2523576068
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.2053013552
Short name T239
Test name
Test status
Simulation time 465474992715 ps
CPU time 1304.17 seconds
Started Jun 29 04:48:29 PM PDT 24
Finished Jun 29 05:10:14 PM PDT 24
Peak memory 224716 kb
Host smart-8033a59a-8449-40dc-951e-c027886f992b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053013552 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.2053013552
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.857515521
Short name T236
Test name
Test status
Simulation time 11039549470 ps
CPU time 12.96 seconds
Started Jun 29 04:51:14 PM PDT 24
Finished Jun 29 04:51:27 PM PDT 24
Peak memory 199800 kb
Host smart-9d8eaf8f-9517-4272-8cc2-95e0e99776f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857515521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.857515521
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.610931690
Short name T177
Test name
Test status
Simulation time 72395413605 ps
CPU time 55.49 seconds
Started Jun 29 04:51:27 PM PDT 24
Finished Jun 29 04:52:23 PM PDT 24
Peak memory 200000 kb
Host smart-cb5c318a-ffed-4f54-a738-9a9c5aa47830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610931690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.610931690
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.2136720095
Short name T228
Test name
Test status
Simulation time 37151358548 ps
CPU time 27.1 seconds
Started Jun 29 04:51:44 PM PDT 24
Finished Jun 29 04:52:11 PM PDT 24
Peak memory 199872 kb
Host smart-97dce34b-5bc5-4e65-a9c6-361a861f355d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136720095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.2136720095
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.137373332
Short name T244
Test name
Test status
Simulation time 107088027403 ps
CPU time 95.73 seconds
Started Jun 29 04:51:50 PM PDT 24
Finished Jun 29 04:53:26 PM PDT 24
Peak memory 199928 kb
Host smart-318e80f8-1f1e-4c73-a289-3bc9abcbd4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137373332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.137373332
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.843439421
Short name T241
Test name
Test status
Simulation time 42563311896 ps
CPU time 37.73 seconds
Started Jun 29 04:48:57 PM PDT 24
Finished Jun 29 04:49:36 PM PDT 24
Peak memory 199800 kb
Host smart-50f24e87-c6e7-40bb-a92b-d08bf817a786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843439421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.843439421
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.3475940603
Short name T141
Test name
Test status
Simulation time 165911071578 ps
CPU time 45.52 seconds
Started Jun 29 04:51:59 PM PDT 24
Finished Jun 29 04:52:45 PM PDT 24
Peak memory 199828 kb
Host smart-876e0913-fad8-4518-885f-b56330db8b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475940603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3475940603
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.3502415317
Short name T226
Test name
Test status
Simulation time 18585635143 ps
CPU time 29.54 seconds
Started Jun 29 04:51:58 PM PDT 24
Finished Jun 29 04:52:28 PM PDT 24
Peak memory 199988 kb
Host smart-fa5024d7-e350-4508-b696-0b6516998585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502415317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3502415317
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3924254461
Short name T227
Test name
Test status
Simulation time 369665072857 ps
CPU time 1516.35 seconds
Started Jun 29 04:49:13 PM PDT 24
Finished Jun 29 05:14:30 PM PDT 24
Peak memory 224668 kb
Host smart-214306bb-99c0-4c04-b158-2f6b5779f9f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924254461 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3924254461
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.3669553204
Short name T252
Test name
Test status
Simulation time 103189201762 ps
CPU time 39.11 seconds
Started Jun 29 04:50:37 PM PDT 24
Finished Jun 29 04:51:17 PM PDT 24
Peak memory 199872 kb
Host smart-75db1f26-4230-49f6-b44d-72b68b245b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669553204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3669553204
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.1293465732
Short name T248
Test name
Test status
Simulation time 65737945424 ps
CPU time 28.8 seconds
Started Jun 29 04:50:50 PM PDT 24
Finished Jun 29 04:51:19 PM PDT 24
Peak memory 199920 kb
Host smart-88e7fe1c-2221-4af2-b40b-09dbafe5175b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293465732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1293465732
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.145060133
Short name T1167
Test name
Test status
Simulation time 273220770 ps
CPU time 1.58 seconds
Started Jun 29 05:34:40 PM PDT 24
Finished Jun 29 05:34:42 PM PDT 24
Peak memory 198080 kb
Host smart-ccf4e5d2-4ccb-4f48-9c90-4be010f36ff8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145060133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.145060133
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4068213142
Short name T1120
Test name
Test status
Simulation time 1029820378 ps
CPU time 1.89 seconds
Started Jun 29 05:34:32 PM PDT 24
Finished Jun 29 05:34:34 PM PDT 24
Peak memory 195816 kb
Host smart-a624edfd-bc55-4c6b-ac7b-909d53be5698
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068213142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.4068213142
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.680983464
Short name T1182
Test name
Test status
Simulation time 80168260 ps
CPU time 0.73 seconds
Started Jun 29 05:34:35 PM PDT 24
Finished Jun 29 05:34:37 PM PDT 24
Peak memory 198812 kb
Host smart-fba08ecb-487f-4f8e-b6ba-82ab29f67cab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680983464 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.680983464
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.266728302
Short name T1119
Test name
Test status
Simulation time 12359014 ps
CPU time 0.57 seconds
Started Jun 29 05:34:34 PM PDT 24
Finished Jun 29 05:34:36 PM PDT 24
Peak memory 195804 kb
Host smart-dd489b10-4ea2-4ce8-94ff-c93ce7d768a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266728302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.266728302
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.1330236371
Short name T1104
Test name
Test status
Simulation time 23961043 ps
CPU time 0.56 seconds
Started Jun 29 05:34:28 PM PDT 24
Finished Jun 29 05:34:30 PM PDT 24
Peak memory 194796 kb
Host smart-5f9832c8-1ccc-4217-afda-971ed510540d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330236371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1330236371
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.4253096424
Short name T1152
Test name
Test status
Simulation time 59659807 ps
CPU time 0.81 seconds
Started Jun 29 05:34:37 PM PDT 24
Finished Jun 29 05:34:38 PM PDT 24
Peak memory 197596 kb
Host smart-22be9098-36d1-436d-a47a-0aee573175e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253096424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.4253096424
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.3478698018
Short name T1157
Test name
Test status
Simulation time 77875332 ps
CPU time 1.68 seconds
Started Jun 29 05:34:28 PM PDT 24
Finished Jun 29 05:34:31 PM PDT 24
Peak memory 200420 kb
Host smart-2c6ee3bd-ead2-4fd0-9f26-57785d99522a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478698018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3478698018
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2929069628
Short name T126
Test name
Test status
Simulation time 219713722 ps
CPU time 1.34 seconds
Started Jun 29 05:34:38 PM PDT 24
Finished Jun 29 05:34:40 PM PDT 24
Peak memory 199704 kb
Host smart-efe8622a-e986-4417-971d-9b1ee53934bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929069628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2929069628
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.402329442
Short name T68
Test name
Test status
Simulation time 27850857 ps
CPU time 0.84 seconds
Started Jun 29 05:34:35 PM PDT 24
Finished Jun 29 05:34:37 PM PDT 24
Peak memory 196664 kb
Host smart-5fc3f7fa-a12b-4fdd-8cd4-3b906894ead5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402329442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.402329442
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.99100792
Short name T1118
Test name
Test status
Simulation time 342817484 ps
CPU time 1.46 seconds
Started Jun 29 05:34:28 PM PDT 24
Finished Jun 29 05:34:31 PM PDT 24
Peak memory 198440 kb
Host smart-a05a3583-1203-4302-8010-e6017e07f007
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99100792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.99100792
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.36737361
Short name T1176
Test name
Test status
Simulation time 19013758 ps
CPU time 0.61 seconds
Started Jun 29 05:34:38 PM PDT 24
Finished Jun 29 05:34:39 PM PDT 24
Peak memory 195736 kb
Host smart-e2079669-a366-4bb6-8bb4-e6cc3d149722
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36737361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.36737361
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1121659114
Short name T1219
Test name
Test status
Simulation time 61937969 ps
CPU time 0.69 seconds
Started Jun 29 05:34:44 PM PDT 24
Finished Jun 29 05:34:46 PM PDT 24
Peak memory 198000 kb
Host smart-c649834e-7bb6-4f5a-a503-6a6b9bf3fcc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121659114 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1121659114
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3008652236
Short name T1135
Test name
Test status
Simulation time 14190630 ps
CPU time 0.6 seconds
Started Jun 29 05:34:28 PM PDT 24
Finished Jun 29 05:34:29 PM PDT 24
Peak memory 195808 kb
Host smart-bf317c37-0862-424b-8981-1dd348ce00ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008652236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3008652236
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.3444287781
Short name T1153
Test name
Test status
Simulation time 19142850 ps
CPU time 0.64 seconds
Started Jun 29 05:34:51 PM PDT 24
Finished Jun 29 05:34:54 PM PDT 24
Peak memory 194784 kb
Host smart-ff32b78a-d199-408a-8ba0-2f3fa7c49552
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444287781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3444287781
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1140630233
Short name T1138
Test name
Test status
Simulation time 16361029 ps
CPU time 0.74 seconds
Started Jun 29 05:34:41 PM PDT 24
Finished Jun 29 05:34:43 PM PDT 24
Peak memory 197308 kb
Host smart-677b6b29-f669-4659-85c3-9b062b1f0322
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140630233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.1140630233
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.2733995770
Short name T1180
Test name
Test status
Simulation time 121149181 ps
CPU time 1.66 seconds
Started Jun 29 05:34:35 PM PDT 24
Finished Jun 29 05:34:38 PM PDT 24
Peak memory 200396 kb
Host smart-2d1f2a69-e821-4b47-b754-65f24ad8ca58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733995770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2733995770
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.730788467
Short name T92
Test name
Test status
Simulation time 151442039 ps
CPU time 0.96 seconds
Started Jun 29 05:34:37 PM PDT 24
Finished Jun 29 05:34:39 PM PDT 24
Peak memory 199376 kb
Host smart-b71d9216-5aa4-4bff-80e4-52a8f8915511
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730788467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.730788467
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2102850577
Short name T1158
Test name
Test status
Simulation time 20007320 ps
CPU time 1.15 seconds
Started Jun 29 05:34:48 PM PDT 24
Finished Jun 29 05:34:51 PM PDT 24
Peak memory 200220 kb
Host smart-2dc6904e-1d13-499e-89f4-f6bada8662a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102850577 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.2102850577
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.2363488993
Short name T1188
Test name
Test status
Simulation time 41680756 ps
CPU time 0.56 seconds
Started Jun 29 05:34:51 PM PDT 24
Finished Jun 29 05:34:54 PM PDT 24
Peak memory 194788 kb
Host smart-965630f7-97a5-410a-b7eb-9f3e2acd4de4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363488993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2363488993
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1498439031
Short name T1159
Test name
Test status
Simulation time 23790989 ps
CPU time 0.66 seconds
Started Jun 29 05:34:47 PM PDT 24
Finished Jun 29 05:34:49 PM PDT 24
Peak memory 196272 kb
Host smart-91206c5c-e90b-4848-9fd2-1cfd342fe238
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498439031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.1498439031
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.2341883590
Short name T1230
Test name
Test status
Simulation time 143094429 ps
CPU time 2.32 seconds
Started Jun 29 05:34:50 PM PDT 24
Finished Jun 29 05:34:55 PM PDT 24
Peak memory 200404 kb
Host smart-f60568f5-fa33-4e2d-9f73-b7d5a7b4e01f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341883590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.2341883590
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1595832636
Short name T1215
Test name
Test status
Simulation time 314825579 ps
CPU time 1.26 seconds
Started Jun 29 05:34:50 PM PDT 24
Finished Jun 29 05:34:54 PM PDT 24
Peak memory 200416 kb
Host smart-89bb26b1-60d0-4702-b6de-8d0ba751b920
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595832636 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.1595832636
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.2786288416
Short name T83
Test name
Test status
Simulation time 40584019 ps
CPU time 0.62 seconds
Started Jun 29 05:34:41 PM PDT 24
Finished Jun 29 05:34:42 PM PDT 24
Peak memory 195852 kb
Host smart-164fd550-7db5-48c5-af72-08694cecd772
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786288416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2786288416
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.3039943843
Short name T1209
Test name
Test status
Simulation time 15704958 ps
CPU time 0.57 seconds
Started Jun 29 05:34:50 PM PDT 24
Finished Jun 29 05:34:53 PM PDT 24
Peak memory 194768 kb
Host smart-7f6c8a38-092a-4248-92be-3e0042d037bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039943843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3039943843
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3824986187
Short name T1196
Test name
Test status
Simulation time 181449908 ps
CPU time 0.69 seconds
Started Jun 29 05:34:50 PM PDT 24
Finished Jun 29 05:34:53 PM PDT 24
Peak memory 197164 kb
Host smart-dd41f8b1-4ed6-4dc0-b840-858b7fd2e995
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824986187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.3824986187
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.1883109778
Short name T1101
Test name
Test status
Simulation time 53872359 ps
CPU time 1.3 seconds
Started Jun 29 05:34:48 PM PDT 24
Finished Jun 29 05:34:51 PM PDT 24
Peak memory 200384 kb
Host smart-1e1a58de-3b84-4dde-af5e-2b5bfbfa429d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883109778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.1883109778
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.4092319092
Short name T88
Test name
Test status
Simulation time 181530757 ps
CPU time 0.97 seconds
Started Jun 29 05:34:52 PM PDT 24
Finished Jun 29 05:34:55 PM PDT 24
Peak memory 199492 kb
Host smart-dd3dddb5-05a5-4c6c-a4ea-60f966fdf3c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092319092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.4092319092
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.119494948
Short name T1126
Test name
Test status
Simulation time 23789254 ps
CPU time 0.77 seconds
Started Jun 29 05:34:53 PM PDT 24
Finished Jun 29 05:34:55 PM PDT 24
Peak memory 199420 kb
Host smart-26ff4f59-35b9-474e-909f-d608fdf9c098
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119494948 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.119494948
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.4135376435
Short name T1160
Test name
Test status
Simulation time 34561651 ps
CPU time 0.62 seconds
Started Jun 29 05:34:48 PM PDT 24
Finished Jun 29 05:34:50 PM PDT 24
Peak memory 195804 kb
Host smart-473dd340-e9a5-4347-b067-6f635c49987c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135376435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.4135376435
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.1701608963
Short name T1142
Test name
Test status
Simulation time 123461904 ps
CPU time 0.58 seconds
Started Jun 29 05:34:48 PM PDT 24
Finished Jun 29 05:34:50 PM PDT 24
Peak memory 194784 kb
Host smart-7650beda-0634-4be7-be72-068f82b354d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701608963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1701608963
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1977332738
Short name T78
Test name
Test status
Simulation time 15256793 ps
CPU time 0.66 seconds
Started Jun 29 05:34:51 PM PDT 24
Finished Jun 29 05:34:54 PM PDT 24
Peak memory 196216 kb
Host smart-85753a7c-5cc2-42ac-b66a-bf35d9fdf358
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977332738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.1977332738
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.924756924
Short name T1186
Test name
Test status
Simulation time 160129907 ps
CPU time 2.14 seconds
Started Jun 29 05:34:44 PM PDT 24
Finished Jun 29 05:34:47 PM PDT 24
Peak memory 200404 kb
Host smart-f69d669c-232a-4d64-91a9-b0c9bdaff047
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924756924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.924756924
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2962226939
Short name T1221
Test name
Test status
Simulation time 151645200 ps
CPU time 1.01 seconds
Started Jun 29 05:34:35 PM PDT 24
Finished Jun 29 05:34:37 PM PDT 24
Peak memory 199316 kb
Host smart-b4384515-48c2-4e1e-895f-c752abb736a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962226939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.2962226939
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2040047908
Short name T1184
Test name
Test status
Simulation time 31734934 ps
CPU time 0.86 seconds
Started Jun 29 05:34:52 PM PDT 24
Finished Jun 29 05:34:55 PM PDT 24
Peak memory 200208 kb
Host smart-5c32b7c9-bca5-4ea6-9dd4-a897a0da894b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040047908 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2040047908
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.4022428634
Short name T1116
Test name
Test status
Simulation time 52272643 ps
CPU time 0.6 seconds
Started Jun 29 05:34:42 PM PDT 24
Finished Jun 29 05:34:43 PM PDT 24
Peak memory 195804 kb
Host smart-0ee07097-bae5-4bbe-80e8-a1978d251948
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022428634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.4022428634
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.3362467519
Short name T1226
Test name
Test status
Simulation time 13855413 ps
CPU time 0.64 seconds
Started Jun 29 05:34:41 PM PDT 24
Finished Jun 29 05:34:42 PM PDT 24
Peak memory 194796 kb
Host smart-7d010b1d-2606-4dce-8b05-409a868863ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362467519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3362467519
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.819853807
Short name T1205
Test name
Test status
Simulation time 50773991 ps
CPU time 0.77 seconds
Started Jun 29 05:34:41 PM PDT 24
Finished Jun 29 05:34:42 PM PDT 24
Peak memory 197884 kb
Host smart-9ea96f82-a45b-41ae-ba49-9a34197e13ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819853807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr
_outstanding.819853807
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.319915362
Short name T1144
Test name
Test status
Simulation time 221971563 ps
CPU time 1.26 seconds
Started Jun 29 05:34:45 PM PDT 24
Finished Jun 29 05:34:47 PM PDT 24
Peak memory 200384 kb
Host smart-f9928bd7-9332-4a73-80d9-a8975786f880
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319915362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.319915362
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1520930789
Short name T1143
Test name
Test status
Simulation time 323861288 ps
CPU time 0.94 seconds
Started Jun 29 05:34:49 PM PDT 24
Finished Jun 29 05:34:52 PM PDT 24
Peak memory 199516 kb
Host smart-e390aa71-375c-49cf-817a-2b25fdf4b47d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520930789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1520930789
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1523680559
Short name T1161
Test name
Test status
Simulation time 97853065 ps
CPU time 0.97 seconds
Started Jun 29 05:34:46 PM PDT 24
Finished Jun 29 05:34:48 PM PDT 24
Peak memory 200220 kb
Host smart-c54cdd28-9dc7-4571-bdac-0cbddb0f9022
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523680559 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.1523680559
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.2320150698
Short name T1124
Test name
Test status
Simulation time 17851913 ps
CPU time 0.72 seconds
Started Jun 29 05:34:50 PM PDT 24
Finished Jun 29 05:34:53 PM PDT 24
Peak memory 195876 kb
Host smart-617b356e-39cc-4cc3-9498-c0503844304b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320150698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2320150698
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.2624665215
Short name T1213
Test name
Test status
Simulation time 15165628 ps
CPU time 0.58 seconds
Started Jun 29 05:34:53 PM PDT 24
Finished Jun 29 05:34:56 PM PDT 24
Peak memory 194720 kb
Host smart-91cd3b79-f5ed-4537-b058-c812bebbcfc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624665215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.2624665215
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2324690746
Short name T1199
Test name
Test status
Simulation time 42946710 ps
CPU time 0.8 seconds
Started Jun 29 05:34:47 PM PDT 24
Finished Jun 29 05:34:50 PM PDT 24
Peak memory 197384 kb
Host smart-04c451ec-da5b-47b4-a5b5-9d05e40ede2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324690746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.2324690746
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.855837819
Short name T1210
Test name
Test status
Simulation time 139665435 ps
CPU time 1.4 seconds
Started Jun 29 05:34:52 PM PDT 24
Finished Jun 29 05:34:55 PM PDT 24
Peak memory 200404 kb
Host smart-46b6651c-7e62-4070-b300-9ced8fd7a535
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855837819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.855837819
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3618997635
Short name T1136
Test name
Test status
Simulation time 212708812 ps
CPU time 0.96 seconds
Started Jun 29 05:34:49 PM PDT 24
Finished Jun 29 05:34:51 PM PDT 24
Peak memory 199476 kb
Host smart-961cb5ee-5504-4510-be00-928ef8971ae0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618997635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3618997635
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.567062378
Short name T1170
Test name
Test status
Simulation time 33266940 ps
CPU time 0.85 seconds
Started Jun 29 05:34:53 PM PDT 24
Finished Jun 29 05:34:56 PM PDT 24
Peak memory 200188 kb
Host smart-c1ae4880-bd7e-4343-a784-1de20829947e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567062378 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.567062378
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.4008020022
Short name T1198
Test name
Test status
Simulation time 13364323 ps
CPU time 0.6 seconds
Started Jun 29 05:34:54 PM PDT 24
Finished Jun 29 05:34:56 PM PDT 24
Peak memory 195796 kb
Host smart-139f81ea-7caa-44fb-ae22-3ab509f64a49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008020022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.4008020022
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2404649501
Short name T1207
Test name
Test status
Simulation time 27656337 ps
CPU time 0.62 seconds
Started Jun 29 05:34:50 PM PDT 24
Finished Jun 29 05:34:54 PM PDT 24
Peak memory 194792 kb
Host smart-49c67418-256e-4d83-9ca3-27da9ce3e8ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404649501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2404649501
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3049519033
Short name T82
Test name
Test status
Simulation time 35596093 ps
CPU time 0.73 seconds
Started Jun 29 05:34:51 PM PDT 24
Finished Jun 29 05:34:54 PM PDT 24
Peak memory 197204 kb
Host smart-01fe8e1d-5ebb-4ad6-8d39-e45412f47174
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049519033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.3049519033
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.2463186486
Short name T1225
Test name
Test status
Simulation time 43045053 ps
CPU time 2.09 seconds
Started Jun 29 05:35:03 PM PDT 24
Finished Jun 29 05:35:06 PM PDT 24
Peak memory 200444 kb
Host smart-d1cf6377-f12e-417d-b1ef-74234a4d5ca0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463186486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2463186486
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2327938197
Short name T1177
Test name
Test status
Simulation time 174299454 ps
CPU time 0.98 seconds
Started Jun 29 05:34:43 PM PDT 24
Finished Jun 29 05:34:45 PM PDT 24
Peak memory 199484 kb
Host smart-ef615aec-bdcd-4c15-bbad-227bbc04f95c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327938197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2327938197
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3335059308
Short name T1149
Test name
Test status
Simulation time 66686919 ps
CPU time 1.06 seconds
Started Jun 29 05:34:50 PM PDT 24
Finished Jun 29 05:34:54 PM PDT 24
Peak memory 200428 kb
Host smart-70e2d32a-9397-49c7-b2fd-53a193545010
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335059308 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.3335059308
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.3942825772
Short name T1193
Test name
Test status
Simulation time 39236091 ps
CPU time 0.59 seconds
Started Jun 29 05:34:53 PM PDT 24
Finished Jun 29 05:34:55 PM PDT 24
Peak memory 195804 kb
Host smart-5e244c3f-882f-4f94-ac41-9fa5adfb096e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942825772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3942825772
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.210676718
Short name T1123
Test name
Test status
Simulation time 77013554 ps
CPU time 0.61 seconds
Started Jun 29 05:34:49 PM PDT 24
Finished Jun 29 05:34:52 PM PDT 24
Peak memory 194796 kb
Host smart-cc7dc268-7287-4cf0-9f88-f8ba0a9df46b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210676718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.210676718
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2475355877
Short name T80
Test name
Test status
Simulation time 53641039 ps
CPU time 0.73 seconds
Started Jun 29 05:34:51 PM PDT 24
Finished Jun 29 05:34:54 PM PDT 24
Peak memory 196464 kb
Host smart-2ebc4578-286a-4370-9ff2-c2c1bf8183bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475355877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.2475355877
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.4273797823
Short name T1181
Test name
Test status
Simulation time 125625036 ps
CPU time 2.18 seconds
Started Jun 29 05:34:54 PM PDT 24
Finished Jun 29 05:34:58 PM PDT 24
Peak memory 200360 kb
Host smart-0802b9aa-415b-493d-b0df-7da1653d21d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273797823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.4273797823
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.4200101900
Short name T125
Test name
Test status
Simulation time 46907747 ps
CPU time 0.94 seconds
Started Jun 29 05:34:55 PM PDT 24
Finished Jun 29 05:34:58 PM PDT 24
Peak memory 199264 kb
Host smart-1e7f2cc1-b947-4a0e-8412-c17e93f210be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200101900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.4200101900
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2613702341
Short name T1145
Test name
Test status
Simulation time 110343097 ps
CPU time 1.3 seconds
Started Jun 29 05:34:55 PM PDT 24
Finished Jun 29 05:34:58 PM PDT 24
Peak memory 200452 kb
Host smart-11786d1d-1da5-43ff-b8c4-9bc187f36930
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613702341 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.2613702341
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.3461594164
Short name T75
Test name
Test status
Simulation time 108422775 ps
CPU time 0.64 seconds
Started Jun 29 05:34:51 PM PDT 24
Finished Jun 29 05:34:54 PM PDT 24
Peak memory 195884 kb
Host smart-9677536a-791c-46ce-9999-a15a8aba01d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461594164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3461594164
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.1809147070
Short name T1171
Test name
Test status
Simulation time 21527506 ps
CPU time 0.58 seconds
Started Jun 29 05:34:50 PM PDT 24
Finished Jun 29 05:34:53 PM PDT 24
Peak memory 194792 kb
Host smart-622026a2-19fc-48d2-b9ad-48ca798f7e53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809147070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.1809147070
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2663768659
Short name T1148
Test name
Test status
Simulation time 30522671 ps
CPU time 0.75 seconds
Started Jun 29 05:34:51 PM PDT 24
Finished Jun 29 05:34:54 PM PDT 24
Peak memory 197288 kb
Host smart-501514bf-088a-447a-8e26-4e5eb89730a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663768659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2663768659
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.4087455601
Short name T1168
Test name
Test status
Simulation time 24963953 ps
CPU time 1.28 seconds
Started Jun 29 05:34:56 PM PDT 24
Finished Jun 29 05:34:59 PM PDT 24
Peak memory 200440 kb
Host smart-2363fd45-9adc-41fc-98da-916e03a71c9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087455601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.4087455601
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2256317707
Short name T1110
Test name
Test status
Simulation time 43842461 ps
CPU time 0.95 seconds
Started Jun 29 05:34:54 PM PDT 24
Finished Jun 29 05:34:57 PM PDT 24
Peak memory 199504 kb
Host smart-4da02b9f-adcc-4f99-92ef-9a0183ac95cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256317707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2256317707
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.7729654
Short name T1112
Test name
Test status
Simulation time 31168442 ps
CPU time 1.52 seconds
Started Jun 29 05:34:51 PM PDT 24
Finished Jun 29 05:34:55 PM PDT 24
Peak memory 200424 kb
Host smart-152c9596-5a6a-497b-83a2-d8c282e21ee3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7729654 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.7729654
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.2573271214
Short name T1206
Test name
Test status
Simulation time 36412518 ps
CPU time 0.58 seconds
Started Jun 29 05:34:54 PM PDT 24
Finished Jun 29 05:34:57 PM PDT 24
Peak memory 195780 kb
Host smart-2704aa81-2c7b-47ef-9ed9-300875894812
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573271214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.2573271214
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3114318878
Short name T1224
Test name
Test status
Simulation time 46987265 ps
CPU time 0.62 seconds
Started Jun 29 05:34:54 PM PDT 24
Finished Jun 29 05:34:56 PM PDT 24
Peak memory 194796 kb
Host smart-0980855a-6462-41b3-8d16-77c16b2baabd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114318878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3114318878
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1367238616
Short name T1222
Test name
Test status
Simulation time 27838758 ps
CPU time 0.74 seconds
Started Jun 29 05:34:50 PM PDT 24
Finished Jun 29 05:34:53 PM PDT 24
Peak memory 197212 kb
Host smart-b661f0a7-4ff7-4852-b956-ddad65f31a5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367238616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.1367238616
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.225834285
Short name T1113
Test name
Test status
Simulation time 105743765 ps
CPU time 1.4 seconds
Started Jun 29 05:34:51 PM PDT 24
Finished Jun 29 05:34:55 PM PDT 24
Peak memory 200444 kb
Host smart-a910c7d6-b0a3-4b4e-beec-de854e689691
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225834285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.225834285
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1438041099
Short name T85
Test name
Test status
Simulation time 841722868 ps
CPU time 1.4 seconds
Started Jun 29 05:34:59 PM PDT 24
Finished Jun 29 05:35:02 PM PDT 24
Peak memory 199668 kb
Host smart-15cb02d4-9242-4eda-843a-6844b638a503
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438041099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1438041099
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.341830555
Short name T1174
Test name
Test status
Simulation time 79333814 ps
CPU time 0.75 seconds
Started Jun 29 05:34:48 PM PDT 24
Finished Jun 29 05:34:51 PM PDT 24
Peak memory 198892 kb
Host smart-8d486004-6a1d-4f1c-9205-e38c92c7c731
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341830555 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.341830555
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.3243469007
Short name T1217
Test name
Test status
Simulation time 75992672 ps
CPU time 0.67 seconds
Started Jun 29 05:34:55 PM PDT 24
Finished Jun 29 05:34:57 PM PDT 24
Peak memory 196244 kb
Host smart-c19aee0e-1b80-414a-a373-0a604f211d42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243469007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3243469007
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.619345562
Short name T1129
Test name
Test status
Simulation time 13454044 ps
CPU time 0.64 seconds
Started Jun 29 05:34:52 PM PDT 24
Finished Jun 29 05:34:55 PM PDT 24
Peak memory 194788 kb
Host smart-183dfc39-b632-4fc3-8d96-63d0fa7dbbe6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619345562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.619345562
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.826402152
Short name T76
Test name
Test status
Simulation time 32280446 ps
CPU time 0.64 seconds
Started Jun 29 05:34:54 PM PDT 24
Finished Jun 29 05:34:57 PM PDT 24
Peak memory 195796 kb
Host smart-12aa5aa3-537c-4d71-8d07-c0c4c864ee9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826402152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr
_outstanding.826402152
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.2895746379
Short name T1200
Test name
Test status
Simulation time 75344891 ps
CPU time 1.18 seconds
Started Jun 29 05:34:49 PM PDT 24
Finished Jun 29 05:34:52 PM PDT 24
Peak memory 200420 kb
Host smart-82b94892-97f7-4480-837b-9528a3b91701
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895746379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2895746379
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1509182333
Short name T1115
Test name
Test status
Simulation time 358041748 ps
CPU time 1.46 seconds
Started Jun 29 05:35:01 PM PDT 24
Finished Jun 29 05:35:04 PM PDT 24
Peak memory 199648 kb
Host smart-f5bf3ba2-9e1e-49a5-989e-71cfb0b48774
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509182333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1509182333
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3063159270
Short name T72
Test name
Test status
Simulation time 66987265 ps
CPU time 0.8 seconds
Started Jun 29 05:34:33 PM PDT 24
Finished Jun 29 05:34:35 PM PDT 24
Peak memory 197024 kb
Host smart-375ba38c-04f1-434b-8741-614d61abd4fc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063159270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3063159270
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1145706533
Short name T1107
Test name
Test status
Simulation time 134354091 ps
CPU time 1.55 seconds
Started Jun 29 05:34:37 PM PDT 24
Finished Jun 29 05:34:39 PM PDT 24
Peak memory 198372 kb
Host smart-86a50fa2-27e8-4d04-b884-51217d3e61e8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145706533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1145706533
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2259040799
Short name T1194
Test name
Test status
Simulation time 13645638 ps
CPU time 0.6 seconds
Started Jun 29 05:34:30 PM PDT 24
Finished Jun 29 05:34:32 PM PDT 24
Peak memory 195744 kb
Host smart-c093f4ef-20f1-4a47-86ea-e58cb4e88708
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259040799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2259040799
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1179735564
Short name T1179
Test name
Test status
Simulation time 83475966 ps
CPU time 1.1 seconds
Started Jun 29 05:34:33 PM PDT 24
Finished Jun 29 05:34:35 PM PDT 24
Peak memory 200456 kb
Host smart-237cda11-585f-43b2-b058-b3d49ec1d5b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179735564 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1179735564
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.2013572397
Short name T1185
Test name
Test status
Simulation time 31714575 ps
CPU time 0.65 seconds
Started Jun 29 05:34:33 PM PDT 24
Finished Jun 29 05:34:35 PM PDT 24
Peak memory 195816 kb
Host smart-d5e227ae-754b-41f3-802e-7c068f4aec82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013572397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2013572397
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3257246451
Short name T1114
Test name
Test status
Simulation time 12580967 ps
CPU time 0.58 seconds
Started Jun 29 05:34:33 PM PDT 24
Finished Jun 29 05:34:35 PM PDT 24
Peak memory 194796 kb
Host smart-dcfb7fa8-170d-4ac6-bd38-78cc3a92eff2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257246451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3257246451
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3891944331
Short name T1227
Test name
Test status
Simulation time 24434891 ps
CPU time 0.73 seconds
Started Jun 29 05:34:39 PM PDT 24
Finished Jun 29 05:34:40 PM PDT 24
Peak memory 197356 kb
Host smart-8e4f53b6-821f-413a-94a9-671e85a564bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891944331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3891944331
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2531572600
Short name T1111
Test name
Test status
Simulation time 210125473 ps
CPU time 1.59 seconds
Started Jun 29 05:34:26 PM PDT 24
Finished Jun 29 05:34:29 PM PDT 24
Peak memory 200368 kb
Host smart-e1da363c-3d43-4598-9e95-fa671af71512
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531572600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2531572600
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1302931141
Short name T86
Test name
Test status
Simulation time 524936167 ps
CPU time 1.24 seconds
Started Jun 29 05:34:29 PM PDT 24
Finished Jun 29 05:34:32 PM PDT 24
Peak memory 199816 kb
Host smart-5587236f-8aff-45f2-8456-587cbbcd3da5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302931141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1302931141
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.3652248387
Short name T1133
Test name
Test status
Simulation time 39485479 ps
CPU time 0.59 seconds
Started Jun 29 05:34:55 PM PDT 24
Finished Jun 29 05:34:57 PM PDT 24
Peak memory 194788 kb
Host smart-4d3de85a-1822-4aad-b490-240b29c0ef08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652248387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3652248387
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.44178113
Short name T1139
Test name
Test status
Simulation time 14332761 ps
CPU time 0.62 seconds
Started Jun 29 05:34:54 PM PDT 24
Finished Jun 29 05:34:57 PM PDT 24
Peak memory 194796 kb
Host smart-5aba1fc8-1120-4d17-9ff7-7e2bbfc7c4fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44178113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.44178113
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1946060792
Short name T1132
Test name
Test status
Simulation time 79374094 ps
CPU time 0.56 seconds
Started Jun 29 05:35:00 PM PDT 24
Finished Jun 29 05:35:01 PM PDT 24
Peak memory 194792 kb
Host smart-a1e555b1-63e4-4c9b-84c0-a7ba93494cbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946060792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1946060792
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2971197228
Short name T1146
Test name
Test status
Simulation time 55365596 ps
CPU time 0.64 seconds
Started Jun 29 05:34:55 PM PDT 24
Finished Jun 29 05:34:57 PM PDT 24
Peak memory 194796 kb
Host smart-e02c64dc-4902-4ce9-ac1c-cf75563d8a8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971197228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2971197228
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.1486676624
Short name T1117
Test name
Test status
Simulation time 13080372 ps
CPU time 0.57 seconds
Started Jun 29 05:34:51 PM PDT 24
Finished Jun 29 05:34:54 PM PDT 24
Peak memory 194788 kb
Host smart-fea2f8f0-6af5-4b9e-96ab-742e709bec7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486676624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1486676624
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.1914741608
Short name T1216
Test name
Test status
Simulation time 243666096 ps
CPU time 0.6 seconds
Started Jun 29 05:34:49 PM PDT 24
Finished Jun 29 05:34:51 PM PDT 24
Peak memory 194788 kb
Host smart-51d2889f-4a58-434a-8a30-ba6a80f0861e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914741608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1914741608
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.3692611708
Short name T1128
Test name
Test status
Simulation time 11814338 ps
CPU time 0.57 seconds
Started Jun 29 05:35:04 PM PDT 24
Finished Jun 29 05:35:05 PM PDT 24
Peak memory 194784 kb
Host smart-bfab93e6-13bb-464c-a7b0-a10d5ed06513
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692611708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3692611708
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.2825613973
Short name T1212
Test name
Test status
Simulation time 30920934 ps
CPU time 0.61 seconds
Started Jun 29 05:34:50 PM PDT 24
Finished Jun 29 05:34:53 PM PDT 24
Peak memory 194784 kb
Host smart-f94967af-0e36-487c-82a8-3bea2a475945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825613973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.2825613973
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.4264969381
Short name T1147
Test name
Test status
Simulation time 45717328 ps
CPU time 0.59 seconds
Started Jun 29 05:35:03 PM PDT 24
Finished Jun 29 05:35:05 PM PDT 24
Peak memory 194720 kb
Host smart-a8a427bc-bfa1-4425-a9e1-a0102e6f44e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264969381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.4264969381
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.3603273871
Short name T1202
Test name
Test status
Simulation time 52773632 ps
CPU time 0.59 seconds
Started Jun 29 05:34:55 PM PDT 24
Finished Jun 29 05:34:58 PM PDT 24
Peak memory 194764 kb
Host smart-c0f23c46-4a7a-4333-ad52-3207e9407295
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603273871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.3603273871
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2753340598
Short name T1232
Test name
Test status
Simulation time 29859221 ps
CPU time 0.85 seconds
Started Jun 29 05:34:38 PM PDT 24
Finished Jun 29 05:34:39 PM PDT 24
Peak memory 196844 kb
Host smart-4c4eb52b-4457-4887-ade4-4ee41d54d5bf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753340598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2753340598
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1210310762
Short name T1203
Test name
Test status
Simulation time 865705768 ps
CPU time 1.52 seconds
Started Jun 29 05:34:37 PM PDT 24
Finished Jun 29 05:34:39 PM PDT 24
Peak memory 198220 kb
Host smart-f5eebd9d-7008-4580-b636-4db5e832d335
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210310762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1210310762
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3606773609
Short name T1195
Test name
Test status
Simulation time 36543900 ps
CPU time 0.59 seconds
Started Jun 29 05:34:47 PM PDT 24
Finished Jun 29 05:34:49 PM PDT 24
Peak memory 195816 kb
Host smart-01f623f7-646c-4ae5-a6a1-a528fc667da7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606773609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3606773609
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1267022511
Short name T1134
Test name
Test status
Simulation time 28701485 ps
CPU time 0.82 seconds
Started Jun 29 05:34:34 PM PDT 24
Finished Jun 29 05:34:36 PM PDT 24
Peak memory 200220 kb
Host smart-61abd693-3b06-4ae5-bff3-e83553ca8c5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267022511 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.1267022511
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.1535325317
Short name T73
Test name
Test status
Simulation time 34442400 ps
CPU time 0.67 seconds
Started Jun 29 05:34:33 PM PDT 24
Finished Jun 29 05:34:35 PM PDT 24
Peak memory 195864 kb
Host smart-16722267-15ef-417b-9945-bc1feeb86b21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535325317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.1535325317
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.544898348
Short name T1125
Test name
Test status
Simulation time 14466616 ps
CPU time 0.6 seconds
Started Jun 29 05:34:34 PM PDT 24
Finished Jun 29 05:34:36 PM PDT 24
Peak memory 194708 kb
Host smart-22e87d5c-f28d-4ee8-a757-e8fb72e64fb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544898348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.544898348
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.306606760
Short name T79
Test name
Test status
Simulation time 300073073 ps
CPU time 0.64 seconds
Started Jun 29 05:34:37 PM PDT 24
Finished Jun 29 05:34:39 PM PDT 24
Peak memory 196144 kb
Host smart-3a51ee72-7fa4-4922-848f-7cda048dad36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306606760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_
outstanding.306606760
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.1622965152
Short name T1175
Test name
Test status
Simulation time 30222411 ps
CPU time 1.61 seconds
Started Jun 29 05:34:42 PM PDT 24
Finished Jun 29 05:34:45 PM PDT 24
Peak memory 200420 kb
Host smart-c3528590-bbd0-4603-8467-80702234479b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622965152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1622965152
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3208392869
Short name T124
Test name
Test status
Simulation time 143133047 ps
CPU time 1.25 seconds
Started Jun 29 05:34:37 PM PDT 24
Finished Jun 29 05:34:39 PM PDT 24
Peak memory 199812 kb
Host smart-35e67955-db65-43db-8ec0-e97e11a7c84c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208392869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3208392869
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.1387350330
Short name T1229
Test name
Test status
Simulation time 14460555 ps
CPU time 0.58 seconds
Started Jun 29 05:34:49 PM PDT 24
Finished Jun 29 05:34:51 PM PDT 24
Peak memory 194808 kb
Host smart-e89a0763-702d-43a1-80ca-3347f4a3a2b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387350330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1387350330
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.1736935924
Short name T1165
Test name
Test status
Simulation time 114541078 ps
CPU time 0.56 seconds
Started Jun 29 05:34:48 PM PDT 24
Finished Jun 29 05:34:50 PM PDT 24
Peak memory 194792 kb
Host smart-1a63c53b-6738-46d9-a006-02e56b8d3312
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736935924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.1736935924
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.110943430
Short name T1098
Test name
Test status
Simulation time 17510873 ps
CPU time 0.58 seconds
Started Jun 29 05:34:54 PM PDT 24
Finished Jun 29 05:34:57 PM PDT 24
Peak memory 194788 kb
Host smart-ae06f6a3-c523-4e75-a403-240d9d770324
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110943430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.110943430
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.838265159
Short name T1163
Test name
Test status
Simulation time 24984027 ps
CPU time 0.61 seconds
Started Jun 29 05:34:56 PM PDT 24
Finished Jun 29 05:34:58 PM PDT 24
Peak memory 194784 kb
Host smart-207b9d30-eb31-48f6-9c8d-d73404eae773
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838265159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.838265159
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.2576149548
Short name T1220
Test name
Test status
Simulation time 13193030 ps
CPU time 0.61 seconds
Started Jun 29 05:34:54 PM PDT 24
Finished Jun 29 05:34:56 PM PDT 24
Peak memory 194792 kb
Host smart-c53aac4a-0bd0-40ef-b8ff-88481825f349
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576149548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2576149548
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1850149843
Short name T1141
Test name
Test status
Simulation time 50023984 ps
CPU time 0.58 seconds
Started Jun 29 05:34:54 PM PDT 24
Finished Jun 29 05:34:57 PM PDT 24
Peak memory 194752 kb
Host smart-2d0d8859-9510-498a-9171-9a0592e880d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850149843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1850149843
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2507663902
Short name T1173
Test name
Test status
Simulation time 36950661 ps
CPU time 0.57 seconds
Started Jun 29 05:34:53 PM PDT 24
Finished Jun 29 05:34:56 PM PDT 24
Peak memory 194796 kb
Host smart-224b0bc4-5863-482a-8872-e26919a95779
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507663902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2507663902
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.3082370134
Short name T1109
Test name
Test status
Simulation time 14614020 ps
CPU time 0.6 seconds
Started Jun 29 05:34:56 PM PDT 24
Finished Jun 29 05:34:58 PM PDT 24
Peak memory 194792 kb
Host smart-02b367d9-d40c-4672-a080-8e2b16884118
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082370134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.3082370134
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.1699875063
Short name T1192
Test name
Test status
Simulation time 77352887 ps
CPU time 0.57 seconds
Started Jun 29 05:34:52 PM PDT 24
Finished Jun 29 05:34:55 PM PDT 24
Peak memory 194784 kb
Host smart-89d752c5-ae81-4057-a099-3958256f88cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699875063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.1699875063
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.2149174298
Short name T1121
Test name
Test status
Simulation time 44401237 ps
CPU time 0.58 seconds
Started Jun 29 05:34:48 PM PDT 24
Finished Jun 29 05:34:50 PM PDT 24
Peak memory 194792 kb
Host smart-3f7e2355-93e4-4ba3-b89e-5fd8e075b679
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149174298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.2149174298
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1121977100
Short name T69
Test name
Test status
Simulation time 36482076 ps
CPU time 0.7 seconds
Started Jun 29 05:34:47 PM PDT 24
Finished Jun 29 05:34:50 PM PDT 24
Peak memory 195840 kb
Host smart-068e8535-c35f-46ba-a54c-813775abb27a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121977100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1121977100
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3008512812
Short name T1105
Test name
Test status
Simulation time 34266311 ps
CPU time 1.42 seconds
Started Jun 29 05:34:40 PM PDT 24
Finished Jun 29 05:34:41 PM PDT 24
Peak memory 197784 kb
Host smart-783df60e-259b-44e0-85a0-0136f2f50a75
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008512812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3008512812
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1808489519
Short name T1103
Test name
Test status
Simulation time 19184475 ps
CPU time 0.59 seconds
Started Jun 29 05:34:43 PM PDT 24
Finished Jun 29 05:34:45 PM PDT 24
Peak memory 195780 kb
Host smart-6160f5d2-3ba2-46c1-8d30-b4ed700b88ab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808489519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1808489519
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3493518752
Short name T1106
Test name
Test status
Simulation time 58727324 ps
CPU time 1.06 seconds
Started Jun 29 05:34:45 PM PDT 24
Finished Jun 29 05:34:47 PM PDT 24
Peak memory 200220 kb
Host smart-8cde6acf-16de-4cba-bb91-bd71b6fd7271
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493518752 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.3493518752
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2854430711
Short name T70
Test name
Test status
Simulation time 14768980 ps
CPU time 0.65 seconds
Started Jun 29 05:34:32 PM PDT 24
Finished Jun 29 05:34:33 PM PDT 24
Peak memory 195908 kb
Host smart-c6c642c3-bb2b-4a20-b9c9-95768aa333ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854430711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2854430711
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.875930316
Short name T1150
Test name
Test status
Simulation time 52584387 ps
CPU time 0.57 seconds
Started Jun 29 05:34:40 PM PDT 24
Finished Jun 29 05:34:41 PM PDT 24
Peak memory 194720 kb
Host smart-9f623b10-fb39-42ed-ac77-ff49b6f7aae2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875930316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.875930316
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2617466469
Short name T74
Test name
Test status
Simulation time 59717204 ps
CPU time 0.71 seconds
Started Jun 29 05:34:44 PM PDT 24
Finished Jun 29 05:34:45 PM PDT 24
Peak memory 196420 kb
Host smart-6be3bae7-9c35-4562-bb92-e3d77390e52d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617466469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.2617466469
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1484835442
Short name T1162
Test name
Test status
Simulation time 215034117 ps
CPU time 1.2 seconds
Started Jun 29 05:34:33 PM PDT 24
Finished Jun 29 05:34:36 PM PDT 24
Peak memory 200412 kb
Host smart-a63defd5-f853-4eb1-b09a-469b953ea93c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484835442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1484835442
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2536826381
Short name T123
Test name
Test status
Simulation time 266192210 ps
CPU time 1.06 seconds
Started Jun 29 05:34:49 PM PDT 24
Finished Jun 29 05:34:52 PM PDT 24
Peak memory 199312 kb
Host smart-cf13c540-575a-4ad2-b93b-cfffb22499a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536826381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2536826381
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3519417911
Short name T1099
Test name
Test status
Simulation time 17600563 ps
CPU time 0.55 seconds
Started Jun 29 05:35:05 PM PDT 24
Finished Jun 29 05:35:06 PM PDT 24
Peak memory 194784 kb
Host smart-99ea1d18-570b-4866-8811-951225bcd5d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519417911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3519417911
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.1347863088
Short name T1156
Test name
Test status
Simulation time 23004369 ps
CPU time 0.59 seconds
Started Jun 29 05:34:51 PM PDT 24
Finished Jun 29 05:34:54 PM PDT 24
Peak memory 194796 kb
Host smart-238561dd-1f5b-46a0-8297-9000334f55cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347863088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1347863088
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.457026918
Short name T1228
Test name
Test status
Simulation time 18328366 ps
CPU time 0.54 seconds
Started Jun 29 05:35:05 PM PDT 24
Finished Jun 29 05:35:06 PM PDT 24
Peak memory 194720 kb
Host smart-d9e38f23-7bb0-43ef-9044-9c30970b7fc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457026918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.457026918
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.3338598748
Short name T1127
Test name
Test status
Simulation time 11349475 ps
CPU time 0.61 seconds
Started Jun 29 05:34:53 PM PDT 24
Finished Jun 29 05:34:55 PM PDT 24
Peak memory 194720 kb
Host smart-7cb243a3-7acd-4c25-aca0-95e8d22d78ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338598748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3338598748
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.2140697048
Short name T1231
Test name
Test status
Simulation time 16305908 ps
CPU time 0.62 seconds
Started Jun 29 05:34:58 PM PDT 24
Finished Jun 29 05:34:59 PM PDT 24
Peak memory 194784 kb
Host smart-1be34667-5863-4032-826c-b405013a2076
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140697048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2140697048
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3082590874
Short name T1108
Test name
Test status
Simulation time 56177765 ps
CPU time 0.6 seconds
Started Jun 29 05:35:03 PM PDT 24
Finished Jun 29 05:35:05 PM PDT 24
Peak memory 194796 kb
Host smart-ab31c09c-e36c-441e-a67e-24c64aed40f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082590874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3082590874
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.511096631
Short name T1169
Test name
Test status
Simulation time 59539324 ps
CPU time 0.59 seconds
Started Jun 29 05:34:54 PM PDT 24
Finished Jun 29 05:34:56 PM PDT 24
Peak memory 194728 kb
Host smart-0be4d92d-193d-42ba-b960-e3f2fa9c6613
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511096631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.511096631
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.3785465581
Short name T1122
Test name
Test status
Simulation time 43271848 ps
CPU time 0.62 seconds
Started Jun 29 05:34:56 PM PDT 24
Finished Jun 29 05:34:58 PM PDT 24
Peak memory 194800 kb
Host smart-02fb8343-e0d5-4b1e-9afc-6dd0febd41ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785465581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3785465581
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.1938211577
Short name T1140
Test name
Test status
Simulation time 15019725 ps
CPU time 0.65 seconds
Started Jun 29 05:35:01 PM PDT 24
Finished Jun 29 05:35:02 PM PDT 24
Peak memory 194788 kb
Host smart-7193bc94-7d6c-48e3-abb0-abc40bf7c4d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938211577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.1938211577
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.241574518
Short name T1204
Test name
Test status
Simulation time 21589025 ps
CPU time 0.58 seconds
Started Jun 29 05:35:03 PM PDT 24
Finished Jun 29 05:35:05 PM PDT 24
Peak memory 194720 kb
Host smart-d605a501-5a45-47cc-8164-c05743f42a35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241574518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.241574518
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.604275907
Short name T1164
Test name
Test status
Simulation time 21768869 ps
CPU time 0.67 seconds
Started Jun 29 05:34:52 PM PDT 24
Finished Jun 29 05:34:54 PM PDT 24
Peak memory 198176 kb
Host smart-18438fdf-9113-4d01-ada5-2722cc11cffe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604275907 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.604275907
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.1298329120
Short name T1130
Test name
Test status
Simulation time 33249932 ps
CPU time 0.61 seconds
Started Jun 29 05:34:55 PM PDT 24
Finished Jun 29 05:34:57 PM PDT 24
Peak memory 195848 kb
Host smart-4d68de26-02a5-4727-ab02-4ba441e238c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298329120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1298329120
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.1803958828
Short name T1211
Test name
Test status
Simulation time 200067675 ps
CPU time 0.59 seconds
Started Jun 29 05:34:46 PM PDT 24
Finished Jun 29 05:34:48 PM PDT 24
Peak memory 194796 kb
Host smart-85152188-37aa-43e0-aac5-da19d0ee5df7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803958828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.1803958828
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3745450972
Short name T1154
Test name
Test status
Simulation time 54521607 ps
CPU time 0.74 seconds
Started Jun 29 05:34:44 PM PDT 24
Finished Jun 29 05:34:45 PM PDT 24
Peak memory 197380 kb
Host smart-2f31bc32-d13c-497e-99a6-e4f678901286
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745450972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.3745450972
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.391331872
Short name T1155
Test name
Test status
Simulation time 317559231 ps
CPU time 1.64 seconds
Started Jun 29 05:34:44 PM PDT 24
Finished Jun 29 05:34:46 PM PDT 24
Peak memory 200444 kb
Host smart-fa1acc71-33ec-44ae-a71d-a16d0450cba1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391331872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.391331872
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.672141540
Short name T1166
Test name
Test status
Simulation time 70893878 ps
CPU time 0.97 seconds
Started Jun 29 05:34:49 PM PDT 24
Finished Jun 29 05:34:53 PM PDT 24
Peak memory 199272 kb
Host smart-c69411ec-265a-4fe2-8baa-8b0a6d853d0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672141540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.672141540
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.744793383
Short name T1178
Test name
Test status
Simulation time 85291767 ps
CPU time 0.74 seconds
Started Jun 29 05:34:49 PM PDT 24
Finished Jun 29 05:34:51 PM PDT 24
Peak memory 199368 kb
Host smart-608d8cc4-c7e3-442f-bb44-fdceb234ae55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744793383 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.744793383
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.589303088
Short name T71
Test name
Test status
Simulation time 27102412 ps
CPU time 0.6 seconds
Started Jun 29 05:34:34 PM PDT 24
Finished Jun 29 05:34:36 PM PDT 24
Peak memory 195804 kb
Host smart-a369b0a2-ee12-4d82-96fd-e74f51b74cbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589303088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.589303088
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.4076068512
Short name T1201
Test name
Test status
Simulation time 16032996 ps
CPU time 0.55 seconds
Started Jun 29 05:34:48 PM PDT 24
Finished Jun 29 05:34:50 PM PDT 24
Peak memory 194720 kb
Host smart-119e1551-1cec-4d00-b572-45c02cad9674
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076068512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.4076068512
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3251564373
Short name T1151
Test name
Test status
Simulation time 34184967 ps
CPU time 0.68 seconds
Started Jun 29 05:34:47 PM PDT 24
Finished Jun 29 05:34:49 PM PDT 24
Peak memory 195956 kb
Host smart-505350a5-7796-4721-aff2-cc2b9e75863d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251564373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.3251564373
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.3225658201
Short name T1218
Test name
Test status
Simulation time 212237815 ps
CPU time 2.33 seconds
Started Jun 29 05:34:44 PM PDT 24
Finished Jun 29 05:34:47 PM PDT 24
Peak memory 200404 kb
Host smart-e771d474-b6de-4b88-8318-e72544853eb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225658201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3225658201
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2588116202
Short name T1190
Test name
Test status
Simulation time 23023670 ps
CPU time 0.67 seconds
Started Jun 29 05:34:43 PM PDT 24
Finished Jun 29 05:34:45 PM PDT 24
Peak memory 197368 kb
Host smart-c40fbe6f-0141-4597-bff2-67a0ab8477f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588116202 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2588116202
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.3842840921
Short name T1172
Test name
Test status
Simulation time 34466014 ps
CPU time 0.57 seconds
Started Jun 29 05:34:35 PM PDT 24
Finished Jun 29 05:34:37 PM PDT 24
Peak memory 195808 kb
Host smart-ece85908-d2ed-4908-ad60-323f32dfad68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842840921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3842840921
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.3621390340
Short name T1100
Test name
Test status
Simulation time 43512159 ps
CPU time 0.58 seconds
Started Jun 29 05:34:55 PM PDT 24
Finished Jun 29 05:34:58 PM PDT 24
Peak memory 194788 kb
Host smart-930dd587-4055-40e1-9d2c-abe2407b0b92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621390340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3621390340
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2063253696
Short name T1191
Test name
Test status
Simulation time 16565470 ps
CPU time 0.73 seconds
Started Jun 29 05:34:47 PM PDT 24
Finished Jun 29 05:34:49 PM PDT 24
Peak memory 197288 kb
Host smart-f3cfc667-e1dc-4759-8961-45fa69040ed1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063253696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2063253696
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2114004206
Short name T1131
Test name
Test status
Simulation time 145648482 ps
CPU time 1.02 seconds
Started Jun 29 05:34:40 PM PDT 24
Finished Jun 29 05:34:41 PM PDT 24
Peak memory 200192 kb
Host smart-d4e0d87d-7b6d-4695-b620-f34c93ed1e8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114004206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2114004206
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2726308382
Short name T1102
Test name
Test status
Simulation time 23895190 ps
CPU time 0.97 seconds
Started Jun 29 05:34:43 PM PDT 24
Finished Jun 29 05:34:44 PM PDT 24
Peak memory 200100 kb
Host smart-6a0a8d15-755b-4fe7-811b-a86a26c380df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726308382 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.2726308382
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.2012130732
Short name T1189
Test name
Test status
Simulation time 14026091 ps
CPU time 0.59 seconds
Started Jun 29 05:34:35 PM PDT 24
Finished Jun 29 05:34:37 PM PDT 24
Peak memory 195804 kb
Host smart-51c5b8e5-fe62-41b1-86f1-7a838d91d388
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012130732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.2012130732
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.1348318398
Short name T1208
Test name
Test status
Simulation time 34843799 ps
CPU time 0.56 seconds
Started Jun 29 05:34:50 PM PDT 24
Finished Jun 29 05:34:53 PM PDT 24
Peak memory 194680 kb
Host smart-0d8e5af9-9037-4bd1-b96f-ab0fa2fd6c41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348318398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.1348318398
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1130614208
Short name T1137
Test name
Test status
Simulation time 66782180 ps
CPU time 0.66 seconds
Started Jun 29 05:34:49 PM PDT 24
Finished Jun 29 05:34:52 PM PDT 24
Peak memory 195072 kb
Host smart-c3eeb4a0-42ce-4501-9eb0-afa4430aa80a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130614208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1130614208
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2391111216
Short name T1223
Test name
Test status
Simulation time 182851680 ps
CPU time 2.53 seconds
Started Jun 29 05:34:41 PM PDT 24
Finished Jun 29 05:34:45 PM PDT 24
Peak memory 200392 kb
Host smart-792a9624-d468-4e0f-ac00-f636c3ab1a25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391111216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2391111216
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3143572805
Short name T1183
Test name
Test status
Simulation time 136673015 ps
CPU time 0.92 seconds
Started Jun 29 05:34:48 PM PDT 24
Finished Jun 29 05:34:50 PM PDT 24
Peak memory 199284 kb
Host smart-11500016-e8f9-43dc-9f7f-4eb56b0b00f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143572805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3143572805
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.973433951
Short name T1187
Test name
Test status
Simulation time 16230701 ps
CPU time 0.74 seconds
Started Jun 29 05:34:50 PM PDT 24
Finished Jun 29 05:34:53 PM PDT 24
Peak memory 199580 kb
Host smart-d7541319-0dc5-4da1-bbcd-84a896895f35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973433951 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.973433951
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.1488682918
Short name T67
Test name
Test status
Simulation time 40424612 ps
CPU time 0.63 seconds
Started Jun 29 05:34:42 PM PDT 24
Finished Jun 29 05:34:43 PM PDT 24
Peak memory 196000 kb
Host smart-cd7a2ee7-c584-46f1-9493-49124b9509d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488682918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1488682918
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.3621144469
Short name T1197
Test name
Test status
Simulation time 21996438 ps
CPU time 0.58 seconds
Started Jun 29 05:34:46 PM PDT 24
Finished Jun 29 05:34:48 PM PDT 24
Peak memory 194796 kb
Host smart-013629f1-24a5-4c73-abb5-c0d7ffd64f3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621144469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.3621144469
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.4264895876
Short name T81
Test name
Test status
Simulation time 176156572 ps
CPU time 0.76 seconds
Started Jun 29 05:34:34 PM PDT 24
Finished Jun 29 05:34:36 PM PDT 24
Peak memory 196280 kb
Host smart-af29a660-869c-46b3-b201-46e63780ef1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264895876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.4264895876
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1886855760
Short name T1214
Test name
Test status
Simulation time 143609521 ps
CPU time 1.49 seconds
Started Jun 29 05:34:45 PM PDT 24
Finished Jun 29 05:34:47 PM PDT 24
Peak memory 200444 kb
Host smart-0a0775f7-b305-43ef-8a22-5b763cffea04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886855760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1886855760
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2281173977
Short name T89
Test name
Test status
Simulation time 220011553 ps
CPU time 1.3 seconds
Started Jun 29 05:34:36 PM PDT 24
Finished Jun 29 05:34:39 PM PDT 24
Peak memory 199412 kb
Host smart-a7988ccc-7a19-4b0d-a9f2-5f4797333ef8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281173977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2281173977
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2422536455
Short name T53
Test name
Test status
Simulation time 22865240 ps
CPU time 0.61 seconds
Started Jun 29 04:48:00 PM PDT 24
Finished Jun 29 04:48:01 PM PDT 24
Peak memory 195552 kb
Host smart-1752db3e-3d96-4fb2-8989-e1c862c9bcc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422536455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2422536455
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.451781591
Short name T178
Test name
Test status
Simulation time 112186542617 ps
CPU time 39.21 seconds
Started Jun 29 04:47:42 PM PDT 24
Finished Jun 29 04:48:21 PM PDT 24
Peak memory 199948 kb
Host smart-03877f2f-9ef4-4ba7-b99a-a55ceaeba66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451781591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.451781591
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.3659316909
Short name T302
Test name
Test status
Simulation time 99886025013 ps
CPU time 163.09 seconds
Started Jun 29 04:47:43 PM PDT 24
Finished Jun 29 04:50:26 PM PDT 24
Peak memory 199908 kb
Host smart-df8f4cfd-9471-44a3-8038-8fcb1997c833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659316909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.3659316909
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.38842018
Short name T1093
Test name
Test status
Simulation time 43395495566 ps
CPU time 60.68 seconds
Started Jun 29 04:47:54 PM PDT 24
Finished Jun 29 04:48:55 PM PDT 24
Peak memory 199868 kb
Host smart-ab8c950f-1101-40a4-9939-608117b4fba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38842018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.38842018
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.2548986833
Short name T553
Test name
Test status
Simulation time 12839687879 ps
CPU time 5.86 seconds
Started Jun 29 04:47:43 PM PDT 24
Finished Jun 29 04:47:50 PM PDT 24
Peak memory 197540 kb
Host smart-2516092f-c3f4-4e06-99d9-05a8e44efa27
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548986833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.2548986833
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.4182656441
Short name T617
Test name
Test status
Simulation time 162663481347 ps
CPU time 1239.33 seconds
Started Jun 29 04:47:41 PM PDT 24
Finished Jun 29 05:08:21 PM PDT 24
Peak memory 199996 kb
Host smart-ce30e725-e853-4af5-bee3-fdcea671b4f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4182656441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.4182656441
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.1814357996
Short name T949
Test name
Test status
Simulation time 138495013 ps
CPU time 0.67 seconds
Started Jun 29 04:47:55 PM PDT 24
Finished Jun 29 04:47:56 PM PDT 24
Peak memory 195888 kb
Host smart-f783d64b-ae12-47d3-9f70-c0f33911bbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814357996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1814357996
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.2767274221
Short name T774
Test name
Test status
Simulation time 134108318185 ps
CPU time 90.54 seconds
Started Jun 29 04:47:46 PM PDT 24
Finished Jun 29 04:49:17 PM PDT 24
Peak memory 200052 kb
Host smart-3a0f45af-140a-40eb-9b7e-2f46ea100610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767274221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.2767274221
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.518196332
Short name T549
Test name
Test status
Simulation time 19594634814 ps
CPU time 302.29 seconds
Started Jun 29 04:47:41 PM PDT 24
Finished Jun 29 04:52:44 PM PDT 24
Peak memory 199996 kb
Host smart-41c8afe2-e609-4f17-b0c8-0bc879ad2c4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=518196332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.518196332
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.748959394
Short name T999
Test name
Test status
Simulation time 3174525741 ps
CPU time 25.09 seconds
Started Jun 29 04:47:50 PM PDT 24
Finished Jun 29 04:48:16 PM PDT 24
Peak memory 199080 kb
Host smart-14ff9216-ac74-426c-b1c7-a047939a2073
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=748959394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.748959394
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.1326341143
Short name T1033
Test name
Test status
Simulation time 29719970864 ps
CPU time 41.09 seconds
Started Jun 29 04:47:54 PM PDT 24
Finished Jun 29 04:48:36 PM PDT 24
Peak memory 199460 kb
Host smart-22f1d55a-15f9-4754-ab92-1a992a003bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326341143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.1326341143
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.3219245383
Short name T882
Test name
Test status
Simulation time 37582928278 ps
CPU time 52.12 seconds
Started Jun 29 04:47:44 PM PDT 24
Finished Jun 29 04:48:37 PM PDT 24
Peak memory 195840 kb
Host smart-be7e9067-fce4-4eb7-a1b5-cbf0f3237418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219245383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.3219245383
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.1151777805
Short name T905
Test name
Test status
Simulation time 109061629 ps
CPU time 0.98 seconds
Started Jun 29 04:47:47 PM PDT 24
Finished Jun 29 04:47:49 PM PDT 24
Peak memory 197596 kb
Host smart-643e369d-0d8f-4fde-b435-3a8533f4ea93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151777805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1151777805
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.43315783
Short name T808
Test name
Test status
Simulation time 40601113244 ps
CPU time 185.73 seconds
Started Jun 29 04:47:44 PM PDT 24
Finished Jun 29 04:50:50 PM PDT 24
Peak memory 199876 kb
Host smart-e50a7263-7780-4a07-afd7-18220d897d94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43315783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.43315783
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.3899497599
Short name T386
Test name
Test status
Simulation time 7358654735 ps
CPU time 8.88 seconds
Started Jun 29 04:47:57 PM PDT 24
Finished Jun 29 04:48:07 PM PDT 24
Peak memory 199972 kb
Host smart-54ae20e1-f8c2-4823-aa62-b5500cd2980a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899497599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.3899497599
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.740160029
Short name T871
Test name
Test status
Simulation time 6771763230 ps
CPU time 3.46 seconds
Started Jun 29 04:47:55 PM PDT 24
Finished Jun 29 04:47:59 PM PDT 24
Peak memory 198716 kb
Host smart-3f76d0a5-f962-4a57-a708-1f2a8c58ae9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740160029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.740160029
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.3193817237
Short name T662
Test name
Test status
Simulation time 24375110 ps
CPU time 0.55 seconds
Started Jun 29 04:47:55 PM PDT 24
Finished Jun 29 04:47:57 PM PDT 24
Peak memory 194232 kb
Host smart-20ddb793-f0e0-4768-a203-28e3d24c612f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193817237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3193817237
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.296741523
Short name T748
Test name
Test status
Simulation time 31811138199 ps
CPU time 28.8 seconds
Started Jun 29 04:47:47 PM PDT 24
Finished Jun 29 04:48:16 PM PDT 24
Peak memory 199972 kb
Host smart-c678e199-fbb4-4122-a36c-8c74151acd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296741523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.296741523
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.899764315
Short name T653
Test name
Test status
Simulation time 218339869725 ps
CPU time 167.74 seconds
Started Jun 29 04:47:56 PM PDT 24
Finished Jun 29 04:50:45 PM PDT 24
Peak memory 199984 kb
Host smart-e32987f9-4584-4dd1-9c4c-05b0b62afc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899764315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.899764315
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2299124081
Short name T897
Test name
Test status
Simulation time 8279716904 ps
CPU time 13.81 seconds
Started Jun 29 04:47:58 PM PDT 24
Finished Jun 29 04:48:13 PM PDT 24
Peak memory 199864 kb
Host smart-71a5badd-bd02-4c8e-b741-b6d288d2251b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299124081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2299124081
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.490859464
Short name T931
Test name
Test status
Simulation time 45518471411 ps
CPU time 60.5 seconds
Started Jun 29 04:48:01 PM PDT 24
Finished Jun 29 04:49:03 PM PDT 24
Peak memory 199956 kb
Host smart-723b8173-d13a-4d8d-b23c-c4293f94283a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490859464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.490859464
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.1171094898
Short name T803
Test name
Test status
Simulation time 142534074697 ps
CPU time 456.19 seconds
Started Jun 29 04:47:40 PM PDT 24
Finished Jun 29 04:55:17 PM PDT 24
Peak memory 199972 kb
Host smart-4681f17f-cc1f-45ed-afea-c935902d3730
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1171094898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1171094898
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.1828572133
Short name T500
Test name
Test status
Simulation time 12499251722 ps
CPU time 5.33 seconds
Started Jun 29 04:47:56 PM PDT 24
Finished Jun 29 04:48:02 PM PDT 24
Peak memory 199900 kb
Host smart-abbf8927-4074-45fa-acf2-d469b26d8a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828572133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1828572133
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_perf.4291823585
Short name T992
Test name
Test status
Simulation time 14082264780 ps
CPU time 144.2 seconds
Started Jun 29 04:47:44 PM PDT 24
Finished Jun 29 04:50:09 PM PDT 24
Peak memory 199880 kb
Host smart-c40faba2-e59a-46a1-85eb-7fabe607c7ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4291823585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.4291823585
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.2024986159
Short name T361
Test name
Test status
Simulation time 5811352243 ps
CPU time 6.3 seconds
Started Jun 29 04:47:55 PM PDT 24
Finished Jun 29 04:48:02 PM PDT 24
Peak memory 198152 kb
Host smart-bcf60392-5100-4f89-8425-5095bb6e26bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2024986159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2024986159
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.2297858605
Short name T853
Test name
Test status
Simulation time 47853764680 ps
CPU time 69.83 seconds
Started Jun 29 04:47:58 PM PDT 24
Finished Jun 29 04:49:09 PM PDT 24
Peak memory 196068 kb
Host smart-14f41e1f-1ab5-4119-acae-e35ec025d055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297858605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2297858605
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.3561569492
Short name T27
Test name
Test status
Simulation time 115568728 ps
CPU time 0.81 seconds
Started Jun 29 04:47:52 PM PDT 24
Finished Jun 29 04:47:54 PM PDT 24
Peak memory 218420 kb
Host smart-2ad09e08-5b04-4169-860f-ed6b8bf1c8f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561569492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3561569492
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.816163519
Short name T606
Test name
Test status
Simulation time 5683617174 ps
CPU time 26.92 seconds
Started Jun 29 04:47:40 PM PDT 24
Finished Jun 29 04:48:07 PM PDT 24
Peak memory 199228 kb
Host smart-8ece0eaa-83ca-4abf-aab0-da8a25d99263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816163519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.816163519
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.2686708564
Short name T902
Test name
Test status
Simulation time 214145798810 ps
CPU time 326.66 seconds
Started Jun 29 04:48:03 PM PDT 24
Finished Jun 29 04:53:30 PM PDT 24
Peak memory 199908 kb
Host smart-ea10e992-b52c-4e8f-b686-64d742b0b80d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686708564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2686708564
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.1064674878
Short name T273
Test name
Test status
Simulation time 7168552867 ps
CPU time 23.25 seconds
Started Jun 29 04:47:52 PM PDT 24
Finished Jun 29 04:48:15 PM PDT 24
Peak memory 199900 kb
Host smart-9c22e865-330c-4da7-8327-9fd05865ccbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064674878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.1064674878
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.1735677511
Short name T275
Test name
Test status
Simulation time 371257944614 ps
CPU time 69.88 seconds
Started Jun 29 04:47:58 PM PDT 24
Finished Jun 29 04:49:08 PM PDT 24
Peak memory 199980 kb
Host smart-dafd15b2-6de2-451e-9d1d-f3ff75f033a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735677511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1735677511
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.1628654313
Short name T854
Test name
Test status
Simulation time 10898659 ps
CPU time 0.59 seconds
Started Jun 29 04:48:10 PM PDT 24
Finished Jun 29 04:48:12 PM PDT 24
Peak memory 195284 kb
Host smart-532a0e90-8bdf-433a-b56d-5f7109a55205
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628654313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.1628654313
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.248467451
Short name T477
Test name
Test status
Simulation time 24979718045 ps
CPU time 40.29 seconds
Started Jun 29 04:48:04 PM PDT 24
Finished Jun 29 04:48:45 PM PDT 24
Peak memory 199972 kb
Host smart-cbeefcd6-0643-459d-8c68-66163eebde51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248467451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.248467451
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.2875296833
Short name T825
Test name
Test status
Simulation time 55119636702 ps
CPU time 33.42 seconds
Started Jun 29 04:48:10 PM PDT 24
Finished Jun 29 04:48:44 PM PDT 24
Peak memory 199588 kb
Host smart-fd6299f4-4b8c-4482-b05b-7e5794aa2100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875296833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2875296833
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.1841461105
Short name T186
Test name
Test status
Simulation time 9594461119 ps
CPU time 17.3 seconds
Started Jun 29 04:48:08 PM PDT 24
Finished Jun 29 04:48:26 PM PDT 24
Peak memory 199804 kb
Host smart-c45644be-c998-404b-a3c2-bd7dd39e310d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841461105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1841461105
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.3995440636
Short name T690
Test name
Test status
Simulation time 78189570326 ps
CPU time 77.85 seconds
Started Jun 29 04:48:08 PM PDT 24
Finished Jun 29 04:49:27 PM PDT 24
Peak memory 199896 kb
Host smart-5d2f8850-f8dd-40c6-b249-c1e11f3269c0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995440636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3995440636
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.3161884375
Short name T1035
Test name
Test status
Simulation time 45339884600 ps
CPU time 79.12 seconds
Started Jun 29 04:48:11 PM PDT 24
Finished Jun 29 04:49:31 PM PDT 24
Peak memory 199888 kb
Host smart-1e2c9981-b012-4665-a7b5-bbfeaa0c3454
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3161884375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3161884375
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.995287764
Short name T593
Test name
Test status
Simulation time 10043126750 ps
CPU time 22.63 seconds
Started Jun 29 04:48:23 PM PDT 24
Finished Jun 29 04:48:46 PM PDT 24
Peak memory 199792 kb
Host smart-b6da6817-27b7-4218-90bd-2652b8dd70ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995287764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.995287764
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_perf.761875859
Short name T665
Test name
Test status
Simulation time 12047882228 ps
CPU time 274.25 seconds
Started Jun 29 04:48:08 PM PDT 24
Finished Jun 29 04:52:43 PM PDT 24
Peak memory 199920 kb
Host smart-89ad6a39-d425-42a6-bf8d-e36d1afc68d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=761875859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.761875859
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.1632859234
Short name T797
Test name
Test status
Simulation time 4425689206 ps
CPU time 15.51 seconds
Started Jun 29 04:48:08 PM PDT 24
Finished Jun 29 04:48:24 PM PDT 24
Peak memory 199268 kb
Host smart-fcee4226-6a1d-4d8e-b12a-93cedaac812c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1632859234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.1632859234
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.3012123466
Short name T167
Test name
Test status
Simulation time 181338645042 ps
CPU time 74.27 seconds
Started Jun 29 04:48:23 PM PDT 24
Finished Jun 29 04:49:38 PM PDT 24
Peak memory 199932 kb
Host smart-abbbedba-ec65-4d50-8e77-1acbd20944ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012123466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3012123466
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3903555382
Short name T571
Test name
Test status
Simulation time 4811505684 ps
CPU time 4.21 seconds
Started Jun 29 04:48:04 PM PDT 24
Finished Jun 29 04:48:09 PM PDT 24
Peak memory 196044 kb
Host smart-0ebf2119-7fad-431c-a153-da2fe9c6ec30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903555382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3903555382
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.1121119887
Short name T768
Test name
Test status
Simulation time 6286298728 ps
CPU time 19.99 seconds
Started Jun 29 04:48:10 PM PDT 24
Finished Jun 29 04:48:31 PM PDT 24
Peak memory 199100 kb
Host smart-b16c7cd4-d44b-40b2-be7a-7e148c31798b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121119887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.1121119887
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.632968260
Short name T323
Test name
Test status
Simulation time 106706336049 ps
CPU time 106.37 seconds
Started Jun 29 04:48:15 PM PDT 24
Finished Jun 29 04:50:02 PM PDT 24
Peak memory 199824 kb
Host smart-99fa5748-c859-42c8-a64e-04e5f9616101
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632968260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.632968260
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.4090030882
Short name T1013
Test name
Test status
Simulation time 1739471912 ps
CPU time 1.75 seconds
Started Jun 29 04:48:23 PM PDT 24
Finished Jun 29 04:48:25 PM PDT 24
Peak memory 199708 kb
Host smart-55e3fae6-a261-44b8-a360-a2d54448682c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090030882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.4090030882
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.878435474
Short name T456
Test name
Test status
Simulation time 61201655741 ps
CPU time 87.02 seconds
Started Jun 29 04:48:02 PM PDT 24
Finished Jun 29 04:49:30 PM PDT 24
Peak memory 199736 kb
Host smart-796925c8-9e4c-4bfa-bb57-8624ff57da41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878435474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.878435474
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.513200449
Short name T8
Test name
Test status
Simulation time 43389092382 ps
CPU time 73.51 seconds
Started Jun 29 04:50:51 PM PDT 24
Finished Jun 29 04:52:05 PM PDT 24
Peak memory 199936 kb
Host smart-e5ba55d4-6322-4f2d-b84a-d59f153fe05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513200449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.513200449
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.4190054901
Short name T322
Test name
Test status
Simulation time 62048292242 ps
CPU time 25.08 seconds
Started Jun 29 04:50:50 PM PDT 24
Finished Jun 29 04:51:16 PM PDT 24
Peak memory 199968 kb
Host smart-220ba50f-6e1c-49e0-a891-05d274cd3ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190054901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.4190054901
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.3911396944
Short name T1043
Test name
Test status
Simulation time 134257709450 ps
CPU time 23.09 seconds
Started Jun 29 04:50:51 PM PDT 24
Finished Jun 29 04:51:14 PM PDT 24
Peak memory 199720 kb
Host smart-616120ba-bcab-45d9-a96e-c37f06c8e766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911396944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.3911396944
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.3492266014
Short name T55
Test name
Test status
Simulation time 176656198034 ps
CPU time 16.36 seconds
Started Jun 29 04:50:51 PM PDT 24
Finished Jun 29 04:51:08 PM PDT 24
Peak memory 199840 kb
Host smart-965a1c3c-ca19-4f5a-84fe-ebbb18825b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492266014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3492266014
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.3359808777
Short name T37
Test name
Test status
Simulation time 149130911280 ps
CPU time 51.36 seconds
Started Jun 29 04:50:52 PM PDT 24
Finished Jun 29 04:51:44 PM PDT 24
Peak memory 200012 kb
Host smart-470d674a-1042-421d-a821-73a5717791b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359808777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3359808777
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.722001798
Short name T761
Test name
Test status
Simulation time 17908567655 ps
CPU time 28.42 seconds
Started Jun 29 04:50:53 PM PDT 24
Finished Jun 29 04:51:22 PM PDT 24
Peak memory 199928 kb
Host smart-a090312b-5138-4686-aaea-1dcfffd92abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722001798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.722001798
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.3435280626
Short name T424
Test name
Test status
Simulation time 38723767965 ps
CPU time 51.57 seconds
Started Jun 29 04:50:50 PM PDT 24
Finished Jun 29 04:51:42 PM PDT 24
Peak memory 199988 kb
Host smart-901a4187-3977-4ff8-b378-910b6f0da13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435280626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3435280626
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_full.974594403
Short name T127
Test name
Test status
Simulation time 46512544493 ps
CPU time 60.03 seconds
Started Jun 29 04:48:16 PM PDT 24
Finished Jun 29 04:49:17 PM PDT 24
Peak memory 199932 kb
Host smart-abead732-2b68-44cb-8db1-6ab98671a49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974594403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.974594403
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.3851111890
Short name T967
Test name
Test status
Simulation time 34663478153 ps
CPU time 57.67 seconds
Started Jun 29 04:48:15 PM PDT 24
Finished Jun 29 04:49:14 PM PDT 24
Peak memory 199916 kb
Host smart-7a62497a-eb2f-4f6a-8b97-4c27488843f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851111890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3851111890
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_intr.1118105086
Short name T1008
Test name
Test status
Simulation time 58875137958 ps
CPU time 29.45 seconds
Started Jun 29 04:48:21 PM PDT 24
Finished Jun 29 04:48:51 PM PDT 24
Peak memory 199980 kb
Host smart-dff775eb-e3a9-4e6b-a505-17970be0ec01
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118105086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1118105086
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.815036713
Short name T475
Test name
Test status
Simulation time 65677699107 ps
CPU time 282.22 seconds
Started Jun 29 04:48:12 PM PDT 24
Finished Jun 29 04:52:55 PM PDT 24
Peak memory 199932 kb
Host smart-7deb1bad-4ae8-4781-ba63-eb036acca3d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=815036713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.815036713
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.2295525530
Short name T376
Test name
Test status
Simulation time 6902321358 ps
CPU time 2.27 seconds
Started Jun 29 04:48:11 PM PDT 24
Finished Jun 29 04:48:14 PM PDT 24
Peak memory 199624 kb
Host smart-894b3d06-b56f-45d8-9fb9-7fa0dfabaf49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295525530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2295525530
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_perf.1450902598
Short name T529
Test name
Test status
Simulation time 9210080568 ps
CPU time 88.85 seconds
Started Jun 29 04:48:15 PM PDT 24
Finished Jun 29 04:49:45 PM PDT 24
Peak memory 199896 kb
Host smart-1b60716a-94d7-4f15-a20d-27568c34baa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1450902598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1450902598
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.4053128815
Short name T970
Test name
Test status
Simulation time 2664034451 ps
CPU time 5.94 seconds
Started Jun 29 04:48:12 PM PDT 24
Finished Jun 29 04:48:19 PM PDT 24
Peak memory 198856 kb
Host smart-c41cb81b-60c5-4ce3-a7cf-6c68016bc6b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4053128815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.4053128815
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.3883847706
Short name T625
Test name
Test status
Simulation time 28142675257 ps
CPU time 49.48 seconds
Started Jun 29 04:48:15 PM PDT 24
Finished Jun 29 04:49:05 PM PDT 24
Peak memory 200008 kb
Host smart-3ae46505-1cf4-47fd-b6fd-f3f7616a4fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883847706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3883847706
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.1986284291
Short name T1097
Test name
Test status
Simulation time 2119941392 ps
CPU time 1.44 seconds
Started Jun 29 04:48:09 PM PDT 24
Finished Jun 29 04:48:11 PM PDT 24
Peak memory 195576 kb
Host smart-70968a89-cf85-4322-bffd-a5112d9641c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986284291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.1986284291
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.4098505088
Short name T1056
Test name
Test status
Simulation time 914711707 ps
CPU time 1.98 seconds
Started Jun 29 04:48:09 PM PDT 24
Finished Jun 29 04:48:12 PM PDT 24
Peak memory 198700 kb
Host smart-2a27eaa2-7b0a-4ceb-a447-426491a1ba84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098505088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.4098505088
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.2029714254
Short name T814
Test name
Test status
Simulation time 314480210268 ps
CPU time 266.04 seconds
Started Jun 29 04:48:32 PM PDT 24
Finished Jun 29 04:52:59 PM PDT 24
Peak memory 199812 kb
Host smart-84702dee-74bc-4781-94bf-c6db06da13f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029714254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.2029714254
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2542622573
Short name T799
Test name
Test status
Simulation time 6556424623 ps
CPU time 9.12 seconds
Started Jun 29 04:48:16 PM PDT 24
Finished Jun 29 04:48:26 PM PDT 24
Peak memory 199264 kb
Host smart-31b9bc21-2a94-423d-9b45-1549c285f08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542622573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2542622573
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.2731583424
Short name T98
Test name
Test status
Simulation time 90446368586 ps
CPU time 139.57 seconds
Started Jun 29 04:48:16 PM PDT 24
Finished Jun 29 04:50:37 PM PDT 24
Peak memory 199996 kb
Host smart-8a2207c3-0be0-4dd8-9c94-ddaad57d25d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731583424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2731583424
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.487240173
Short name T217
Test name
Test status
Simulation time 25176645987 ps
CPU time 9.87 seconds
Started Jun 29 04:50:51 PM PDT 24
Finished Jun 29 04:51:01 PM PDT 24
Peak memory 199680 kb
Host smart-8a0799e4-3d78-44f4-86e0-b40e84342ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487240173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.487240173
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.570525533
Short name T733
Test name
Test status
Simulation time 117814667671 ps
CPU time 90.8 seconds
Started Jun 29 04:50:58 PM PDT 24
Finished Jun 29 04:52:29 PM PDT 24
Peak memory 199968 kb
Host smart-a7471c7c-92b3-472e-b257-ce33bd18357a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570525533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.570525533
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.172580863
Short name T612
Test name
Test status
Simulation time 39875495629 ps
CPU time 17.61 seconds
Started Jun 29 04:50:59 PM PDT 24
Finished Jun 29 04:51:17 PM PDT 24
Peak memory 199920 kb
Host smart-3d81555e-fa01-4443-b125-b5174259eb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172580863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.172580863
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.122237123
Short name T816
Test name
Test status
Simulation time 106137012187 ps
CPU time 38.16 seconds
Started Jun 29 04:51:01 PM PDT 24
Finished Jun 29 04:51:39 PM PDT 24
Peak memory 199792 kb
Host smart-ef103fa0-11eb-4421-b954-d9b715f49155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122237123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.122237123
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2235662826
Short name T523
Test name
Test status
Simulation time 56021920912 ps
CPU time 151.29 seconds
Started Jun 29 04:50:59 PM PDT 24
Finished Jun 29 04:53:31 PM PDT 24
Peak memory 199904 kb
Host smart-e69e62ef-823f-4061-bad7-4d5d05cf8266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235662826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2235662826
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.703627719
Short name T901
Test name
Test status
Simulation time 104973152074 ps
CPU time 37.74 seconds
Started Jun 29 04:50:57 PM PDT 24
Finished Jun 29 04:51:36 PM PDT 24
Peak memory 200136 kb
Host smart-a8d4f567-568b-476f-8b46-3732c0d67537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703627719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.703627719
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.3658504634
Short name T883
Test name
Test status
Simulation time 39165874939 ps
CPU time 63.57 seconds
Started Jun 29 04:50:58 PM PDT 24
Finished Jun 29 04:52:03 PM PDT 24
Peak memory 199892 kb
Host smart-3baf9ed5-7519-478b-832b-77ac3fb92a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658504634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3658504634
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.807277252
Short name T645
Test name
Test status
Simulation time 17954051 ps
CPU time 0.56 seconds
Started Jun 29 04:48:16 PM PDT 24
Finished Jun 29 04:48:18 PM PDT 24
Peak memory 194756 kb
Host smart-6c6539e5-1c61-4724-a7b8-867535531b0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807277252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.807277252
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3857828477
Short name T870
Test name
Test status
Simulation time 132234948120 ps
CPU time 78.29 seconds
Started Jun 29 04:48:11 PM PDT 24
Finished Jun 29 04:49:30 PM PDT 24
Peak memory 199908 kb
Host smart-affc9b71-9bf8-40ff-9fa2-2a8b3e825f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857828477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3857828477
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.37239831
Short name T547
Test name
Test status
Simulation time 49003835206 ps
CPU time 19.69 seconds
Started Jun 29 04:48:17 PM PDT 24
Finished Jun 29 04:48:38 PM PDT 24
Peak memory 199916 kb
Host smart-ceba9014-1ea0-4a0d-af21-3d49f827861e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37239831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.37239831
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.3635168861
Short name T343
Test name
Test status
Simulation time 91972652974 ps
CPU time 64.9 seconds
Started Jun 29 04:48:25 PM PDT 24
Finished Jun 29 04:49:31 PM PDT 24
Peak memory 199916 kb
Host smart-f1172816-a824-4fb5-8aae-706d8132acc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635168861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.3635168861
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.2970161912
Short name T340
Test name
Test status
Simulation time 57258463134 ps
CPU time 48.19 seconds
Started Jun 29 04:48:12 PM PDT 24
Finished Jun 29 04:49:01 PM PDT 24
Peak memory 199980 kb
Host smart-2ee9474a-c109-4dde-addc-fa14abf825d7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970161912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2970161912
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.2766669357
Short name T639
Test name
Test status
Simulation time 86199355743 ps
CPU time 143.48 seconds
Started Jun 29 04:48:04 PM PDT 24
Finished Jun 29 04:50:28 PM PDT 24
Peak memory 199972 kb
Host smart-9b80f220-850b-4719-81b1-63b3c2ac0148
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2766669357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2766669357
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.4158751655
Short name T403
Test name
Test status
Simulation time 9249098873 ps
CPU time 5.3 seconds
Started Jun 29 04:48:17 PM PDT 24
Finished Jun 29 04:48:23 PM PDT 24
Peak memory 198348 kb
Host smart-1ec259d9-e535-4889-b1a4-3ecf9afe99d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158751655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.4158751655
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_perf.1931535045
Short name T580
Test name
Test status
Simulation time 16417965108 ps
CPU time 127.87 seconds
Started Jun 29 04:48:14 PM PDT 24
Finished Jun 29 04:50:22 PM PDT 24
Peak memory 199980 kb
Host smart-c6c00a67-c5e1-4597-a3f9-319581f043ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1931535045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1931535045
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.1636115732
Short name T95
Test name
Test status
Simulation time 7086209828 ps
CPU time 69 seconds
Started Jun 29 04:48:03 PM PDT 24
Finished Jun 29 04:49:12 PM PDT 24
Peak memory 198308 kb
Host smart-1b9cfc58-cd8d-4018-837c-806e0b2edac1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1636115732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1636115732
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.4035104442
Short name T509
Test name
Test status
Simulation time 159206917186 ps
CPU time 69.37 seconds
Started Jun 29 04:48:22 PM PDT 24
Finished Jun 29 04:49:32 PM PDT 24
Peak memory 199836 kb
Host smart-c458cff0-967c-47ed-a66e-4c5d1d80a7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035104442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.4035104442
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.318421772
Short name T773
Test name
Test status
Simulation time 3098648355 ps
CPU time 1.32 seconds
Started Jun 29 04:48:12 PM PDT 24
Finished Jun 29 04:48:14 PM PDT 24
Peak memory 196400 kb
Host smart-92d523e4-5e84-44dc-b2bc-dc59b5e09a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318421772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.318421772
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.607599885
Short name T679
Test name
Test status
Simulation time 5875811882 ps
CPU time 7.21 seconds
Started Jun 29 04:48:27 PM PDT 24
Finished Jun 29 04:48:34 PM PDT 24
Peak memory 199836 kb
Host smart-1231da47-4532-4fa1-acc7-71b32bb9f5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607599885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.607599885
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.1151952273
Short name T458
Test name
Test status
Simulation time 434977009723 ps
CPU time 477.88 seconds
Started Jun 29 04:48:31 PM PDT 24
Finished Jun 29 04:56:30 PM PDT 24
Peak memory 199968 kb
Host smart-c5946f40-b6d4-4747-b092-ab9ee205f57b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151952273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1151952273
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.2876911798
Short name T896
Test name
Test status
Simulation time 838025421 ps
CPU time 5.44 seconds
Started Jun 29 04:48:27 PM PDT 24
Finished Jun 29 04:48:33 PM PDT 24
Peak memory 198256 kb
Host smart-c67cdc64-0864-4c50-97be-94d219f0391d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876911798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.2876911798
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.3244800563
Short name T859
Test name
Test status
Simulation time 34938558307 ps
CPU time 26.67 seconds
Started Jun 29 04:48:13 PM PDT 24
Finished Jun 29 04:48:40 PM PDT 24
Peak memory 199888 kb
Host smart-67ed24d4-82a5-4aaf-a88f-592a0fc29e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244800563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.3244800563
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.2181886260
Short name T1049
Test name
Test status
Simulation time 17391825380 ps
CPU time 12.96 seconds
Started Jun 29 04:50:58 PM PDT 24
Finished Jun 29 04:51:11 PM PDT 24
Peak memory 198888 kb
Host smart-f79919e5-9671-4934-9784-fb2f4cef8221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181886260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.2181886260
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.1790273967
Short name T568
Test name
Test status
Simulation time 143093674422 ps
CPU time 219.02 seconds
Started Jun 29 04:51:02 PM PDT 24
Finished Jun 29 04:54:41 PM PDT 24
Peak memory 199680 kb
Host smart-0ef79f3c-2e5f-4c54-983c-97181ccbfa3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790273967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1790273967
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.1513543746
Short name T348
Test name
Test status
Simulation time 163915954641 ps
CPU time 118.93 seconds
Started Jun 29 04:51:00 PM PDT 24
Finished Jun 29 04:52:59 PM PDT 24
Peak memory 199988 kb
Host smart-c73235e9-4553-4a90-878d-3998cd388789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513543746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1513543746
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.772185891
Short name T374
Test name
Test status
Simulation time 109710727113 ps
CPU time 161.17 seconds
Started Jun 29 04:51:01 PM PDT 24
Finished Jun 29 04:53:43 PM PDT 24
Peak memory 199952 kb
Host smart-9545415a-11db-4a78-a317-c396faae7623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772185891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.772185891
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.3672197922
Short name T885
Test name
Test status
Simulation time 117710386022 ps
CPU time 47.34 seconds
Started Jun 29 04:50:58 PM PDT 24
Finished Jun 29 04:51:46 PM PDT 24
Peak memory 199904 kb
Host smart-6d84eb57-0b62-4979-86eb-ecb5d18b75eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672197922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.3672197922
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.3539160662
Short name T570
Test name
Test status
Simulation time 15888691814 ps
CPU time 20.94 seconds
Started Jun 29 04:51:00 PM PDT 24
Finished Jun 29 04:51:21 PM PDT 24
Peak memory 199728 kb
Host smart-e05aea91-e32f-438e-8e8a-1d01cdd89ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539160662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.3539160662
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.3723498216
Short name T491
Test name
Test status
Simulation time 17695908140 ps
CPU time 30.03 seconds
Started Jun 29 04:50:57 PM PDT 24
Finished Jun 29 04:51:27 PM PDT 24
Peak memory 199752 kb
Host smart-e6253d6c-0bc1-4471-afdb-916d415826ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723498216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3723498216
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.2582582841
Short name T23
Test name
Test status
Simulation time 13702007 ps
CPU time 0.64 seconds
Started Jun 29 04:48:23 PM PDT 24
Finished Jun 29 04:48:24 PM PDT 24
Peak memory 195296 kb
Host smart-ea064a8a-d7ed-4a84-89af-97c929fcabcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582582841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.2582582841
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.3976700442
Short name T417
Test name
Test status
Simulation time 183152841948 ps
CPU time 90.8 seconds
Started Jun 29 04:48:25 PM PDT 24
Finished Jun 29 04:49:56 PM PDT 24
Peak memory 200016 kb
Host smart-b1e2f051-3597-4edb-a675-3d2fbf711540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976700442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.3976700442
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.3774577834
Short name T1017
Test name
Test status
Simulation time 41333655021 ps
CPU time 54.15 seconds
Started Jun 29 04:48:10 PM PDT 24
Finished Jun 29 04:49:05 PM PDT 24
Peak memory 199984 kb
Host smart-64a0a60e-05c9-4037-97af-9ef8ec6b6f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774577834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.3774577834
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.2627532249
Short name T466
Test name
Test status
Simulation time 42864783046 ps
CPU time 58.47 seconds
Started Jun 29 04:48:17 PM PDT 24
Finished Jun 29 04:49:17 PM PDT 24
Peak memory 199988 kb
Host smart-28c6cc32-b7de-4bed-900d-2528b2967c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627532249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2627532249
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.2492519337
Short name T464
Test name
Test status
Simulation time 15588548682 ps
CPU time 24.15 seconds
Started Jun 29 04:48:20 PM PDT 24
Finished Jun 29 04:48:45 PM PDT 24
Peak memory 199908 kb
Host smart-7520fa36-9f0d-47c0-9017-4ba38543b230
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492519337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2492519337
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.2283350391
Short name T864
Test name
Test status
Simulation time 97225398424 ps
CPU time 361.46 seconds
Started Jun 29 04:48:24 PM PDT 24
Finished Jun 29 04:54:26 PM PDT 24
Peak memory 199992 kb
Host smart-dd160051-1625-4b31-8e47-94cf1b0bffb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2283350391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2283350391
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.2346798941
Short name T517
Test name
Test status
Simulation time 9069988258 ps
CPU time 24.68 seconds
Started Jun 29 04:48:15 PM PDT 24
Finished Jun 29 04:48:41 PM PDT 24
Peak memory 199824 kb
Host smart-1e6e9a7a-bbf7-4e8e-9246-7440127e99f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346798941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.2346798941
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.761486438
Short name T558
Test name
Test status
Simulation time 10757459668 ps
CPU time 17.11 seconds
Started Jun 29 04:48:22 PM PDT 24
Finished Jun 29 04:48:40 PM PDT 24
Peak memory 199988 kb
Host smart-5a0775af-ec9d-41b8-b2c4-bc6be3bf2dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761486438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.761486438
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.2731468383
Short name T18
Test name
Test status
Simulation time 10344722547 ps
CPU time 510.85 seconds
Started Jun 29 04:48:17 PM PDT 24
Finished Jun 29 04:56:49 PM PDT 24
Peak memory 199980 kb
Host smart-432a2e19-5ca8-4989-a9c0-3d9bd99e264c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2731468383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2731468383
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.3524300274
Short name T802
Test name
Test status
Simulation time 4612977344 ps
CPU time 34.89 seconds
Started Jun 29 04:48:13 PM PDT 24
Finished Jun 29 04:48:48 PM PDT 24
Peak memory 199148 kb
Host smart-e6f776d1-bc96-4b14-a1d8-0872226a6919
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3524300274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3524300274
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.3828409792
Short name T849
Test name
Test status
Simulation time 48507465304 ps
CPU time 46.6 seconds
Started Jun 29 04:48:15 PM PDT 24
Finished Jun 29 04:49:03 PM PDT 24
Peak memory 199868 kb
Host smart-693a828c-9b0d-4a82-a981-0ca0174a13f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828409792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3828409792
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.2670090439
Short name T635
Test name
Test status
Simulation time 2519653135 ps
CPU time 4.64 seconds
Started Jun 29 04:48:16 PM PDT 24
Finished Jun 29 04:48:22 PM PDT 24
Peak memory 195656 kb
Host smart-5d161b7e-7a40-4c5f-97ca-c47a4d3ee7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670090439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2670090439
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.658018784
Short name T721
Test name
Test status
Simulation time 584020885 ps
CPU time 1.28 seconds
Started Jun 29 04:48:15 PM PDT 24
Finished Jun 29 04:48:17 PM PDT 24
Peak memory 198812 kb
Host smart-821a247c-5521-45dc-b043-a9f8c8e5c48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658018784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.658018784
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.1265602355
Short name T1081
Test name
Test status
Simulation time 48462671297 ps
CPU time 423.89 seconds
Started Jun 29 04:48:22 PM PDT 24
Finished Jun 29 04:55:27 PM PDT 24
Peak memory 199912 kb
Host smart-87b9a5c9-4ad4-4c12-a7d4-aa12f2f7d675
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265602355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1265602355
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.622946381
Short name T105
Test name
Test status
Simulation time 288447211900 ps
CPU time 484.73 seconds
Started Jun 29 04:48:31 PM PDT 24
Finished Jun 29 04:56:37 PM PDT 24
Peak memory 216444 kb
Host smart-a04ba58d-ab48-46e3-bfa0-6a85c6b77b84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622946381 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.622946381
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.2642215545
Short name T510
Test name
Test status
Simulation time 453277697 ps
CPU time 1.42 seconds
Started Jun 29 04:48:17 PM PDT 24
Finished Jun 29 04:48:19 PM PDT 24
Peak memory 198296 kb
Host smart-51ea5339-4af5-4b53-9550-0604f7c1c1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642215545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.2642215545
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.3346776933
Short name T339
Test name
Test status
Simulation time 38387222143 ps
CPU time 65.21 seconds
Started Jun 29 04:48:28 PM PDT 24
Finished Jun 29 04:49:34 PM PDT 24
Peak memory 199920 kb
Host smart-3e339f9f-bd53-441d-abd8-12e32b191125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346776933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3346776933
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.3534717572
Short name T188
Test name
Test status
Simulation time 292033878413 ps
CPU time 126.4 seconds
Started Jun 29 04:51:01 PM PDT 24
Finished Jun 29 04:53:07 PM PDT 24
Peak memory 199716 kb
Host smart-ec4a4928-a15b-4b3b-b943-ab1536e50f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534717572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3534717572
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.2519128719
Short name T131
Test name
Test status
Simulation time 68132612189 ps
CPU time 96.34 seconds
Started Jun 29 04:50:59 PM PDT 24
Finished Jun 29 04:52:36 PM PDT 24
Peak memory 199924 kb
Host smart-c8db072f-0b16-470b-b87d-0d99258e329d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519128719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2519128719
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.2447210380
Short name T928
Test name
Test status
Simulation time 81725175666 ps
CPU time 128.52 seconds
Started Jun 29 04:51:01 PM PDT 24
Finished Jun 29 04:53:10 PM PDT 24
Peak memory 199708 kb
Host smart-1e6edca0-5ede-4279-a8a8-5f35d6d6eafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447210380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2447210380
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.2271460731
Short name T840
Test name
Test status
Simulation time 22409402936 ps
CPU time 27.6 seconds
Started Jun 29 04:51:02 PM PDT 24
Finished Jun 29 04:51:30 PM PDT 24
Peak memory 199348 kb
Host smart-e93e92a8-c2f9-4272-9cbe-0a05421f4f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271460731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.2271460731
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.2853144349
Short name T481
Test name
Test status
Simulation time 122929329409 ps
CPU time 44.63 seconds
Started Jun 29 04:50:57 PM PDT 24
Finished Jun 29 04:51:42 PM PDT 24
Peak memory 199676 kb
Host smart-d36dc24a-323c-4c8f-a070-22c9ebe020fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853144349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.2853144349
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.2917977215
Short name T783
Test name
Test status
Simulation time 19225386391 ps
CPU time 11.8 seconds
Started Jun 29 04:51:02 PM PDT 24
Finished Jun 29 04:51:14 PM PDT 24
Peak memory 199828 kb
Host smart-3bf20880-de54-44e9-9cb5-5fdb6fb7a3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917977215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.2917977215
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2244546755
Short name T414
Test name
Test status
Simulation time 83762389815 ps
CPU time 23.68 seconds
Started Jun 29 04:50:59 PM PDT 24
Finished Jun 29 04:51:23 PM PDT 24
Peak memory 199904 kb
Host smart-67496da7-5580-471d-82e3-29226e8e48dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244546755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2244546755
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.289492159
Short name T344
Test name
Test status
Simulation time 109414604481 ps
CPU time 18.24 seconds
Started Jun 29 04:51:02 PM PDT 24
Finished Jun 29 04:51:20 PM PDT 24
Peak memory 199952 kb
Host smart-e5e7009a-82f7-42ff-995d-9fac875f82f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289492159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.289492159
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.1581794238
Short name T599
Test name
Test status
Simulation time 14565679 ps
CPU time 0.56 seconds
Started Jun 29 04:48:15 PM PDT 24
Finished Jun 29 04:48:16 PM PDT 24
Peak memory 195304 kb
Host smart-321a149a-1a9a-4f94-8562-44b8b41fb642
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581794238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1581794238
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.165352631
Short name T792
Test name
Test status
Simulation time 47048213869 ps
CPU time 68.49 seconds
Started Jun 29 04:48:29 PM PDT 24
Finished Jun 29 04:49:38 PM PDT 24
Peak memory 199812 kb
Host smart-fbdbd465-9e07-49b1-b8fd-e5e3add22021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165352631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.165352631
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.201175986
Short name T42
Test name
Test status
Simulation time 48778169652 ps
CPU time 37.63 seconds
Started Jun 29 04:48:26 PM PDT 24
Finished Jun 29 04:49:04 PM PDT 24
Peak memory 199968 kb
Host smart-6782b955-36c8-4810-bb1b-08a60a5c5728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201175986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.201175986
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.2703589394
Short name T1010
Test name
Test status
Simulation time 56038646505 ps
CPU time 84.92 seconds
Started Jun 29 04:48:20 PM PDT 24
Finished Jun 29 04:49:45 PM PDT 24
Peak memory 199988 kb
Host smart-c52ab701-a16a-4130-9506-71f25cf8be83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703589394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.2703589394
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.4065583326
Short name T96
Test name
Test status
Simulation time 14685742601 ps
CPU time 8.77 seconds
Started Jun 29 04:48:13 PM PDT 24
Finished Jun 29 04:48:22 PM PDT 24
Peak memory 199928 kb
Host smart-254934a5-bc52-4b4e-838d-78118fcf8479
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065583326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.4065583326
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.559153992
Short name T649
Test name
Test status
Simulation time 59069367181 ps
CPU time 319.35 seconds
Started Jun 29 04:48:16 PM PDT 24
Finished Jun 29 04:53:36 PM PDT 24
Peak memory 199952 kb
Host smart-546a2f9d-e02f-4cd5-9cc4-4aea6999e51e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=559153992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.559153992
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3384697234
Short name T398
Test name
Test status
Simulation time 13185652824 ps
CPU time 18.94 seconds
Started Jun 29 04:48:16 PM PDT 24
Finished Jun 29 04:48:37 PM PDT 24
Peak memory 199836 kb
Host smart-032c9acc-d21f-4123-88c4-16bcfa11a454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384697234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3384697234
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_perf.1115325329
Short name T644
Test name
Test status
Simulation time 16154808909 ps
CPU time 856.91 seconds
Started Jun 29 04:48:28 PM PDT 24
Finished Jun 29 05:02:46 PM PDT 24
Peak memory 199980 kb
Host smart-b50d6112-6d25-455e-929d-77e9bcd5409b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1115325329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1115325329
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.4268790349
Short name T1029
Test name
Test status
Simulation time 2661775557 ps
CPU time 5.08 seconds
Started Jun 29 04:48:15 PM PDT 24
Finished Jun 29 04:48:21 PM PDT 24
Peak memory 199284 kb
Host smart-489f09aa-8097-4860-b4aa-9dfa33b82af4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4268790349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.4268790349
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.1289484707
Short name T842
Test name
Test status
Simulation time 49735592325 ps
CPU time 75.55 seconds
Started Jun 29 04:48:17 PM PDT 24
Finished Jun 29 04:49:34 PM PDT 24
Peak memory 199964 kb
Host smart-4f16666f-5728-4f72-952a-bbdc80d0e470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289484707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1289484707
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1227437395
Short name T921
Test name
Test status
Simulation time 49708390067 ps
CPU time 10.71 seconds
Started Jun 29 04:48:33 PM PDT 24
Finished Jun 29 04:48:44 PM PDT 24
Peak memory 196224 kb
Host smart-230f8541-52cc-4840-a7cb-86b3f05086f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227437395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1227437395
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.552527961
Short name T589
Test name
Test status
Simulation time 106058382 ps
CPU time 0.81 seconds
Started Jun 29 04:48:14 PM PDT 24
Finished Jun 29 04:48:16 PM PDT 24
Peak memory 196784 kb
Host smart-c4cefd12-43e3-4f3f-95ca-0c47de5f5ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552527961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.552527961
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.235266855
Short name T518
Test name
Test status
Simulation time 163650741 ps
CPU time 1 seconds
Started Jun 29 04:48:17 PM PDT 24
Finished Jun 29 04:48:19 PM PDT 24
Peak memory 197192 kb
Host smart-04d38d45-1274-499d-9745-7c06af076dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235266855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.235266855
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.29134832
Short name T782
Test name
Test status
Simulation time 45644067207 ps
CPU time 92.09 seconds
Started Jun 29 04:48:15 PM PDT 24
Finished Jun 29 04:49:48 PM PDT 24
Peak memory 199920 kb
Host smart-1ca00ecd-6cac-40fb-8306-0b9e2199dd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29134832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.29134832
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.2537233714
Short name T469
Test name
Test status
Simulation time 189998227776 ps
CPU time 59.65 seconds
Started Jun 29 04:50:55 PM PDT 24
Finished Jun 29 04:51:55 PM PDT 24
Peak memory 199940 kb
Host smart-b816c9fe-d620-4f89-b321-c5c5ceff6566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537233714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.2537233714
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.1450080316
Short name T1040
Test name
Test status
Simulation time 42059225727 ps
CPU time 70.32 seconds
Started Jun 29 04:51:02 PM PDT 24
Finished Jun 29 04:52:13 PM PDT 24
Peak memory 199904 kb
Host smart-a0f63840-fa84-49c4-b0a9-45398c609567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450080316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1450080316
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.880810200
Short name T1075
Test name
Test status
Simulation time 77965565402 ps
CPU time 223.4 seconds
Started Jun 29 04:50:58 PM PDT 24
Finished Jun 29 04:54:42 PM PDT 24
Peak memory 199952 kb
Host smart-79d90e7d-7105-46e9-891c-d27a8cb77de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880810200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.880810200
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3254927871
Short name T1018
Test name
Test status
Simulation time 35248936381 ps
CPU time 20.15 seconds
Started Jun 29 04:50:57 PM PDT 24
Finished Jun 29 04:51:17 PM PDT 24
Peak memory 199928 kb
Host smart-02bc269d-932e-44e2-b887-21ef320924ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254927871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3254927871
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2393383640
Short name T857
Test name
Test status
Simulation time 32356177240 ps
CPU time 28.62 seconds
Started Jun 29 04:50:57 PM PDT 24
Finished Jun 29 04:51:26 PM PDT 24
Peak memory 199984 kb
Host smart-3e73668a-2f33-4569-9d6b-f58467ce1d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393383640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2393383640
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2863408827
Short name T205
Test name
Test status
Simulation time 84204838135 ps
CPU time 132.67 seconds
Started Jun 29 04:50:59 PM PDT 24
Finished Jun 29 04:53:12 PM PDT 24
Peak memory 199976 kb
Host smart-ee023eab-673d-4b33-8092-6f6006da601b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863408827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2863408827
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.2715954192
Short name T655
Test name
Test status
Simulation time 169435058254 ps
CPU time 27.96 seconds
Started Jun 29 04:51:03 PM PDT 24
Finished Jun 29 04:51:31 PM PDT 24
Peak memory 199932 kb
Host smart-26b36a18-6fee-4adc-b078-dc36360b366f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715954192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2715954192
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.464017513
Short name T346
Test name
Test status
Simulation time 131550210790 ps
CPU time 152.66 seconds
Started Jun 29 04:51:07 PM PDT 24
Finished Jun 29 04:53:40 PM PDT 24
Peak memory 199196 kb
Host smart-c71eeeab-f17d-4f34-a663-3952326c7949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464017513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.464017513
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.4090786288
Short name T48
Test name
Test status
Simulation time 99949471018 ps
CPU time 147.28 seconds
Started Jun 29 04:51:06 PM PDT 24
Finished Jun 29 04:53:34 PM PDT 24
Peak memory 199652 kb
Host smart-96e42c5d-f812-460f-baed-7d7f9010d384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090786288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.4090786288
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.1108408765
Short name T486
Test name
Test status
Simulation time 195922122811 ps
CPU time 119.34 seconds
Started Jun 29 04:51:06 PM PDT 24
Finished Jun 29 04:53:05 PM PDT 24
Peak memory 199952 kb
Host smart-ee956abb-4232-4b1c-a0cb-1339ae134d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108408765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1108408765
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.3427999277
Short name T791
Test name
Test status
Simulation time 13339054 ps
CPU time 0.58 seconds
Started Jun 29 04:48:19 PM PDT 24
Finished Jun 29 04:48:20 PM PDT 24
Peak memory 195304 kb
Host smart-7f5ed2f2-f021-471b-bec2-c8d7c63b447c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427999277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3427999277
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.167257514
Short name T741
Test name
Test status
Simulation time 34500135041 ps
CPU time 49.27 seconds
Started Jun 29 04:48:18 PM PDT 24
Finished Jun 29 04:49:08 PM PDT 24
Peak memory 199944 kb
Host smart-8640e756-ae10-43b8-a879-989e9c5cbdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167257514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.167257514
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.3745999057
Short name T264
Test name
Test status
Simulation time 89353525697 ps
CPU time 152.99 seconds
Started Jun 29 04:48:16 PM PDT 24
Finished Jun 29 04:50:50 PM PDT 24
Peak memory 199948 kb
Host smart-bd2f0657-c72d-470d-952f-bf8c077eedcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745999057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3745999057
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2694357510
Short name T234
Test name
Test status
Simulation time 25543128178 ps
CPU time 26.61 seconds
Started Jun 29 04:48:31 PM PDT 24
Finished Jun 29 04:48:59 PM PDT 24
Peak memory 199928 kb
Host smart-08633eca-1f7d-4d46-8be6-34967c79757b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694357510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2694357510
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.1637567093
Short name T3
Test name
Test status
Simulation time 68092053036 ps
CPU time 96.38 seconds
Started Jun 29 04:48:17 PM PDT 24
Finished Jun 29 04:49:55 PM PDT 24
Peak memory 199836 kb
Host smart-64f386aa-106a-4f79-a8f2-d36331df793c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637567093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1637567093
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_loopback.696928517
Short name T1091
Test name
Test status
Simulation time 5875674401 ps
CPU time 5.77 seconds
Started Jun 29 04:48:15 PM PDT 24
Finished Jun 29 04:48:21 PM PDT 24
Peak memory 199944 kb
Host smart-2e0a50be-1a1e-4736-8203-7910e25ecf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696928517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.696928517
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_perf.3640338475
Short name T1032
Test name
Test status
Simulation time 7306699955 ps
CPU time 332.72 seconds
Started Jun 29 04:48:16 PM PDT 24
Finished Jun 29 04:53:50 PM PDT 24
Peak memory 199980 kb
Host smart-60f2b680-bdae-4f6d-88ad-25d2bcbc5f16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3640338475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3640338475
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3147402635
Short name T888
Test name
Test status
Simulation time 7157361271 ps
CPU time 65.22 seconds
Started Jun 29 04:48:15 PM PDT 24
Finished Jun 29 04:49:21 PM PDT 24
Peak memory 199252 kb
Host smart-a86aa004-89e8-449a-8fb3-a91baee1eba8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3147402635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3147402635
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.2879990068
Short name T433
Test name
Test status
Simulation time 74979079214 ps
CPU time 23.49 seconds
Started Jun 29 04:48:33 PM PDT 24
Finished Jun 29 04:48:57 PM PDT 24
Peak memory 199928 kb
Host smart-e4b3c193-802b-4a10-bcc2-85f221226e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879990068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.2879990068
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.4232223907
Short name T873
Test name
Test status
Simulation time 89928920764 ps
CPU time 33.43 seconds
Started Jun 29 04:48:31 PM PDT 24
Finished Jun 29 04:49:06 PM PDT 24
Peak memory 195592 kb
Host smart-a87f170d-d312-4337-af45-ffe13d554661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232223907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.4232223907
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.1056774543
Short name T44
Test name
Test status
Simulation time 6052612870 ps
CPU time 10.25 seconds
Started Jun 29 04:48:13 PM PDT 24
Finished Jun 29 04:48:24 PM PDT 24
Peak memory 199908 kb
Host smart-8d94a4bb-4915-4942-ae03-50b1cb5c3b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056774543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1056774543
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.4287691728
Short name T725
Test name
Test status
Simulation time 52946090320 ps
CPU time 152.9 seconds
Started Jun 29 04:48:34 PM PDT 24
Finished Jun 29 04:51:07 PM PDT 24
Peak memory 208284 kb
Host smart-e1132591-147d-4225-bd4a-24aaff7744be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287691728 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.4287691728
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.3021212839
Short name T511
Test name
Test status
Simulation time 7982248963 ps
CPU time 9.19 seconds
Started Jun 29 04:48:17 PM PDT 24
Finished Jun 29 04:48:28 PM PDT 24
Peak memory 199796 kb
Host smart-c1bba992-a934-42ae-a316-c73e3e5d4341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021212839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3021212839
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.4291116296
Short name T250
Test name
Test status
Simulation time 82738907217 ps
CPU time 30.06 seconds
Started Jun 29 04:51:08 PM PDT 24
Finished Jun 29 04:51:38 PM PDT 24
Peak memory 199924 kb
Host smart-f2f92d09-3f54-4993-8936-a07564405912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291116296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.4291116296
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.1780107002
Short name T652
Test name
Test status
Simulation time 56443841154 ps
CPU time 21.04 seconds
Started Jun 29 04:51:07 PM PDT 24
Finished Jun 29 04:51:28 PM PDT 24
Peak memory 199836 kb
Host smart-d5d30e1c-84d0-41cf-9891-1d5729595461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780107002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1780107002
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1695586219
Short name T715
Test name
Test status
Simulation time 37401822159 ps
CPU time 52.51 seconds
Started Jun 29 04:51:04 PM PDT 24
Finished Jun 29 04:51:57 PM PDT 24
Peak memory 199868 kb
Host smart-a7a67497-4e62-4bae-a5c5-ae908547b121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695586219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1695586219
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.3014602237
Short name T722
Test name
Test status
Simulation time 29019162085 ps
CPU time 19.45 seconds
Started Jun 29 04:51:05 PM PDT 24
Finished Jun 29 04:51:25 PM PDT 24
Peak memory 199904 kb
Host smart-c2c35b12-345c-4488-921c-77ca93143002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014602237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3014602237
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.3061843835
Short name T162
Test name
Test status
Simulation time 28890009714 ps
CPU time 17.48 seconds
Started Jun 29 04:51:05 PM PDT 24
Finished Jun 29 04:51:23 PM PDT 24
Peak memory 199924 kb
Host smart-86f2c42b-c7e0-46c6-9dce-f494ed744e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061843835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3061843835
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.3752614533
Short name T392
Test name
Test status
Simulation time 27728325132 ps
CPU time 52.97 seconds
Started Jun 29 04:51:06 PM PDT 24
Finished Jun 29 04:52:00 PM PDT 24
Peak memory 199752 kb
Host smart-bcf74125-445b-4cdc-83eb-a442d45bf0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752614533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3752614533
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2623048081
Short name T621
Test name
Test status
Simulation time 38402749653 ps
CPU time 67.48 seconds
Started Jun 29 04:51:04 PM PDT 24
Finished Jun 29 04:52:12 PM PDT 24
Peak memory 199816 kb
Host smart-3ff8954e-cde5-4e5f-95dd-d4599e8f2a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623048081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2623048081
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.2288861380
Short name T393
Test name
Test status
Simulation time 216187091403 ps
CPU time 76.12 seconds
Started Jun 29 04:51:04 PM PDT 24
Finished Jun 29 04:52:21 PM PDT 24
Peak memory 199904 kb
Host smart-e9596f53-3489-4cf7-a222-1fa771999922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288861380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2288861380
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.679394980
Short name T6
Test name
Test status
Simulation time 30719382134 ps
CPU time 14.65 seconds
Started Jun 29 04:51:05 PM PDT 24
Finished Jun 29 04:51:21 PM PDT 24
Peak memory 199988 kb
Host smart-d121d719-ec90-45f9-a425-e8c9a709f835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679394980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.679394980
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.978051335
Short name T784
Test name
Test status
Simulation time 15523886 ps
CPU time 0.58 seconds
Started Jun 29 04:48:30 PM PDT 24
Finished Jun 29 04:48:31 PM PDT 24
Peak memory 195304 kb
Host smart-16d073ee-7b95-4d25-9b0f-a45d05110856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978051335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.978051335
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.1585473806
Short name T1036
Test name
Test status
Simulation time 126426022401 ps
CPU time 191.71 seconds
Started Jun 29 04:48:24 PM PDT 24
Finished Jun 29 04:51:36 PM PDT 24
Peak memory 199908 kb
Host smart-b9a6c97a-df75-45bb-bae6-143d57b9bed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585473806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.1585473806
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2402643746
Short name T714
Test name
Test status
Simulation time 25141301968 ps
CPU time 39.05 seconds
Started Jun 29 04:48:19 PM PDT 24
Finished Jun 29 04:48:59 PM PDT 24
Peak memory 199924 kb
Host smart-ca6144ce-3e3d-4ff2-822f-8ca85b7573f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402643746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2402643746
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.2410658808
Short name T927
Test name
Test status
Simulation time 48466256100 ps
CPU time 21.64 seconds
Started Jun 29 04:48:30 PM PDT 24
Finished Jun 29 04:48:52 PM PDT 24
Peak memory 199904 kb
Host smart-c5038232-2487-4957-abb1-3a1949ddfebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410658808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2410658808
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.3408875478
Short name T559
Test name
Test status
Simulation time 26428475038 ps
CPU time 13.95 seconds
Started Jun 29 04:48:17 PM PDT 24
Finished Jun 29 04:48:32 PM PDT 24
Peak memory 196976 kb
Host smart-a4bfd84d-e2e1-41bc-a0bb-af04b66ca06e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408875478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.3408875478
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.2702453021
Short name T387
Test name
Test status
Simulation time 308326112279 ps
CPU time 821.73 seconds
Started Jun 29 04:48:36 PM PDT 24
Finished Jun 29 05:02:18 PM PDT 24
Peak memory 199868 kb
Host smart-295046f3-f1e5-4bab-8247-a93ae6d5b0df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2702453021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2702453021
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.1883721622
Short name T620
Test name
Test status
Simulation time 5772231064 ps
CPU time 3.9 seconds
Started Jun 29 04:48:18 PM PDT 24
Finished Jun 29 04:48:23 PM PDT 24
Peak memory 199360 kb
Host smart-81dfb7ec-d6e6-429c-8500-103478d43f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883721622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1883721622
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_perf.3677589717
Short name T401
Test name
Test status
Simulation time 9528848808 ps
CPU time 242.45 seconds
Started Jun 29 04:48:34 PM PDT 24
Finished Jun 29 04:52:37 PM PDT 24
Peak memory 199836 kb
Host smart-4f50c88e-0e51-45a3-aa75-a0fbf3e0335c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3677589717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.3677589717
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.1448184357
Short name T432
Test name
Test status
Simulation time 1591766819 ps
CPU time 3.39 seconds
Started Jun 29 04:48:26 PM PDT 24
Finished Jun 29 04:48:30 PM PDT 24
Peak memory 198116 kb
Host smart-b63ed8d9-d191-4bf6-afc1-9df53a680177
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1448184357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1448184357
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.1552101384
Short name T352
Test name
Test status
Simulation time 15273735388 ps
CPU time 10.98 seconds
Started Jun 29 04:48:18 PM PDT 24
Finished Jun 29 04:48:30 PM PDT 24
Peak memory 199364 kb
Host smart-b116c7a6-bf73-40be-821a-3fc0bf3ac48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552101384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.1552101384
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.3376954461
Short name T607
Test name
Test status
Simulation time 3660719950 ps
CPU time 1.9 seconds
Started Jun 29 04:48:18 PM PDT 24
Finished Jun 29 04:48:21 PM PDT 24
Peak memory 196224 kb
Host smart-ef53b649-b962-4828-ba79-528b6c7b7af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376954461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.3376954461
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.4266293894
Short name T660
Test name
Test status
Simulation time 449741484 ps
CPU time 1.52 seconds
Started Jun 29 04:48:28 PM PDT 24
Finished Jun 29 04:48:30 PM PDT 24
Peak memory 198132 kb
Host smart-74bb4106-a307-40e1-ae6b-76315ac97a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266293894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.4266293894
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.2080160677
Short name T111
Test name
Test status
Simulation time 76627766331 ps
CPU time 119.98 seconds
Started Jun 29 04:48:31 PM PDT 24
Finished Jun 29 04:50:32 PM PDT 24
Peak memory 199912 kb
Host smart-a52df1bb-ccc1-42ca-bfb8-569afa9bfd8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080160677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.2080160677
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.4187941595
Short name T313
Test name
Test status
Simulation time 2329968735 ps
CPU time 2.08 seconds
Started Jun 29 04:48:20 PM PDT 24
Finished Jun 29 04:48:22 PM PDT 24
Peak memory 198868 kb
Host smart-2f35ca93-e21c-449d-ad4c-da68ff67f685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187941595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.4187941595
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.2833806870
Short name T881
Test name
Test status
Simulation time 5778106375 ps
CPU time 8.8 seconds
Started Jun 29 04:48:30 PM PDT 24
Finished Jun 29 04:48:40 PM PDT 24
Peak memory 197512 kb
Host smart-2bfb9b64-642b-4b61-affd-a437d11b4d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833806870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2833806870
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.3588639496
Short name T898
Test name
Test status
Simulation time 36771504666 ps
CPU time 61.2 seconds
Started Jun 29 04:51:06 PM PDT 24
Finished Jun 29 04:52:08 PM PDT 24
Peak memory 199688 kb
Host smart-94b7fd9f-5f14-4368-bae4-735a8cbd9afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588639496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3588639496
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2597312877
Short name T958
Test name
Test status
Simulation time 66967885985 ps
CPU time 314.78 seconds
Started Jun 29 04:51:03 PM PDT 24
Finished Jun 29 04:56:18 PM PDT 24
Peak memory 199920 kb
Host smart-db5a0fc9-7747-4fb9-9878-56a912eaae05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597312877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2597312877
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.1478470740
Short name T923
Test name
Test status
Simulation time 98317254397 ps
CPU time 108.79 seconds
Started Jun 29 04:51:05 PM PDT 24
Finished Jun 29 04:52:55 PM PDT 24
Peak memory 199952 kb
Host smart-cb408744-22a0-4081-948a-f75e9f8234bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478470740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.1478470740
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.2200799024
Short name T233
Test name
Test status
Simulation time 161799390040 ps
CPU time 87.56 seconds
Started Jun 29 04:51:06 PM PDT 24
Finished Jun 29 04:52:34 PM PDT 24
Peak memory 199956 kb
Host smart-973b4f42-4a93-47e9-ab12-fd4e954fa862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200799024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2200799024
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.3615433030
Short name T341
Test name
Test status
Simulation time 116691278352 ps
CPU time 47.38 seconds
Started Jun 29 04:51:05 PM PDT 24
Finished Jun 29 04:51:53 PM PDT 24
Peak memory 199904 kb
Host smart-06fd8037-0fea-459d-9aef-8650b7090370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615433030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3615433030
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1183885302
Short name T1027
Test name
Test status
Simulation time 96048477322 ps
CPU time 112.81 seconds
Started Jun 29 04:51:15 PM PDT 24
Finished Jun 29 04:53:09 PM PDT 24
Peak memory 199864 kb
Host smart-6274283b-1d70-4dec-bc50-6eae3bdc816d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183885302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1183885302
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2765845549
Short name T45
Test name
Test status
Simulation time 37277156456 ps
CPU time 36.05 seconds
Started Jun 29 04:51:13 PM PDT 24
Finished Jun 29 04:51:49 PM PDT 24
Peak memory 199948 kb
Host smart-7148fbc4-1e13-4da4-87f2-ef74bd3a9954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765845549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2765845549
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.2793205250
Short name T587
Test name
Test status
Simulation time 34342274 ps
CPU time 0.56 seconds
Started Jun 29 04:48:27 PM PDT 24
Finished Jun 29 04:48:28 PM PDT 24
Peak memory 195592 kb
Host smart-70a371be-d317-486d-9460-acb4a8985deb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793205250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2793205250
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.2568885548
Short name T1051
Test name
Test status
Simulation time 137146423608 ps
CPU time 194.94 seconds
Started Jun 29 04:48:34 PM PDT 24
Finished Jun 29 04:51:50 PM PDT 24
Peak memory 199988 kb
Host smart-9693c065-922e-400e-b632-b4ab1a264916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568885548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.2568885548
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_intr.1098705224
Short name T359
Test name
Test status
Simulation time 32008988943 ps
CPU time 50.44 seconds
Started Jun 29 04:48:21 PM PDT 24
Finished Jun 29 04:49:12 PM PDT 24
Peak memory 199992 kb
Host smart-b46003f7-c8dc-4992-aa92-b91429d011e3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098705224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.1098705224
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.222523903
Short name T867
Test name
Test status
Simulation time 85161870369 ps
CPU time 235.38 seconds
Started Jun 29 04:48:17 PM PDT 24
Finished Jun 29 04:52:14 PM PDT 24
Peak memory 199912 kb
Host smart-1c387cdf-ef43-4f3a-8643-325deafb6ec5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=222523903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.222523903
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.3696664990
Short name T835
Test name
Test status
Simulation time 7341829729 ps
CPU time 14.01 seconds
Started Jun 29 04:48:19 PM PDT 24
Finished Jun 29 04:48:34 PM PDT 24
Peak memory 199932 kb
Host smart-1031a5fa-ebb9-405b-822c-d26b2799fe50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696664990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.3696664990
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_perf.3098838354
Short name T494
Test name
Test status
Simulation time 21828867906 ps
CPU time 245.6 seconds
Started Jun 29 04:48:17 PM PDT 24
Finished Jun 29 04:52:24 PM PDT 24
Peak memory 199980 kb
Host smart-75a8c9dc-bcb9-4fc8-8731-6239c37f9b8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3098838354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.3098838354
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.2341520533
Short name T807
Test name
Test status
Simulation time 6238795892 ps
CPU time 57.27 seconds
Started Jun 29 04:48:22 PM PDT 24
Finished Jun 29 04:49:20 PM PDT 24
Peak memory 198188 kb
Host smart-19714704-5bf0-4035-875a-752e08742d9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2341520533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2341520533
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.1794400576
Short name T567
Test name
Test status
Simulation time 105960560837 ps
CPU time 40.51 seconds
Started Jun 29 04:48:26 PM PDT 24
Finished Jun 29 04:49:07 PM PDT 24
Peak memory 199316 kb
Host smart-e22b1a1c-8d36-4d1a-951b-7515e81162c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794400576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1794400576
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.3409157692
Short name T279
Test name
Test status
Simulation time 37664786733 ps
CPU time 61.96 seconds
Started Jun 29 04:48:22 PM PDT 24
Finished Jun 29 04:49:25 PM PDT 24
Peak memory 195844 kb
Host smart-af02649f-14f7-4cbd-b4ee-de946a167b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409157692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3409157692
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.1948921696
Short name T1001
Test name
Test status
Simulation time 295863281 ps
CPU time 0.95 seconds
Started Jun 29 04:48:19 PM PDT 24
Finished Jun 29 04:48:21 PM PDT 24
Peak memory 198796 kb
Host smart-57785db9-7a1f-4900-bb35-6058c5977b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948921696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1948921696
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.3254015604
Short name T22
Test name
Test status
Simulation time 292236558166 ps
CPU time 616.5 seconds
Started Jun 29 04:48:18 PM PDT 24
Finished Jun 29 04:58:35 PM PDT 24
Peak memory 199936 kb
Host smart-507d1bec-fb30-4615-8463-d9fae088da0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254015604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.3254015604
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.245444902
Short name T1004
Test name
Test status
Simulation time 1320062323 ps
CPU time 3.25 seconds
Started Jun 29 04:48:18 PM PDT 24
Finished Jun 29 04:48:22 PM PDT 24
Peak memory 199448 kb
Host smart-bd133ea6-4d16-4158-958b-91989eddef7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245444902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.245444902
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.2859678979
Short name T430
Test name
Test status
Simulation time 101662954547 ps
CPU time 65.52 seconds
Started Jun 29 04:48:31 PM PDT 24
Finished Jun 29 04:49:38 PM PDT 24
Peak memory 199968 kb
Host smart-e12e3269-1af8-4a4c-a492-5549cc59b5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859678979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2859678979
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.2943620856
Short name T215
Test name
Test status
Simulation time 32973981497 ps
CPU time 30.52 seconds
Started Jun 29 04:51:14 PM PDT 24
Finished Jun 29 04:51:45 PM PDT 24
Peak memory 199936 kb
Host smart-296ab7c7-b4da-4b1b-a609-2f0bb1b1cfa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943620856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2943620856
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.4173056081
Short name T872
Test name
Test status
Simulation time 168111036627 ps
CPU time 311.32 seconds
Started Jun 29 04:51:15 PM PDT 24
Finished Jun 29 04:56:27 PM PDT 24
Peak memory 199968 kb
Host smart-d175ddb5-4c16-4e5a-9aa6-c384eba1631c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173056081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.4173056081
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.3035979149
Short name T1061
Test name
Test status
Simulation time 41802983654 ps
CPU time 17.5 seconds
Started Jun 29 04:51:13 PM PDT 24
Finished Jun 29 04:51:31 PM PDT 24
Peak memory 199988 kb
Host smart-7d503ee9-efe0-4313-91eb-53c3d02e07a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035979149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3035979149
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.3497059793
Short name T189
Test name
Test status
Simulation time 82328616617 ps
CPU time 203.41 seconds
Started Jun 29 04:51:14 PM PDT 24
Finished Jun 29 04:54:38 PM PDT 24
Peak memory 199988 kb
Host smart-5d138612-c1fa-4538-97c8-aff10814bd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497059793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3497059793
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.3987203099
Short name T830
Test name
Test status
Simulation time 174712879130 ps
CPU time 145.76 seconds
Started Jun 29 04:51:13 PM PDT 24
Finished Jun 29 04:53:40 PM PDT 24
Peak memory 199728 kb
Host smart-4649b5e2-6b8c-459a-a3e0-00d9347b07d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987203099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3987203099
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.28529441
Short name T113
Test name
Test status
Simulation time 18388813614 ps
CPU time 21.05 seconds
Started Jun 29 04:51:14 PM PDT 24
Finished Jun 29 04:51:35 PM PDT 24
Peak memory 199952 kb
Host smart-1b5b427c-1c88-4fd3-9921-8c42cdb6f784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28529441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.28529441
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.190312928
Short name T211
Test name
Test status
Simulation time 57782412872 ps
CPU time 88.79 seconds
Started Jun 29 04:51:14 PM PDT 24
Finished Jun 29 04:52:43 PM PDT 24
Peak memory 199956 kb
Host smart-a4fe9f94-9b17-496f-8629-0201937a5e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190312928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.190312928
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.2786543570
Short name T41
Test name
Test status
Simulation time 14077383870 ps
CPU time 12.73 seconds
Started Jun 29 04:51:16 PM PDT 24
Finished Jun 29 04:51:29 PM PDT 24
Peak memory 199680 kb
Host smart-dfb99f54-c1f9-45b4-b056-2ba8d053b4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786543570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.2786543570
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.1230988760
Short name T860
Test name
Test status
Simulation time 31178480 ps
CPU time 0.54 seconds
Started Jun 29 04:48:37 PM PDT 24
Finished Jun 29 04:48:38 PM PDT 24
Peak memory 194384 kb
Host smart-878b80c7-924e-458a-aecf-3bde90297dca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230988760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1230988760
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.1299128409
Short name T423
Test name
Test status
Simulation time 134226002538 ps
CPU time 313.96 seconds
Started Jun 29 04:48:27 PM PDT 24
Finished Jun 29 04:53:41 PM PDT 24
Peak memory 199900 kb
Host smart-3a86402d-1d6a-4e07-b612-9129f1cce50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299128409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.1299128409
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2092328721
Short name T182
Test name
Test status
Simulation time 62296713346 ps
CPU time 85.12 seconds
Started Jun 29 04:48:33 PM PDT 24
Finished Jun 29 04:49:59 PM PDT 24
Peak memory 199980 kb
Host smart-76ae089e-25c2-4c50-873c-ebf54373ae10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092328721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2092328721
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.2536856085
Short name T214
Test name
Test status
Simulation time 69475230726 ps
CPU time 107.87 seconds
Started Jun 29 04:48:24 PM PDT 24
Finished Jun 29 04:50:12 PM PDT 24
Peak memory 199928 kb
Host smart-aa2117b6-7cf2-480c-9c29-8e24c92c8a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536856085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2536856085
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.2480085089
Short name T319
Test name
Test status
Simulation time 30467578967 ps
CPU time 9.78 seconds
Started Jun 29 04:48:35 PM PDT 24
Finished Jun 29 04:48:45 PM PDT 24
Peak memory 199888 kb
Host smart-b13cb636-1a8c-4155-94f2-5f457e332c83
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480085089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.2480085089
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.4004117170
Short name T450
Test name
Test status
Simulation time 95439389023 ps
CPU time 698.88 seconds
Started Jun 29 04:48:26 PM PDT 24
Finished Jun 29 05:00:05 PM PDT 24
Peak memory 199972 kb
Host smart-e026a5b2-804d-4895-b7b7-1a3a1ae4739c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4004117170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.4004117170
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.4051422284
Short name T595
Test name
Test status
Simulation time 4714816221 ps
CPU time 6.61 seconds
Started Jun 29 04:48:30 PM PDT 24
Finished Jun 29 04:48:37 PM PDT 24
Peak memory 199516 kb
Host smart-d19ce1a2-b080-423c-ad83-f87191ae6283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051422284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.4051422284
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_perf.4137898256
Short name T260
Test name
Test status
Simulation time 14156539816 ps
CPU time 312.56 seconds
Started Jun 29 04:48:28 PM PDT 24
Finished Jun 29 04:53:41 PM PDT 24
Peak memory 199980 kb
Host smart-82ef2f86-0823-452c-98c4-579a334384d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4137898256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.4137898256
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.1839771085
Short name T533
Test name
Test status
Simulation time 2011308862 ps
CPU time 12.18 seconds
Started Jun 29 04:48:33 PM PDT 24
Finished Jun 29 04:48:46 PM PDT 24
Peak memory 199040 kb
Host smart-5a111073-abb2-40f6-a58d-29f66fec5b2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1839771085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1839771085
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.342812566
Short name T541
Test name
Test status
Simulation time 68896011880 ps
CPU time 33.96 seconds
Started Jun 29 04:48:36 PM PDT 24
Finished Jun 29 04:49:10 PM PDT 24
Peak memory 199984 kb
Host smart-6549f580-317b-4d7e-ba93-ac0ad3ee15aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342812566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.342812566
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.3469495312
Short name T603
Test name
Test status
Simulation time 35212095237 ps
CPU time 4.21 seconds
Started Jun 29 04:48:26 PM PDT 24
Finished Jun 29 04:48:30 PM PDT 24
Peak memory 195936 kb
Host smart-0d46ec33-a4e9-413f-af32-dfe4b76df86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469495312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3469495312
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.1850071788
Short name T969
Test name
Test status
Simulation time 6054111740 ps
CPU time 13.85 seconds
Started Jun 29 04:48:17 PM PDT 24
Finished Jun 29 04:48:32 PM PDT 24
Peak memory 199816 kb
Host smart-7af0e1b8-7dfc-48c0-ab57-725cb27bacbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850071788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1850071788
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.3094242920
Short name T122
Test name
Test status
Simulation time 30697075490 ps
CPU time 1045.02 seconds
Started Jun 29 04:48:27 PM PDT 24
Finished Jun 29 05:05:52 PM PDT 24
Peak memory 199888 kb
Host smart-0695633d-03dc-4292-a43f-840c6dd09d6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094242920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3094242920
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.461433814
Short name T583
Test name
Test status
Simulation time 7442603784 ps
CPU time 12.37 seconds
Started Jun 29 04:48:32 PM PDT 24
Finished Jun 29 04:48:45 PM PDT 24
Peak memory 199756 kb
Host smart-873864a3-5c41-4eba-994c-5a88aea41ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461433814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.461433814
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.95134860
Short name T910
Test name
Test status
Simulation time 12489660065 ps
CPU time 17.95 seconds
Started Jun 29 04:48:31 PM PDT 24
Finished Jun 29 04:48:49 PM PDT 24
Peak memory 196544 kb
Host smart-4d2eff00-dbbc-4e10-a754-506ddc49280d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95134860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.95134860
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.3571601904
Short name T471
Test name
Test status
Simulation time 161102010934 ps
CPU time 247.42 seconds
Started Jun 29 04:51:16 PM PDT 24
Finished Jun 29 04:55:23 PM PDT 24
Peak memory 199904 kb
Host smart-d8bb8294-d00b-49cb-baab-b27c902dabf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571601904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3571601904
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.2655355420
Short name T200
Test name
Test status
Simulation time 57836183778 ps
CPU time 118.78 seconds
Started Jun 29 04:51:14 PM PDT 24
Finished Jun 29 04:53:14 PM PDT 24
Peak memory 199960 kb
Host smart-6b14e99a-f1e1-4fb8-91c3-9e2868b65b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655355420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2655355420
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3380280208
Short name T833
Test name
Test status
Simulation time 16443409481 ps
CPU time 13.4 seconds
Started Jun 29 04:51:15 PM PDT 24
Finished Jun 29 04:51:29 PM PDT 24
Peak memory 198784 kb
Host smart-5432c801-b2d1-42d8-ae6b-1157b8a4e555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380280208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3380280208
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.395733960
Short name T934
Test name
Test status
Simulation time 43221341375 ps
CPU time 29.09 seconds
Started Jun 29 04:51:20 PM PDT 24
Finished Jun 29 04:51:49 PM PDT 24
Peak memory 199920 kb
Host smart-0a8cd1c0-6b6c-4339-a25f-b31df9af0bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395733960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.395733960
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.658903755
Short name T1052
Test name
Test status
Simulation time 27279810351 ps
CPU time 43.9 seconds
Started Jun 29 04:51:20 PM PDT 24
Finished Jun 29 04:52:04 PM PDT 24
Peak memory 199956 kb
Host smart-6cecaefe-ab30-48db-b3bc-17f69cd1d61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658903755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.658903755
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.2688484538
Short name T246
Test name
Test status
Simulation time 20273107624 ps
CPU time 28.46 seconds
Started Jun 29 04:51:22 PM PDT 24
Finished Jun 29 04:51:51 PM PDT 24
Peak memory 199988 kb
Host smart-adfa5a99-40cd-4d90-bed3-f078fddfa4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688484538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2688484538
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.471577153
Short name T245
Test name
Test status
Simulation time 168298953295 ps
CPU time 26.92 seconds
Started Jun 29 04:51:22 PM PDT 24
Finished Jun 29 04:51:49 PM PDT 24
Peak memory 199804 kb
Host smart-5c24ade8-a5eb-4792-8477-39d6f780e49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471577153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.471577153
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.3331889332
Short name T331
Test name
Test status
Simulation time 123414914730 ps
CPU time 174.2 seconds
Started Jun 29 04:51:19 PM PDT 24
Finished Jun 29 04:54:13 PM PDT 24
Peak memory 199992 kb
Host smart-5ea90ac5-6dab-4ee8-a10f-799ddc9bbe3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331889332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.3331889332
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3987111762
Short name T674
Test name
Test status
Simulation time 38211843748 ps
CPU time 84.78 seconds
Started Jun 29 04:51:21 PM PDT 24
Finished Jun 29 04:52:47 PM PDT 24
Peak memory 199988 kb
Host smart-046377cb-79e8-42cb-92e5-b03bba8c6253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987111762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3987111762
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.3305457878
Short name T457
Test name
Test status
Simulation time 129353975524 ps
CPU time 14.64 seconds
Started Jun 29 04:51:29 PM PDT 24
Finished Jun 29 04:51:44 PM PDT 24
Peak memory 199260 kb
Host smart-144f1cbd-e27f-409a-a996-2e5d1cbb6343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305457878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3305457878
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2647519219
Short name T356
Test name
Test status
Simulation time 15485092 ps
CPU time 0.57 seconds
Started Jun 29 04:48:32 PM PDT 24
Finished Jun 29 04:48:33 PM PDT 24
Peak memory 195304 kb
Host smart-134c028e-9e4f-4c08-9d79-beec26d9a6b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647519219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2647519219
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.2189089639
Short name T861
Test name
Test status
Simulation time 241936722001 ps
CPU time 31.44 seconds
Started Jun 29 04:48:27 PM PDT 24
Finished Jun 29 04:48:59 PM PDT 24
Peak memory 199956 kb
Host smart-7f4558e0-d650-4f8c-b353-0319b368e1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189089639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.2189089639
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.3979318905
Short name T276
Test name
Test status
Simulation time 8530344629 ps
CPU time 13.17 seconds
Started Jun 29 04:48:24 PM PDT 24
Finished Jun 29 04:48:38 PM PDT 24
Peak memory 199156 kb
Host smart-6f6678dc-7cc3-44a3-bb64-e88e48fa3116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979318905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.3979318905
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2472812525
Short name T413
Test name
Test status
Simulation time 41712904372 ps
CPU time 14.92 seconds
Started Jun 29 04:48:33 PM PDT 24
Finished Jun 29 04:48:48 PM PDT 24
Peak memory 199812 kb
Host smart-6a200304-0a4c-4b57-8864-1953f0637c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472812525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2472812525
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.1421916230
Short name T493
Test name
Test status
Simulation time 11782611470 ps
CPU time 14.85 seconds
Started Jun 29 04:48:36 PM PDT 24
Finished Jun 29 04:48:51 PM PDT 24
Peak memory 199884 kb
Host smart-bd970e91-9a20-49c7-96f4-0d9ca45d4748
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421916230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1421916230
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.1743092323
Short name T696
Test name
Test status
Simulation time 173290924855 ps
CPU time 1262.49 seconds
Started Jun 29 04:48:31 PM PDT 24
Finished Jun 29 05:09:34 PM PDT 24
Peak memory 199908 kb
Host smart-9749f1f7-36ed-4461-9bbc-eecc6e159827
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1743092323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.1743092323
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.2944376481
Short name T670
Test name
Test status
Simulation time 2252532065 ps
CPU time 3.63 seconds
Started Jun 29 04:48:36 PM PDT 24
Finished Jun 29 04:48:40 PM PDT 24
Peak memory 198712 kb
Host smart-6067e3cc-f556-4dd8-9c61-bae9894cde1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944376481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2944376481
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_perf.1523701442
Short name T371
Test name
Test status
Simulation time 8668606307 ps
CPU time 243.72 seconds
Started Jun 29 04:48:36 PM PDT 24
Finished Jun 29 04:52:40 PM PDT 24
Peak memory 199980 kb
Host smart-ee9a0a86-6103-4a07-b059-ed1feaf584db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1523701442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1523701442
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.2824705003
Short name T829
Test name
Test status
Simulation time 3496697424 ps
CPU time 8.24 seconds
Started Jun 29 04:48:25 PM PDT 24
Finished Jun 29 04:48:34 PM PDT 24
Peak memory 198000 kb
Host smart-58691dc5-8b05-438a-965d-bce5778c8f31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2824705003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.2824705003
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.897138687
Short name T769
Test name
Test status
Simulation time 47896437289 ps
CPU time 42.06 seconds
Started Jun 29 04:48:44 PM PDT 24
Finished Jun 29 04:49:27 PM PDT 24
Peak memory 199984 kb
Host smart-9e16bc3f-c718-4b8b-999f-061d8878ac20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897138687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.897138687
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.2105070351
Short name T839
Test name
Test status
Simulation time 51860585469 ps
CPU time 69.14 seconds
Started Jun 29 04:48:32 PM PDT 24
Finished Jun 29 04:49:42 PM PDT 24
Peak memory 196424 kb
Host smart-20bba502-3569-479e-b90a-29593a865259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105070351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.2105070351
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.1046049290
Short name T270
Test name
Test status
Simulation time 555112599 ps
CPU time 3.75 seconds
Started Jun 29 04:48:35 PM PDT 24
Finished Jun 29 04:48:39 PM PDT 24
Peak memory 198284 kb
Host smart-a6b7a2be-e837-4b44-99ef-d5bb9aa052e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046049290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1046049290
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.692805080
Short name T65
Test name
Test status
Simulation time 193909497510 ps
CPU time 436.81 seconds
Started Jun 29 04:48:32 PM PDT 24
Finished Jun 29 04:55:50 PM PDT 24
Peak memory 216496 kb
Host smart-d23153d8-45b6-4877-a0b8-3e0b74d7869e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692805080 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.692805080
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.1142972005
Short name T321
Test name
Test status
Simulation time 1366784052 ps
CPU time 2.56 seconds
Started Jun 29 04:48:31 PM PDT 24
Finished Jun 29 04:48:34 PM PDT 24
Peak memory 199440 kb
Host smart-be5d908c-3cc7-4850-a997-136b87613bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142972005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1142972005
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.1895646933
Short name T971
Test name
Test status
Simulation time 116913167890 ps
CPU time 51.16 seconds
Started Jun 29 04:48:34 PM PDT 24
Finished Jun 29 04:49:25 PM PDT 24
Peak memory 199888 kb
Host smart-52a94aca-f1ee-4405-b4d7-cbb777dac0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895646933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1895646933
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.3918979126
Short name T906
Test name
Test status
Simulation time 53203713446 ps
CPU time 28.94 seconds
Started Jun 29 04:51:20 PM PDT 24
Finished Jun 29 04:51:50 PM PDT 24
Peak memory 199956 kb
Host smart-1d935073-8496-4f5c-baaf-34c3c55fca9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918979126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3918979126
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.239280988
Short name T1026
Test name
Test status
Simulation time 106813793191 ps
CPU time 91.73 seconds
Started Jun 29 04:51:19 PM PDT 24
Finished Jun 29 04:52:51 PM PDT 24
Peak memory 199992 kb
Host smart-90e7935c-03bb-40b7-b46e-bdab74a05037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239280988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.239280988
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2729296040
Short name T851
Test name
Test status
Simulation time 20292136989 ps
CPU time 28.87 seconds
Started Jun 29 04:51:20 PM PDT 24
Finished Jun 29 04:51:50 PM PDT 24
Peak memory 199500 kb
Host smart-b47d96b4-774b-40bf-a5cc-dbc3c207d735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729296040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2729296040
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.2076027908
Short name T194
Test name
Test status
Simulation time 15467956390 ps
CPU time 21.51 seconds
Started Jun 29 04:51:20 PM PDT 24
Finished Jun 29 04:51:43 PM PDT 24
Peak memory 199864 kb
Host smart-4a03b475-bd95-4e91-87a3-3a34d460ac5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076027908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.2076027908
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.2712777391
Short name T180
Test name
Test status
Simulation time 31420874263 ps
CPU time 12.17 seconds
Started Jun 29 04:51:21 PM PDT 24
Finished Jun 29 04:51:34 PM PDT 24
Peak memory 199948 kb
Host smart-df3172ce-6bd4-4b36-9f20-d89e527fe726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712777391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2712777391
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3063273896
Short name T948
Test name
Test status
Simulation time 145278412209 ps
CPU time 85.39 seconds
Started Jun 29 04:51:21 PM PDT 24
Finished Jun 29 04:52:47 PM PDT 24
Peak memory 199900 kb
Host smart-eb044c75-ea5c-4e40-8a38-ed66eee691ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063273896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3063273896
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2379695455
Short name T922
Test name
Test status
Simulation time 48924798150 ps
CPU time 22.77 seconds
Started Jun 29 04:51:20 PM PDT 24
Finished Jun 29 04:51:44 PM PDT 24
Peak memory 199876 kb
Host smart-f1c516cd-d764-460d-a17f-54e4ca256b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379695455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2379695455
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.4268246778
Short name T1014
Test name
Test status
Simulation time 105665913402 ps
CPU time 114.32 seconds
Started Jun 29 04:51:28 PM PDT 24
Finished Jun 29 04:53:23 PM PDT 24
Peak memory 199940 kb
Host smart-b738f696-06eb-4f12-9e51-e3feac391ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268246778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.4268246778
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.1273027645
Short name T684
Test name
Test status
Simulation time 140592907506 ps
CPU time 48.26 seconds
Started Jun 29 04:51:20 PM PDT 24
Finished Jun 29 04:52:08 PM PDT 24
Peak memory 199960 kb
Host smart-ebb783c4-78a8-41d2-82ef-ceac6ac56949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273027645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1273027645
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.103197743
Short name T964
Test name
Test status
Simulation time 39626862328 ps
CPU time 20.96 seconds
Started Jun 29 04:51:23 PM PDT 24
Finished Jun 29 04:51:45 PM PDT 24
Peak memory 199928 kb
Host smart-b18b9c20-e374-4cb7-8ea5-8d7b574a7900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103197743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.103197743
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.1728997650
Short name T1057
Test name
Test status
Simulation time 82102138 ps
CPU time 0.56 seconds
Started Jun 29 04:47:54 PM PDT 24
Finished Jun 29 04:47:55 PM PDT 24
Peak memory 195140 kb
Host smart-dca582a2-2b6b-44bf-9d18-dfba2a2eabc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728997650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1728997650
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.312136884
Short name T779
Test name
Test status
Simulation time 66235286724 ps
CPU time 95.66 seconds
Started Jun 29 04:48:02 PM PDT 24
Finished Jun 29 04:49:39 PM PDT 24
Peak memory 199928 kb
Host smart-c827753e-7567-4d64-b5de-0726944805b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312136884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.312136884
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3222317775
Short name T863
Test name
Test status
Simulation time 12847630036 ps
CPU time 5.58 seconds
Started Jun 29 04:47:43 PM PDT 24
Finished Jun 29 04:47:50 PM PDT 24
Peak memory 199652 kb
Host smart-f4ac762f-cb37-4e45-83e0-2e736fceb260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222317775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3222317775
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.1219419278
Short name T207
Test name
Test status
Simulation time 73334680037 ps
CPU time 24.43 seconds
Started Jun 29 04:47:54 PM PDT 24
Finished Jun 29 04:48:19 PM PDT 24
Peak memory 199924 kb
Host smart-3708e1b8-7ea7-4b13-9330-820854cdd42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219419278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1219419278
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.178999418
Short name T815
Test name
Test status
Simulation time 11286776571 ps
CPU time 6.06 seconds
Started Jun 29 04:47:58 PM PDT 24
Finished Jun 29 04:48:04 PM PDT 24
Peak memory 199684 kb
Host smart-75aa158c-b6a1-4106-b3cb-a50c3c66768c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178999418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.178999418
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.188983793
Short name T535
Test name
Test status
Simulation time 152872199785 ps
CPU time 286.57 seconds
Started Jun 29 04:47:58 PM PDT 24
Finished Jun 29 04:52:46 PM PDT 24
Peak memory 199828 kb
Host smart-9c1f68b2-4116-4117-a019-7d7314579d7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=188983793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.188983793
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.2723773533
Short name T1090
Test name
Test status
Simulation time 8821145584 ps
CPU time 9.23 seconds
Started Jun 29 04:48:00 PM PDT 24
Finished Jun 29 04:48:10 PM PDT 24
Peak memory 198988 kb
Host smart-a74fa96a-2a43-4d78-8f00-048701afef22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723773533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2723773533
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_perf.708480723
Short name T1055
Test name
Test status
Simulation time 17963525658 ps
CPU time 1026.6 seconds
Started Jun 29 04:48:01 PM PDT 24
Finished Jun 29 05:05:09 PM PDT 24
Peak memory 199948 kb
Host smart-5989590c-c46a-4fa5-96b9-0501ecbf75a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=708480723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.708480723
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.2457354062
Short name T102
Test name
Test status
Simulation time 1491164263 ps
CPU time 3.19 seconds
Started Jun 29 04:47:55 PM PDT 24
Finished Jun 29 04:47:59 PM PDT 24
Peak memory 197996 kb
Host smart-ce050719-6b62-43ef-8480-4ffcb21527a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2457354062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2457354062
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.2514748977
Short name T936
Test name
Test status
Simulation time 31534499091 ps
CPU time 13.37 seconds
Started Jun 29 04:48:05 PM PDT 24
Finished Jun 29 04:48:19 PM PDT 24
Peak memory 199912 kb
Host smart-8cfaf12f-e5e5-4253-b86f-36a1a3808a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514748977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.2514748977
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2226078308
Short name T586
Test name
Test status
Simulation time 35562515883 ps
CPU time 47.62 seconds
Started Jun 29 04:48:01 PM PDT 24
Finished Jun 29 04:48:49 PM PDT 24
Peak memory 196048 kb
Host smart-9b3d5aef-4ac9-4b38-81e8-35099192eb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226078308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2226078308
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.798794395
Short name T26
Test name
Test status
Simulation time 116081471 ps
CPU time 0.8 seconds
Started Jun 29 04:47:45 PM PDT 24
Finished Jun 29 04:47:47 PM PDT 24
Peak memory 218124 kb
Host smart-8cdb1c55-2017-4e36-8009-d1fbcfee6d1d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798794395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.798794395
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.5816502
Short name T1020
Test name
Test status
Simulation time 272003028 ps
CPU time 1.14 seconds
Started Jun 29 04:48:00 PM PDT 24
Finished Jun 29 04:48:02 PM PDT 24
Peak memory 198196 kb
Host smart-87a610fd-a560-4c8f-a285-aaf1d36d7810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5816502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.5816502
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.298683793
Short name T747
Test name
Test status
Simulation time 178086363461 ps
CPU time 854.22 seconds
Started Jun 29 04:47:57 PM PDT 24
Finished Jun 29 05:02:12 PM PDT 24
Peak memory 199832 kb
Host smart-476be424-fbbb-4b4f-b601-74d3f63416ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298683793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.298683793
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.1752710895
Short name T62
Test name
Test status
Simulation time 35697032019 ps
CPU time 269.76 seconds
Started Jun 29 04:47:57 PM PDT 24
Finished Jun 29 04:52:27 PM PDT 24
Peak memory 215548 kb
Host smart-da46f043-9154-401b-b4d1-2c1f20d897db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752710895 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.1752710895
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1770188360
Short name T664
Test name
Test status
Simulation time 759919298 ps
CPU time 3.63 seconds
Started Jun 29 04:47:47 PM PDT 24
Finished Jun 29 04:47:56 PM PDT 24
Peak memory 199212 kb
Host smart-62bd5532-ce06-4329-9aae-2cd4aaff7c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770188360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1770188360
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.2527940411
Short name T502
Test name
Test status
Simulation time 70979132300 ps
CPU time 32.88 seconds
Started Jun 29 04:47:58 PM PDT 24
Finished Jun 29 04:48:32 PM PDT 24
Peak memory 199916 kb
Host smart-b175fa7f-25c3-4015-afab-0e8c684b3021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527940411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.2527940411
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.3625332610
Short name T698
Test name
Test status
Simulation time 14215019 ps
CPU time 0.56 seconds
Started Jun 29 04:48:39 PM PDT 24
Finished Jun 29 04:48:40 PM PDT 24
Peak memory 195304 kb
Host smart-5a86b86d-81ee-4559-8a88-5ecd1e0088b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625332610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3625332610
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.715723433
Short name T577
Test name
Test status
Simulation time 231641868881 ps
CPU time 190.69 seconds
Started Jun 29 04:48:38 PM PDT 24
Finished Jun 29 04:51:49 PM PDT 24
Peak memory 199932 kb
Host smart-635e58c7-59b7-4e1c-a1d8-f44922411a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715723433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.715723433
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.3952311417
Short name T285
Test name
Test status
Simulation time 192154237816 ps
CPU time 21.46 seconds
Started Jun 29 04:48:25 PM PDT 24
Finished Jun 29 04:48:48 PM PDT 24
Peak memory 199928 kb
Host smart-cc5b848f-acef-4b7b-a565-107c53abc011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952311417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3952311417
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.1525523395
Short name T579
Test name
Test status
Simulation time 123759646166 ps
CPU time 52.95 seconds
Started Jun 29 04:48:31 PM PDT 24
Finished Jun 29 04:49:25 PM PDT 24
Peak memory 199896 kb
Host smart-69818970-1ca3-4318-b67d-45cea0cad73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525523395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1525523395
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.2298533753
Short name T694
Test name
Test status
Simulation time 26421488725 ps
CPU time 9.16 seconds
Started Jun 29 04:48:34 PM PDT 24
Finished Jun 29 04:48:43 PM PDT 24
Peak memory 199852 kb
Host smart-4a7a6713-0d24-414a-8517-c9591f4076a8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298533753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.2298533753
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.3956329463
Short name T564
Test name
Test status
Simulation time 121874678557 ps
CPU time 245.77 seconds
Started Jun 29 04:48:38 PM PDT 24
Finished Jun 29 04:52:44 PM PDT 24
Peak memory 199992 kb
Host smart-7192c5df-035e-45d0-bfb1-5c2c7d00097d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3956329463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3956329463
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.3507104506
Short name T1006
Test name
Test status
Simulation time 8546879233 ps
CPU time 4.51 seconds
Started Jun 29 04:48:39 PM PDT 24
Finished Jun 29 04:48:45 PM PDT 24
Peak memory 199028 kb
Host smart-e4f9e271-7079-474c-b210-17098a6b3453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507104506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.3507104506
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_perf.1393069339
Short name T712
Test name
Test status
Simulation time 21582270715 ps
CPU time 771.13 seconds
Started Jun 29 04:48:39 PM PDT 24
Finished Jun 29 05:01:30 PM PDT 24
Peak memory 199920 kb
Host smart-6a07bef4-497e-4a54-a3e4-8fb9e3854c1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1393069339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.1393069339
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.2498767081
Short name T1045
Test name
Test status
Simulation time 1295326363 ps
CPU time 1.08 seconds
Started Jun 29 04:48:27 PM PDT 24
Finished Jun 29 04:48:29 PM PDT 24
Peak memory 195588 kb
Host smart-9eca7506-b0dd-4416-86d6-eaf41c8a03d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2498767081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2498767081
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.1021709258
Short name T738
Test name
Test status
Simulation time 27632419227 ps
CPU time 46.52 seconds
Started Jun 29 04:48:38 PM PDT 24
Finished Jun 29 04:49:25 PM PDT 24
Peak memory 199900 kb
Host smart-7bb991e2-6e03-4284-8abd-e919dc4b8de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021709258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1021709258
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.497568553
Short name T20
Test name
Test status
Simulation time 2866059615 ps
CPU time 1.67 seconds
Started Jun 29 04:48:37 PM PDT 24
Finished Jun 29 04:48:39 PM PDT 24
Peak memory 196420 kb
Host smart-138738b4-5f70-432f-90ea-245a67129632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497568553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.497568553
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.3175468977
Short name T933
Test name
Test status
Simulation time 688753386 ps
CPU time 2.87 seconds
Started Jun 29 04:48:33 PM PDT 24
Finished Jun 29 04:48:37 PM PDT 24
Peak memory 198332 kb
Host smart-b7fe1bdd-e146-4bef-9135-2f10ca6da220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175468977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3175468977
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.3725065120
Short name T911
Test name
Test status
Simulation time 251879151064 ps
CPU time 148.45 seconds
Started Jun 29 04:48:42 PM PDT 24
Finished Jun 29 04:51:11 PM PDT 24
Peak memory 199828 kb
Host smart-59e9d6cb-e734-4f2a-92a6-57d38428b00c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725065120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.3725065120
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.274785528
Short name T108
Test name
Test status
Simulation time 59153922899 ps
CPU time 1157.09 seconds
Started Jun 29 04:48:40 PM PDT 24
Finished Jun 29 05:07:58 PM PDT 24
Peak memory 216520 kb
Host smart-032f1f1a-135e-4411-a708-59e57c0aa870
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274785528 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.274785528
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.1078340609
Short name T465
Test name
Test status
Simulation time 6995364138 ps
CPU time 11.57 seconds
Started Jun 29 04:48:37 PM PDT 24
Finished Jun 29 04:48:49 PM PDT 24
Peak memory 199648 kb
Host smart-eb9f455f-5435-478b-9307-311db3efb69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078340609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1078340609
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.3176457302
Short name T370
Test name
Test status
Simulation time 81672674010 ps
CPU time 182.75 seconds
Started Jun 29 04:48:32 PM PDT 24
Finished Jun 29 04:51:35 PM PDT 24
Peak memory 199964 kb
Host smart-0ef87cc2-d578-495b-9d10-26a00ac804fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176457302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3176457302
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.3425070055
Short name T976
Test name
Test status
Simulation time 172757123161 ps
CPU time 90.78 seconds
Started Jun 29 04:51:21 PM PDT 24
Finished Jun 29 04:52:52 PM PDT 24
Peak memory 199748 kb
Host smart-982ba3e1-a615-46bf-9db5-294f86a7d91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425070055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3425070055
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3539218403
Short name T680
Test name
Test status
Simulation time 77628149646 ps
CPU time 37.78 seconds
Started Jun 29 04:51:27 PM PDT 24
Finished Jun 29 04:52:05 PM PDT 24
Peak memory 199924 kb
Host smart-4a9b60e3-752e-4162-a3dc-917b29d5c2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539218403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3539218403
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1017755485
Short name T875
Test name
Test status
Simulation time 15799008775 ps
CPU time 23.9 seconds
Started Jun 29 04:51:20 PM PDT 24
Finished Jun 29 04:51:45 PM PDT 24
Peak memory 199988 kb
Host smart-c1529129-c694-4fb5-a147-b568271a348c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017755485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1017755485
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.644143899
Short name T304
Test name
Test status
Simulation time 93989215316 ps
CPU time 40.08 seconds
Started Jun 29 04:51:21 PM PDT 24
Finished Jun 29 04:52:02 PM PDT 24
Peak memory 199904 kb
Host smart-3660dc3f-e242-4dcd-8daa-73a184786c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644143899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.644143899
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.2727363243
Short name T789
Test name
Test status
Simulation time 95737464361 ps
CPU time 42.74 seconds
Started Jun 29 04:51:20 PM PDT 24
Finished Jun 29 04:52:03 PM PDT 24
Peak memory 199896 kb
Host smart-3a62f0a3-252a-4305-b283-0b7a682a56d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727363243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2727363243
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1810405246
Short name T497
Test name
Test status
Simulation time 145656100743 ps
CPU time 58.66 seconds
Started Jun 29 04:51:21 PM PDT 24
Finished Jun 29 04:52:20 PM PDT 24
Peak memory 199908 kb
Host smart-1e2f5d7c-f1a8-4c55-a235-ab4f7de0305f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810405246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1810405246
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.2608378338
Short name T38
Test name
Test status
Simulation time 115722742743 ps
CPU time 175.03 seconds
Started Jun 29 04:51:29 PM PDT 24
Finished Jun 29 04:54:25 PM PDT 24
Peak memory 199364 kb
Host smart-727e8839-bf16-4990-9d1f-b48b589b903c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608378338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.2608378338
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.334933358
Short name T190
Test name
Test status
Simulation time 20899735754 ps
CPU time 30.69 seconds
Started Jun 29 04:51:27 PM PDT 24
Finished Jun 29 04:51:58 PM PDT 24
Peak memory 199928 kb
Host smart-5d4f4b3f-1317-4166-810f-d0c520f39798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334933358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.334933358
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.253140725
Short name T1048
Test name
Test status
Simulation time 93993844 ps
CPU time 0.58 seconds
Started Jun 29 04:48:39 PM PDT 24
Finished Jun 29 04:48:40 PM PDT 24
Peak memory 195304 kb
Host smart-836c0b1a-cfc1-4a40-a83a-b4d143131e7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253140725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.253140725
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.169371625
Short name T600
Test name
Test status
Simulation time 152700645461 ps
CPU time 248.29 seconds
Started Jun 29 04:48:37 PM PDT 24
Finished Jun 29 04:52:46 PM PDT 24
Peak memory 199992 kb
Host smart-910ad0e4-6a40-457f-b197-21f1da462976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169371625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.169371625
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.2767741909
Short name T377
Test name
Test status
Simulation time 29190037600 ps
CPU time 13.96 seconds
Started Jun 29 04:48:41 PM PDT 24
Finished Jun 29 04:48:55 PM PDT 24
Peak memory 199924 kb
Host smart-4a5a6f9d-ac2d-40f6-85a1-2e1e534d52dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767741909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2767741909
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_intr.2397621966
Short name T596
Test name
Test status
Simulation time 46944099951 ps
CPU time 73.79 seconds
Started Jun 29 04:48:39 PM PDT 24
Finished Jun 29 04:49:54 PM PDT 24
Peak memory 199772 kb
Host smart-b03cc729-2288-4633-9dcd-8bc6b7dd88e9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397621966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2397621966
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.1091126997
Short name T972
Test name
Test status
Simulation time 62707802132 ps
CPU time 427.21 seconds
Started Jun 29 04:48:45 PM PDT 24
Finished Jun 29 04:55:53 PM PDT 24
Peak memory 199864 kb
Host smart-04735998-2eb3-4ad1-a637-33e76291168e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1091126997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.1091126997
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2766452006
Short name T545
Test name
Test status
Simulation time 10709846374 ps
CPU time 10.53 seconds
Started Jun 29 04:48:40 PM PDT 24
Finished Jun 29 04:48:51 PM PDT 24
Peak memory 199908 kb
Host smart-34d2af74-03ee-42c9-8294-1b0651666fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766452006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2766452006
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.1440122536
Short name T820
Test name
Test status
Simulation time 32456047786 ps
CPU time 46.04 seconds
Started Jun 29 04:48:38 PM PDT 24
Finished Jun 29 04:49:24 PM PDT 24
Peak memory 200040 kb
Host smart-b63840e9-7a48-4659-aded-356f58273d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440122536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1440122536
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.670842015
Short name T984
Test name
Test status
Simulation time 8109116052 ps
CPU time 118.4 seconds
Started Jun 29 04:48:45 PM PDT 24
Finished Jun 29 04:50:45 PM PDT 24
Peak memory 199812 kb
Host smart-4123a923-ff67-439d-8052-2798070fd3ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=670842015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.670842015
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3955360748
Short name T1059
Test name
Test status
Simulation time 7281271500 ps
CPU time 63.17 seconds
Started Jun 29 04:48:35 PM PDT 24
Finished Jun 29 04:49:39 PM PDT 24
Peak memory 198200 kb
Host smart-4c774789-cbc2-4437-828f-9d4df6958ae7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3955360748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3955360748
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.2857565801
Short name T980
Test name
Test status
Simulation time 33435120692 ps
CPU time 71.08 seconds
Started Jun 29 04:48:44 PM PDT 24
Finished Jun 29 04:49:57 PM PDT 24
Peak memory 200008 kb
Host smart-bd9b8670-13cc-4b44-bd8d-2962cdc538dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857565801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2857565801
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.1631603773
Short name T397
Test name
Test status
Simulation time 6252716087 ps
CPU time 3.36 seconds
Started Jun 29 04:48:34 PM PDT 24
Finished Jun 29 04:48:38 PM PDT 24
Peak memory 196432 kb
Host smart-45a28df0-4ed8-4303-bc70-d1f6456c6985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631603773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1631603773
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.1215506070
Short name T315
Test name
Test status
Simulation time 662625052 ps
CPU time 3.55 seconds
Started Jun 29 04:48:37 PM PDT 24
Finished Jun 29 04:48:41 PM PDT 24
Peak memory 199804 kb
Host smart-a5d11894-394b-4203-848a-2809ace8e44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215506070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1215506070
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.3736362959
Short name T327
Test name
Test status
Simulation time 185445324566 ps
CPU time 1214.64 seconds
Started Jun 29 04:48:40 PM PDT 24
Finished Jun 29 05:08:56 PM PDT 24
Peak memory 199936 kb
Host smart-a320be82-9922-4ad3-bc4d-30868966d243
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736362959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.3736362959
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.4085268675
Short name T877
Test name
Test status
Simulation time 34493040261 ps
CPU time 397.89 seconds
Started Jun 29 04:48:44 PM PDT 24
Finished Jun 29 04:55:22 PM PDT 24
Peak memory 216428 kb
Host smart-616a1f52-2dff-4f3d-bcdd-b86280ad651f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085268675 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.4085268675
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.3832593016
Short name T551
Test name
Test status
Simulation time 6401631024 ps
CPU time 14.3 seconds
Started Jun 29 04:48:45 PM PDT 24
Finished Jun 29 04:49:00 PM PDT 24
Peak memory 199828 kb
Host smart-5d407a93-debf-4a62-beb7-080d376fb4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832593016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3832593016
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.4212046271
Short name T1096
Test name
Test status
Simulation time 18248314837 ps
CPU time 17.78 seconds
Started Jun 29 04:48:39 PM PDT 24
Finished Jun 29 04:48:58 PM PDT 24
Peak memory 199912 kb
Host smart-299b48e3-43a5-4b6f-b12e-878ccc9cdbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212046271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.4212046271
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.2964363594
Short name T283
Test name
Test status
Simulation time 41555032969 ps
CPU time 18.74 seconds
Started Jun 29 04:51:29 PM PDT 24
Finished Jun 29 04:51:48 PM PDT 24
Peak memory 199988 kb
Host smart-8295e2df-06f3-4e4e-8963-a2c2e1aa7ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964363594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.2964363594
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.262891727
Short name T610
Test name
Test status
Simulation time 78624424608 ps
CPU time 145.06 seconds
Started Jun 29 04:51:30 PM PDT 24
Finished Jun 29 04:53:56 PM PDT 24
Peak memory 199744 kb
Host smart-29718bf9-8d6a-437e-9621-7216be4fd0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262891727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.262891727
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.3436828391
Short name T633
Test name
Test status
Simulation time 16538367973 ps
CPU time 23.27 seconds
Started Jun 29 04:51:27 PM PDT 24
Finished Jun 29 04:51:51 PM PDT 24
Peak memory 199904 kb
Host smart-b01c63d4-704a-4cae-879c-86e60613c263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436828391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.3436828391
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.4033892359
Short name T736
Test name
Test status
Simulation time 19010975985 ps
CPU time 30.73 seconds
Started Jun 29 04:51:29 PM PDT 24
Finished Jun 29 04:52:00 PM PDT 24
Peak memory 199928 kb
Host smart-90fad14f-61ce-4678-9b65-d32a5d8d942e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033892359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.4033892359
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.922257035
Short name T646
Test name
Test status
Simulation time 22107393523 ps
CPU time 30.34 seconds
Started Jun 29 04:51:28 PM PDT 24
Finished Jun 29 04:51:59 PM PDT 24
Peak memory 199988 kb
Host smart-0edd170a-03ae-43c9-9874-a83ba1eb5e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922257035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.922257035
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.141978893
Short name T1087
Test name
Test status
Simulation time 144454285100 ps
CPU time 176.59 seconds
Started Jun 29 04:51:28 PM PDT 24
Finished Jun 29 04:54:25 PM PDT 24
Peak memory 199992 kb
Host smart-1e745899-2836-4ec1-9266-b1f0d96f3772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141978893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.141978893
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.2597813231
Short name T164
Test name
Test status
Simulation time 50971549362 ps
CPU time 70.62 seconds
Started Jun 29 04:51:30 PM PDT 24
Finished Jun 29 04:52:41 PM PDT 24
Peak memory 199708 kb
Host smart-79ca4ad2-8d56-455d-8876-7c3c52866e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597813231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2597813231
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.3415704811
Short name T451
Test name
Test status
Simulation time 161661381550 ps
CPU time 114.64 seconds
Started Jun 29 04:51:28 PM PDT 24
Finished Jun 29 04:53:24 PM PDT 24
Peak memory 199888 kb
Host smart-00096604-eceb-4617-a054-c888167a51aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415704811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.3415704811
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.825529755
Short name T100
Test name
Test status
Simulation time 111684048596 ps
CPU time 279.74 seconds
Started Jun 29 04:51:28 PM PDT 24
Finished Jun 29 04:56:08 PM PDT 24
Peak memory 199928 kb
Host smart-a6fff7bb-8db8-4ae1-946b-b0a7e453f0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825529755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.825529755
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2666643530
Short name T904
Test name
Test status
Simulation time 20948588492 ps
CPU time 31.47 seconds
Started Jun 29 04:51:30 PM PDT 24
Finished Jun 29 04:52:02 PM PDT 24
Peak memory 199984 kb
Host smart-e495d693-fd5e-416d-9229-cbb23cb665c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666643530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2666643530
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.3290200227
Short name T945
Test name
Test status
Simulation time 38881453 ps
CPU time 0.58 seconds
Started Jun 29 04:48:44 PM PDT 24
Finished Jun 29 04:48:46 PM PDT 24
Peak memory 195304 kb
Host smart-e9f0952e-5810-41e4-ad7e-15ace8a6d731
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290200227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.3290200227
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.1760653766
Short name T590
Test name
Test status
Simulation time 132793218960 ps
CPU time 214.62 seconds
Started Jun 29 04:48:39 PM PDT 24
Finished Jun 29 04:52:14 PM PDT 24
Peak memory 199904 kb
Host smart-ed5c364e-3b77-4cca-b3f1-671cfa3038da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760653766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1760653766
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.3954227553
Short name T575
Test name
Test status
Simulation time 67091890481 ps
CPU time 141.1 seconds
Started Jun 29 04:48:45 PM PDT 24
Finished Jun 29 04:51:07 PM PDT 24
Peak memory 199912 kb
Host smart-205966c7-8686-4525-b191-b9dba06499b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954227553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3954227553
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.3957593209
Short name T601
Test name
Test status
Simulation time 88875364842 ps
CPU time 30.31 seconds
Started Jun 29 04:48:41 PM PDT 24
Finished Jun 29 04:49:12 PM PDT 24
Peak memory 199840 kb
Host smart-25620153-be56-4dcc-a75e-72aeefcdc023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957593209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3957593209
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.1375258121
Short name T1071
Test name
Test status
Simulation time 69268214847 ps
CPU time 48.66 seconds
Started Jun 29 04:48:45 PM PDT 24
Finished Jun 29 04:49:35 PM PDT 24
Peak memory 199928 kb
Host smart-36aa24a1-bb69-41c6-b17b-9e414b936862
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375258121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1375258121
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.3395640404
Short name T259
Test name
Test status
Simulation time 121836083726 ps
CPU time 208.08 seconds
Started Jun 29 04:48:45 PM PDT 24
Finished Jun 29 04:52:14 PM PDT 24
Peak memory 199996 kb
Host smart-fc16cc2c-6014-4451-a66d-cd6727b2ed1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3395640404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3395640404
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.653152424
Short name T667
Test name
Test status
Simulation time 10243542531 ps
CPU time 4.41 seconds
Started Jun 29 04:48:53 PM PDT 24
Finished Jun 29 04:48:58 PM PDT 24
Peak memory 199860 kb
Host smart-ed96f757-4857-4fda-90d0-378a05ab4959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653152424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.653152424
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.1619115988
Short name T1088
Test name
Test status
Simulation time 74674648514 ps
CPU time 24.03 seconds
Started Jun 29 04:48:43 PM PDT 24
Finished Jun 29 04:49:08 PM PDT 24
Peak memory 199888 kb
Host smart-0c051998-12af-41de-b873-74ac6807e5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619115988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.1619115988
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.830677748
Short name T268
Test name
Test status
Simulation time 11768565315 ps
CPU time 292.54 seconds
Started Jun 29 04:48:40 PM PDT 24
Finished Jun 29 04:53:33 PM PDT 24
Peak memory 199944 kb
Host smart-9c62c0e1-acfe-495e-a17f-02a37f5a1f1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=830677748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.830677748
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.2784892908
Short name T49
Test name
Test status
Simulation time 2765187453 ps
CPU time 6.38 seconds
Started Jun 29 04:48:35 PM PDT 24
Finished Jun 29 04:48:42 PM PDT 24
Peak memory 198300 kb
Host smart-5237fc8a-194b-48fe-be07-19246aa9b892
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2784892908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2784892908
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.2145641495
Short name T960
Test name
Test status
Simulation time 53422326068 ps
CPU time 33.31 seconds
Started Jun 29 04:48:53 PM PDT 24
Finished Jun 29 04:49:27 PM PDT 24
Peak memory 199948 kb
Host smart-9fcbdcca-3e24-4044-ae6a-b8ca83622985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145641495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2145641495
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.351408662
Short name T623
Test name
Test status
Simulation time 6776720998 ps
CPU time 6.2 seconds
Started Jun 29 04:48:52 PM PDT 24
Finished Jun 29 04:48:59 PM PDT 24
Peak memory 196228 kb
Host smart-3743eb8a-dd6e-4330-aebb-451c85450289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351408662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.351408662
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1844002342
Short name T569
Test name
Test status
Simulation time 430369062 ps
CPU time 2.5 seconds
Started Jun 29 04:48:39 PM PDT 24
Finished Jun 29 04:48:42 PM PDT 24
Peak memory 199280 kb
Host smart-5a8d1386-80ff-4ac3-b7bd-b2759e714083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844002342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1844002342
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.4290316387
Short name T428
Test name
Test status
Simulation time 8390968601 ps
CPU time 7.98 seconds
Started Jun 29 04:48:45 PM PDT 24
Finished Jun 29 04:48:54 PM PDT 24
Peak memory 199880 kb
Host smart-ba7da3b8-16db-4e4e-be86-4aea1c4a3152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290316387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.4290316387
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.1048126639
Short name T445
Test name
Test status
Simulation time 18758351072 ps
CPU time 25.78 seconds
Started Jun 29 04:48:35 PM PDT 24
Finished Jun 29 04:49:02 PM PDT 24
Peak memory 199972 kb
Host smart-ff67b52e-3a98-4c60-9ac9-87850343a2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048126639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1048126639
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1949240075
Short name T221
Test name
Test status
Simulation time 20585125655 ps
CPU time 33.17 seconds
Started Jun 29 04:51:30 PM PDT 24
Finished Jun 29 04:52:04 PM PDT 24
Peak memory 199792 kb
Host smart-c9390e90-4cbc-49b4-bb49-d86d7833b614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949240075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1949240075
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.1179241226
Short name T1073
Test name
Test status
Simulation time 121770352971 ps
CPU time 53.8 seconds
Started Jun 29 04:51:36 PM PDT 24
Finished Jun 29 04:52:30 PM PDT 24
Peak memory 199988 kb
Host smart-60e7b3ee-0d66-4266-aa01-6d6bf3098cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179241226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1179241226
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.4257042653
Short name T775
Test name
Test status
Simulation time 65387257984 ps
CPU time 157.33 seconds
Started Jun 29 04:51:35 PM PDT 24
Finished Jun 29 04:54:13 PM PDT 24
Peak memory 199892 kb
Host smart-8e7993f4-379a-4a1f-9c99-b71ba92cc392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257042653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.4257042653
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.3484208422
Short name T912
Test name
Test status
Simulation time 91476464122 ps
CPU time 137.73 seconds
Started Jun 29 04:51:36 PM PDT 24
Finished Jun 29 04:53:54 PM PDT 24
Peak memory 199744 kb
Host smart-e0c519ad-d715-4b34-93eb-e26d49aa0fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484208422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3484208422
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.2564586233
Short name T711
Test name
Test status
Simulation time 57365221374 ps
CPU time 43.2 seconds
Started Jun 29 04:51:35 PM PDT 24
Finished Jun 29 04:52:19 PM PDT 24
Peak memory 199904 kb
Host smart-28c89e7e-5368-4acb-9c48-91ac2c45e6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564586233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2564586233
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.4202553533
Short name T212
Test name
Test status
Simulation time 40634750970 ps
CPU time 31.08 seconds
Started Jun 29 04:51:37 PM PDT 24
Finished Jun 29 04:52:08 PM PDT 24
Peak memory 198600 kb
Host smart-09a7e377-1c0b-4af3-8a5f-4dfc00b4e357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202553533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.4202553533
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.145028925
Short name T947
Test name
Test status
Simulation time 292256980308 ps
CPU time 38.81 seconds
Started Jun 29 04:51:35 PM PDT 24
Finished Jun 29 04:52:14 PM PDT 24
Peak memory 199960 kb
Host smart-025f7143-50ff-400c-8372-167febb7d1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145028925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.145028925
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.2134353780
Short name T143
Test name
Test status
Simulation time 40249350639 ps
CPU time 20.37 seconds
Started Jun 29 04:51:36 PM PDT 24
Finished Jun 29 04:51:57 PM PDT 24
Peak memory 199988 kb
Host smart-d8c99b9f-b777-483d-bb4e-757a366cf9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134353780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2134353780
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.2122107161
Short name T1069
Test name
Test status
Simulation time 9220966936 ps
CPU time 20.1 seconds
Started Jun 29 04:51:35 PM PDT 24
Finished Jun 29 04:51:56 PM PDT 24
Peak memory 199976 kb
Host smart-8bc4751c-e008-41c5-924a-5a51b35be56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122107161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2122107161
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.3461530
Short name T919
Test name
Test status
Simulation time 42679836 ps
CPU time 0.56 seconds
Started Jun 29 04:48:44 PM PDT 24
Finished Jun 29 04:48:45 PM PDT 24
Peak memory 195304 kb
Host smart-0c9c7085-cce4-4791-8334-49bf97d4c3dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.3461530
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.336777570
Short name T956
Test name
Test status
Simulation time 168565323870 ps
CPU time 145.19 seconds
Started Jun 29 04:48:44 PM PDT 24
Finished Jun 29 04:51:10 PM PDT 24
Peak memory 199992 kb
Host smart-375ff6f3-9d96-4026-b5af-75d6d447a7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336777570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.336777570
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.867982438
Short name T855
Test name
Test status
Simulation time 44910200271 ps
CPU time 71.56 seconds
Started Jun 29 04:48:53 PM PDT 24
Finished Jun 29 04:50:05 PM PDT 24
Peak memory 199896 kb
Host smart-4bb2dfd3-45f4-4481-be7c-e7b10275dc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867982438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.867982438
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.231379536
Short name T166
Test name
Test status
Simulation time 10713287627 ps
CPU time 8.97 seconds
Started Jun 29 04:48:51 PM PDT 24
Finished Jun 29 04:49:00 PM PDT 24
Peak memory 199512 kb
Host smart-51257c50-6e70-4d84-9e79-18f91a0764b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231379536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.231379536
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.3655040401
Short name T409
Test name
Test status
Simulation time 42805311282 ps
CPU time 38.86 seconds
Started Jun 29 04:48:46 PM PDT 24
Finished Jun 29 04:49:25 PM PDT 24
Peak memory 199836 kb
Host smart-92c4dabd-308d-4198-9359-865833066970
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655040401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3655040401
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1012420309
Short name T917
Test name
Test status
Simulation time 112195964320 ps
CPU time 619.09 seconds
Started Jun 29 04:48:43 PM PDT 24
Finished Jun 29 04:59:03 PM PDT 24
Peak memory 199880 kb
Host smart-5876394a-097f-42c6-9668-2beced5b0954
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1012420309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1012420309
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.3632538432
Short name T848
Test name
Test status
Simulation time 12299478299 ps
CPU time 20.39 seconds
Started Jun 29 04:48:41 PM PDT 24
Finished Jun 29 04:49:02 PM PDT 24
Peak memory 199924 kb
Host smart-686c9b27-215b-4745-a0a6-c8ccc5b9134c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632538432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3632538432
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_perf.3776837487
Short name T19
Test name
Test status
Simulation time 31293861863 ps
CPU time 1411.81 seconds
Started Jun 29 04:48:42 PM PDT 24
Finished Jun 29 05:12:14 PM PDT 24
Peak memory 199976 kb
Host smart-761dfb19-0111-431b-b321-fed9cbab35eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3776837487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3776837487
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.4007781239
Short name T1089
Test name
Test status
Simulation time 2686162599 ps
CPU time 4.98 seconds
Started Jun 29 04:48:54 PM PDT 24
Finished Jun 29 04:48:59 PM PDT 24
Peak memory 198368 kb
Host smart-4be22922-033c-42da-9e31-f258f50aecfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4007781239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.4007781239
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1573637966
Short name T112
Test name
Test status
Simulation time 49121564064 ps
CPU time 67.6 seconds
Started Jun 29 04:48:47 PM PDT 24
Finished Jun 29 04:49:55 PM PDT 24
Peak memory 199880 kb
Host smart-f13cc4e8-bed3-489a-8b5b-f21e56f5ff07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573637966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1573637966
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.4063114520
Short name T474
Test name
Test status
Simulation time 1404575101 ps
CPU time 2.74 seconds
Started Jun 29 04:48:57 PM PDT 24
Finished Jun 29 04:49:01 PM PDT 24
Peak memory 195420 kb
Host smart-72c6a8a9-1498-4856-bd82-a6cd4d10b3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063114520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.4063114520
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.1530882500
Short name T366
Test name
Test status
Simulation time 131678013 ps
CPU time 0.92 seconds
Started Jun 29 04:48:43 PM PDT 24
Finished Jun 29 04:48:45 PM PDT 24
Peak memory 197868 kb
Host smart-c8703015-cef7-4ce2-8700-10dc13371129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530882500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1530882500
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.4200296534
Short name T9
Test name
Test status
Simulation time 1685617120 ps
CPU time 1.53 seconds
Started Jun 29 04:48:53 PM PDT 24
Finished Jun 29 04:48:55 PM PDT 24
Peak memory 198708 kb
Host smart-77b3266e-a524-484e-859e-fa3a2766e4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200296534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.4200296534
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.2942758350
Short name T512
Test name
Test status
Simulation time 8927032690 ps
CPU time 17.95 seconds
Started Jun 29 04:48:40 PM PDT 24
Finished Jun 29 04:48:59 PM PDT 24
Peak memory 199996 kb
Host smart-e75b47cd-e4af-4e5f-9fe5-9c559b459c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942758350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.2942758350
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2489537764
Short name T940
Test name
Test status
Simulation time 109203387200 ps
CPU time 211.75 seconds
Started Jun 29 04:51:35 PM PDT 24
Finished Jun 29 04:55:07 PM PDT 24
Peak memory 199928 kb
Host smart-df3133fd-64b9-49f7-9490-25e04f14fe55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489537764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2489537764
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1724429240
Short name T311
Test name
Test status
Simulation time 27665848016 ps
CPU time 45.99 seconds
Started Jun 29 04:51:35 PM PDT 24
Finished Jun 29 04:52:22 PM PDT 24
Peak memory 199844 kb
Host smart-bc49c2f0-865c-43fd-aded-a9a430db18e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724429240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1724429240
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.2767492185
Short name T492
Test name
Test status
Simulation time 26839114409 ps
CPU time 22.84 seconds
Started Jun 29 04:51:36 PM PDT 24
Finished Jun 29 04:52:00 PM PDT 24
Peak memory 198604 kb
Host smart-a9d9fdf5-4bcd-42a3-a1e1-e633ebd16b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767492185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2767492185
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.1767575550
Short name T813
Test name
Test status
Simulation time 72106481260 ps
CPU time 102.83 seconds
Started Jun 29 04:51:35 PM PDT 24
Finished Jun 29 04:53:19 PM PDT 24
Peak memory 199928 kb
Host smart-d250ea9a-3296-4e1b-bd22-3649aa5fb5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767575550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.1767575550
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2828155640
Short name T962
Test name
Test status
Simulation time 67190506702 ps
CPU time 30.43 seconds
Started Jun 29 04:51:47 PM PDT 24
Finished Jun 29 04:52:18 PM PDT 24
Peak memory 199960 kb
Host smart-758b7c52-58ef-49a3-be1c-57334dc7c210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828155640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2828155640
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.3123920985
Short name T755
Test name
Test status
Simulation time 53062792261 ps
CPU time 87.3 seconds
Started Jun 29 04:51:43 PM PDT 24
Finished Jun 29 04:53:12 PM PDT 24
Peak memory 199928 kb
Host smart-1beefad6-83c4-4b9c-9e41-48b456b6c9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123920985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.3123920985
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3927669599
Short name T152
Test name
Test status
Simulation time 26285169488 ps
CPU time 40.1 seconds
Started Jun 29 04:51:42 PM PDT 24
Finished Jun 29 04:52:23 PM PDT 24
Peak memory 199968 kb
Host smart-89ae3949-152a-4b99-9868-a9a0903a03ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927669599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3927669599
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.1569887054
Short name T740
Test name
Test status
Simulation time 48209265683 ps
CPU time 126.94 seconds
Started Jun 29 04:51:42 PM PDT 24
Finished Jun 29 04:53:50 PM PDT 24
Peak memory 199876 kb
Host smart-2403d9e8-45f3-4c5e-a158-ede9e42cb0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569887054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.1569887054
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.333690486
Short name T193
Test name
Test status
Simulation time 22302945926 ps
CPU time 37.21 seconds
Started Jun 29 04:51:47 PM PDT 24
Finished Jun 29 04:52:24 PM PDT 24
Peak memory 199716 kb
Host smart-cd1a1f7e-8f52-41f9-a4d3-16b438c944d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333690486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.333690486
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.4030313484
Short name T880
Test name
Test status
Simulation time 53563613 ps
CPU time 0.55 seconds
Started Jun 29 04:48:50 PM PDT 24
Finished Jun 29 04:48:51 PM PDT 24
Peak memory 195284 kb
Host smart-5db0dff5-dbbc-409d-89b2-850dd9f82e20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030313484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.4030313484
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.4208978544
Short name T103
Test name
Test status
Simulation time 16734699805 ps
CPU time 29.58 seconds
Started Jun 29 04:48:47 PM PDT 24
Finished Jun 29 04:49:17 PM PDT 24
Peak memory 199904 kb
Host smart-78516530-3615-421f-8dd1-c9ecc7091035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208978544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.4208978544
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.4028211253
Short name T677
Test name
Test status
Simulation time 29993335267 ps
CPU time 51.4 seconds
Started Jun 29 04:48:57 PM PDT 24
Finished Jun 29 04:49:49 PM PDT 24
Peak memory 199896 kb
Host smart-2fa5a3ea-e64e-478a-8830-61431530e1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028211253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.4028211253
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.1189659712
Short name T647
Test name
Test status
Simulation time 44888835452 ps
CPU time 18.88 seconds
Started Jun 29 04:48:48 PM PDT 24
Finished Jun 29 04:49:08 PM PDT 24
Peak memory 200012 kb
Host smart-a4ce04ce-ff62-4d08-b364-d094ee50c76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189659712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1189659712
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.3559475165
Short name T363
Test name
Test status
Simulation time 10461829480 ps
CPU time 1.92 seconds
Started Jun 29 04:48:54 PM PDT 24
Finished Jun 29 04:48:56 PM PDT 24
Peak memory 198596 kb
Host smart-25ac6818-7d8c-49aa-b64c-60d7d499306d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559475165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3559475165
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.2776044453
Short name T59
Test name
Test status
Simulation time 112863263309 ps
CPU time 267.39 seconds
Started Jun 29 04:48:49 PM PDT 24
Finished Jun 29 04:53:17 PM PDT 24
Peak memory 199908 kb
Host smart-845bc7db-9aff-4e6b-82e1-36050ee07b05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2776044453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.2776044453
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3955039542
Short name T10
Test name
Test status
Simulation time 3358075251 ps
CPU time 2.19 seconds
Started Jun 29 04:48:48 PM PDT 24
Finished Jun 29 04:48:51 PM PDT 24
Peak memory 196308 kb
Host smart-fc1bd4ba-8701-4e9b-a751-26ba0bc711e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955039542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3955039542
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_perf.1656699249
Short name T269
Test name
Test status
Simulation time 11408593213 ps
CPU time 31.01 seconds
Started Jun 29 04:48:47 PM PDT 24
Finished Jun 29 04:49:18 PM PDT 24
Peak memory 199980 kb
Host smart-f17d78ca-535b-4f13-a8fc-6d7c0d47a5cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1656699249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.1656699249
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.4172187264
Short name T375
Test name
Test status
Simulation time 3804819989 ps
CPU time 17.25 seconds
Started Jun 29 04:48:49 PM PDT 24
Finished Jun 29 04:49:07 PM PDT 24
Peak memory 198104 kb
Host smart-45d27837-5a02-4c13-9edb-646fd1b2988b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4172187264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.4172187264
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.2427940772
Short name T515
Test name
Test status
Simulation time 22423223355 ps
CPU time 9.53 seconds
Started Jun 29 04:48:54 PM PDT 24
Finished Jun 29 04:49:04 PM PDT 24
Peak memory 199920 kb
Host smart-33e4d81b-a816-47f4-84ee-c66355afffa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427940772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.2427940772
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.213499775
Short name T538
Test name
Test status
Simulation time 423433327 ps
CPU time 1.03 seconds
Started Jun 29 04:48:50 PM PDT 24
Finished Jun 29 04:48:51 PM PDT 24
Peak memory 195380 kb
Host smart-dc4779d7-6f6e-4e1f-bc7a-3f22bbaa380f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213499775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.213499775
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.4026890806
Short name T702
Test name
Test status
Simulation time 5735260533 ps
CPU time 6.26 seconds
Started Jun 29 04:48:53 PM PDT 24
Finished Jun 29 04:48:59 PM PDT 24
Peak memory 199652 kb
Host smart-0cf459e1-08e5-4d66-b9ca-c89cf5b466c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026890806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.4026890806
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.90290000
Short name T107
Test name
Test status
Simulation time 26645939540 ps
CPU time 215.84 seconds
Started Jun 29 04:48:49 PM PDT 24
Finished Jun 29 04:52:26 PM PDT 24
Peak memory 216576 kb
Host smart-09d779fb-fdea-4559-9f66-761e3cea4817
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90290000 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.90290000
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.1895982622
Short name T616
Test name
Test status
Simulation time 7789004317 ps
CPU time 11.53 seconds
Started Jun 29 04:48:50 PM PDT 24
Finished Jun 29 04:49:03 PM PDT 24
Peak memory 200204 kb
Host smart-7454e9b9-a76f-4f4c-9929-89826347e9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895982622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1895982622
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.141120970
Short name T918
Test name
Test status
Simulation time 19354909543 ps
CPU time 29.58 seconds
Started Jun 29 04:48:53 PM PDT 24
Finished Jun 29 04:49:23 PM PDT 24
Peak memory 199600 kb
Host smart-fc0a9c88-4742-48cb-a8c7-b549d47f3ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141120970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.141120970
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.1007138561
Short name T219
Test name
Test status
Simulation time 20857453031 ps
CPU time 15.39 seconds
Started Jun 29 04:51:45 PM PDT 24
Finished Jun 29 04:52:00 PM PDT 24
Peak memory 199964 kb
Host smart-321f2d7f-0b00-477a-a592-767b8bcdce4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007138561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.1007138561
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3302810291
Short name T253
Test name
Test status
Simulation time 21402126132 ps
CPU time 36.67 seconds
Started Jun 29 04:51:47 PM PDT 24
Finished Jun 29 04:52:24 PM PDT 24
Peak memory 199960 kb
Host smart-92f9c4c6-8abc-4f35-a7fc-bf1e67d738e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302810291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3302810291
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.2919846128
Short name T312
Test name
Test status
Simulation time 164612200328 ps
CPU time 56.91 seconds
Started Jun 29 04:51:44 PM PDT 24
Finished Jun 29 04:52:41 PM PDT 24
Peak memory 199968 kb
Host smart-eb571450-15e9-49ff-bb62-96d5d2ffea7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919846128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2919846128
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.3853851747
Short name T408
Test name
Test status
Simulation time 8982442340 ps
CPU time 17.86 seconds
Started Jun 29 04:51:43 PM PDT 24
Finished Jun 29 04:52:02 PM PDT 24
Peak memory 199988 kb
Host smart-71dd3091-6bf7-4a02-b052-662e4f310f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853851747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3853851747
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2172615752
Short name T749
Test name
Test status
Simulation time 17325358339 ps
CPU time 17.71 seconds
Started Jun 29 04:51:47 PM PDT 24
Finished Jun 29 04:52:05 PM PDT 24
Peak memory 199956 kb
Host smart-0f5fe71e-4a43-487d-85bb-35a3001a2b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172615752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2172615752
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.1789447602
Short name T1024
Test name
Test status
Simulation time 71718513576 ps
CPU time 22.94 seconds
Started Jun 29 04:51:44 PM PDT 24
Finished Jun 29 04:52:08 PM PDT 24
Peak memory 199904 kb
Host smart-d8ce7f2a-af26-43a4-a9f4-ea59a1e33cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789447602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1789447602
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.3812364224
Short name T142
Test name
Test status
Simulation time 73469247686 ps
CPU time 26.03 seconds
Started Jun 29 04:51:42 PM PDT 24
Finished Jun 29 04:52:09 PM PDT 24
Peak memory 199928 kb
Host smart-ab0a6c29-dd65-4a19-8fa2-05414e801d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812364224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3812364224
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.1272559636
Short name T224
Test name
Test status
Simulation time 28032302310 ps
CPU time 12.81 seconds
Started Jun 29 04:51:45 PM PDT 24
Finished Jun 29 04:51:58 PM PDT 24
Peak memory 199724 kb
Host smart-d7a9e27e-6031-437c-96a2-d0fe65e4041b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272559636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.1272559636
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.3153025059
Short name T265
Test name
Test status
Simulation time 64214309527 ps
CPU time 118.38 seconds
Started Jun 29 04:51:43 PM PDT 24
Finished Jun 29 04:53:43 PM PDT 24
Peak memory 199908 kb
Host smart-15062a54-0bdd-4865-b7b1-93478dbfc447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153025059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3153025059
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.256316021
Short name T1083
Test name
Test status
Simulation time 12529254 ps
CPU time 0.54 seconds
Started Jun 29 04:48:49 PM PDT 24
Finished Jun 29 04:48:50 PM PDT 24
Peak memory 194280 kb
Host smart-7c1d60e1-4b68-4315-ac39-c9fcdf3596e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256316021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.256316021
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.2534087440
Short name T289
Test name
Test status
Simulation time 103285440183 ps
CPU time 90.73 seconds
Started Jun 29 04:48:50 PM PDT 24
Finished Jun 29 04:50:22 PM PDT 24
Peak memory 199868 kb
Host smart-0d9d18c3-dbd1-4c4d-a8db-350c68027335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534087440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2534087440
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.806865242
Short name T752
Test name
Test status
Simulation time 57121864326 ps
CPU time 95.93 seconds
Started Jun 29 04:48:55 PM PDT 24
Finished Jun 29 04:50:32 PM PDT 24
Peak memory 199924 kb
Host smart-a37e2116-08e6-4c52-8ca6-c43e08afb630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806865242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.806865242
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.4082676617
Short name T146
Test name
Test status
Simulation time 59394083633 ps
CPU time 96.16 seconds
Started Jun 29 04:48:50 PM PDT 24
Finished Jun 29 04:50:27 PM PDT 24
Peak memory 199880 kb
Host smart-661db521-1dfa-4e46-8912-05625c705d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082676617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.4082676617
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.2553253640
Short name T118
Test name
Test status
Simulation time 353060806717 ps
CPU time 467.36 seconds
Started Jun 29 04:48:49 PM PDT 24
Finished Jun 29 04:56:37 PM PDT 24
Peak memory 199652 kb
Host smart-05d429e7-4149-4bba-8928-656e026f2646
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553253640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2553253640
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_loopback.4090291500
Short name T592
Test name
Test status
Simulation time 3581697477 ps
CPU time 7.31 seconds
Started Jun 29 04:48:49 PM PDT 24
Finished Jun 29 04:48:57 PM PDT 24
Peak memory 198864 kb
Host smart-fe3573c7-fdc8-4eba-9bd5-bdabaa7a2ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090291500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.4090291500
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_perf.499689277
Short name T496
Test name
Test status
Simulation time 8623256416 ps
CPU time 477.09 seconds
Started Jun 29 04:48:48 PM PDT 24
Finished Jun 29 04:56:47 PM PDT 24
Peak memory 199980 kb
Host smart-feeda8cf-7699-4a7f-ab27-ba4345f4ed06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=499689277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.499689277
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.2761479217
Short name T705
Test name
Test status
Simulation time 1927580264 ps
CPU time 1.01 seconds
Started Jun 29 04:48:47 PM PDT 24
Finished Jun 29 04:48:49 PM PDT 24
Peak memory 198124 kb
Host smart-7079614e-cd29-4b0d-aad7-485b7324d264
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2761479217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.2761479217
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.3934112704
Short name T256
Test name
Test status
Simulation time 19832427690 ps
CPU time 11.86 seconds
Started Jun 29 04:48:50 PM PDT 24
Finished Jun 29 04:49:03 PM PDT 24
Peak memory 198064 kb
Host smart-3128f7c1-d6b3-4069-9588-bbe9d7e2be6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934112704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3934112704
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.2352201975
Short name T524
Test name
Test status
Simulation time 38240933129 ps
CPU time 54.11 seconds
Started Jun 29 04:48:48 PM PDT 24
Finished Jun 29 04:49:43 PM PDT 24
Peak memory 195764 kb
Host smart-8c4109d0-4e23-43b0-878f-e189a41a4017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352201975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.2352201975
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.3420378359
Short name T552
Test name
Test status
Simulation time 449614457 ps
CPU time 1.42 seconds
Started Jun 29 04:48:49 PM PDT 24
Finished Jun 29 04:48:51 PM PDT 24
Peak memory 199704 kb
Host smart-847bbe4a-b49b-475a-9c4c-8917c6e41970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420378359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.3420378359
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.158295487
Short name T1019
Test name
Test status
Simulation time 6189238317 ps
CPU time 15.22 seconds
Started Jun 29 04:48:50 PM PDT 24
Finished Jun 29 04:49:06 PM PDT 24
Peak memory 199952 kb
Host smart-7c23d6ad-2184-4f9c-a6e5-263f1854c1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158295487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.158295487
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.3062224462
Short name T724
Test name
Test status
Simulation time 90091728615 ps
CPU time 126.22 seconds
Started Jun 29 04:48:50 PM PDT 24
Finished Jun 29 04:50:57 PM PDT 24
Peak memory 198492 kb
Host smart-d7482034-5a13-4001-9760-fd58be127889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062224462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3062224462
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.1413905018
Short name T1000
Test name
Test status
Simulation time 47530350590 ps
CPU time 556.67 seconds
Started Jun 29 04:51:43 PM PDT 24
Finished Jun 29 05:01:01 PM PDT 24
Peak memory 199896 kb
Host smart-4ba9bb7b-c5af-42c8-b5c0-d2e8718f4cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413905018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1413905018
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.980515035
Short name T539
Test name
Test status
Simulation time 115334943552 ps
CPU time 182.58 seconds
Started Jun 29 04:51:51 PM PDT 24
Finished Jun 29 04:54:54 PM PDT 24
Peak memory 199984 kb
Host smart-2dbfdb19-3d9a-4c78-954b-3209f00ea90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980515035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.980515035
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.938905393
Short name T537
Test name
Test status
Simulation time 9643931709 ps
CPU time 5.32 seconds
Started Jun 29 04:51:50 PM PDT 24
Finished Jun 29 04:51:56 PM PDT 24
Peak memory 199932 kb
Host smart-5fdc788f-3353-44fa-a915-f13e4645007c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938905393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.938905393
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.891900536
Short name T942
Test name
Test status
Simulation time 127868407781 ps
CPU time 25.87 seconds
Started Jun 29 04:51:51 PM PDT 24
Finished Jun 29 04:52:17 PM PDT 24
Peak memory 199916 kb
Host smart-3ec22c0b-becf-4808-92b6-69dc71dfc6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891900536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.891900536
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.4127584128
Short name T985
Test name
Test status
Simulation time 24856386482 ps
CPU time 10.12 seconds
Started Jun 29 04:51:53 PM PDT 24
Finished Jun 29 04:52:04 PM PDT 24
Peak memory 199984 kb
Host smart-22c3e63b-1da1-4d6b-a06d-ff4f0d14a88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127584128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.4127584128
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.735363318
Short name T550
Test name
Test status
Simulation time 9777792666 ps
CPU time 14.68 seconds
Started Jun 29 04:51:51 PM PDT 24
Finished Jun 29 04:52:06 PM PDT 24
Peak memory 199956 kb
Host smart-e0a5cd5f-63a2-4687-8ecb-cb171f6b78ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735363318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.735363318
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3992290083
Short name T998
Test name
Test status
Simulation time 28325607847 ps
CPU time 46.37 seconds
Started Jun 29 04:51:50 PM PDT 24
Finished Jun 29 04:52:37 PM PDT 24
Peak memory 199864 kb
Host smart-81610d03-6ef6-40bd-8f42-c77bc556031c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992290083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3992290083
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.991347939
Short name T225
Test name
Test status
Simulation time 22005954389 ps
CPU time 6.16 seconds
Started Jun 29 04:51:48 PM PDT 24
Finished Jun 29 04:51:55 PM PDT 24
Peak memory 199884 kb
Host smart-d8b34132-9999-47b6-9e14-d648f3f032a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991347939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.991347939
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.954312706
Short name T490
Test name
Test status
Simulation time 12889208 ps
CPU time 0.55 seconds
Started Jun 29 04:49:00 PM PDT 24
Finished Jun 29 04:49:01 PM PDT 24
Peak memory 195556 kb
Host smart-960e9630-ecdc-45b0-9d9f-b73d0ae34dad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954312706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.954312706
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.4070907795
Short name T548
Test name
Test status
Simulation time 44777366958 ps
CPU time 73.99 seconds
Started Jun 29 04:48:55 PM PDT 24
Finished Jun 29 04:50:10 PM PDT 24
Peak memory 199992 kb
Host smart-f93a0780-6475-4a35-a904-39ca880a52eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070907795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.4070907795
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1363001921
Short name T314
Test name
Test status
Simulation time 97148542180 ps
CPU time 59.46 seconds
Started Jun 29 04:48:57 PM PDT 24
Finished Jun 29 04:49:58 PM PDT 24
Peak memory 199984 kb
Host smart-218484fa-5538-44da-abf1-cbf670a3c695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363001921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1363001921
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.2796955997
Short name T476
Test name
Test status
Simulation time 159048221762 ps
CPU time 163.53 seconds
Started Jun 29 04:48:56 PM PDT 24
Finished Jun 29 04:51:41 PM PDT 24
Peak memory 199908 kb
Host smart-af6d2149-2c2f-4568-8ea6-7b8db06fd236
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2796955997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.2796955997
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.2460788105
Short name T893
Test name
Test status
Simulation time 470446291 ps
CPU time 0.88 seconds
Started Jun 29 04:48:56 PM PDT 24
Finished Jun 29 04:48:57 PM PDT 24
Peak memory 195964 kb
Host smart-aef289bd-f3cf-438e-8f95-93dd632f1306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460788105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.2460788105
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_perf.1713296193
Short name T426
Test name
Test status
Simulation time 8619304868 ps
CPU time 478.35 seconds
Started Jun 29 04:48:55 PM PDT 24
Finished Jun 29 04:56:54 PM PDT 24
Peak memory 199980 kb
Host smart-ef40ce5a-a7f2-4f9d-9ec5-588e35c00771
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1713296193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.1713296193
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.1960439319
Short name T419
Test name
Test status
Simulation time 5507093483 ps
CPU time 53.35 seconds
Started Jun 29 04:48:56 PM PDT 24
Finished Jun 29 04:49:50 PM PDT 24
Peak memory 198304 kb
Host smart-951ae6e9-1f1a-45bc-8710-7a4100a3a6f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1960439319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1960439319
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.2898966280
Short name T598
Test name
Test status
Simulation time 24868923039 ps
CPU time 36.48 seconds
Started Jun 29 04:48:57 PM PDT 24
Finished Jun 29 04:49:35 PM PDT 24
Peak memory 199984 kb
Host smart-83c528b6-b197-45a0-b63f-471454fa3a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898966280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2898966280
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.4064019235
Short name T452
Test name
Test status
Simulation time 3215768175 ps
CPU time 6.17 seconds
Started Jun 29 04:48:56 PM PDT 24
Finished Jun 29 04:49:03 PM PDT 24
Peak memory 196416 kb
Host smart-86319064-1b24-4afe-9b7b-19275414ed30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064019235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.4064019235
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.2092554539
Short name T754
Test name
Test status
Simulation time 732347693 ps
CPU time 3.85 seconds
Started Jun 29 04:48:50 PM PDT 24
Finished Jun 29 04:48:55 PM PDT 24
Peak memory 198428 kb
Host smart-b2a55d2f-99a9-4b91-a5db-ab1fbc616945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092554539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2092554539
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.2227923183
Short name T13
Test name
Test status
Simulation time 31385175035 ps
CPU time 342.44 seconds
Started Jun 29 04:48:55 PM PDT 24
Finished Jun 29 04:54:38 PM PDT 24
Peak memory 216208 kb
Host smart-d5b7203d-6116-4934-9267-ed4e9305c62f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227923183 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.2227923183
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.3263971875
Short name T771
Test name
Test status
Simulation time 7849410425 ps
CPU time 13.8 seconds
Started Jun 29 04:48:55 PM PDT 24
Finished Jun 29 04:49:09 PM PDT 24
Peak memory 199432 kb
Host smart-5b567e55-191d-4855-8beb-8a455b0e5b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263971875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3263971875
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2471990893
Short name T258
Test name
Test status
Simulation time 10516767382 ps
CPU time 29.74 seconds
Started Jun 29 04:48:56 PM PDT 24
Finished Jun 29 04:49:27 PM PDT 24
Peak memory 199916 kb
Host smart-665ddad4-7ddd-4668-9a53-eb23c88a67e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471990893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2471990893
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.620614881
Short name T858
Test name
Test status
Simulation time 173183064161 ps
CPU time 89.06 seconds
Started Jun 29 04:51:50 PM PDT 24
Finished Jun 29 04:53:19 PM PDT 24
Peak memory 200008 kb
Host smart-285c4ab6-eb77-433e-9be9-9263cb720d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620614881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.620614881
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.3829690188
Short name T192
Test name
Test status
Simulation time 103757207519 ps
CPU time 131.5 seconds
Started Jun 29 04:51:50 PM PDT 24
Finished Jun 29 04:54:02 PM PDT 24
Peak memory 199988 kb
Host smart-ccfeff6e-7707-42e1-8dbf-0deadb6122d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829690188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.3829690188
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.1811333665
Short name T467
Test name
Test status
Simulation time 166074612582 ps
CPU time 249.35 seconds
Started Jun 29 04:51:54 PM PDT 24
Finished Jun 29 04:56:03 PM PDT 24
Peak memory 199988 kb
Host smart-854d7411-ef19-4ca8-a07b-fcfa9d6a7c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811333665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1811333665
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1314711637
Short name T760
Test name
Test status
Simulation time 33878450149 ps
CPU time 49 seconds
Started Jun 29 04:51:50 PM PDT 24
Finished Jun 29 04:52:39 PM PDT 24
Peak memory 199828 kb
Host smart-042658f7-24e6-4329-bc7c-8afb0c6f56e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314711637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1314711637
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.3720796207
Short name T218
Test name
Test status
Simulation time 113404359338 ps
CPU time 107.68 seconds
Started Jun 29 04:51:51 PM PDT 24
Finished Jun 29 04:53:39 PM PDT 24
Peak memory 200012 kb
Host smart-eca4eb6a-a43f-48b4-aabc-2613057f1d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720796207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3720796207
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.617789414
Short name T198
Test name
Test status
Simulation time 215754227898 ps
CPU time 269.77 seconds
Started Jun 29 04:51:52 PM PDT 24
Finished Jun 29 04:56:22 PM PDT 24
Peak memory 199988 kb
Host smart-2158d21b-4c74-4732-aaf1-87744aa24583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617789414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.617789414
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.1025556074
Short name T222
Test name
Test status
Simulation time 71180914492 ps
CPU time 89.46 seconds
Started Jun 29 04:51:49 PM PDT 24
Finished Jun 29 04:53:19 PM PDT 24
Peak memory 199904 kb
Host smart-178d8efe-a3c4-4c6c-bf18-b5d97dd67f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025556074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.1025556074
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.724372024
Short name T1060
Test name
Test status
Simulation time 20468266236 ps
CPU time 44.52 seconds
Started Jun 29 04:51:52 PM PDT 24
Finished Jun 29 04:52:37 PM PDT 24
Peak memory 199952 kb
Host smart-20689234-fb9d-4810-b515-5df614e03476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724372024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.724372024
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.2915683327
Short name T609
Test name
Test status
Simulation time 98272748663 ps
CPU time 144.83 seconds
Started Jun 29 04:51:53 PM PDT 24
Finished Jun 29 04:54:18 PM PDT 24
Peak memory 199988 kb
Host smart-435062da-0c7f-4086-9b8e-6346f065eef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915683327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2915683327
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.305534949
Short name T776
Test name
Test status
Simulation time 8798582509 ps
CPU time 7.2 seconds
Started Jun 29 04:51:53 PM PDT 24
Finished Jun 29 04:52:00 PM PDT 24
Peak memory 199984 kb
Host smart-c7615f07-3e22-4cb1-96ce-b0355408a153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305534949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.305534949
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.614812921
Short name T25
Test name
Test status
Simulation time 14245181 ps
CPU time 0.56 seconds
Started Jun 29 04:48:57 PM PDT 24
Finished Jun 29 04:48:59 PM PDT 24
Peak memory 195228 kb
Host smart-a8d30afd-43f8-4c07-bd7e-4e2c6614692f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614812921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.614812921
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.4088932600
Short name T307
Test name
Test status
Simulation time 111559558762 ps
CPU time 68.18 seconds
Started Jun 29 04:48:58 PM PDT 24
Finished Jun 29 04:50:07 PM PDT 24
Peak memory 199872 kb
Host smart-6a1517e2-b340-4855-8f8e-dadc4a8e765a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088932600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.4088932600
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.2898872763
Short name T137
Test name
Test status
Simulation time 23073440312 ps
CPU time 36.39 seconds
Started Jun 29 04:48:55 PM PDT 24
Finished Jun 29 04:49:32 PM PDT 24
Peak memory 199760 kb
Host smart-41aeb419-d7c9-4b42-abc7-249040d9f937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898872763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.2898872763
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.672106001
Short name T742
Test name
Test status
Simulation time 96225984087 ps
CPU time 65.04 seconds
Started Jun 29 04:48:55 PM PDT 24
Finished Jun 29 04:50:01 PM PDT 24
Peak memory 199844 kb
Host smart-b694de17-6582-4520-90bb-df3f79eb2bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672106001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.672106001
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.67676203
Short name T900
Test name
Test status
Simulation time 28066089136 ps
CPU time 11.65 seconds
Started Jun 29 04:48:57 PM PDT 24
Finished Jun 29 04:49:10 PM PDT 24
Peak memory 199932 kb
Host smart-c5332e4d-f68a-44a4-abcc-90a37c0a2184
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67676203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.67676203
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.674411977
Short name T978
Test name
Test status
Simulation time 116287456054 ps
CPU time 914.44 seconds
Started Jun 29 04:48:58 PM PDT 24
Finished Jun 29 05:04:14 PM PDT 24
Peak memory 200188 kb
Host smart-c9553127-862d-4596-8030-6cbcdcde74ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=674411977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.674411977
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.3042789333
Short name T381
Test name
Test status
Simulation time 4494278869 ps
CPU time 3.42 seconds
Started Jun 29 04:48:56 PM PDT 24
Finished Jun 29 04:49:00 PM PDT 24
Peak memory 198460 kb
Host smart-8a92a121-f7b6-4bb2-a503-12e732b8d232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042789333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3042789333
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_perf.518885411
Short name T303
Test name
Test status
Simulation time 7327530410 ps
CPU time 386.86 seconds
Started Jun 29 04:48:59 PM PDT 24
Finished Jun 29 04:55:27 PM PDT 24
Peak memory 199952 kb
Host smart-0383a2ff-4eb3-4784-a293-e2a19bfd6146
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=518885411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.518885411
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.3213506570
Short name T661
Test name
Test status
Simulation time 5895965730 ps
CPU time 11.55 seconds
Started Jun 29 04:48:56 PM PDT 24
Finished Jun 29 04:49:08 PM PDT 24
Peak memory 199216 kb
Host smart-66bda9a2-91bc-4f8b-b557-cc237701e84a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3213506570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3213506570
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.3698895012
Short name T271
Test name
Test status
Simulation time 125987948154 ps
CPU time 67.82 seconds
Started Jun 29 04:48:57 PM PDT 24
Finished Jun 29 04:50:06 PM PDT 24
Peak memory 199984 kb
Host smart-fb98ff41-24b9-485f-82de-7cf9a22defd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698895012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3698895012
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.1208979397
Short name T325
Test name
Test status
Simulation time 82524731180 ps
CPU time 127.09 seconds
Started Jun 29 04:48:55 PM PDT 24
Finished Jun 29 04:51:03 PM PDT 24
Peak memory 196224 kb
Host smart-1a67952b-f230-40e5-ad42-d1dfb28fb1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208979397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1208979397
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.1152053010
Short name T602
Test name
Test status
Simulation time 919436723 ps
CPU time 1.89 seconds
Started Jun 29 04:48:59 PM PDT 24
Finished Jun 29 04:49:01 PM PDT 24
Peak memory 198352 kb
Host smart-b9845eb8-0964-4baf-8dee-4ca70c410c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152053010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1152053010
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.3461465564
Short name T671
Test name
Test status
Simulation time 66746208868 ps
CPU time 180.28 seconds
Started Jun 29 04:48:57 PM PDT 24
Finished Jun 29 04:51:59 PM PDT 24
Peak memory 215652 kb
Host smart-60776844-1711-43e7-89ef-f41162bd0467
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461465564 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.3461465564
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.807657783
Short name T416
Test name
Test status
Simulation time 745647917 ps
CPU time 2.72 seconds
Started Jun 29 04:48:59 PM PDT 24
Finished Jun 29 04:49:02 PM PDT 24
Peak memory 199872 kb
Host smart-52d3a10e-9123-4754-90f3-431c368a5aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807657783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.807657783
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.3097159395
Short name T615
Test name
Test status
Simulation time 58103014343 ps
CPU time 24.45 seconds
Started Jun 29 04:48:57 PM PDT 24
Finished Jun 29 04:49:22 PM PDT 24
Peak memory 199908 kb
Host smart-3f335e96-f53f-49e6-9e39-14f7824008bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097159395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3097159395
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.2108431041
Short name T306
Test name
Test status
Simulation time 25234388274 ps
CPU time 40.04 seconds
Started Jun 29 04:51:51 PM PDT 24
Finished Jun 29 04:52:31 PM PDT 24
Peak memory 199968 kb
Host smart-f31bc153-d28a-4fef-ae36-cc67c57f7292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108431041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.2108431041
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.3307428613
Short name T951
Test name
Test status
Simulation time 106981098843 ps
CPU time 149.34 seconds
Started Jun 29 04:51:52 PM PDT 24
Finished Jun 29 04:54:22 PM PDT 24
Peak memory 199984 kb
Host smart-e24a4d5d-cbab-4ea1-b727-8b54dbe141ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307428613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3307428613
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.767777697
Short name T800
Test name
Test status
Simulation time 33448067475 ps
CPU time 19.44 seconds
Started Jun 29 04:51:52 PM PDT 24
Finished Jun 29 04:52:12 PM PDT 24
Peak memory 199852 kb
Host smart-06e186b4-d883-4b4e-9cb4-ad4ca64797f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767777697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.767777697
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.3475001934
Short name T345
Test name
Test status
Simulation time 42857617132 ps
CPU time 26.72 seconds
Started Jun 29 04:51:59 PM PDT 24
Finished Jun 29 04:52:26 PM PDT 24
Peak memory 199988 kb
Host smart-d303ff43-7774-45d7-9dbd-681964d83b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475001934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3475001934
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.897283478
Short name T199
Test name
Test status
Simulation time 33275196521 ps
CPU time 24.75 seconds
Started Jun 29 04:51:59 PM PDT 24
Finished Jun 29 04:52:24 PM PDT 24
Peak memory 199936 kb
Host smart-e5c30b0c-617f-4177-a020-435c046b4fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897283478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.897283478
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.2079043395
Short name T656
Test name
Test status
Simulation time 37928486694 ps
CPU time 31.63 seconds
Started Jun 29 04:51:57 PM PDT 24
Finished Jun 29 04:52:29 PM PDT 24
Peak memory 199988 kb
Host smart-0a74e42c-f1b7-494d-bf22-75600c0d1a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079043395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2079043395
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.3826406410
Short name T735
Test name
Test status
Simulation time 36842456502 ps
CPU time 28.89 seconds
Started Jun 29 04:51:57 PM PDT 24
Finished Jun 29 04:52:26 PM PDT 24
Peak memory 200012 kb
Host smart-9d6968de-f8d1-49bb-b5d3-a47071bf26fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826406410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3826406410
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.3805365737
Short name T505
Test name
Test status
Simulation time 127838500985 ps
CPU time 53.15 seconds
Started Jun 29 04:51:57 PM PDT 24
Finished Jun 29 04:52:50 PM PDT 24
Peak memory 199920 kb
Host smart-9c11f45a-593f-4f22-a800-5f6a1cd48898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805365737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3805365737
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.983125538
Short name T847
Test name
Test status
Simulation time 94244418492 ps
CPU time 39.54 seconds
Started Jun 29 04:51:58 PM PDT 24
Finished Jun 29 04:52:38 PM PDT 24
Peak memory 199952 kb
Host smart-68d54bdb-06c4-4b13-8a08-414770b34ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983125538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.983125538
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.291925367
Short name T1066
Test name
Test status
Simulation time 29996651 ps
CPU time 0.57 seconds
Started Jun 29 04:49:03 PM PDT 24
Finished Jun 29 04:49:04 PM PDT 24
Peak memory 195588 kb
Host smart-8bc6b0e3-f15c-47fb-ac36-3b5d46177c43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291925367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.291925367
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.2699283140
Short name T1079
Test name
Test status
Simulation time 103809922062 ps
CPU time 22.31 seconds
Started Jun 29 04:49:02 PM PDT 24
Finished Jun 29 04:49:25 PM PDT 24
Peak memory 199988 kb
Host smart-7ce23318-ee44-4df4-a81c-0de5005c6fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699283140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2699283140
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.1742348217
Short name T744
Test name
Test status
Simulation time 255625430938 ps
CPU time 96.29 seconds
Started Jun 29 04:49:09 PM PDT 24
Finished Jun 29 04:50:46 PM PDT 24
Peak memory 199928 kb
Host smart-7420c2b7-51eb-4f79-a247-28b3f387060f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742348217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.1742348217
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.3988626795
Short name T955
Test name
Test status
Simulation time 33210471563 ps
CPU time 13.96 seconds
Started Jun 29 04:49:05 PM PDT 24
Finished Jun 29 04:49:20 PM PDT 24
Peak memory 199900 kb
Host smart-94ef1047-c5de-4634-a845-47f9b2089e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988626795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.3988626795
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.2021334622
Short name T534
Test name
Test status
Simulation time 110093815331 ps
CPU time 81.19 seconds
Started Jun 29 04:49:05 PM PDT 24
Finished Jun 29 04:50:27 PM PDT 24
Peak memory 199980 kb
Host smart-3ebc693c-4cb9-4db5-ba77-82d415a16687
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021334622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.2021334622
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.1297519287
Short name T811
Test name
Test status
Simulation time 102387353023 ps
CPU time 540.54 seconds
Started Jun 29 04:49:05 PM PDT 24
Finished Jun 29 04:58:06 PM PDT 24
Peak memory 200188 kb
Host smart-02bafa16-bbbf-40c6-b589-88713e8d523c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1297519287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.1297519287
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.3359267339
Short name T378
Test name
Test status
Simulation time 1290668617 ps
CPU time 1.7 seconds
Started Jun 29 04:49:07 PM PDT 24
Finished Jun 29 04:49:09 PM PDT 24
Peak memory 195404 kb
Host smart-34ef43b7-51f3-44f5-94d1-5ecfb5f9d9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359267339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.3359267339
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_perf.943939608
Short name T542
Test name
Test status
Simulation time 14091953039 ps
CPU time 167.19 seconds
Started Jun 29 04:49:09 PM PDT 24
Finished Jun 29 04:51:56 PM PDT 24
Peak memory 199920 kb
Host smart-347f0c4e-6842-480e-ace5-a971260f986b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=943939608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.943939608
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.3113664451
Short name T482
Test name
Test status
Simulation time 2089749371 ps
CPU time 11.61 seconds
Started Jun 29 04:49:06 PM PDT 24
Finished Jun 29 04:49:18 PM PDT 24
Peak memory 197928 kb
Host smart-33ae9acf-f1f8-49e2-8392-05ea43f9a423
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3113664451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.3113664451
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.2702872726
Short name T134
Test name
Test status
Simulation time 100856539310 ps
CPU time 50.17 seconds
Started Jun 29 04:49:09 PM PDT 24
Finished Jun 29 04:49:59 PM PDT 24
Peak memory 199980 kb
Host smart-5154a93a-249f-48ef-a702-40e05160ae51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702872726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2702872726
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.2128852699
Short name T973
Test name
Test status
Simulation time 1887948636 ps
CPU time 1.27 seconds
Started Jun 29 04:49:06 PM PDT 24
Finished Jun 29 04:49:08 PM PDT 24
Peak memory 195584 kb
Host smart-edae2110-8df7-434c-b453-36eb33126997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128852699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2128852699
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.22400067
Short name T763
Test name
Test status
Simulation time 473924330 ps
CPU time 1.46 seconds
Started Jun 29 04:48:58 PM PDT 24
Finished Jun 29 04:49:00 PM PDT 24
Peak memory 198932 kb
Host smart-ea916d2d-3c85-4d35-a406-29a2c543ca22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22400067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.22400067
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.3193006524
Short name T953
Test name
Test status
Simulation time 5025857829 ps
CPU time 9.64 seconds
Started Jun 29 04:49:03 PM PDT 24
Finished Jun 29 04:49:13 PM PDT 24
Peak memory 200032 kb
Host smart-c44300b5-b2a4-44b1-976e-3aa7c75940fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193006524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3193006524
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.1646028822
Short name T335
Test name
Test status
Simulation time 53699406415 ps
CPU time 806.4 seconds
Started Jun 29 04:49:09 PM PDT 24
Finished Jun 29 05:02:36 PM PDT 24
Peak memory 216492 kb
Host smart-28bb8d9d-d959-4ce6-906c-8ed44d32bd19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646028822 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.1646028822
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.2359519625
Short name T380
Test name
Test status
Simulation time 1007299791 ps
CPU time 4.09 seconds
Started Jun 29 04:49:05 PM PDT 24
Finished Jun 29 04:49:10 PM PDT 24
Peak memory 199900 kb
Host smart-be7a6e33-6f35-4418-82df-cdcb601a9782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359519625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2359519625
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.2896431068
Short name T793
Test name
Test status
Simulation time 54372555994 ps
CPU time 45.77 seconds
Started Jun 29 04:49:07 PM PDT 24
Finished Jun 29 04:49:53 PM PDT 24
Peak memory 199852 kb
Host smart-c66951f9-d07e-4990-916e-3401550591fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896431068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.2896431068
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.3147460147
Short name T841
Test name
Test status
Simulation time 30074310658 ps
CPU time 29.21 seconds
Started Jun 29 04:51:57 PM PDT 24
Finished Jun 29 04:52:27 PM PDT 24
Peak memory 199992 kb
Host smart-60510acf-93be-4df1-bce6-2f2b43298092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147460147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3147460147
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.3194083979
Short name T809
Test name
Test status
Simulation time 83205570686 ps
CPU time 27.32 seconds
Started Jun 29 04:51:58 PM PDT 24
Finished Jun 29 04:52:25 PM PDT 24
Peak memory 199952 kb
Host smart-31d0ac0e-626c-48d8-a8f5-338407529d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194083979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3194083979
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.980799467
Short name T251
Test name
Test status
Simulation time 24962708870 ps
CPU time 11.66 seconds
Started Jun 29 04:51:59 PM PDT 24
Finished Jun 29 04:52:11 PM PDT 24
Peak memory 199076 kb
Host smart-298017d3-acbb-4da0-9b83-4f278c10992d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980799467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.980799467
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.3663191463
Short name T229
Test name
Test status
Simulation time 123663859297 ps
CPU time 56.31 seconds
Started Jun 29 04:51:58 PM PDT 24
Finished Jun 29 04:52:55 PM PDT 24
Peak memory 199876 kb
Host smart-8ff350cd-b490-4d92-8231-5a9d1a5fc0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663191463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3663191463
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.978810673
Short name T404
Test name
Test status
Simulation time 40706454914 ps
CPU time 14.91 seconds
Started Jun 29 04:52:03 PM PDT 24
Finished Jun 29 04:52:18 PM PDT 24
Peak memory 199948 kb
Host smart-d3a0f77c-8018-454e-a962-82ded045235f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978810673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.978810673
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.795072996
Short name T707
Test name
Test status
Simulation time 33870867008 ps
CPU time 14.7 seconds
Started Jun 29 04:51:58 PM PDT 24
Finished Jun 29 04:52:14 PM PDT 24
Peak memory 199924 kb
Host smart-792a88ad-0c6d-4b00-9594-1cad392ce9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795072996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.795072996
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3826484569
Short name T636
Test name
Test status
Simulation time 92018211027 ps
CPU time 22.58 seconds
Started Jun 29 04:52:03 PM PDT 24
Finished Jun 29 04:52:26 PM PDT 24
Peak memory 199928 kb
Host smart-e34ca9c5-4369-4b3e-a6fe-3578accd61cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826484569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3826484569
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.3225329055
Short name T204
Test name
Test status
Simulation time 52925643732 ps
CPU time 72.38 seconds
Started Jun 29 04:51:58 PM PDT 24
Finished Jun 29 04:53:11 PM PDT 24
Peak memory 199984 kb
Host smart-c96d0a95-838e-475b-a002-f9cfc5590e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225329055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.3225329055
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.3461782564
Short name T197
Test name
Test status
Simulation time 18424415070 ps
CPU time 25.07 seconds
Started Jun 29 04:51:59 PM PDT 24
Finished Jun 29 04:52:25 PM PDT 24
Peak memory 199788 kb
Host smart-dda4855b-45c4-4ffa-b24c-68ac02e617ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461782564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3461782564
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.1085255648
Short name T1021
Test name
Test status
Simulation time 74106131 ps
CPU time 0.56 seconds
Started Jun 29 04:49:05 PM PDT 24
Finished Jun 29 04:49:06 PM PDT 24
Peak memory 195272 kb
Host smart-bb46ff31-5288-4c93-a6b0-aa86cced58f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085255648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1085255648
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.1050340627
Short name T585
Test name
Test status
Simulation time 122287083016 ps
CPU time 197 seconds
Started Jun 29 04:49:10 PM PDT 24
Finished Jun 29 04:52:27 PM PDT 24
Peak memory 199988 kb
Host smart-57b061b5-55d0-4c34-addb-2d45bcbad2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050340627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.1050340627
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.2857159364
Short name T1038
Test name
Test status
Simulation time 73335964330 ps
CPU time 105.33 seconds
Started Jun 29 04:49:05 PM PDT 24
Finished Jun 29 04:50:51 PM PDT 24
Peak memory 199984 kb
Host smart-2062a48d-2f5a-46f4-b803-d279c5865cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857159364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2857159364
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.821586038
Short name T368
Test name
Test status
Simulation time 56696086976 ps
CPU time 52.05 seconds
Started Jun 29 04:49:03 PM PDT 24
Finished Jun 29 04:49:55 PM PDT 24
Peak memory 199808 kb
Host smart-712b4c60-bc6c-4749-9fbb-35188f30188f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821586038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.821586038
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.359985242
Short name T943
Test name
Test status
Simulation time 25490485657 ps
CPU time 7.82 seconds
Started Jun 29 04:49:04 PM PDT 24
Finished Jun 29 04:49:13 PM PDT 24
Peak memory 197860 kb
Host smart-1e781f18-a8fc-4289-952c-9cbf94be4b93
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359985242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.359985242
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.3047366632
Short name T1002
Test name
Test status
Simulation time 66050743567 ps
CPU time 337.48 seconds
Started Jun 29 04:49:04 PM PDT 24
Finished Jun 29 04:54:42 PM PDT 24
Peak memory 199968 kb
Host smart-6b151c87-3ded-4bad-9ac8-5d3994a77a3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3047366632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.3047366632
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.3327245023
Short name T488
Test name
Test status
Simulation time 8150264445 ps
CPU time 11.05 seconds
Started Jun 29 04:49:03 PM PDT 24
Finished Jun 29 04:49:15 PM PDT 24
Peak memory 198512 kb
Host smart-926a7c87-9ada-4972-b60f-a1e79279658a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327245023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.3327245023
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_perf.456338310
Short name T691
Test name
Test status
Simulation time 7974470515 ps
CPU time 222.93 seconds
Started Jun 29 04:49:05 PM PDT 24
Finished Jun 29 04:52:49 PM PDT 24
Peak memory 199980 kb
Host smart-bdf594d6-3bf3-47d1-8260-e845629e5ac4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=456338310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.456338310
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.258896594
Short name T624
Test name
Test status
Simulation time 3729034399 ps
CPU time 3.49 seconds
Started Jun 29 04:49:03 PM PDT 24
Finished Jun 29 04:49:07 PM PDT 24
Peak memory 197964 kb
Host smart-1d8f684d-e548-424a-b265-733dd7240df0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=258896594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.258896594
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.737812581
Short name T115
Test name
Test status
Simulation time 2751674912 ps
CPU time 2.74 seconds
Started Jun 29 04:49:10 PM PDT 24
Finished Jun 29 04:49:13 PM PDT 24
Peak memory 196488 kb
Host smart-3141cf27-6690-480c-8673-d9d5b6107d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737812581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.737812581
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.2198812380
Short name T1046
Test name
Test status
Simulation time 544664446 ps
CPU time 1.92 seconds
Started Jun 29 04:49:09 PM PDT 24
Finished Jun 29 04:49:11 PM PDT 24
Peak memory 198460 kb
Host smart-a075b36f-933d-475d-bd53-3b52cb791640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198812380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.2198812380
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.451951778
Short name T1047
Test name
Test status
Simulation time 75530099056 ps
CPU time 35.51 seconds
Started Jun 29 04:49:05 PM PDT 24
Finished Jun 29 04:49:41 PM PDT 24
Peak memory 199980 kb
Host smart-99df0dfd-82ba-4900-9171-4342bec21168
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451951778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.451951778
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.645697889
Short name T333
Test name
Test status
Simulation time 32098621331 ps
CPU time 648.8 seconds
Started Jun 29 04:49:05 PM PDT 24
Finished Jun 29 04:59:55 PM PDT 24
Peak memory 216040 kb
Host smart-c26de79d-d717-4360-b7e0-762c32810b1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645697889 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.645697889
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1225100408
Short name T827
Test name
Test status
Simulation time 1860937061 ps
CPU time 2.97 seconds
Started Jun 29 04:49:04 PM PDT 24
Finished Jun 29 04:49:07 PM PDT 24
Peak memory 199664 kb
Host smart-c4d6c884-c912-4bf4-b0df-ebf4ce44ced6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225100408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1225100408
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.3529410085
Short name T462
Test name
Test status
Simulation time 38388683142 ps
CPU time 50.43 seconds
Started Jun 29 04:49:03 PM PDT 24
Finished Jun 29 04:49:54 PM PDT 24
Peak memory 199988 kb
Host smart-7045da19-629c-4a4d-9f65-bf1bd566967d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529410085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3529410085
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.398275493
Short name T435
Test name
Test status
Simulation time 140129440037 ps
CPU time 14.86 seconds
Started Jun 29 04:51:58 PM PDT 24
Finished Jun 29 04:52:13 PM PDT 24
Peak memory 198908 kb
Host smart-cbe8149b-78a0-49ef-bd23-55b89fadae67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398275493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.398275493
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.3102046425
Short name T695
Test name
Test status
Simulation time 43091032150 ps
CPU time 68.72 seconds
Started Jun 29 04:52:03 PM PDT 24
Finished Jun 29 04:53:12 PM PDT 24
Peak memory 199988 kb
Host smart-d42edfde-2a18-4bd4-b2dd-ac45e388a91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102046425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.3102046425
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.2374109547
Short name T349
Test name
Test status
Simulation time 135813939906 ps
CPU time 200.3 seconds
Started Jun 29 04:51:58 PM PDT 24
Finished Jun 29 04:55:19 PM PDT 24
Peak memory 199904 kb
Host smart-08162184-6078-4871-b754-a8ed34385cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374109547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.2374109547
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.1201054404
Short name T630
Test name
Test status
Simulation time 23213828616 ps
CPU time 40.97 seconds
Started Jun 29 04:51:58 PM PDT 24
Finished Jun 29 04:52:40 PM PDT 24
Peak memory 199952 kb
Host smart-c5a2b670-0b4b-49e8-b365-f2bf1572dae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201054404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1201054404
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.2520775486
Short name T1082
Test name
Test status
Simulation time 17874031559 ps
CPU time 29.95 seconds
Started Jun 29 04:51:58 PM PDT 24
Finished Jun 29 04:52:29 PM PDT 24
Peak memory 199920 kb
Host smart-6fef8ecc-dc33-40a5-ab02-6d46f5b2ce52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520775486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.2520775486
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.1988941479
Short name T794
Test name
Test status
Simulation time 111056194387 ps
CPU time 30.26 seconds
Started Jun 29 04:52:03 PM PDT 24
Finished Jun 29 04:52:34 PM PDT 24
Peak memory 199968 kb
Host smart-1f640f0c-923b-4592-93a0-3ca5aaf7c06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988941479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1988941479
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.1258896755
Short name T932
Test name
Test status
Simulation time 114577823054 ps
CPU time 97.89 seconds
Started Jun 29 04:51:57 PM PDT 24
Finished Jun 29 04:53:36 PM PDT 24
Peak memory 199988 kb
Host smart-914fb51e-a921-4040-bc0b-c3e62b01c9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258896755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1258896755
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.733263124
Short name T172
Test name
Test status
Simulation time 61727393648 ps
CPU time 24.91 seconds
Started Jun 29 04:52:03 PM PDT 24
Finished Jun 29 04:52:28 PM PDT 24
Peak memory 199928 kb
Host smart-129ae49b-6b0d-4f52-ba09-d39f2a19c0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733263124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.733263124
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3700465140
Short name T574
Test name
Test status
Simulation time 28735367943 ps
CPU time 42.87 seconds
Started Jun 29 04:51:58 PM PDT 24
Finished Jun 29 04:52:41 PM PDT 24
Peak memory 199904 kb
Host smart-83f577cd-6e2e-4b06-ba90-ea711f5b4f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700465140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3700465140
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.4114128931
Short name T717
Test name
Test status
Simulation time 25897334 ps
CPU time 0.54 seconds
Started Jun 29 04:47:55 PM PDT 24
Finished Jun 29 04:47:56 PM PDT 24
Peak memory 195424 kb
Host smart-8010af7f-7f76-4e23-a42a-e663298c8948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114128931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.4114128931
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.211396110
Short name T563
Test name
Test status
Simulation time 126879551644 ps
CPU time 49.28 seconds
Started Jun 29 04:47:54 PM PDT 24
Finished Jun 29 04:48:44 PM PDT 24
Peak memory 199940 kb
Host smart-e1a6db81-271d-4828-b06f-4b5dcb68d23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211396110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.211396110
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.1637747612
Short name T369
Test name
Test status
Simulation time 134457665282 ps
CPU time 64.43 seconds
Started Jun 29 04:48:03 PM PDT 24
Finished Jun 29 04:49:08 PM PDT 24
Peak memory 199984 kb
Host smart-de88d5fd-4c8d-41f5-a716-eb33c2c9e357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637747612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.1637747612
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.3008893670
Short name T332
Test name
Test status
Simulation time 169008095340 ps
CPU time 42 seconds
Started Jun 29 04:47:58 PM PDT 24
Finished Jun 29 04:48:41 PM PDT 24
Peak memory 199960 kb
Host smart-b21e8a1b-23eb-4f41-bd90-9da450509aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008893670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.3008893670
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.1930933024
Short name T15
Test name
Test status
Simulation time 7687861702 ps
CPU time 8.2 seconds
Started Jun 29 04:47:58 PM PDT 24
Finished Jun 29 04:48:07 PM PDT 24
Peak memory 199368 kb
Host smart-4c62dee1-f8f4-431b-9d5c-243fe4d3caa9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930933024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1930933024
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.3894062845
Short name T716
Test name
Test status
Simulation time 126708937231 ps
CPU time 415.58 seconds
Started Jun 29 04:47:53 PM PDT 24
Finished Jun 29 04:54:49 PM PDT 24
Peak memory 199888 kb
Host smart-6fc3bf21-6b82-467e-b3dd-06daa38a5708
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3894062845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3894062845
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.3491574998
Short name T757
Test name
Test status
Simulation time 6752373606 ps
CPU time 7.52 seconds
Started Jun 29 04:47:49 PM PDT 24
Finished Jun 29 04:47:56 PM PDT 24
Peak memory 198908 kb
Host smart-0ce8331c-b46d-4657-a960-6bccc013313b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491574998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3491574998
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.3083720130
Short name T277
Test name
Test status
Simulation time 25995159509 ps
CPU time 11.68 seconds
Started Jun 29 04:47:47 PM PDT 24
Finished Jun 29 04:48:00 PM PDT 24
Peak memory 199968 kb
Host smart-6d119c5d-2fe0-4893-a49d-10a25bac3f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083720130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.3083720130
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.3318209400
Short name T926
Test name
Test status
Simulation time 9869168537 ps
CPU time 422.16 seconds
Started Jun 29 04:47:52 PM PDT 24
Finished Jun 29 04:54:55 PM PDT 24
Peak memory 199880 kb
Host smart-c4fabefe-9c34-4c51-ae83-a7bf40bd718e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3318209400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3318209400
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.4039524062
Short name T822
Test name
Test status
Simulation time 5427068151 ps
CPU time 4.87 seconds
Started Jun 29 04:47:45 PM PDT 24
Finished Jun 29 04:47:51 PM PDT 24
Peak memory 198200 kb
Host smart-c904f3a4-6483-495e-8320-3592f04e0b30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4039524062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.4039524062
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.1223528260
Short name T40
Test name
Test status
Simulation time 67395794730 ps
CPU time 27.9 seconds
Started Jun 29 04:48:02 PM PDT 24
Finished Jun 29 04:48:31 PM PDT 24
Peak memory 199900 kb
Host smart-d79f5127-5a09-495b-84ff-5ec23cfaf5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223528260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1223528260
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.236220154
Short name T287
Test name
Test status
Simulation time 40579899398 ps
CPU time 59.36 seconds
Started Jun 29 04:48:02 PM PDT 24
Finished Jun 29 04:49:02 PM PDT 24
Peak memory 196708 kb
Host smart-9937e650-9c51-49a1-8ae8-a4a7b74d5f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236220154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.236220154
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.468895957
Short name T93
Test name
Test status
Simulation time 206857387 ps
CPU time 0.76 seconds
Started Jun 29 04:47:53 PM PDT 24
Finished Jun 29 04:47:54 PM PDT 24
Peak memory 218320 kb
Host smart-ed734eed-16c7-4fc5-8b32-dd47db0ffcb5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468895957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.468895957
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.2351882344
Short name T764
Test name
Test status
Simulation time 915712957 ps
CPU time 2.15 seconds
Started Jun 29 04:47:58 PM PDT 24
Finished Jun 29 04:48:01 PM PDT 24
Peak memory 198956 kb
Host smart-f6f4db42-f573-47be-8643-3753b2c69521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351882344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2351882344
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.1987622948
Short name T950
Test name
Test status
Simulation time 126206563965 ps
CPU time 537.34 seconds
Started Jun 29 04:48:04 PM PDT 24
Finished Jun 29 04:57:02 PM PDT 24
Peak memory 216340 kb
Host smart-27294dd8-54d1-47dc-a130-65d6f34bc423
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987622948 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.1987622948
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2359869678
Short name T832
Test name
Test status
Simulation time 6762169676 ps
CPU time 11.18 seconds
Started Jun 29 04:47:58 PM PDT 24
Finished Jun 29 04:48:10 PM PDT 24
Peak memory 199756 kb
Host smart-9bd4f4ea-dc0a-4a10-8813-580117a3816b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359869678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2359869678
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.734954000
Short name T422
Test name
Test status
Simulation time 29302517565 ps
CPU time 25.63 seconds
Started Jun 29 04:47:49 PM PDT 24
Finished Jun 29 04:48:15 PM PDT 24
Peak memory 199980 kb
Host smart-1370528e-375c-4edf-8cc7-d87d6edf1519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734954000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.734954000
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.3031968169
Short name T622
Test name
Test status
Simulation time 21781635 ps
CPU time 0.56 seconds
Started Jun 29 04:49:14 PM PDT 24
Finished Jun 29 04:49:15 PM PDT 24
Peak memory 195304 kb
Host smart-7b08e2cc-e153-4c40-a655-63bfe5dc5d30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031968169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3031968169
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3805381211
Short name T418
Test name
Test status
Simulation time 144502368808 ps
CPU time 43.64 seconds
Started Jun 29 04:49:14 PM PDT 24
Finished Jun 29 04:49:58 PM PDT 24
Peak memory 199988 kb
Host smart-29f6e9e9-dce4-4c71-91c1-22d2dce2e9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805381211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3805381211
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.2948547409
Short name T461
Test name
Test status
Simulation time 21770345274 ps
CPU time 34.08 seconds
Started Jun 29 04:49:13 PM PDT 24
Finished Jun 29 04:49:48 PM PDT 24
Peak memory 199924 kb
Host smart-cade3e4f-617b-43b7-ae73-ba109006c5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948547409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.2948547409
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3030568759
Short name T750
Test name
Test status
Simulation time 17296468924 ps
CPU time 24.3 seconds
Started Jun 29 04:49:12 PM PDT 24
Finished Jun 29 04:49:37 PM PDT 24
Peak memory 199944 kb
Host smart-b6029620-8395-4d71-bc56-1d54796a2d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030568759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3030568759
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.321911375
Short name T439
Test name
Test status
Simulation time 4464209494 ps
CPU time 1.89 seconds
Started Jun 29 04:49:13 PM PDT 24
Finished Jun 29 04:49:16 PM PDT 24
Peak memory 196708 kb
Host smart-c0f195fa-78fc-4418-907d-7db9e168e3aa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321911375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.321911375
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.2170854090
Short name T429
Test name
Test status
Simulation time 114237791995 ps
CPU time 642.07 seconds
Started Jun 29 04:49:12 PM PDT 24
Finished Jun 29 04:59:55 PM PDT 24
Peak memory 199972 kb
Host smart-f77bb329-cc83-4618-a507-9ee8f713d599
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2170854090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.2170854090
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.2343708451
Short name T987
Test name
Test status
Simulation time 2342322393 ps
CPU time 1.6 seconds
Started Jun 29 04:49:13 PM PDT 24
Finished Jun 29 04:49:15 PM PDT 24
Peak memory 197512 kb
Host smart-1dc13402-442f-42c0-9065-c0ce97c00203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343708451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.2343708451
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.2811836385
Short name T16
Test name
Test status
Simulation time 5452374172 ps
CPU time 9.96 seconds
Started Jun 29 04:49:12 PM PDT 24
Finished Jun 29 04:49:23 PM PDT 24
Peak memory 198332 kb
Host smart-b3fbd531-b003-4880-be4b-b71a4643d8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811836385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2811836385
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.1011720344
Short name T692
Test name
Test status
Simulation time 16922426750 ps
CPU time 982.2 seconds
Started Jun 29 04:49:14 PM PDT 24
Finished Jun 29 05:05:37 PM PDT 24
Peak memory 199880 kb
Host smart-0a56dee3-5afe-44cd-93ca-17e2eb14556f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1011720344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1011720344
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.4036328046
Short name T758
Test name
Test status
Simulation time 3499878337 ps
CPU time 30.48 seconds
Started Jun 29 04:49:12 PM PDT 24
Finished Jun 29 04:49:44 PM PDT 24
Peak memory 198036 kb
Host smart-5414c2b4-279e-4a89-923e-b0316e17db00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4036328046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.4036328046
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.2354383605
Short name T324
Test name
Test status
Simulation time 2939783306 ps
CPU time 2.53 seconds
Started Jun 29 04:49:14 PM PDT 24
Finished Jun 29 04:49:17 PM PDT 24
Peak memory 196316 kb
Host smart-da3d01f5-7454-471b-b85f-31ba111bc43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354383605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2354383605
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3527867980
Short name T1095
Test name
Test status
Simulation time 649453667 ps
CPU time 2.38 seconds
Started Jun 29 04:49:05 PM PDT 24
Finished Jun 29 04:49:08 PM PDT 24
Peak memory 198244 kb
Host smart-04d9d63e-95f9-4a82-9278-4ff54c1c2e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527867980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3527867980
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.1891405760
Short name T961
Test name
Test status
Simulation time 398924614423 ps
CPU time 1843.67 seconds
Started Jun 29 04:49:15 PM PDT 24
Finished Jun 29 05:19:59 PM PDT 24
Peak memory 199912 kb
Host smart-8cb6aec6-69bb-45c0-afe5-305f61e1ac28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891405760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1891405760
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.720656750
Short name T709
Test name
Test status
Simulation time 672186496 ps
CPU time 2.94 seconds
Started Jun 29 04:49:12 PM PDT 24
Finished Jun 29 04:49:16 PM PDT 24
Peak memory 199056 kb
Host smart-d166a233-e18a-4a1e-8fe0-fcfe2c6130ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720656750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.720656750
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.2638391710
Short name T913
Test name
Test status
Simulation time 40929875903 ps
CPU time 68.99 seconds
Started Jun 29 04:49:03 PM PDT 24
Finished Jun 29 04:50:12 PM PDT 24
Peak memory 199980 kb
Host smart-b6219ac1-cdb3-4b3f-9765-1561b6fdf81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638391710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2638391710
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.3046671081
Short name T411
Test name
Test status
Simulation time 13758446 ps
CPU time 0.55 seconds
Started Jun 29 04:49:19 PM PDT 24
Finished Jun 29 04:49:20 PM PDT 24
Peak memory 195304 kb
Host smart-56959226-5210-474d-a26e-cdf0f9f5f3bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046671081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3046671081
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.32455444
Short name T156
Test name
Test status
Simulation time 45132555011 ps
CPU time 36.56 seconds
Started Jun 29 04:49:13 PM PDT 24
Finished Jun 29 04:49:50 PM PDT 24
Peak memory 199996 kb
Host smart-d73995a7-cc64-4dac-86d2-51994bff3c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32455444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.32455444
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.2285047157
Short name T710
Test name
Test status
Simulation time 93378113949 ps
CPU time 66.51 seconds
Started Jun 29 04:49:11 PM PDT 24
Finished Jun 29 04:50:18 PM PDT 24
Peak memory 199664 kb
Host smart-b36b8ec3-67dd-4add-bcfd-67339a385164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285047157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.2285047157
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.1268056603
Short name T431
Test name
Test status
Simulation time 169515195660 ps
CPU time 83.44 seconds
Started Jun 29 04:49:13 PM PDT 24
Finished Jun 29 04:50:37 PM PDT 24
Peak memory 199952 kb
Host smart-301c4df6-9ddf-4e07-909b-909d884a34ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268056603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1268056603
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.1536827180
Short name T286
Test name
Test status
Simulation time 15643445594 ps
CPU time 25.44 seconds
Started Jun 29 04:49:13 PM PDT 24
Finished Jun 29 04:49:39 PM PDT 24
Peak memory 199916 kb
Host smart-aefce4f3-682e-46d3-b14b-06c8620255d2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536827180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.1536827180
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.1203321002
Short name T110
Test name
Test status
Simulation time 221212339721 ps
CPU time 267.68 seconds
Started Jun 29 04:49:15 PM PDT 24
Finished Jun 29 04:53:43 PM PDT 24
Peak memory 199912 kb
Host smart-287c513d-107a-4431-a4cc-c2eb4bb0d2a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1203321002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1203321002
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.3060715896
Short name T362
Test name
Test status
Simulation time 4708074262 ps
CPU time 5.32 seconds
Started Jun 29 04:49:14 PM PDT 24
Finished Jun 29 04:49:20 PM PDT 24
Peak memory 198720 kb
Host smart-43aa33bf-06c4-4976-ae45-fe8dc716c6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060715896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3060715896
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_perf.3830776493
Short name T1067
Test name
Test status
Simulation time 12096351183 ps
CPU time 318.41 seconds
Started Jun 29 04:49:14 PM PDT 24
Finished Jun 29 04:54:33 PM PDT 24
Peak memory 199980 kb
Host smart-6a198752-f0f5-4554-83b6-c77123f17eee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3830776493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3830776493
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.1225934674
Short name T385
Test name
Test status
Simulation time 5452520632 ps
CPU time 44.26 seconds
Started Jun 29 04:49:13 PM PDT 24
Finished Jun 29 04:49:58 PM PDT 24
Peak memory 198320 kb
Host smart-076c994a-7256-4cbf-8fd8-2509e6a8cd71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1225934674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1225934674
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1940663074
Short name T824
Test name
Test status
Simulation time 105084539962 ps
CPU time 41.15 seconds
Started Jun 29 04:49:12 PM PDT 24
Finished Jun 29 04:49:54 PM PDT 24
Peak memory 199840 kb
Host smart-540dcd6d-8bdf-4523-b17c-841374644a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940663074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1940663074
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.2152242699
Short name T1044
Test name
Test status
Simulation time 2687745067 ps
CPU time 1.76 seconds
Started Jun 29 04:49:13 PM PDT 24
Finished Jun 29 04:49:16 PM PDT 24
Peak memory 195876 kb
Host smart-54b0c2af-75b7-4613-b772-bbcdf66a42b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152242699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.2152242699
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.1625161873
Short name T1070
Test name
Test status
Simulation time 10570594715 ps
CPU time 30.7 seconds
Started Jun 29 04:49:10 PM PDT 24
Finished Jun 29 04:49:41 PM PDT 24
Peak memory 199444 kb
Host smart-53afaac8-366a-445e-89e6-93ee5a7dc805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625161873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1625161873
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1151700169
Short name T147
Test name
Test status
Simulation time 349578374907 ps
CPU time 211.88 seconds
Started Jun 29 04:49:23 PM PDT 24
Finished Jun 29 04:52:56 PM PDT 24
Peak memory 199944 kb
Host smart-6ec26cc0-47c3-43f4-8cc2-3dcd7a42e14f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151700169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1151700169
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.352502867
Short name T60
Test name
Test status
Simulation time 318042542602 ps
CPU time 1322.06 seconds
Started Jun 29 04:49:14 PM PDT 24
Finished Jun 29 05:11:17 PM PDT 24
Peak memory 224564 kb
Host smart-46f680ef-ad11-445a-b617-515206ddded0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352502867 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.352502867
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.439864605
Short name T278
Test name
Test status
Simulation time 6175715251 ps
CPU time 12.26 seconds
Started Jun 29 04:49:13 PM PDT 24
Finished Jun 29 04:49:27 PM PDT 24
Peak memory 199820 kb
Host smart-08628eeb-88a1-446e-b661-5330ffad53af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439864605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.439864605
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.3196908613
Short name T389
Test name
Test status
Simulation time 7480136045 ps
CPU time 3.46 seconds
Started Jun 29 04:49:13 PM PDT 24
Finished Jun 29 04:49:17 PM PDT 24
Peak memory 198028 kb
Host smart-01469888-3db2-4998-83b7-af6f52ec0718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196908613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3196908613
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1795780263
Short name T657
Test name
Test status
Simulation time 34671745 ps
CPU time 0.57 seconds
Started Jun 29 04:49:21 PM PDT 24
Finished Jun 29 04:49:22 PM PDT 24
Peak memory 195304 kb
Host smart-65723612-08db-4a0b-8301-e1447a268edf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795780263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1795780263
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.3733899075
Short name T666
Test name
Test status
Simulation time 144026580893 ps
CPU time 36.22 seconds
Started Jun 29 04:49:21 PM PDT 24
Finished Jun 29 04:49:59 PM PDT 24
Peak memory 199992 kb
Host smart-0891fdd5-d9b3-4da5-b1d0-3f4ccb35acb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733899075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3733899075
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2013149350
Short name T767
Test name
Test status
Simulation time 34150494440 ps
CPU time 46.86 seconds
Started Jun 29 04:49:20 PM PDT 24
Finished Jun 29 04:50:07 PM PDT 24
Peak memory 199864 kb
Host smart-0941dadb-0e8f-4840-ae02-7dac9c4529cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013149350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2013149350
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.3203159192
Short name T914
Test name
Test status
Simulation time 32220497828 ps
CPU time 48.42 seconds
Started Jun 29 04:49:19 PM PDT 24
Finished Jun 29 04:50:07 PM PDT 24
Peak memory 199868 kb
Host smart-91d4d324-b447-4c8a-b006-272b47b1f256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203159192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3203159192
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.3874666373
Short name T1085
Test name
Test status
Simulation time 13531601314 ps
CPU time 2.45 seconds
Started Jun 29 04:49:24 PM PDT 24
Finished Jun 29 04:49:28 PM PDT 24
Peak memory 196248 kb
Host smart-9a9fef64-dc81-415d-b2f7-94a8753b704a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874666373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3874666373
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.4106770565
Short name T531
Test name
Test status
Simulation time 122690747587 ps
CPU time 304.58 seconds
Started Jun 29 04:49:24 PM PDT 24
Finished Jun 29 04:54:30 PM PDT 24
Peak memory 199880 kb
Host smart-4c717f56-fb6e-4ddb-9ad3-7ffba167bd16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4106770565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.4106770565
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.4114215027
Short name T437
Test name
Test status
Simulation time 4940050859 ps
CPU time 9.21 seconds
Started Jun 29 04:49:20 PM PDT 24
Finished Jun 29 04:49:29 PM PDT 24
Peak memory 198904 kb
Host smart-0b29e9d6-0e2f-4d86-adbf-6e157d0f2652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114215027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.4114215027
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_perf.1372317137
Short name T638
Test name
Test status
Simulation time 21097583436 ps
CPU time 1225.53 seconds
Started Jun 29 04:49:23 PM PDT 24
Finished Jun 29 05:09:50 PM PDT 24
Peak memory 199832 kb
Host smart-3eec71d2-c2d6-4832-9c14-1808adc8ee0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1372317137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1372317137
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.1351625654
Short name T834
Test name
Test status
Simulation time 6337701693 ps
CPU time 52.79 seconds
Started Jun 29 04:49:21 PM PDT 24
Finished Jun 29 04:50:15 PM PDT 24
Peak memory 198208 kb
Host smart-35d6b21b-96de-4ffc-8d02-3bf97341aa76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1351625654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.1351625654
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.1563435467
Short name T516
Test name
Test status
Simulation time 294313512729 ps
CPU time 167.52 seconds
Started Jun 29 04:49:23 PM PDT 24
Finished Jun 29 04:52:11 PM PDT 24
Peak memory 199820 kb
Host smart-5926ea7e-fa3a-46e3-86cb-3fb05dfe4343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563435467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.1563435467
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.2702884432
Short name T683
Test name
Test status
Simulation time 49252780838 ps
CPU time 32.66 seconds
Started Jun 29 04:49:24 PM PDT 24
Finished Jun 29 04:49:59 PM PDT 24
Peak memory 195724 kb
Host smart-9efe639c-5b9f-41f7-a66c-be7cd9fa8956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702884432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2702884432
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.747475921
Short name T582
Test name
Test status
Simulation time 762054469 ps
CPU time 1.38 seconds
Started Jun 29 04:49:23 PM PDT 24
Finished Jun 29 04:49:25 PM PDT 24
Peak memory 199860 kb
Host smart-67fa78ee-8b9a-446b-9cc3-660dd67f1373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747475921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.747475921
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3768640608
Short name T1
Test name
Test status
Simulation time 7045932561 ps
CPU time 21.4 seconds
Started Jun 29 04:49:19 PM PDT 24
Finished Jun 29 04:49:41 PM PDT 24
Peak memory 199916 kb
Host smart-ae044d86-c7d4-4bde-aa6d-d3001d8ff728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768640608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3768640608
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.2112518302
Short name T739
Test name
Test status
Simulation time 95591831868 ps
CPU time 49.5 seconds
Started Jun 29 04:49:22 PM PDT 24
Finished Jun 29 04:50:12 PM PDT 24
Peak memory 199936 kb
Host smart-b1b7874a-ff5a-40e9-b12d-e9ae521c8a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112518302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2112518302
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.2576671638
Short name T412
Test name
Test status
Simulation time 14508534 ps
CPU time 0.56 seconds
Started Jun 29 04:49:24 PM PDT 24
Finished Jun 29 04:49:26 PM PDT 24
Peak memory 195308 kb
Host smart-68484fd8-c6d0-416d-9245-fd5153d08558
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576671638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2576671638
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.1869257775
Short name T648
Test name
Test status
Simulation time 148113708857 ps
CPU time 110.72 seconds
Started Jun 29 04:49:23 PM PDT 24
Finished Jun 29 04:51:16 PM PDT 24
Peak memory 199932 kb
Host smart-c85fc138-5730-441f-8a01-e8f6fa4ce039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869257775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1869257775
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.927374474
Short name T959
Test name
Test status
Simulation time 154211873872 ps
CPU time 237.33 seconds
Started Jun 29 04:49:24 PM PDT 24
Finished Jun 29 04:53:22 PM PDT 24
Peak memory 199840 kb
Host smart-d2edc4d3-aaef-490b-a3b7-c83125024110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927374474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.927374474
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.1213499623
Short name T159
Test name
Test status
Simulation time 31181419260 ps
CPU time 13.23 seconds
Started Jun 29 04:49:24 PM PDT 24
Finished Jun 29 04:49:39 PM PDT 24
Peak memory 199928 kb
Host smart-9d56be8e-b35d-422f-a220-434caeb1bcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213499623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.1213499623
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.3938637979
Short name T659
Test name
Test status
Simulation time 25016891392 ps
CPU time 43.89 seconds
Started Jun 29 04:49:23 PM PDT 24
Finished Jun 29 04:50:08 PM PDT 24
Peak memory 199908 kb
Host smart-6f627819-febc-4c72-a61b-f133d9adaf6b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938637979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3938637979
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.4098379860
Short name T513
Test name
Test status
Simulation time 136879205117 ps
CPU time 1086.76 seconds
Started Jun 29 04:49:24 PM PDT 24
Finished Jun 29 05:07:33 PM PDT 24
Peak memory 199852 kb
Host smart-42695e8b-a6e7-4c63-8f3d-0f510d529707
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4098379860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.4098379860
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.565588935
Short name T669
Test name
Test status
Simulation time 3822465391 ps
CPU time 2.32 seconds
Started Jun 29 04:49:21 PM PDT 24
Finished Jun 29 04:49:24 PM PDT 24
Peak memory 198540 kb
Host smart-3dff9a21-7922-45b7-97aa-288c9a9367b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565588935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.565588935
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_perf.3705940431
Short name T499
Test name
Test status
Simulation time 27539961440 ps
CPU time 793.27 seconds
Started Jun 29 04:49:20 PM PDT 24
Finished Jun 29 05:02:34 PM PDT 24
Peak memory 199980 kb
Host smart-f9c5e753-510e-4ffb-b361-1238ebaa1c35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3705940431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3705940431
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.2530959934
Short name T1015
Test name
Test status
Simulation time 5278908282 ps
CPU time 46.55 seconds
Started Jun 29 04:49:21 PM PDT 24
Finished Jun 29 04:50:08 PM PDT 24
Peak memory 198100 kb
Host smart-0903e165-7605-44d5-8125-b9184fc49c95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2530959934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2530959934
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.3695567969
Short name T454
Test name
Test status
Simulation time 17230353474 ps
CPU time 26.74 seconds
Started Jun 29 04:49:20 PM PDT 24
Finished Jun 29 04:49:47 PM PDT 24
Peak memory 199916 kb
Host smart-c7b3dd84-26e7-4361-86f2-e582a44210ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695567969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3695567969
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1261015096
Short name T650
Test name
Test status
Simulation time 4044927257 ps
CPU time 2.23 seconds
Started Jun 29 04:49:22 PM PDT 24
Finished Jun 29 04:49:25 PM PDT 24
Peak memory 196416 kb
Host smart-129e4809-282b-42d8-9875-dacbd347083c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261015096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1261015096
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3975245417
Short name T728
Test name
Test status
Simulation time 932568124 ps
CPU time 3.82 seconds
Started Jun 29 04:49:24 PM PDT 24
Finished Jun 29 04:49:29 PM PDT 24
Peak memory 199824 kb
Host smart-dd467ee1-49ff-4135-a508-238bcdb867a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975245417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3975245417
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.408296991
Short name T298
Test name
Test status
Simulation time 294297848707 ps
CPU time 535.75 seconds
Started Jun 29 04:49:23 PM PDT 24
Finished Jun 29 04:58:20 PM PDT 24
Peak memory 199900 kb
Host smart-6dd65da7-d4d4-4b89-a570-b1d04473eeeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408296991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.408296991
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.334797233
Short name T334
Test name
Test status
Simulation time 296427687985 ps
CPU time 1118.02 seconds
Started Jun 29 04:49:21 PM PDT 24
Finished Jun 29 05:07:59 PM PDT 24
Peak memory 232432 kb
Host smart-154ef0b4-c365-46f4-a566-4b96615a7108
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334797233 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.334797233
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.680600019
Short name T663
Test name
Test status
Simulation time 1105229343 ps
CPU time 3.31 seconds
Started Jun 29 04:49:24 PM PDT 24
Finished Jun 29 04:49:29 PM PDT 24
Peak memory 198428 kb
Host smart-8b37d104-ed5c-4bc1-8697-5dee67c502db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680600019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.680600019
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.741343540
Short name T846
Test name
Test status
Simulation time 211614868948 ps
CPU time 41.54 seconds
Started Jun 29 04:49:20 PM PDT 24
Finished Jun 29 04:50:02 PM PDT 24
Peak memory 199920 kb
Host smart-2e483793-a607-4c47-bea1-ab89e1ea8c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741343540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.741343540
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1323303280
Short name T723
Test name
Test status
Simulation time 21810136 ps
CPU time 0.56 seconds
Started Jun 29 04:49:29 PM PDT 24
Finished Jun 29 04:49:31 PM PDT 24
Peak memory 194280 kb
Host smart-f6af30ce-de3d-4414-9a7f-dc4b073a135c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323303280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1323303280
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.898134540
Short name T930
Test name
Test status
Simulation time 47528493006 ps
CPU time 42.07 seconds
Started Jun 29 04:49:23 PM PDT 24
Finished Jun 29 04:50:06 PM PDT 24
Peak memory 199992 kb
Host smart-a407eb3e-41f0-42ac-94b3-005638a7419e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898134540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.898134540
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.511780580
Short name T572
Test name
Test status
Simulation time 116253315182 ps
CPU time 103.56 seconds
Started Jun 29 04:49:24 PM PDT 24
Finished Jun 29 04:51:09 PM PDT 24
Peak memory 199808 kb
Host smart-dcc60650-7092-4775-b092-cb07f4b3ca08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511780580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.511780580
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.1188118685
Short name T892
Test name
Test status
Simulation time 18780700415 ps
CPU time 18.73 seconds
Started Jun 29 04:49:23 PM PDT 24
Finished Jun 29 04:49:43 PM PDT 24
Peak memory 199832 kb
Host smart-240f8c30-d87a-4b52-949a-86a6e0b8ecc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188118685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.1188118685
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3332338640
Short name T952
Test name
Test status
Simulation time 43468669555 ps
CPU time 35.15 seconds
Started Jun 29 04:49:19 PM PDT 24
Finished Jun 29 04:49:54 PM PDT 24
Peak memory 199976 kb
Host smart-8446759b-a29d-4ad8-8b32-7eb9923f00a2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332338640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3332338640
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.821409404
Short name T1062
Test name
Test status
Simulation time 80411744388 ps
CPU time 620.35 seconds
Started Jun 29 04:49:30 PM PDT 24
Finished Jun 29 04:59:52 PM PDT 24
Peak memory 199912 kb
Host smart-92c2da69-a15b-4bf5-b2fe-c055120f8eaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=821409404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.821409404
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3650086807
Short name T780
Test name
Test status
Simulation time 5747270918 ps
CPU time 4.25 seconds
Started Jun 29 04:49:25 PM PDT 24
Finished Jun 29 04:49:30 PM PDT 24
Peak memory 199692 kb
Host smart-16576e8f-b055-4824-b343-187a8662d30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650086807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3650086807
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_perf.4164777561
Short name T751
Test name
Test status
Simulation time 12965423256 ps
CPU time 38.22 seconds
Started Jun 29 04:49:20 PM PDT 24
Finished Jun 29 04:49:59 PM PDT 24
Peak memory 199980 kb
Host smart-2505b4e4-3089-46b8-94df-ed7aaa10c1ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4164777561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.4164777561
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.411452111
Short name T772
Test name
Test status
Simulation time 4357392867 ps
CPU time 17.88 seconds
Started Jun 29 04:49:24 PM PDT 24
Finished Jun 29 04:49:43 PM PDT 24
Peak memory 199140 kb
Host smart-b7f1d19e-4dea-47c7-b216-c9921c73e439
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=411452111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.411452111
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.901514057
Short name T801
Test name
Test status
Simulation time 77380493189 ps
CPU time 54.41 seconds
Started Jun 29 04:49:23 PM PDT 24
Finished Jun 29 04:50:18 PM PDT 24
Peak memory 199964 kb
Host smart-4afd82a8-3f45-4e88-9121-fe4c3c81ed85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901514057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.901514057
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.790261578
Short name T383
Test name
Test status
Simulation time 6744601491 ps
CPU time 3.52 seconds
Started Jun 29 04:49:21 PM PDT 24
Finished Jun 29 04:49:25 PM PDT 24
Peak memory 196420 kb
Host smart-6305e79e-5887-4d2d-96fe-a63ccacf1793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790261578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.790261578
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.1396334584
Short name T526
Test name
Test status
Simulation time 734063266 ps
CPU time 1.92 seconds
Started Jun 29 04:49:23 PM PDT 24
Finished Jun 29 04:49:27 PM PDT 24
Peak memory 199692 kb
Host smart-fb433a6a-8aa1-49a7-9ec8-2f930ce323a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396334584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.1396334584
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.3186676970
Short name T796
Test name
Test status
Simulation time 187703233467 ps
CPU time 39.77 seconds
Started Jun 29 04:49:30 PM PDT 24
Finished Jun 29 04:50:11 PM PDT 24
Peak memory 199916 kb
Host smart-0432028e-12ed-440f-995b-b6b4667dc4c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186676970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.3186676970
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.766069294
Short name T997
Test name
Test status
Simulation time 26493677521 ps
CPU time 555.49 seconds
Started Jun 29 04:49:28 PM PDT 24
Finished Jun 29 04:58:45 PM PDT 24
Peak memory 216416 kb
Host smart-6ef24b61-c7fd-440f-b802-db9a97f7bf97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766069294 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.766069294
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.2277285719
Short name T672
Test name
Test status
Simulation time 219520848 ps
CPU time 1.28 seconds
Started Jun 29 04:49:24 PM PDT 24
Finished Jun 29 04:49:26 PM PDT 24
Peak memory 198344 kb
Host smart-f26c0e36-9cd7-409f-9ccd-66cbb76bf059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277285719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.2277285719
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.4164549552
Short name T651
Test name
Test status
Simulation time 28887777582 ps
CPU time 44.3 seconds
Started Jun 29 04:49:22 PM PDT 24
Finished Jun 29 04:50:07 PM PDT 24
Peak memory 199916 kb
Host smart-94e944ee-af13-4300-80c9-6d37df5dcf7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164549552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.4164549552
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.3200936704
Short name T402
Test name
Test status
Simulation time 26600638 ps
CPU time 0.56 seconds
Started Jun 29 04:49:27 PM PDT 24
Finished Jun 29 04:49:29 PM PDT 24
Peak memory 195304 kb
Host smart-68fc0a98-cdee-48c4-809d-2cf56d46b6d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200936704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3200936704
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.2151733954
Short name T181
Test name
Test status
Simulation time 28810101915 ps
CPU time 26.76 seconds
Started Jun 29 04:49:27 PM PDT 24
Finished Jun 29 04:49:55 PM PDT 24
Peak memory 199960 kb
Host smart-cbff957e-6e01-44fc-a1e6-413ed29713d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151733954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2151733954
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.3180793068
Short name T514
Test name
Test status
Simulation time 273183817226 ps
CPU time 107.13 seconds
Started Jun 29 04:49:29 PM PDT 24
Finished Jun 29 04:51:17 PM PDT 24
Peak memory 199988 kb
Host smart-21c116f2-08cc-4039-a993-10c70b82b110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180793068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.3180793068
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.172673309
Short name T689
Test name
Test status
Simulation time 117745715767 ps
CPU time 46.46 seconds
Started Jun 29 04:49:29 PM PDT 24
Finished Jun 29 04:50:16 PM PDT 24
Peak memory 196564 kb
Host smart-34b59611-1a2d-4b1c-8c1e-a94547778136
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172673309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.172673309
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3837325670
Short name T390
Test name
Test status
Simulation time 247115108986 ps
CPU time 194.95 seconds
Started Jun 29 04:49:29 PM PDT 24
Finished Jun 29 04:52:45 PM PDT 24
Peak memory 199852 kb
Host smart-f0d02f49-bb9b-484b-9f04-cbe88d37b681
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3837325670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3837325670
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3165098350
Short name T866
Test name
Test status
Simulation time 6575613450 ps
CPU time 5.44 seconds
Started Jun 29 04:49:30 PM PDT 24
Finished Jun 29 04:49:37 PM PDT 24
Peak memory 199992 kb
Host smart-d1cbaa67-8e71-485d-bd48-a2003de1c805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165098350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3165098350
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_perf.694344555
Short name T619
Test name
Test status
Simulation time 10251102972 ps
CPU time 157.5 seconds
Started Jun 29 04:49:28 PM PDT 24
Finished Jun 29 04:52:07 PM PDT 24
Peak memory 199956 kb
Host smart-30805bcf-dd61-4c49-a2fa-0b09797fed7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=694344555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.694344555
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.377906290
Short name T719
Test name
Test status
Simulation time 3664367140 ps
CPU time 29.67 seconds
Started Jun 29 04:49:29 PM PDT 24
Finished Jun 29 04:50:00 PM PDT 24
Peak memory 199252 kb
Host smart-768ddea0-fb83-41f9-8b77-3dd382fd3446
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=377906290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.377906290
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.1192123270
Short name T501
Test name
Test status
Simulation time 195899923654 ps
CPU time 294.56 seconds
Started Jun 29 04:49:30 PM PDT 24
Finished Jun 29 04:54:26 PM PDT 24
Peak memory 199984 kb
Host smart-d1387008-11af-48de-8779-80f97a2d85bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192123270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1192123270
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.2083244754
Short name T21
Test name
Test status
Simulation time 3496439773 ps
CPU time 3.36 seconds
Started Jun 29 04:49:27 PM PDT 24
Finished Jun 29 04:49:32 PM PDT 24
Peak memory 196004 kb
Host smart-41734a7c-fd32-419e-addf-8ceebe3d710e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083244754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2083244754
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.3829570599
Short name T382
Test name
Test status
Simulation time 272593524 ps
CPU time 1.2 seconds
Started Jun 29 04:49:27 PM PDT 24
Finished Jun 29 04:49:29 PM PDT 24
Peak memory 199272 kb
Host smart-5f10952f-8ce0-475c-b32f-cf47f87c7022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829570599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3829570599
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.518479153
Short name T611
Test name
Test status
Simulation time 80787126620 ps
CPU time 355.21 seconds
Started Jun 29 04:49:27 PM PDT 24
Finished Jun 29 04:55:23 PM PDT 24
Peak memory 200020 kb
Host smart-b59bce1c-e6d9-4e3e-9b64-c1e800d6c32d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518479153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.518479153
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.3281436121
Short name T1037
Test name
Test status
Simulation time 1738140535 ps
CPU time 2.8 seconds
Started Jun 29 04:49:33 PM PDT 24
Finished Jun 29 04:49:36 PM PDT 24
Peak memory 199676 kb
Host smart-184f28ca-10b5-4c61-9a43-a4ece95f4188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281436121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3281436121
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.3562810538
Short name T823
Test name
Test status
Simulation time 64575657212 ps
CPU time 29.93 seconds
Started Jun 29 04:49:30 PM PDT 24
Finished Jun 29 04:50:01 PM PDT 24
Peak memory 199956 kb
Host smart-161d9834-4d04-423a-9986-1946cf38b495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562810538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3562810538
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.686004611
Short name T916
Test name
Test status
Simulation time 25826911 ps
CPU time 0.57 seconds
Started Jun 29 04:49:36 PM PDT 24
Finished Jun 29 04:49:37 PM PDT 24
Peak memory 195300 kb
Host smart-caf81a3a-5c7d-4dae-bc25-ab95d7df6979
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686004611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.686004611
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.1090422443
Short name T903
Test name
Test status
Simulation time 2791978227 ps
CPU time 6.14 seconds
Started Jun 29 04:49:30 PM PDT 24
Finished Jun 29 04:49:37 PM PDT 24
Peak memory 200196 kb
Host smart-873b2f14-64cd-4d88-8258-766943beffe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090422443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.1090422443
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.788510132
Short name T693
Test name
Test status
Simulation time 153361152799 ps
CPU time 26.58 seconds
Started Jun 29 04:49:30 PM PDT 24
Finished Jun 29 04:49:57 PM PDT 24
Peak memory 199988 kb
Host smart-3d1f1ab2-0f64-4756-b14a-0b92ffc28ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788510132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.788510132
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.3474936102
Short name T367
Test name
Test status
Simulation time 26677268506 ps
CPU time 15.3 seconds
Started Jun 29 04:49:30 PM PDT 24
Finished Jun 29 04:49:46 PM PDT 24
Peak memory 199980 kb
Host smart-9d941887-95db-4000-b3f9-c25065f570e2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474936102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3474936102
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.534931931
Short name T753
Test name
Test status
Simulation time 120313093614 ps
CPU time 391.23 seconds
Started Jun 29 04:49:36 PM PDT 24
Finished Jun 29 04:56:08 PM PDT 24
Peak memory 199936 kb
Host smart-1bf83519-a277-4248-b81c-1e326309bb19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=534931931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.534931931
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.2120615062
Short name T521
Test name
Test status
Simulation time 7501244983 ps
CPU time 12.8 seconds
Started Jun 29 04:49:38 PM PDT 24
Finished Jun 29 04:49:51 PM PDT 24
Peak memory 199700 kb
Host smart-3adf6322-5d34-4179-a169-ed1872ab963b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120615062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2120615062
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_perf.1510874855
Short name T288
Test name
Test status
Simulation time 24014312567 ps
CPU time 1197.07 seconds
Started Jun 29 04:49:36 PM PDT 24
Finished Jun 29 05:09:34 PM PDT 24
Peak memory 199980 kb
Host smart-c8268b7a-6b0f-4f83-8cae-7b10dd2917d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1510874855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1510874855
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3100463024
Short name T391
Test name
Test status
Simulation time 2969623283 ps
CPU time 4.21 seconds
Started Jun 29 04:49:29 PM PDT 24
Finished Jun 29 04:49:34 PM PDT 24
Peak memory 198048 kb
Host smart-ac1cf7c6-d13b-4823-b2eb-2c3ee070a8e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3100463024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3100463024
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.4140190372
Short name T57
Test name
Test status
Simulation time 41792533963 ps
CPU time 33.84 seconds
Started Jun 29 04:49:35 PM PDT 24
Finished Jun 29 04:50:09 PM PDT 24
Peak memory 199636 kb
Host smart-6037ccb9-6304-4925-b27a-3e7da8373f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140190372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.4140190372
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.1106297652
Short name T637
Test name
Test status
Simulation time 673759666 ps
CPU time 1.53 seconds
Started Jun 29 04:49:39 PM PDT 24
Finished Jun 29 04:49:41 PM PDT 24
Peak memory 195384 kb
Host smart-7aec64c5-18e3-49fc-abd9-26893c72e35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106297652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1106297652
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.970076681
Short name T876
Test name
Test status
Simulation time 482113860 ps
CPU time 2.43 seconds
Started Jun 29 04:49:28 PM PDT 24
Finished Jun 29 04:49:32 PM PDT 24
Peak memory 198620 kb
Host smart-539d022e-3de3-493c-b5e7-2063d8e6cc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970076681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.970076681
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1291367646
Short name T862
Test name
Test status
Simulation time 41304848205 ps
CPU time 263.87 seconds
Started Jun 29 04:49:36 PM PDT 24
Finished Jun 29 04:54:00 PM PDT 24
Peak memory 216524 kb
Host smart-1190b177-f8fa-497f-819d-51071e3fa3bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291367646 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1291367646
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.2630771981
Short name T856
Test name
Test status
Simulation time 1515032790 ps
CPU time 1.54 seconds
Started Jun 29 04:49:37 PM PDT 24
Finished Jun 29 04:49:39 PM PDT 24
Peak memory 198704 kb
Host smart-849fa18f-e210-4d0d-9a42-b969e3157cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630771981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2630771981
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1374420529
Short name T565
Test name
Test status
Simulation time 13178975944 ps
CPU time 4.87 seconds
Started Jun 29 04:49:27 PM PDT 24
Finished Jun 29 04:49:33 PM PDT 24
Peak memory 197084 kb
Host smart-02cdc32b-8e9b-4edb-be39-0c6c2c937f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374420529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1374420529
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.2753597540
Short name T675
Test name
Test status
Simulation time 45062224 ps
CPU time 0.54 seconds
Started Jun 29 04:49:36 PM PDT 24
Finished Jun 29 04:49:37 PM PDT 24
Peak memory 195304 kb
Host smart-d5cf293c-2aee-4112-9d2d-b783f249fe70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753597540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.2753597540
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.3725997690
Short name T175
Test name
Test status
Simulation time 137064874443 ps
CPU time 25.16 seconds
Started Jun 29 04:49:44 PM PDT 24
Finished Jun 29 04:50:10 PM PDT 24
Peak memory 199880 kb
Host smart-e8e502fd-a8b7-401c-b452-64efeb0b566e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725997690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3725997690
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.3426229334
Short name T643
Test name
Test status
Simulation time 90779940220 ps
CPU time 9.33 seconds
Started Jun 29 04:49:35 PM PDT 24
Finished Jun 29 04:49:45 PM PDT 24
Peak memory 199868 kb
Host smart-48047d3d-e546-4e87-a5be-fd68098ca5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426229334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3426229334
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_intr.483994043
Short name T120
Test name
Test status
Simulation time 66384730116 ps
CPU time 35.38 seconds
Started Jun 29 04:49:35 PM PDT 24
Finished Jun 29 04:50:11 PM PDT 24
Peak memory 199892 kb
Host smart-91c50be4-deaf-491e-b6d4-bf1632ef3926
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483994043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.483994043
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.4173087378
Short name T310
Test name
Test status
Simulation time 98456913753 ps
CPU time 408.07 seconds
Started Jun 29 04:49:40 PM PDT 24
Finished Jun 29 04:56:29 PM PDT 24
Peak memory 198960 kb
Host smart-79c9307a-1e5c-49d3-9631-34d57764d496
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4173087378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.4173087378
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2922116010
Short name T470
Test name
Test status
Simulation time 228039028 ps
CPU time 0.89 seconds
Started Jun 29 04:49:44 PM PDT 24
Finished Jun 29 04:49:46 PM PDT 24
Peak memory 198056 kb
Host smart-95020dd2-5a9e-4def-aa87-8d887a63065f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922116010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2922116010
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_perf.1693765868
Short name T434
Test name
Test status
Simulation time 20195841217 ps
CPU time 217.25 seconds
Started Jun 29 04:49:40 PM PDT 24
Finished Jun 29 04:53:17 PM PDT 24
Peak memory 199980 kb
Host smart-5833f08b-7f76-43ac-b8a4-9c863935115b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1693765868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1693765868
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.3122170278
Short name T731
Test name
Test status
Simulation time 4956029251 ps
CPU time 43.93 seconds
Started Jun 29 04:49:35 PM PDT 24
Finished Jun 29 04:50:19 PM PDT 24
Peak memory 199260 kb
Host smart-acc6d0f8-9a1d-4cc1-abe5-7b15359c33bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3122170278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3122170278
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.4063218716
Short name T293
Test name
Test status
Simulation time 62691366408 ps
CPU time 15.05 seconds
Started Jun 29 04:49:36 PM PDT 24
Finished Jun 29 04:49:52 PM PDT 24
Peak memory 199584 kb
Host smart-80cb63c2-6737-4546-889c-2821b2ed311a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063218716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.4063218716
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3902260397
Short name T358
Test name
Test status
Simulation time 3090724228 ps
CPU time 5.08 seconds
Started Jun 29 04:49:44 PM PDT 24
Finished Jun 29 04:49:50 PM PDT 24
Peak memory 196104 kb
Host smart-d79d8730-d02a-4d3a-a993-577e8ff6ee03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902260397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3902260397
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3529982110
Short name T300
Test name
Test status
Simulation time 509495088 ps
CPU time 1.27 seconds
Started Jun 29 04:49:34 PM PDT 24
Finished Jun 29 04:49:36 PM PDT 24
Peak memory 199664 kb
Host smart-3266c5e7-db4d-4ca3-9ebc-85f28c12d458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529982110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3529982110
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.2820581410
Short name T1034
Test name
Test status
Simulation time 7468013555 ps
CPU time 11.62 seconds
Started Jun 29 04:49:40 PM PDT 24
Finished Jun 29 04:49:52 PM PDT 24
Peak memory 199892 kb
Host smart-5bbdfbc9-80eb-4fb2-87eb-f38a6741251e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820581410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.2820581410
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.4083046342
Short name T329
Test name
Test status
Simulation time 94123311129 ps
CPU time 187.92 seconds
Started Jun 29 04:49:35 PM PDT 24
Finished Jun 29 04:52:43 PM PDT 24
Peak memory 199928 kb
Host smart-8d61d542-2995-45f2-95cb-9f322a50e34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083046342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.4083046342
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.1353100891
Short name T355
Test name
Test status
Simulation time 13185852 ps
CPU time 0.56 seconds
Started Jun 29 04:49:46 PM PDT 24
Finished Jun 29 04:49:47 PM PDT 24
Peak memory 195252 kb
Host smart-b3903a0b-5429-44ad-90a2-ff208a0970e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353100891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1353100891
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.471951763
Short name T654
Test name
Test status
Simulation time 55211946860 ps
CPU time 35.39 seconds
Started Jun 29 04:49:43 PM PDT 24
Finished Jun 29 04:50:19 PM PDT 24
Peak memory 199848 kb
Host smart-7aea3b0f-8ffa-49c3-9e03-142166f283db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471951763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.471951763
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.2176091277
Short name T887
Test name
Test status
Simulation time 90838267406 ps
CPU time 204.21 seconds
Started Jun 29 04:49:40 PM PDT 24
Finished Jun 29 04:53:05 PM PDT 24
Peak memory 199900 kb
Host smart-49c146cb-41e2-4324-84c6-1e5be6e6b77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176091277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2176091277
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.1917469058
Short name T879
Test name
Test status
Simulation time 65560651236 ps
CPU time 114.35 seconds
Started Jun 29 04:49:41 PM PDT 24
Finished Jun 29 04:51:36 PM PDT 24
Peak memory 199900 kb
Host smart-1fc0d4b4-805b-4583-9c74-21237e773ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917469058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1917469058
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.2992537629
Short name T1058
Test name
Test status
Simulation time 7889673186 ps
CPU time 4.59 seconds
Started Jun 29 04:49:35 PM PDT 24
Finished Jun 29 04:49:40 PM PDT 24
Peak memory 198764 kb
Host smart-6c721c98-8a3d-48fc-8670-50fad5d16f5c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992537629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2992537629
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.1279232659
Short name T678
Test name
Test status
Simulation time 40727688082 ps
CPU time 34.71 seconds
Started Jun 29 04:49:44 PM PDT 24
Finished Jun 29 04:50:19 PM PDT 24
Peak memory 199996 kb
Host smart-c41dba4b-5651-468a-b3f9-9d1264f9d889
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1279232659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1279232659
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1609538032
Short name T353
Test name
Test status
Simulation time 3074715276 ps
CPU time 6.02 seconds
Started Jun 29 04:49:43 PM PDT 24
Finished Jun 29 04:49:50 PM PDT 24
Peak memory 197560 kb
Host smart-2d83e6f8-213d-494a-abea-c9a9fc77f522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609538032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1609538032
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_perf.1511441687
Short name T455
Test name
Test status
Simulation time 24908113406 ps
CPU time 154.56 seconds
Started Jun 29 04:49:42 PM PDT 24
Finished Jun 29 04:52:17 PM PDT 24
Peak memory 199980 kb
Host smart-ed06fea2-1f36-46e5-8228-6a309d89d5df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1511441687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1511441687
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.2672498012
Short name T703
Test name
Test status
Simulation time 3786530917 ps
CPU time 7.76 seconds
Started Jun 29 04:49:44 PM PDT 24
Finished Jun 29 04:49:53 PM PDT 24
Peak memory 198780 kb
Host smart-209548c4-5ce6-462c-a4e1-0f293d89914d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2672498012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2672498012
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.735791298
Short name T540
Test name
Test status
Simulation time 83898660657 ps
CPU time 37.04 seconds
Started Jun 29 04:49:44 PM PDT 24
Finished Jun 29 04:50:22 PM PDT 24
Peak memory 200200 kb
Host smart-e5c67b6a-30a5-4116-96b3-74c3dd2a9268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735791298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.735791298
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.3843278693
Short name T631
Test name
Test status
Simulation time 4937401594 ps
CPU time 8.16 seconds
Started Jun 29 04:49:43 PM PDT 24
Finished Jun 29 04:49:52 PM PDT 24
Peak memory 196224 kb
Host smart-118c2eff-eb37-4531-a55c-d54790578630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843278693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3843278693
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.50701969
Short name T787
Test name
Test status
Simulation time 5743666375 ps
CPU time 5.66 seconds
Started Jun 29 04:49:35 PM PDT 24
Finished Jun 29 04:49:41 PM PDT 24
Peak memory 199604 kb
Host smart-4c6f0b4f-c640-4f69-9ef0-282679ab879b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50701969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.50701969
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.733338870
Short name T938
Test name
Test status
Simulation time 44040258178 ps
CPU time 73.13 seconds
Started Jun 29 04:49:44 PM PDT 24
Finished Jun 29 04:50:58 PM PDT 24
Peak memory 199852 kb
Host smart-b5b70e19-f33f-4d8f-9cd7-4e3dbc584cd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733338870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.733338870
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.3917611110
Short name T556
Test name
Test status
Simulation time 812188332 ps
CPU time 2.8 seconds
Started Jun 29 04:49:42 PM PDT 24
Finished Jun 29 04:49:46 PM PDT 24
Peak memory 199584 kb
Host smart-108fb240-264c-4961-b366-c2f6c93cae62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917611110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.3917611110
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.378897233
Short name T128
Test name
Test status
Simulation time 18890638248 ps
CPU time 14.98 seconds
Started Jun 29 04:49:43 PM PDT 24
Finished Jun 29 04:49:59 PM PDT 24
Peak memory 199892 kb
Host smart-5a9576da-e712-45f4-9307-2132efe6b15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378897233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.378897233
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.4159768861
Short name T981
Test name
Test status
Simulation time 13417621 ps
CPU time 0.55 seconds
Started Jun 29 04:49:45 PM PDT 24
Finished Jun 29 04:49:46 PM PDT 24
Peak memory 195588 kb
Host smart-2548c4fd-c607-49b5-a085-6561e8921441
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159768861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.4159768861
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.3773582590
Short name T726
Test name
Test status
Simulation time 18542203271 ps
CPU time 25.82 seconds
Started Jun 29 04:49:44 PM PDT 24
Finished Jun 29 04:50:11 PM PDT 24
Peak memory 199844 kb
Host smart-238c179e-1e68-47cb-832a-e69a33f5f5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773582590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.3773582590
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.4144265374
Short name T394
Test name
Test status
Simulation time 80308914014 ps
CPU time 90.06 seconds
Started Jun 29 04:49:42 PM PDT 24
Finished Jun 29 04:51:13 PM PDT 24
Peak memory 199928 kb
Host smart-b73440a1-c521-444c-8005-5404c26fb200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144265374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.4144265374
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.730783678
Short name T925
Test name
Test status
Simulation time 61772677413 ps
CPU time 34.99 seconds
Started Jun 29 04:49:43 PM PDT 24
Finished Jun 29 04:50:19 PM PDT 24
Peak memory 199824 kb
Host smart-1824cf0a-328c-4aed-9fdf-bf13a279764f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730783678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.730783678
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.2166619454
Short name T777
Test name
Test status
Simulation time 90786910424 ps
CPU time 190.86 seconds
Started Jun 29 04:49:43 PM PDT 24
Finished Jun 29 04:52:55 PM PDT 24
Peak memory 199884 kb
Host smart-26db75fc-dfe7-4e3e-a6d2-d379181fa55c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166619454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.2166619454
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.3116478242
Short name T405
Test name
Test status
Simulation time 22879050965 ps
CPU time 54.46 seconds
Started Jun 29 04:49:43 PM PDT 24
Finished Jun 29 04:50:38 PM PDT 24
Peak memory 199880 kb
Host smart-17303c22-9fbb-41a3-8558-8729d4c0e6d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3116478242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.3116478242
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.3418673290
Short name T443
Test name
Test status
Simulation time 8766823332 ps
CPU time 5.76 seconds
Started Jun 29 04:49:43 PM PDT 24
Finished Jun 29 04:49:50 PM PDT 24
Peak memory 199740 kb
Host smart-26fbb4f6-1aa6-4535-b4e9-2538d0df2c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418673290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.3418673290
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_perf.4270969676
Short name T1012
Test name
Test status
Simulation time 12246625938 ps
CPU time 297.85 seconds
Started Jun 29 04:49:45 PM PDT 24
Finished Jun 29 04:54:43 PM PDT 24
Peak memory 199948 kb
Host smart-8592a6d6-affb-4f0b-91cb-9386d7ae809e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4270969676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.4270969676
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.4129643743
Short name T756
Test name
Test status
Simulation time 5850805844 ps
CPU time 52.97 seconds
Started Jun 29 04:49:47 PM PDT 24
Finished Jun 29 04:50:40 PM PDT 24
Peak memory 198672 kb
Host smart-34898e2c-18bc-4a74-9743-83eadcb404ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4129643743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.4129643743
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.84344111
Short name T673
Test name
Test status
Simulation time 46290606998 ps
CPU time 70.62 seconds
Started Jun 29 04:49:43 PM PDT 24
Finished Jun 29 04:50:55 PM PDT 24
Peak memory 200012 kb
Host smart-b1a8ff43-0103-4168-a92e-5c51aa544e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84344111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.84344111
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.3563304976
Short name T1009
Test name
Test status
Simulation time 2996384104 ps
CPU time 5.2 seconds
Started Jun 29 04:49:42 PM PDT 24
Finished Jun 29 04:49:48 PM PDT 24
Peak memory 195948 kb
Host smart-a7c787e3-d9c6-48e7-aa06-c08fd7065237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563304976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.3563304976
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.4277957963
Short name T687
Test name
Test status
Simulation time 480551850 ps
CPU time 1.26 seconds
Started Jun 29 04:49:43 PM PDT 24
Finished Jun 29 04:49:45 PM PDT 24
Peak memory 198544 kb
Host smart-d1bc2c58-c9c1-4bf7-9659-dc57e2fbb8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277957963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.4277957963
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.1170456106
Short name T732
Test name
Test status
Simulation time 18155394552 ps
CPU time 453.62 seconds
Started Jun 29 04:49:43 PM PDT 24
Finished Jun 29 04:57:18 PM PDT 24
Peak memory 215664 kb
Host smart-5f8f6f1d-0619-4abf-8a49-c90b2276328b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170456106 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.1170456106
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.3909237113
Short name T305
Test name
Test status
Simulation time 2975135856 ps
CPU time 1.58 seconds
Started Jun 29 04:49:43 PM PDT 24
Finished Jun 29 04:49:46 PM PDT 24
Peak memory 198372 kb
Host smart-5410faa5-d4d3-4042-af32-755d85a251f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909237113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3909237113
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1509185384
Short name T436
Test name
Test status
Simulation time 616541469 ps
CPU time 1.24 seconds
Started Jun 29 04:49:46 PM PDT 24
Finished Jun 29 04:49:48 PM PDT 24
Peak memory 197052 kb
Host smart-67c8d2e4-7af2-4b5e-a0cc-efa090bdd4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509185384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1509185384
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.4185631144
Short name T425
Test name
Test status
Simulation time 23359347 ps
CPU time 0.6 seconds
Started Jun 29 04:48:02 PM PDT 24
Finished Jun 29 04:48:04 PM PDT 24
Peak memory 195592 kb
Host smart-209330fa-c295-4187-a2b7-854ebf34f45e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185631144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.4185631144
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1774224717
Short name T1028
Test name
Test status
Simulation time 114066028054 ps
CPU time 159.54 seconds
Started Jun 29 04:47:56 PM PDT 24
Finished Jun 29 04:50:36 PM PDT 24
Peak memory 199836 kb
Host smart-930bfef6-cc5b-4b28-b417-f1c928b9c78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774224717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1774224717
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.900706276
Short name T1031
Test name
Test status
Simulation time 17601582340 ps
CPU time 29.69 seconds
Started Jun 29 04:48:19 PM PDT 24
Finished Jun 29 04:48:49 PM PDT 24
Peak memory 199840 kb
Host smart-93f6c2cc-0ddc-4172-a4d4-0a1da2e9022a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900706276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.900706276
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.749002903
Short name T713
Test name
Test status
Simulation time 15047963851 ps
CPU time 32.74 seconds
Started Jun 29 04:48:04 PM PDT 24
Finished Jun 29 04:48:37 PM PDT 24
Peak memory 199896 kb
Host smart-0083e057-d3e7-498f-b041-d4d7f823abe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749002903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.749002903
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.3424717923
Short name T284
Test name
Test status
Simulation time 37517432967 ps
CPU time 67.3 seconds
Started Jun 29 04:48:11 PM PDT 24
Finished Jun 29 04:49:19 PM PDT 24
Peak memory 199776 kb
Host smart-6abb28ba-8df3-474e-b0c9-b0e91023dac9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424717923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3424717923
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.1372528443
Short name T843
Test name
Test status
Simulation time 165131052091 ps
CPU time 967.69 seconds
Started Jun 29 04:47:58 PM PDT 24
Finished Jun 29 05:04:07 PM PDT 24
Peak memory 199908 kb
Host smart-cbf90c56-fadf-43a0-b55d-09224667d737
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1372528443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1372528443
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.3046150147
Short name T400
Test name
Test status
Simulation time 4687999686 ps
CPU time 3.11 seconds
Started Jun 29 04:48:12 PM PDT 24
Finished Jun 29 04:48:16 PM PDT 24
Peak memory 198324 kb
Host smart-fc27a1d2-c8b4-41e3-8333-ef60a6a0931a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046150147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3046150147
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_perf.255889485
Short name T347
Test name
Test status
Simulation time 26459838476 ps
CPU time 1282.57 seconds
Started Jun 29 04:47:53 PM PDT 24
Finished Jun 29 05:09:16 PM PDT 24
Peak memory 199828 kb
Host smart-41e30e3e-82d8-4159-a816-f0fa4ab58ceb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=255889485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.255889485
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.843893100
Short name T557
Test name
Test status
Simulation time 1913748334 ps
CPU time 6.65 seconds
Started Jun 29 04:47:52 PM PDT 24
Finished Jun 29 04:47:59 PM PDT 24
Peak memory 198244 kb
Host smart-71ec809b-72ed-44e1-87eb-bc41cfc6fd2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=843893100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.843893100
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.201145021
Short name T473
Test name
Test status
Simulation time 137388621525 ps
CPU time 55.62 seconds
Started Jun 29 04:48:01 PM PDT 24
Finished Jun 29 04:48:57 PM PDT 24
Peak memory 199928 kb
Host smart-efa30d63-e5c8-44be-ad20-15d39a0cbeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201145021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.201145021
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.3461760583
Short name T326
Test name
Test status
Simulation time 4006159058 ps
CPU time 7.15 seconds
Started Jun 29 04:47:56 PM PDT 24
Finished Jun 29 04:48:04 PM PDT 24
Peak memory 196420 kb
Host smart-b0e3555e-42aa-42ff-8fb8-ab3cf8f6e655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461760583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.3461760583
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.1025355431
Short name T94
Test name
Test status
Simulation time 55573913 ps
CPU time 0.85 seconds
Started Jun 29 04:48:04 PM PDT 24
Finished Jun 29 04:48:06 PM PDT 24
Peak memory 218248 kb
Host smart-fcec7b0b-408e-4c32-99fa-95a15533a9e6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025355431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.1025355431
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.3208164037
Short name T578
Test name
Test status
Simulation time 6247372859 ps
CPU time 14.58 seconds
Started Jun 29 04:47:51 PM PDT 24
Finished Jun 29 04:48:06 PM PDT 24
Peak memory 199808 kb
Host smart-23eb05d8-de9a-4e51-bf68-2c5922ef4cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208164037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3208164037
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.237527791
Short name T532
Test name
Test status
Simulation time 13938215188 ps
CPU time 23 seconds
Started Jun 29 04:47:58 PM PDT 24
Finished Jun 29 04:48:22 PM PDT 24
Peak memory 199912 kb
Host smart-475d7372-157d-45c9-bd7f-2cbb3331f1f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237527791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.237527791
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.691398047
Short name T891
Test name
Test status
Simulation time 66690021057 ps
CPU time 1109.16 seconds
Started Jun 29 04:47:54 PM PDT 24
Finished Jun 29 05:06:24 PM PDT 24
Peak memory 224604 kb
Host smart-8b7c7e4a-4226-4d3a-b5b8-28099e8af9d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691398047 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.691398047
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.4097475248
Short name T396
Test name
Test status
Simulation time 6455926630 ps
CPU time 12.11 seconds
Started Jun 29 04:47:57 PM PDT 24
Finished Jun 29 04:48:10 PM PDT 24
Peak memory 199896 kb
Host smart-e11f9f63-38e0-4779-a32a-42513b112728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097475248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.4097475248
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.1449205372
Short name T281
Test name
Test status
Simulation time 91872795975 ps
CPU time 93.28 seconds
Started Jun 29 04:47:54 PM PDT 24
Finished Jun 29 04:49:28 PM PDT 24
Peak memory 199944 kb
Host smart-44c055db-a78a-4123-b664-787aee7b1760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449205372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.1449205372
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.1024357288
Short name T685
Test name
Test status
Simulation time 38445935 ps
CPU time 0.55 seconds
Started Jun 29 04:49:52 PM PDT 24
Finished Jun 29 04:49:53 PM PDT 24
Peak memory 195304 kb
Host smart-3bf28f47-f0e8-4a9b-9ca3-9cba3403bbf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024357288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.1024357288
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.1834458449
Short name T594
Test name
Test status
Simulation time 30723407378 ps
CPU time 50.69 seconds
Started Jun 29 04:49:48 PM PDT 24
Finished Jun 29 04:50:39 PM PDT 24
Peak memory 199992 kb
Host smart-7b465d3b-b200-4be6-91fe-08337ecb16c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834458449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.1834458449
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.1074918343
Short name T1053
Test name
Test status
Simulation time 25971497131 ps
CPU time 43.63 seconds
Started Jun 29 04:49:43 PM PDT 24
Finished Jun 29 04:50:27 PM PDT 24
Peak memory 199832 kb
Host smart-576a2072-d26e-4ea7-9211-6b953f451177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074918343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1074918343
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.640961625
Short name T97
Test name
Test status
Simulation time 11022200718 ps
CPU time 17.98 seconds
Started Jun 29 04:49:42 PM PDT 24
Finished Jun 29 04:50:02 PM PDT 24
Peak memory 199988 kb
Host smart-85d5bac4-f87f-48bc-82e8-d137e2c9ef2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640961625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.640961625
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.762515486
Short name T372
Test name
Test status
Simulation time 10251630558 ps
CPU time 8.45 seconds
Started Jun 29 04:49:43 PM PDT 24
Finished Jun 29 04:49:53 PM PDT 24
Peak memory 196580 kb
Host smart-3ae4f1d3-f785-4740-8bea-f8b4f3aa495e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762515486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.762515486
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2254173720
Short name T1050
Test name
Test status
Simulation time 188886876505 ps
CPU time 835.62 seconds
Started Jun 29 04:49:49 PM PDT 24
Finished Jun 29 05:03:46 PM PDT 24
Peak memory 199968 kb
Host smart-cea6c62f-ad29-4ee1-9c90-8e6dce99f3af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2254173720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2254173720
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.953619850
Short name T373
Test name
Test status
Simulation time 4490141319 ps
CPU time 3.86 seconds
Started Jun 29 04:49:50 PM PDT 24
Finished Jun 29 04:49:54 PM PDT 24
Peak memory 198556 kb
Host smart-d06ccb6d-3b8f-47e6-8fe9-b2322bb47ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953619850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.953619850
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_perf.2086447877
Short name T618
Test name
Test status
Simulation time 11960518076 ps
CPU time 182.43 seconds
Started Jun 29 04:49:55 PM PDT 24
Finished Jun 29 04:52:58 PM PDT 24
Peak memory 199944 kb
Host smart-892478f6-c580-443c-a2f4-cc792ce47f95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2086447877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2086447877
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.3648826891
Short name T561
Test name
Test status
Simulation time 1495740125 ps
CPU time 5.23 seconds
Started Jun 29 04:49:45 PM PDT 24
Finished Jun 29 04:49:51 PM PDT 24
Peak memory 198080 kb
Host smart-317c539b-461d-482e-a4ff-55c925b2c4c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3648826891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3648826891
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.846510862
Short name T1080
Test name
Test status
Simulation time 60129374563 ps
CPU time 73.7 seconds
Started Jun 29 04:49:50 PM PDT 24
Finished Jun 29 04:51:04 PM PDT 24
Peak memory 199932 kb
Host smart-67efd454-560f-442e-9bc5-c0cf6eaec617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846510862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.846510862
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.2904557971
Short name T1016
Test name
Test status
Simulation time 3384172586 ps
CPU time 1.95 seconds
Started Jun 29 04:49:51 PM PDT 24
Finished Jun 29 04:49:53 PM PDT 24
Peak memory 196064 kb
Host smart-11be6969-496b-4972-9c3a-940955f10094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904557971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2904557971
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.157200187
Short name T388
Test name
Test status
Simulation time 5809541192 ps
CPU time 25.57 seconds
Started Jun 29 04:49:44 PM PDT 24
Finished Jun 29 04:50:10 PM PDT 24
Peak memory 199948 kb
Host smart-3d9ef21d-6655-419e-a258-1cb981e36c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157200187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.157200187
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.1572256581
Short name T730
Test name
Test status
Simulation time 45909425904 ps
CPU time 438.44 seconds
Started Jun 29 04:49:49 PM PDT 24
Finished Jun 29 04:57:08 PM PDT 24
Peak memory 216492 kb
Host smart-be87c6fe-de57-44ab-a907-5b0b94988cea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572256581 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.1572256581
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.1683122963
Short name T746
Test name
Test status
Simulation time 892695187 ps
CPU time 2.42 seconds
Started Jun 29 04:49:46 PM PDT 24
Finished Jun 29 04:49:49 PM PDT 24
Peak memory 199136 kb
Host smart-44305875-6d39-4cda-a553-b2b9454a8ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683122963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.1683122963
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.4218038187
Short name T1086
Test name
Test status
Simulation time 52708074377 ps
CPU time 89.69 seconds
Started Jun 29 04:49:47 PM PDT 24
Finished Jun 29 04:51:18 PM PDT 24
Peak memory 199948 kb
Host smart-8d782af2-630e-4538-af15-29cc05a433b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218038187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.4218038187
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.1999435695
Short name T681
Test name
Test status
Simulation time 33052358 ps
CPU time 0.63 seconds
Started Jun 29 04:49:58 PM PDT 24
Finished Jun 29 04:50:00 PM PDT 24
Peak memory 195276 kb
Host smart-d711f509-f306-40cd-b3cf-66c61cd00807
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999435695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1999435695
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.330364714
Short name T406
Test name
Test status
Simulation time 35472537706 ps
CPU time 51.13 seconds
Started Jun 29 04:49:49 PM PDT 24
Finished Jun 29 04:50:41 PM PDT 24
Peak memory 199916 kb
Host smart-e8f68cf5-1fcd-492e-bf9c-206f0b7029a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330364714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.330364714
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3627378828
Short name T489
Test name
Test status
Simulation time 19217517914 ps
CPU time 10.59 seconds
Started Jun 29 04:49:54 PM PDT 24
Finished Jun 29 04:50:05 PM PDT 24
Peak memory 199992 kb
Host smart-83be6bb6-e2ab-48d1-94d8-216c37b66f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627378828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3627378828
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.537170671
Short name T890
Test name
Test status
Simulation time 55508591147 ps
CPU time 29.29 seconds
Started Jun 29 04:49:52 PM PDT 24
Finished Jun 29 04:50:22 PM PDT 24
Peak memory 199952 kb
Host smart-f612073c-3df1-4919-8b30-3f97b4ddf32e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537170671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.537170671
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.9169021
Short name T263
Test name
Test status
Simulation time 209974413348 ps
CPU time 124.44 seconds
Started Jun 29 04:49:53 PM PDT 24
Finished Jun 29 04:51:58 PM PDT 24
Peak memory 199916 kb
Host smart-8adb0cc6-b40b-4289-b29c-788b3767f352
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=9169021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.9169021
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.3596743659
Short name T357
Test name
Test status
Simulation time 4811569957 ps
CPU time 5.85 seconds
Started Jun 29 04:49:50 PM PDT 24
Finished Jun 29 04:49:56 PM PDT 24
Peak memory 198340 kb
Host smart-ae03a19d-5749-4788-8629-4caed131432f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596743659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3596743659
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.2666122823
Short name T342
Test name
Test status
Simulation time 38316176161 ps
CPU time 14.08 seconds
Started Jun 29 04:49:51 PM PDT 24
Finished Jun 29 04:50:06 PM PDT 24
Peak memory 199784 kb
Host smart-a8baf67a-6d4b-4eb8-a5ab-dd41f50abca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666122823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.2666122823
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.1606837153
Short name T507
Test name
Test status
Simulation time 28494485734 ps
CPU time 695.16 seconds
Started Jun 29 04:49:52 PM PDT 24
Finished Jun 29 05:01:28 PM PDT 24
Peak memory 199980 kb
Host smart-d4057dd7-901c-44e9-9671-512787fe3e67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1606837153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1606837153
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.2028421872
Short name T821
Test name
Test status
Simulation time 4833898106 ps
CPU time 21.95 seconds
Started Jun 29 04:49:55 PM PDT 24
Finished Jun 29 04:50:18 PM PDT 24
Peak memory 199244 kb
Host smart-f5acac92-14dd-4d7b-9256-e8352c8155d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2028421872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2028421872
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.2656409187
Short name T280
Test name
Test status
Simulation time 15910916919 ps
CPU time 7.72 seconds
Started Jun 29 04:49:52 PM PDT 24
Finished Jun 29 04:50:00 PM PDT 24
Peak memory 199600 kb
Host smart-6c161dd8-30ea-49cd-929f-a273b5a04a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656409187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2656409187
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.507671887
Short name T453
Test name
Test status
Simulation time 5083857001 ps
CPU time 2.51 seconds
Started Jun 29 04:49:51 PM PDT 24
Finished Jun 29 04:49:54 PM PDT 24
Peak memory 196228 kb
Host smart-92b9120f-5baf-4624-82f8-fb92af721bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507671887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.507671887
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.163721991
Short name T989
Test name
Test status
Simulation time 5761233099 ps
CPU time 16.33 seconds
Started Jun 29 04:49:51 PM PDT 24
Finished Jun 29 04:50:07 PM PDT 24
Peak memory 199736 kb
Host smart-e07e2c50-26b8-47a8-a9ce-544ff77ccee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163721991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.163721991
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.3511402713
Short name T874
Test name
Test status
Simulation time 6679374199 ps
CPU time 18.21 seconds
Started Jun 29 04:49:50 PM PDT 24
Finished Jun 29 04:50:09 PM PDT 24
Peak memory 199880 kb
Host smart-7d9ff757-27fd-4547-966c-cf74ba0e2004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511402713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3511402713
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.1521843165
Short name T781
Test name
Test status
Simulation time 18287972256 ps
CPU time 15.69 seconds
Started Jun 29 04:49:51 PM PDT 24
Finished Jun 29 04:50:07 PM PDT 24
Peak memory 199824 kb
Host smart-019abc4c-7008-4630-b997-9c0de90c1d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521843165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1521843165
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.17207717
Short name T354
Test name
Test status
Simulation time 13107817 ps
CPU time 0.58 seconds
Started Jun 29 04:49:59 PM PDT 24
Finished Jun 29 04:50:01 PM PDT 24
Peak memory 195304 kb
Host smart-935503db-6744-49f4-811f-92a2d33adad8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17207717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.17207717
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.3141487491
Short name T129
Test name
Test status
Simulation time 33777988931 ps
CPU time 58.1 seconds
Started Jun 29 04:49:59 PM PDT 24
Finished Jun 29 04:50:58 PM PDT 24
Peak memory 199864 kb
Host smart-8b4c92a5-eb78-46f6-8ef3-848bcccecfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141487491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3141487491
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.596854821
Short name T257
Test name
Test status
Simulation time 35437709020 ps
CPU time 16.12 seconds
Started Jun 29 04:50:00 PM PDT 24
Finished Jun 29 04:50:17 PM PDT 24
Peak memory 199344 kb
Host smart-7f5952d2-e180-48f5-9ca2-3a8fd6107789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596854821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.596854821
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.1265776185
Short name T729
Test name
Test status
Simulation time 37863095036 ps
CPU time 95.12 seconds
Started Jun 29 04:49:58 PM PDT 24
Finished Jun 29 04:51:35 PM PDT 24
Peak memory 199988 kb
Host smart-c2296b9e-5365-470d-b9a2-eaa43618821b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265776185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.1265776185
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2924322002
Short name T484
Test name
Test status
Simulation time 27854847565 ps
CPU time 46.57 seconds
Started Jun 29 04:49:59 PM PDT 24
Finished Jun 29 04:50:47 PM PDT 24
Peak memory 198640 kb
Host smart-7b1f67ae-353f-4dd5-98b8-73ffd4f6ff1c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924322002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2924322002
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.1917248911
Short name T262
Test name
Test status
Simulation time 97971474387 ps
CPU time 297.96 seconds
Started Jun 29 04:50:00 PM PDT 24
Finished Jun 29 04:54:59 PM PDT 24
Peak memory 199732 kb
Host smart-51de9d92-70f9-4469-87db-5bf521945a61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1917248911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.1917248911
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.1185298231
Short name T14
Test name
Test status
Simulation time 6464482781 ps
CPU time 21.57 seconds
Started Jun 29 04:49:58 PM PDT 24
Finished Jun 29 04:50:21 PM PDT 24
Peak memory 199956 kb
Host smart-aa3a4945-7505-4b22-bc75-d485cebca740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185298231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1185298231
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_perf.1938837104
Short name T525
Test name
Test status
Simulation time 9925358568 ps
CPU time 552.96 seconds
Started Jun 29 04:49:58 PM PDT 24
Finished Jun 29 04:59:13 PM PDT 24
Peak memory 199920 kb
Host smart-da548579-635f-4451-b5c0-9cee9eae45cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1938837104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1938837104
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.2235894221
Short name T562
Test name
Test status
Simulation time 6459800598 ps
CPU time 62.75 seconds
Started Jun 29 04:49:58 PM PDT 24
Finished Jun 29 04:51:03 PM PDT 24
Peak memory 199272 kb
Host smart-24512a54-f956-4287-8a23-5d4d2d2cad3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2235894221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.2235894221
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.2459815757
Short name T294
Test name
Test status
Simulation time 109908078332 ps
CPU time 177.37 seconds
Started Jun 29 04:49:59 PM PDT 24
Finished Jun 29 04:52:57 PM PDT 24
Peak memory 199944 kb
Host smart-b85a259f-f2da-46b0-bf04-53581d1bc1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459815757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2459815757
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.4229384387
Short name T320
Test name
Test status
Simulation time 1639948042 ps
CPU time 3.14 seconds
Started Jun 29 04:49:59 PM PDT 24
Finished Jun 29 04:50:03 PM PDT 24
Peak memory 195344 kb
Host smart-5bb17423-9439-48d6-8f72-4579a10b76f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229384387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.4229384387
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.1778034441
Short name T421
Test name
Test status
Simulation time 5758123773 ps
CPU time 10.75 seconds
Started Jun 29 04:49:59 PM PDT 24
Finished Jun 29 04:50:11 PM PDT 24
Peak memory 199884 kb
Host smart-b29ec106-2390-4ec1-a252-842deef176a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778034441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1778034441
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3643941596
Short name T170
Test name
Test status
Simulation time 351144293006 ps
CPU time 900.71 seconds
Started Jun 29 04:49:58 PM PDT 24
Finished Jun 29 05:05:00 PM PDT 24
Peak memory 226540 kb
Host smart-153d4221-a39c-4a44-ab96-b754896cd498
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643941596 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3643941596
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.4193717307
Short name T995
Test name
Test status
Simulation time 1293691061 ps
CPU time 3.98 seconds
Started Jun 29 04:50:00 PM PDT 24
Finished Jun 29 04:50:05 PM PDT 24
Peak memory 199588 kb
Host smart-357d2ddf-7e13-4944-832f-0d657641fd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193717307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.4193717307
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.1638454129
Short name T338
Test name
Test status
Simulation time 18974248403 ps
CPU time 14.09 seconds
Started Jun 29 04:49:58 PM PDT 24
Finished Jun 29 04:50:13 PM PDT 24
Peak memory 196672 kb
Host smart-dc4889cc-7ac6-4455-b6b3-f17c7e65f73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638454129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1638454129
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.842724786
Short name T360
Test name
Test status
Simulation time 13116952 ps
CPU time 0.57 seconds
Started Jun 29 04:50:06 PM PDT 24
Finished Jun 29 04:50:08 PM PDT 24
Peak memory 195304 kb
Host smart-d08aca57-46c4-498c-b384-90fd96fe3e27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842724786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.842724786
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1647665981
Short name T296
Test name
Test status
Simulation time 22866502822 ps
CPU time 35.83 seconds
Started Jun 29 04:50:00 PM PDT 24
Finished Jun 29 04:50:37 PM PDT 24
Peak memory 199812 kb
Host smart-06735c5b-1b46-4514-ad9e-b6d62dd627a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647665981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1647665981
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.706045335
Short name T988
Test name
Test status
Simulation time 258041088938 ps
CPU time 119.59 seconds
Started Jun 29 04:49:59 PM PDT 24
Finished Jun 29 04:52:00 PM PDT 24
Peak memory 199900 kb
Host smart-5a6ca9b1-4f7b-4a19-bc70-cfc3c223284a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706045335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.706045335
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.2119563935
Short name T150
Test name
Test status
Simulation time 52470878993 ps
CPU time 88.09 seconds
Started Jun 29 04:50:00 PM PDT 24
Finished Jun 29 04:51:29 PM PDT 24
Peak memory 199864 kb
Host smart-64b452da-f638-4df6-94fc-414961c1a384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119563935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2119563935
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.1508653166
Short name T785
Test name
Test status
Simulation time 27254936559 ps
CPU time 21.55 seconds
Started Jun 29 04:49:58 PM PDT 24
Finished Jun 29 04:50:21 PM PDT 24
Peak memory 199760 kb
Host smart-3916fbf4-837b-4bd9-b926-aee09061c1f5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508653166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1508653166
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.2648407254
Short name T301
Test name
Test status
Simulation time 285248610681 ps
CPU time 196.79 seconds
Started Jun 29 04:50:06 PM PDT 24
Finished Jun 29 04:53:23 PM PDT 24
Peak memory 199952 kb
Host smart-8dd54335-44c3-49bb-8767-91ba4dbe674a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2648407254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.2648407254
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.3527930622
Short name T699
Test name
Test status
Simulation time 13318137767 ps
CPU time 24.4 seconds
Started Jun 29 04:49:59 PM PDT 24
Finished Jun 29 04:50:24 PM PDT 24
Peak memory 199800 kb
Host smart-0f4bc000-df5b-416e-9aa2-a4f08fbdb516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527930622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3527930622
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_perf.1810361353
Short name T449
Test name
Test status
Simulation time 13521382783 ps
CPU time 772.2 seconds
Started Jun 29 04:49:58 PM PDT 24
Finished Jun 29 05:02:52 PM PDT 24
Peak memory 199980 kb
Host smart-15fddb42-7851-4b40-ab8e-0ecabf7fbc71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1810361353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1810361353
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.962840691
Short name T706
Test name
Test status
Simulation time 2006029215 ps
CPU time 9.54 seconds
Started Jun 29 04:49:57 PM PDT 24
Finished Jun 29 04:50:07 PM PDT 24
Peak memory 198004 kb
Host smart-2a579346-e3d7-46c7-b60f-f2cf30b5ac91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=962840691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.962840691
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.3690369536
Short name T519
Test name
Test status
Simulation time 125490106591 ps
CPU time 88.18 seconds
Started Jun 29 04:50:00 PM PDT 24
Finished Jun 29 04:51:29 PM PDT 24
Peak memory 199860 kb
Host smart-79c8f82a-8aea-44b0-b2a4-f5c887ef5c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690369536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3690369536
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.3901126311
Short name T819
Test name
Test status
Simulation time 1633663786 ps
CPU time 1.21 seconds
Started Jun 29 04:49:59 PM PDT 24
Finished Jun 29 04:50:02 PM PDT 24
Peak memory 195396 kb
Host smart-8e698514-7213-481a-be0b-9394baa6a304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901126311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3901126311
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1170742854
Short name T440
Test name
Test status
Simulation time 266728831 ps
CPU time 1.46 seconds
Started Jun 29 04:50:00 PM PDT 24
Finished Jun 29 04:50:03 PM PDT 24
Peak memory 198540 kb
Host smart-7302bd08-80ea-4aa7-b076-6045aec25fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170742854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1170742854
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.2628731186
Short name T117
Test name
Test status
Simulation time 192136189003 ps
CPU time 363.08 seconds
Started Jun 29 04:50:09 PM PDT 24
Finished Jun 29 04:56:12 PM PDT 24
Peak memory 199944 kb
Host smart-70839cf4-710a-4483-bf01-32c37f523dfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628731186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2628731186
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3365882449
Short name T597
Test name
Test status
Simulation time 6329149755 ps
CPU time 17.51 seconds
Started Jun 29 04:49:58 PM PDT 24
Finished Jun 29 04:50:17 PM PDT 24
Peak memory 199920 kb
Host smart-22dfaa95-918d-4788-9d60-f783a9443b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365882449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3365882449
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.3799982212
Short name T254
Test name
Test status
Simulation time 74332017110 ps
CPU time 80.3 seconds
Started Jun 29 04:49:58 PM PDT 24
Finished Jun 29 04:51:19 PM PDT 24
Peak memory 199824 kb
Host smart-3c089a28-0c6c-4278-9dfc-54306af8489d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799982212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.3799982212
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.757468956
Short name T554
Test name
Test status
Simulation time 12948016 ps
CPU time 0.58 seconds
Started Jun 29 04:50:06 PM PDT 24
Finished Jun 29 04:50:07 PM PDT 24
Peak memory 194532 kb
Host smart-281df981-e2ad-40fe-8110-83e16cd91fb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757468956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.757468956
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.1820062347
Short name T826
Test name
Test status
Simulation time 57422791704 ps
CPU time 24.57 seconds
Started Jun 29 04:50:05 PM PDT 24
Finished Jun 29 04:50:30 PM PDT 24
Peak memory 199988 kb
Host smart-405837a6-6961-4c9f-a298-c39d1b70b4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820062347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1820062347
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.4038594663
Short name T786
Test name
Test status
Simulation time 123761320802 ps
CPU time 128.21 seconds
Started Jun 29 04:50:06 PM PDT 24
Finished Jun 29 04:52:15 PM PDT 24
Peak memory 199940 kb
Host smart-4d75009d-bd91-4d6b-b3cf-ee1a26bb3cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038594663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.4038594663
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2386604013
Short name T187
Test name
Test status
Simulation time 36845537582 ps
CPU time 51.46 seconds
Started Jun 29 04:50:08 PM PDT 24
Finished Jun 29 04:51:00 PM PDT 24
Peak memory 199916 kb
Host smart-9f412bb0-be56-4069-8f8a-14740e15ff3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386604013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2386604013
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.1171554226
Short name T810
Test name
Test status
Simulation time 8568158269 ps
CPU time 18.23 seconds
Started Jun 29 04:50:08 PM PDT 24
Finished Jun 29 04:50:27 PM PDT 24
Peak memory 199980 kb
Host smart-7dc4084f-f3d2-4bf3-b476-cbf4861daa96
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171554226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1171554226
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.4146402097
Short name T1041
Test name
Test status
Simulation time 92339388957 ps
CPU time 648.48 seconds
Started Jun 29 04:50:07 PM PDT 24
Finished Jun 29 05:00:56 PM PDT 24
Peak memory 199996 kb
Host smart-68d2db28-9321-45ce-ad81-2a712abc864c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4146402097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.4146402097
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1559951796
Short name T503
Test name
Test status
Simulation time 5882424342 ps
CPU time 11.39 seconds
Started Jun 29 04:50:06 PM PDT 24
Finished Jun 29 04:50:19 PM PDT 24
Peak memory 199844 kb
Host smart-2b5f9dd9-5727-480c-a183-0c109a61fcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559951796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1559951796
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_perf.2017289288
Short name T420
Test name
Test status
Simulation time 10555454276 ps
CPU time 207.06 seconds
Started Jun 29 04:50:06 PM PDT 24
Finished Jun 29 04:53:34 PM PDT 24
Peak memory 199896 kb
Host smart-065da0c5-9b29-4d4a-8ae9-e94e733582d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2017289288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2017289288
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.1230817699
Short name T658
Test name
Test status
Simulation time 2078799327 ps
CPU time 5.73 seconds
Started Jun 29 04:50:06 PM PDT 24
Finished Jun 29 04:50:13 PM PDT 24
Peak memory 198084 kb
Host smart-c65f30b6-120c-4df5-8d16-226083031800
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1230817699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1230817699
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.3802877184
Short name T682
Test name
Test status
Simulation time 42264217413 ps
CPU time 13.22 seconds
Started Jun 29 04:50:07 PM PDT 24
Finished Jun 29 04:50:21 PM PDT 24
Peak memory 199168 kb
Host smart-93e00277-6ae4-496e-879a-f3f110e4e41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802877184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3802877184
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.418148263
Short name T994
Test name
Test status
Simulation time 1378776371 ps
CPU time 1.71 seconds
Started Jun 29 04:50:05 PM PDT 24
Finished Jun 29 04:50:08 PM PDT 24
Peak memory 195408 kb
Host smart-b28b7883-7fb3-4210-bd40-0155fb84cb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418148263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.418148263
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.1484389753
Short name T975
Test name
Test status
Simulation time 692025392 ps
CPU time 1.71 seconds
Started Jun 29 04:50:05 PM PDT 24
Finished Jun 29 04:50:07 PM PDT 24
Peak memory 199784 kb
Host smart-a6036e34-f06f-4709-a0eb-cbcb65f46181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484389753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1484389753
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.908385279
Short name T438
Test name
Test status
Simulation time 6405684734 ps
CPU time 17.85 seconds
Started Jun 29 04:50:07 PM PDT 24
Finished Jun 29 04:50:26 PM PDT 24
Peak memory 199644 kb
Host smart-5342230f-5732-4658-ba68-1aeffc50c42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908385279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.908385279
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.3011233082
Short name T297
Test name
Test status
Simulation time 87623743071 ps
CPU time 33.27 seconds
Started Jun 29 04:50:07 PM PDT 24
Finished Jun 29 04:50:41 PM PDT 24
Peak memory 199936 kb
Host smart-0a6d24d9-ca93-4752-ae83-0bd5b3ee9628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011233082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3011233082
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3763101705
Short name T720
Test name
Test status
Simulation time 28656659 ps
CPU time 0.55 seconds
Started Jun 29 04:50:15 PM PDT 24
Finished Jun 29 04:50:16 PM PDT 24
Peak memory 194280 kb
Host smart-e4f9cb8f-5bb7-4e67-8a4c-663f47dd2a0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763101705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3763101705
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.1603415921
Short name T478
Test name
Test status
Simulation time 285162763804 ps
CPU time 31 seconds
Started Jun 29 04:50:06 PM PDT 24
Finished Jun 29 04:50:38 PM PDT 24
Peak memory 199888 kb
Host smart-76298331-fd0b-4eaa-a1a9-ec4ac085840e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603415921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1603415921
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.717125909
Short name T309
Test name
Test status
Simulation time 228885952861 ps
CPU time 49.06 seconds
Started Jun 29 04:50:04 PM PDT 24
Finished Jun 29 04:50:54 PM PDT 24
Peak memory 199788 kb
Host smart-a25524ab-4c92-4022-8048-7454bb7a7598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717125909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.717125909
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.480685364
Short name T46
Test name
Test status
Simulation time 17958127817 ps
CPU time 33.64 seconds
Started Jun 29 04:50:05 PM PDT 24
Finished Jun 29 04:50:39 PM PDT 24
Peak memory 199872 kb
Host smart-7c3d9efa-eaf6-4e14-beff-48221aa31707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480685364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.480685364
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.305580502
Short name T460
Test name
Test status
Simulation time 70663174907 ps
CPU time 54.4 seconds
Started Jun 29 04:50:08 PM PDT 24
Finished Jun 29 04:51:03 PM PDT 24
Peak memory 199936 kb
Host smart-9a84454c-fbe2-40b2-b973-842f5ca48975
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305580502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.305580502
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.1490136776
Short name T291
Test name
Test status
Simulation time 293666147242 ps
CPU time 594.68 seconds
Started Jun 29 04:50:11 PM PDT 24
Finished Jun 29 05:00:06 PM PDT 24
Peak memory 199732 kb
Host smart-672dcbc2-31e3-4cea-8a09-1e2d858bf482
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1490136776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1490136776
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.429481707
Short name T1065
Test name
Test status
Simulation time 12424932759 ps
CPU time 15.44 seconds
Started Jun 29 04:50:06 PM PDT 24
Finished Jun 29 04:50:22 PM PDT 24
Peak memory 198556 kb
Host smart-6b9f811e-7c9c-43a1-a9f8-7f6f260e0e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429481707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.429481707
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.3921871075
Short name T983
Test name
Test status
Simulation time 113860831446 ps
CPU time 22.2 seconds
Started Jun 29 04:50:06 PM PDT 24
Finished Jun 29 04:50:29 PM PDT 24
Peak memory 200048 kb
Host smart-41e7d04c-a003-4840-a65e-a05272dc95ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921871075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.3921871075
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.3964902767
Short name T686
Test name
Test status
Simulation time 21889003247 ps
CPU time 602.51 seconds
Started Jun 29 04:50:07 PM PDT 24
Finished Jun 29 05:00:10 PM PDT 24
Peak memory 199984 kb
Host smart-cdfb9b8e-aceb-4c92-9acb-a5e42d4aa728
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3964902767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3964902767
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.4118609680
Short name T944
Test name
Test status
Simulation time 4528118894 ps
CPU time 36.57 seconds
Started Jun 29 04:50:05 PM PDT 24
Finished Jun 29 04:50:43 PM PDT 24
Peak memory 198160 kb
Host smart-cc9b9065-2916-49ef-801b-4d2d2651b1f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4118609680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.4118609680
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.2907196909
Short name T915
Test name
Test status
Simulation time 85104052121 ps
CPU time 114.82 seconds
Started Jun 29 04:50:07 PM PDT 24
Finished Jun 29 04:52:03 PM PDT 24
Peak memory 199868 kb
Host smart-6dfae335-b125-44d1-8940-a1f777c52739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907196909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2907196909
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.2076894763
Short name T700
Test name
Test status
Simulation time 5763744550 ps
CPU time 9.45 seconds
Started Jun 29 04:50:06 PM PDT 24
Finished Jun 29 04:50:16 PM PDT 24
Peak memory 195960 kb
Host smart-56d2b7b3-8163-4bfe-bbfc-98f6bb3147f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076894763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2076894763
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.4050723442
Short name T1063
Test name
Test status
Simulation time 488306702 ps
CPU time 1.62 seconds
Started Jun 29 04:50:05 PM PDT 24
Finished Jun 29 04:50:08 PM PDT 24
Peak memory 198404 kb
Host smart-e315f1e2-9ada-4c81-8552-553092a778da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050723442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.4050723442
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.860702344
Short name T468
Test name
Test status
Simulation time 6771156721 ps
CPU time 21.97 seconds
Started Jun 29 04:50:07 PM PDT 24
Finished Jun 29 04:50:30 PM PDT 24
Peak memory 199792 kb
Host smart-57c8174f-0eca-4476-b57f-89760ddb5b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860702344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.860702344
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.1669546527
Short name T795
Test name
Test status
Simulation time 44357504842 ps
CPU time 40.75 seconds
Started Jun 29 04:50:11 PM PDT 24
Finished Jun 29 04:50:52 PM PDT 24
Peak memory 199936 kb
Host smart-0b3fcb9f-82d0-475c-aa69-4b5e27e4de4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669546527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1669546527
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.3085935342
Short name T1064
Test name
Test status
Simulation time 23951306 ps
CPU time 0.56 seconds
Started Jun 29 04:50:17 PM PDT 24
Finished Jun 29 04:50:18 PM PDT 24
Peak memory 195504 kb
Host smart-a8a4579f-f59b-4e90-ac70-2dba99b34a99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085935342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3085935342
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.2253061532
Short name T1084
Test name
Test status
Simulation time 81559631250 ps
CPU time 36.1 seconds
Started Jun 29 04:50:15 PM PDT 24
Finished Jun 29 04:50:52 PM PDT 24
Peak memory 199928 kb
Host smart-a8d10891-e07e-4455-9b26-7634ef336c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253061532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2253061532
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.4283747526
Short name T136
Test name
Test status
Simulation time 17364753673 ps
CPU time 13.39 seconds
Started Jun 29 04:50:13 PM PDT 24
Finished Jun 29 04:50:27 PM PDT 24
Peak memory 198180 kb
Host smart-6e6e9776-7a43-4156-920f-709ad2177fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283747526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.4283747526
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.4227536733
Short name T1094
Test name
Test status
Simulation time 137115765179 ps
CPU time 66.26 seconds
Started Jun 29 04:50:14 PM PDT 24
Finished Jun 29 04:51:20 PM PDT 24
Peak memory 199952 kb
Host smart-000158a1-38cd-4513-8998-255745cea7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227536733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.4227536733
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.451473795
Short name T676
Test name
Test status
Simulation time 5363293252 ps
CPU time 8.59 seconds
Started Jun 29 04:50:17 PM PDT 24
Finished Jun 29 04:50:26 PM PDT 24
Peak memory 195936 kb
Host smart-c764a9ab-d864-4669-a34c-f0606bcdade3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451473795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.451473795
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3239846006
Short name T974
Test name
Test status
Simulation time 118714574721 ps
CPU time 291.06 seconds
Started Jun 29 04:50:16 PM PDT 24
Finished Jun 29 04:55:07 PM PDT 24
Peak memory 199912 kb
Host smart-0500dfb9-a171-4d30-b466-eb91fd792797
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3239846006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3239846006
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.1736313168
Short name T804
Test name
Test status
Simulation time 6666312749 ps
CPU time 5.99 seconds
Started Jun 29 04:50:16 PM PDT 24
Finished Jun 29 04:50:22 PM PDT 24
Peak memory 199736 kb
Host smart-7b805139-1b9a-496f-a2cb-3c55ddaf9f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736313168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.1736313168
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.1365242512
Short name T743
Test name
Test status
Simulation time 61545087872 ps
CPU time 10.83 seconds
Started Jun 29 04:50:14 PM PDT 24
Finished Jun 29 04:50:25 PM PDT 24
Peak memory 198388 kb
Host smart-ab038524-52bc-4d57-9e46-8bc9fb11134a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365242512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.1365242512
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.3067783691
Short name T364
Test name
Test status
Simulation time 17612665491 ps
CPU time 847.85 seconds
Started Jun 29 04:50:12 PM PDT 24
Finished Jun 29 05:04:20 PM PDT 24
Peak memory 199896 kb
Host smart-47322a40-4db7-4732-82dd-05b5c6bd8f03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3067783691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3067783691
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.1635553777
Short name T759
Test name
Test status
Simulation time 4657916500 ps
CPU time 2.45 seconds
Started Jun 29 04:50:18 PM PDT 24
Finished Jun 29 04:50:21 PM PDT 24
Peak memory 198760 kb
Host smart-a7ac098c-7f6a-40d2-8959-7ffdc0f2bd69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1635553777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.1635553777
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.380918903
Short name T762
Test name
Test status
Simulation time 89989077797 ps
CPU time 127.5 seconds
Started Jun 29 04:50:12 PM PDT 24
Finished Jun 29 04:52:20 PM PDT 24
Peak memory 199984 kb
Host smart-2ee3651f-3ca2-4a38-ba35-453dc196a2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380918903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.380918903
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3438506930
Short name T737
Test name
Test status
Simulation time 44710174020 ps
CPU time 68.43 seconds
Started Jun 29 04:50:15 PM PDT 24
Finished Jun 29 04:51:24 PM PDT 24
Peak memory 196728 kb
Host smart-86e8d83b-1bb0-43bd-af0e-f0a2e4a16209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438506930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3438506930
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.914594127
Short name T295
Test name
Test status
Simulation time 6265358064 ps
CPU time 32.06 seconds
Started Jun 29 04:50:15 PM PDT 24
Finished Jun 29 04:50:48 PM PDT 24
Peak memory 199716 kb
Host smart-90b32ea4-ba9d-4ece-b031-63829659b26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914594127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.914594127
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.2879941703
Short name T889
Test name
Test status
Simulation time 117812769480 ps
CPU time 2065.92 seconds
Started Jun 29 04:50:12 PM PDT 24
Finished Jun 29 05:24:38 PM PDT 24
Peak memory 199972 kb
Host smart-a69a5ac9-3108-4d75-b6cd-e6790b4e016c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879941703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.2879941703
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.2088797183
Short name T1030
Test name
Test status
Simulation time 128427641225 ps
CPU time 888.52 seconds
Started Jun 29 04:50:14 PM PDT 24
Finished Jun 29 05:05:03 PM PDT 24
Peak memory 216500 kb
Host smart-eeb4a933-6941-4c35-b511-aef780c4f27a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088797183 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2088797183
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.835625163
Short name T292
Test name
Test status
Simulation time 7034277425 ps
CPU time 26.93 seconds
Started Jun 29 04:50:15 PM PDT 24
Finished Jun 29 04:50:42 PM PDT 24
Peak memory 199916 kb
Host smart-2a001da8-8a23-44ea-98ac-21c6bb9a6994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835625163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.835625163
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1918281278
Short name T536
Test name
Test status
Simulation time 17994962985 ps
CPU time 33.09 seconds
Started Jun 29 04:50:14 PM PDT 24
Finished Jun 29 04:50:47 PM PDT 24
Peak memory 199996 kb
Host smart-34f57c4a-ba09-4e5c-88b0-968744b9515c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918281278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1918281278
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.2453183586
Short name T591
Test name
Test status
Simulation time 21633798 ps
CPU time 0.59 seconds
Started Jun 29 04:50:21 PM PDT 24
Finished Jun 29 04:50:22 PM PDT 24
Peak memory 194656 kb
Host smart-42dda5aa-cfd5-4ce0-86bc-48919e555c41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453183586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2453183586
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.1702751838
Short name T770
Test name
Test status
Simulation time 59839947182 ps
CPU time 26.86 seconds
Started Jun 29 04:50:14 PM PDT 24
Finished Jun 29 04:50:42 PM PDT 24
Peak memory 199996 kb
Host smart-2b0c98cc-2c6d-4cdd-b58c-a460813e471a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702751838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1702751838
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.4124840810
Short name T1074
Test name
Test status
Simulation time 155203723121 ps
CPU time 50.31 seconds
Started Jun 29 04:50:15 PM PDT 24
Finished Jun 29 04:51:05 PM PDT 24
Peak memory 199860 kb
Host smart-1529510c-51fc-4bc1-9883-7a12754b9d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124840810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.4124840810
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.964374344
Short name T242
Test name
Test status
Simulation time 129145211863 ps
CPU time 201.41 seconds
Started Jun 29 04:50:16 PM PDT 24
Finished Jun 29 04:53:38 PM PDT 24
Peak memory 199968 kb
Host smart-881a371c-7e6a-4367-98a0-477b5047a411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964374344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.964374344
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.2220027709
Short name T629
Test name
Test status
Simulation time 18462124166 ps
CPU time 47.98 seconds
Started Jun 29 04:50:13 PM PDT 24
Finished Jun 29 04:51:01 PM PDT 24
Peak memory 199860 kb
Host smart-e82f01d3-2a79-4cfc-916d-6cb52ff57c3b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220027709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2220027709
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.330601046
Short name T778
Test name
Test status
Simulation time 116785068537 ps
CPU time 567.63 seconds
Started Jun 29 04:50:24 PM PDT 24
Finished Jun 29 04:59:52 PM PDT 24
Peak memory 199912 kb
Host smart-e9948b8d-27b5-4d6a-b49b-7aff532abd0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=330601046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.330601046
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.3707479201
Short name T1039
Test name
Test status
Simulation time 5430734895 ps
CPU time 12.32 seconds
Started Jun 29 04:50:14 PM PDT 24
Finished Jun 29 04:50:26 PM PDT 24
Peak memory 198980 kb
Host smart-375ca6fa-a0fd-4c16-90b0-e1def536f809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707479201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3707479201
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_perf.3929164886
Short name T788
Test name
Test status
Simulation time 2830796975 ps
CPU time 42.1 seconds
Started Jun 29 04:50:15 PM PDT 24
Finished Jun 29 04:50:58 PM PDT 24
Peak memory 199980 kb
Host smart-3dc1462b-e0c1-4cdc-b840-281a947fec21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3929164886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.3929164886
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.4281365877
Short name T520
Test name
Test status
Simulation time 2223016233 ps
CPU time 8.8 seconds
Started Jun 29 04:50:16 PM PDT 24
Finished Jun 29 04:50:25 PM PDT 24
Peak memory 198076 kb
Host smart-2cacbd68-13f5-4404-b534-b890517d1604
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4281365877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.4281365877
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.2031657693
Short name T704
Test name
Test status
Simulation time 29768596656 ps
CPU time 49.32 seconds
Started Jun 29 04:50:14 PM PDT 24
Finished Jun 29 04:51:04 PM PDT 24
Peak memory 199924 kb
Host smart-f9f99525-a5df-4046-8992-673d43ac3276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031657693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.2031657693
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.179688698
Short name T993
Test name
Test status
Simulation time 37938419926 ps
CPU time 56.9 seconds
Started Jun 29 04:50:15 PM PDT 24
Finished Jun 29 04:51:12 PM PDT 24
Peak memory 195776 kb
Host smart-5e9a0ccd-4cd6-40b7-97e9-bb526b0bdf1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179688698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.179688698
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.1733386569
Short name T546
Test name
Test status
Simulation time 553162154 ps
CPU time 1.84 seconds
Started Jun 29 04:50:15 PM PDT 24
Finished Jun 29 04:50:18 PM PDT 24
Peak memory 198788 kb
Host smart-3552070e-c632-4aa2-b157-dda0a4f1c164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733386569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.1733386569
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.482446731
Short name T708
Test name
Test status
Simulation time 180981334162 ps
CPU time 826.26 seconds
Started Jun 29 04:50:23 PM PDT 24
Finished Jun 29 05:04:10 PM PDT 24
Peak memory 199960 kb
Host smart-e9b66aca-37a0-4ff5-a829-57b9ec794a4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482446731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.482446731
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.2342440077
Short name T991
Test name
Test status
Simulation time 233695865906 ps
CPU time 711.54 seconds
Started Jun 29 04:50:22 PM PDT 24
Finished Jun 29 05:02:15 PM PDT 24
Peak memory 216468 kb
Host smart-a2d3c526-0d7b-4eac-bf8c-0ab0a87adb6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342440077 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.2342440077
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2562977420
Short name T395
Test name
Test status
Simulation time 2928481479 ps
CPU time 2.03 seconds
Started Jun 29 04:50:18 PM PDT 24
Finished Jun 29 04:50:20 PM PDT 24
Peak memory 198740 kb
Host smart-50c59554-9c00-49fc-ad36-b2d501297e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562977420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2562977420
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.2129120147
Short name T718
Test name
Test status
Simulation time 64377017334 ps
CPU time 25.07 seconds
Started Jun 29 04:50:16 PM PDT 24
Finished Jun 29 04:50:41 PM PDT 24
Peak memory 199720 kb
Host smart-d07209f7-8ec0-4488-a2c5-e3fcd1227c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129120147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2129120147
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3772548130
Short name T498
Test name
Test status
Simulation time 23492706 ps
CPU time 0.57 seconds
Started Jun 29 04:50:22 PM PDT 24
Finished Jun 29 04:50:23 PM PDT 24
Peak memory 195260 kb
Host smart-cbe78598-d1bc-4fb7-834f-8dbdc692e203
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772548130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3772548130
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.3446696592
Short name T441
Test name
Test status
Simulation time 177586611576 ps
CPU time 215.79 seconds
Started Jun 29 04:50:21 PM PDT 24
Finished Jun 29 04:53:57 PM PDT 24
Peak memory 199900 kb
Host smart-63a9e22f-8bec-4c4c-854c-f87eb2b3a498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446696592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.3446696592
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.2648300218
Short name T817
Test name
Test status
Simulation time 118750311559 ps
CPU time 53.57 seconds
Started Jun 29 04:50:24 PM PDT 24
Finished Jun 29 04:51:18 PM PDT 24
Peak memory 199804 kb
Host smart-6a670798-a8f7-4f73-ba5f-7832096b72aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648300218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.2648300218
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.2374424747
Short name T528
Test name
Test status
Simulation time 9971334341 ps
CPU time 7.19 seconds
Started Jun 29 04:50:23 PM PDT 24
Finished Jun 29 04:50:31 PM PDT 24
Peak memory 199920 kb
Host smart-866a712e-5e4c-4460-b3aa-7a7fe3d750bd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374424747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2374424747
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.4271401719
Short name T850
Test name
Test status
Simulation time 155153605650 ps
CPU time 408.52 seconds
Started Jun 29 04:50:23 PM PDT 24
Finished Jun 29 04:57:12 PM PDT 24
Peak memory 199888 kb
Host smart-0c72758d-e419-4006-af15-04d33b78b423
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4271401719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.4271401719
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.3865897753
Short name T954
Test name
Test status
Simulation time 1016656547 ps
CPU time 1.03 seconds
Started Jun 29 04:50:20 PM PDT 24
Finished Jun 29 04:50:21 PM PDT 24
Peak memory 195424 kb
Host smart-5e13ea5a-4846-4610-b196-0fe816cb03e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865897753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.3865897753
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_perf.1206804651
Short name T836
Test name
Test status
Simulation time 1620141510 ps
CPU time 14.88 seconds
Started Jun 29 04:50:21 PM PDT 24
Finished Jun 29 04:50:36 PM PDT 24
Peak memory 199856 kb
Host smart-3df74739-a7e6-4111-bdc9-521c017bed84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1206804651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.1206804651
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2452528416
Short name T527
Test name
Test status
Simulation time 6035931850 ps
CPU time 28.71 seconds
Started Jun 29 04:50:25 PM PDT 24
Finished Jun 29 04:50:54 PM PDT 24
Peak memory 199124 kb
Host smart-066ce123-e6cd-4cdf-a48a-1cb51384954f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2452528416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2452528416
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.4005165218
Short name T463
Test name
Test status
Simulation time 87224556671 ps
CPU time 39.08 seconds
Started Jun 29 04:50:21 PM PDT 24
Finished Jun 29 04:51:01 PM PDT 24
Peak memory 199812 kb
Host smart-5075be01-0560-49ab-8b90-9fc708f2b4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005165218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.4005165218
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1798214618
Short name T399
Test name
Test status
Simulation time 3708021413 ps
CPU time 2.02 seconds
Started Jun 29 04:50:20 PM PDT 24
Finished Jun 29 04:50:23 PM PDT 24
Peak memory 196472 kb
Host smart-880df8f2-0aa6-47a1-9c96-36f4c77ff9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798214618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1798214618
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3254201681
Short name T308
Test name
Test status
Simulation time 699068400 ps
CPU time 2.37 seconds
Started Jun 29 04:50:22 PM PDT 24
Finished Jun 29 04:50:25 PM PDT 24
Peak memory 198884 kb
Host smart-f1a971e1-9035-4ad0-90ef-bc3c8eff6dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254201681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3254201681
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.2230161410
Short name T668
Test name
Test status
Simulation time 238826073045 ps
CPU time 838.75 seconds
Started Jun 29 04:50:22 PM PDT 24
Finished Jun 29 05:04:21 PM PDT 24
Peak memory 216492 kb
Host smart-6e71c2b4-0027-49dc-b737-d8cbfdbb3a1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230161410 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.2230161410
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1745663791
Short name T734
Test name
Test status
Simulation time 2094597653 ps
CPU time 2.54 seconds
Started Jun 29 04:50:22 PM PDT 24
Finished Jun 29 04:50:25 PM PDT 24
Peak memory 199516 kb
Host smart-873fd101-2a0f-4a36-8724-cc34db6fe1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745663791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1745663791
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.859085279
Short name T968
Test name
Test status
Simulation time 59389651087 ps
CPU time 49.05 seconds
Started Jun 29 04:50:22 PM PDT 24
Finished Jun 29 04:51:12 PM PDT 24
Peak memory 199984 kb
Host smart-e8552cf6-e220-4ee7-8d04-080fad134c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859085279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.859085279
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.554903974
Short name T415
Test name
Test status
Simulation time 12925815 ps
CPU time 0.57 seconds
Started Jun 29 04:50:31 PM PDT 24
Finished Jun 29 04:50:32 PM PDT 24
Peak memory 195588 kb
Host smart-37705ee0-811c-4008-8a97-ea146affb009
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554903974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.554903974
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.3280101586
Short name T581
Test name
Test status
Simulation time 41132956436 ps
CPU time 73.02 seconds
Started Jun 29 04:50:22 PM PDT 24
Finished Jun 29 04:51:36 PM PDT 24
Peak memory 199932 kb
Host smart-d66fb117-636b-4f2b-ba55-eee45f72dbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280101586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3280101586
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.487376484
Short name T982
Test name
Test status
Simulation time 94024731012 ps
CPU time 51.23 seconds
Started Jun 29 04:50:23 PM PDT 24
Finished Jun 29 04:51:15 PM PDT 24
Peak memory 199924 kb
Host smart-431b35dd-9f5e-4f88-9db5-33bdc97b6c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487376484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.487376484
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.3621565727
Short name T232
Test name
Test status
Simulation time 32494260609 ps
CPU time 50.01 seconds
Started Jun 29 04:50:23 PM PDT 24
Finished Jun 29 04:51:14 PM PDT 24
Peak memory 199988 kb
Host smart-9bcf75ec-5052-42df-95fe-97adf3970c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621565727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3621565727
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.2356952689
Short name T317
Test name
Test status
Simulation time 64196992731 ps
CPU time 20.21 seconds
Started Jun 29 04:50:21 PM PDT 24
Finished Jun 29 04:50:42 PM PDT 24
Peak memory 199980 kb
Host smart-d5369baa-91be-4d6a-a072-bc6b125fdec3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356952689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.2356952689
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.4247931120
Short name T605
Test name
Test status
Simulation time 109312213050 ps
CPU time 705.11 seconds
Started Jun 29 04:50:30 PM PDT 24
Finished Jun 29 05:02:15 PM PDT 24
Peak memory 199900 kb
Host smart-d02fba51-bd7f-4f9c-99fb-d52829b6ba3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4247931120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.4247931120
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.3159442419
Short name T895
Test name
Test status
Simulation time 1360575031 ps
CPU time 2.58 seconds
Started Jun 29 04:50:29 PM PDT 24
Finished Jun 29 04:50:32 PM PDT 24
Peak memory 196088 kb
Host smart-09a09197-2a84-4910-860b-d93bf52b2d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159442419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.3159442419
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_perf.1482928
Short name T459
Test name
Test status
Simulation time 9992528578 ps
CPU time 212.67 seconds
Started Jun 29 04:50:33 PM PDT 24
Finished Jun 29 04:54:06 PM PDT 24
Peak memory 199932 kb
Host smart-ea6f21af-9ab5-4ac0-aef2-fb64f01627d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1482928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1482928
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.426096822
Short name T588
Test name
Test status
Simulation time 3155501322 ps
CPU time 27.93 seconds
Started Jun 29 04:50:23 PM PDT 24
Finished Jun 29 04:50:51 PM PDT 24
Peak memory 198972 kb
Host smart-612d007d-651f-44b2-9199-e0dd63d43727
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=426096822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.426096822
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.4251127605
Short name T1025
Test name
Test status
Simulation time 48311111750 ps
CPU time 20.29 seconds
Started Jun 29 04:50:23 PM PDT 24
Finished Jun 29 04:50:44 PM PDT 24
Peak memory 199840 kb
Host smart-64e6b606-fc69-477d-9765-16d2dd7ba156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251127605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.4251127605
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.4285943211
Short name T837
Test name
Test status
Simulation time 677723410 ps
CPU time 0.89 seconds
Started Jun 29 04:50:21 PM PDT 24
Finished Jun 29 04:50:22 PM PDT 24
Peak memory 195416 kb
Host smart-0f4f186e-0a7e-4791-80ea-5ba46e4a5478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285943211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.4285943211
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.902166881
Short name T530
Test name
Test status
Simulation time 5284370991 ps
CPU time 15.62 seconds
Started Jun 29 04:50:20 PM PDT 24
Finished Jun 29 04:50:36 PM PDT 24
Peak memory 199672 kb
Host smart-33a2e2bb-2348-4e8c-9f80-9ddcaac0fef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902166881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.902166881
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2194383268
Short name T584
Test name
Test status
Simulation time 1997997610 ps
CPU time 1.91 seconds
Started Jun 29 04:50:30 PM PDT 24
Finished Jun 29 04:50:32 PM PDT 24
Peak memory 198308 kb
Host smart-f145d6d5-bd77-4ea4-91af-0f3eaace19f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194383268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2194383268
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2284330990
Short name T50
Test name
Test status
Simulation time 122279742514 ps
CPU time 77.62 seconds
Started Jun 29 04:50:22 PM PDT 24
Finished Jun 29 04:51:40 PM PDT 24
Peak memory 199936 kb
Host smart-db150b5e-8336-443b-9796-588d359c05cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284330990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2284330990
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.2194620349
Short name T114
Test name
Test status
Simulation time 42612435 ps
CPU time 0.56 seconds
Started Jun 29 04:48:01 PM PDT 24
Finished Jun 29 04:48:03 PM PDT 24
Peak memory 195220 kb
Host smart-df926c76-1c40-4b2f-9111-6db1b95c4787
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194620349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2194620349
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1942762206
Short name T566
Test name
Test status
Simulation time 14662186784 ps
CPU time 23.47 seconds
Started Jun 29 04:47:59 PM PDT 24
Finished Jun 29 04:48:23 PM PDT 24
Peak memory 199992 kb
Host smart-04d5d635-3434-422a-81bb-f2923ca1abcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942762206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1942762206
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.4101988479
Short name T576
Test name
Test status
Simulation time 144713217693 ps
CPU time 154.02 seconds
Started Jun 29 04:48:08 PM PDT 24
Finished Jun 29 04:50:43 PM PDT 24
Peak memory 199908 kb
Host smart-0f6e1239-4a12-4776-a142-f9081f54b268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101988479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.4101988479
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.993526641
Short name T350
Test name
Test status
Simulation time 16685544478 ps
CPU time 26.92 seconds
Started Jun 29 04:47:59 PM PDT 24
Finished Jun 29 04:48:26 PM PDT 24
Peak memory 199780 kb
Host smart-47cde192-afe0-4054-a7e7-5b91f0233cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993526641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.993526641
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.3726029012
Short name T4
Test name
Test status
Simulation time 17497820029 ps
CPU time 31.24 seconds
Started Jun 29 04:47:55 PM PDT 24
Finished Jun 29 04:48:27 PM PDT 24
Peak memory 199956 kb
Host smart-59f325e4-4dd0-4662-be19-5e8404e8b069
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726029012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3726029012
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.3747531866
Short name T485
Test name
Test status
Simulation time 95516827691 ps
CPU time 746.08 seconds
Started Jun 29 04:48:02 PM PDT 24
Finished Jun 29 05:00:29 PM PDT 24
Peak memory 199912 kb
Host smart-cf22557a-4e8c-46f9-b578-0044687d10c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3747531866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.3747531866
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.531303209
Short name T941
Test name
Test status
Simulation time 864935353 ps
CPU time 1.25 seconds
Started Jun 29 04:48:12 PM PDT 24
Finished Jun 29 04:48:14 PM PDT 24
Peak memory 196948 kb
Host smart-47d41d56-7aa6-46ff-b47b-93ea0674d096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531303209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.531303209
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_perf.1356501253
Short name T261
Test name
Test status
Simulation time 32042969163 ps
CPU time 119.95 seconds
Started Jun 29 04:48:08 PM PDT 24
Finished Jun 29 04:50:08 PM PDT 24
Peak memory 199944 kb
Host smart-66b7c797-c864-4690-80ef-4e0c3b4e97fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1356501253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.1356501253
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.2893948260
Short name T365
Test name
Test status
Simulation time 3488028326 ps
CPU time 27.44 seconds
Started Jun 29 04:48:06 PM PDT 24
Finished Jun 29 04:48:34 PM PDT 24
Peak memory 197928 kb
Host smart-cb30bc67-2faf-462a-9f9e-fd12d5b38ada
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2893948260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2893948260
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.3892057245
Short name T1068
Test name
Test status
Simulation time 119025483574 ps
CPU time 29.4 seconds
Started Jun 29 04:47:54 PM PDT 24
Finished Jun 29 04:48:23 PM PDT 24
Peak memory 198188 kb
Host smart-e85d795a-1d9f-4193-922a-d16b08305435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892057245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3892057245
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.2112917859
Short name T920
Test name
Test status
Simulation time 1947646541 ps
CPU time 2.17 seconds
Started Jun 29 04:48:11 PM PDT 24
Finished Jun 29 04:48:14 PM PDT 24
Peak memory 195464 kb
Host smart-357078ef-cbe2-4357-a265-7a5ffc29c4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112917859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.2112917859
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.2639257755
Short name T1011
Test name
Test status
Simulation time 298513170 ps
CPU time 1.15 seconds
Started Jun 29 04:47:54 PM PDT 24
Finished Jun 29 04:47:55 PM PDT 24
Peak memory 198752 kb
Host smart-8f4ad3f8-9da3-4a0b-a943-223386092f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639257755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2639257755
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.2739709115
Short name T852
Test name
Test status
Simulation time 13074737601 ps
CPU time 175.84 seconds
Started Jun 29 04:47:59 PM PDT 24
Finished Jun 29 04:50:55 PM PDT 24
Peak memory 215504 kb
Host smart-3db63ad1-18f0-4818-ab56-85137dc0f832
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739709115 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.2739709115
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.2941720911
Short name T573
Test name
Test status
Simulation time 6550380530 ps
CPU time 20.72 seconds
Started Jun 29 04:47:57 PM PDT 24
Finished Jun 29 04:48:18 PM PDT 24
Peak memory 199840 kb
Host smart-1b004787-838d-4b0a-8abc-5e5e19168b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941720911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.2941720911
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.1380103118
Short name T844
Test name
Test status
Simulation time 50519234971 ps
CPU time 80.97 seconds
Started Jun 29 04:48:00 PM PDT 24
Finished Jun 29 04:49:21 PM PDT 24
Peak memory 200208 kb
Host smart-493cc447-b496-4b44-83ea-236ef5a3271d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380103118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1380103118
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.2461576865
Short name T935
Test name
Test status
Simulation time 165126525098 ps
CPU time 288.21 seconds
Started Jun 29 04:50:28 PM PDT 24
Finished Jun 29 04:55:17 PM PDT 24
Peak memory 199984 kb
Host smart-7102e10a-5ec9-4fd1-99fd-95bc43f1f50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461576865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2461576865
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.1735038907
Short name T939
Test name
Test status
Simulation time 9178604871 ps
CPU time 13.63 seconds
Started Jun 29 04:50:30 PM PDT 24
Finished Jun 29 04:50:44 PM PDT 24
Peak memory 199844 kb
Host smart-81fd497f-26be-4c85-8ecc-01d04e6855ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735038907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1735038907
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.1242778753
Short name T106
Test name
Test status
Simulation time 251471546060 ps
CPU time 244.13 seconds
Started Jun 29 04:50:29 PM PDT 24
Finished Jun 29 04:54:34 PM PDT 24
Peak memory 210056 kb
Host smart-f60b1351-f407-4137-ac7f-cc452c18f46d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242778753 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.1242778753
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.157734438
Short name T899
Test name
Test status
Simulation time 70098171344 ps
CPU time 98.54 seconds
Started Jun 29 04:50:29 PM PDT 24
Finished Jun 29 04:52:08 PM PDT 24
Peak memory 199928 kb
Host smart-25f00a99-b9bc-4bd8-b420-0454c4a432b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157734438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.157734438
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.642468272
Short name T963
Test name
Test status
Simulation time 90062751496 ps
CPU time 400.77 seconds
Started Jun 29 04:50:30 PM PDT 24
Finished Jun 29 04:57:12 PM PDT 24
Peak memory 216412 kb
Host smart-317ac9d9-7bc9-4c22-9062-2e97a8f18744
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642468272 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.642468272
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.1066819406
Short name T35
Test name
Test status
Simulation time 38500558795 ps
CPU time 555.61 seconds
Started Jun 29 04:50:31 PM PDT 24
Finished Jun 29 04:59:47 PM PDT 24
Peak memory 216308 kb
Host smart-ef7ab045-94c2-4cd3-a641-0bc0ac748e2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066819406 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.1066819406
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3225723805
Short name T504
Test name
Test status
Simulation time 50055526590 ps
CPU time 82.24 seconds
Started Jun 29 04:50:32 PM PDT 24
Finished Jun 29 04:51:55 PM PDT 24
Peak memory 200012 kb
Host smart-fde5e9ab-3859-4ce6-a6c5-3279c8a0e280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225723805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3225723805
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.4183711767
Short name T965
Test name
Test status
Simulation time 27826186161 ps
CPU time 623.22 seconds
Started Jun 29 04:50:29 PM PDT 24
Finished Jun 29 05:00:52 PM PDT 24
Peak memory 215540 kb
Host smart-d5d2e47f-30b4-4fd3-b32a-a8282ab72e2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183711767 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.4183711767
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.2791195339
Short name T818
Test name
Test status
Simulation time 25378041206 ps
CPU time 39.04 seconds
Started Jun 29 04:50:30 PM PDT 24
Finished Jun 29 04:51:09 PM PDT 24
Peak memory 199840 kb
Host smart-8eab1821-747e-4ae8-9d45-ff225e4ca3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791195339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.2791195339
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.2795630115
Short name T634
Test name
Test status
Simulation time 63342922501 ps
CPU time 201.8 seconds
Started Jun 29 04:50:28 PM PDT 24
Finished Jun 29 04:53:51 PM PDT 24
Peak memory 209416 kb
Host smart-be71ba9e-6e86-4821-911f-1fcb94c1a4c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795630115 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.2795630115
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.3272391106
Short name T2
Test name
Test status
Simulation time 67231213763 ps
CPU time 55.5 seconds
Started Jun 29 04:50:31 PM PDT 24
Finished Jun 29 04:51:27 PM PDT 24
Peak memory 199928 kb
Host smart-4e208b45-5411-406f-b843-3df1f12a39af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272391106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3272391106
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.2246974453
Short name T805
Test name
Test status
Simulation time 156741730589 ps
CPU time 69.07 seconds
Started Jun 29 04:50:29 PM PDT 24
Finished Jun 29 04:51:38 PM PDT 24
Peak memory 199952 kb
Host smart-dc31a698-3159-4558-8cea-b43f1d487288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246974453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.2246974453
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.4198477441
Short name T878
Test name
Test status
Simulation time 28502780 ps
CPU time 0.6 seconds
Started Jun 29 04:48:03 PM PDT 24
Finished Jun 29 04:48:05 PM PDT 24
Peak memory 195588 kb
Host smart-332ec52e-4c62-4d69-9c98-d16b4769459d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198477441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.4198477441
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.3552506229
Short name T604
Test name
Test status
Simulation time 16963330768 ps
CPU time 8.82 seconds
Started Jun 29 04:47:56 PM PDT 24
Finished Jun 29 04:48:05 PM PDT 24
Peak memory 199988 kb
Host smart-baa80acd-6cf1-4de3-ab1d-285fab9ea470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552506229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3552506229
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.2157367910
Short name T868
Test name
Test status
Simulation time 148898990306 ps
CPU time 23.94 seconds
Started Jun 29 04:48:04 PM PDT 24
Finished Jun 29 04:48:29 PM PDT 24
Peak memory 199924 kb
Host smart-ec93df96-44fd-4157-91f8-675dc16c6ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157367910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2157367910
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.2572009200
Short name T828
Test name
Test status
Simulation time 106027873608 ps
CPU time 81.17 seconds
Started Jun 29 04:48:01 PM PDT 24
Finished Jun 29 04:49:22 PM PDT 24
Peak memory 199896 kb
Host smart-87bab8f8-db95-40ef-afcd-c44d5461faa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572009200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.2572009200
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.2854430407
Short name T39
Test name
Test status
Simulation time 204214160957 ps
CPU time 42.47 seconds
Started Jun 29 04:47:58 PM PDT 24
Finished Jun 29 04:48:41 PM PDT 24
Peak memory 199920 kb
Host smart-aa930fe2-5585-46a3-a5d2-c00b4e970333
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854430407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2854430407
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.2421956560
Short name T480
Test name
Test status
Simulation time 109817735660 ps
CPU time 513.03 seconds
Started Jun 29 04:48:00 PM PDT 24
Finished Jun 29 04:56:34 PM PDT 24
Peak memory 199948 kb
Host smart-454a2796-e095-431f-b10a-7c663693dae5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2421956560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2421956560
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.1692291158
Short name T869
Test name
Test status
Simulation time 5575949032 ps
CPU time 2.92 seconds
Started Jun 29 04:48:21 PM PDT 24
Finished Jun 29 04:48:24 PM PDT 24
Peak memory 198552 kb
Host smart-c64af95c-65df-4826-aa32-8e206c370185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692291158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1692291158
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_perf.141474225
Short name T1007
Test name
Test status
Simulation time 15607838803 ps
CPU time 761.31 seconds
Started Jun 29 04:47:55 PM PDT 24
Finished Jun 29 05:00:37 PM PDT 24
Peak memory 199936 kb
Host smart-a484039a-5f48-4aa3-9edc-6e4ac772a9dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=141474225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.141474225
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.2770700933
Short name T697
Test name
Test status
Simulation time 1905929928 ps
CPU time 4.91 seconds
Started Jun 29 04:48:00 PM PDT 24
Finished Jun 29 04:48:06 PM PDT 24
Peak memory 198104 kb
Host smart-c3157218-e209-4293-9722-67c7ef08d5a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2770700933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.2770700933
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.2978154559
Short name T555
Test name
Test status
Simulation time 51346516096 ps
CPU time 48.23 seconds
Started Jun 29 04:48:02 PM PDT 24
Finished Jun 29 04:48:51 PM PDT 24
Peak memory 199960 kb
Host smart-acfa173f-23b8-44e8-baf0-0f4bf97f9776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978154559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2978154559
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.720303904
Short name T255
Test name
Test status
Simulation time 4074046886 ps
CPU time 2.02 seconds
Started Jun 29 04:48:54 PM PDT 24
Finished Jun 29 04:48:57 PM PDT 24
Peak memory 195180 kb
Host smart-555bad04-91e8-4276-ad8e-9a445aec7e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720303904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.720303904
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.820872893
Short name T838
Test name
Test status
Simulation time 295937698 ps
CPU time 1.42 seconds
Started Jun 29 04:48:10 PM PDT 24
Finished Jun 29 04:48:12 PM PDT 24
Peak memory 198700 kb
Host smart-6cace083-6884-462e-a5c0-55b56aa9bec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820872893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.820872893
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.2545734356
Short name T479
Test name
Test status
Simulation time 27937884652 ps
CPU time 373.52 seconds
Started Jun 29 04:48:01 PM PDT 24
Finished Jun 29 04:54:15 PM PDT 24
Peak memory 199968 kb
Host smart-8bce2eb1-9d03-47e6-8e34-d220feff42bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545734356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2545734356
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.4160153434
Short name T506
Test name
Test status
Simulation time 72515191555 ps
CPU time 672.6 seconds
Started Jun 29 04:48:03 PM PDT 24
Finished Jun 29 04:59:17 PM PDT 24
Peak memory 216516 kb
Host smart-7382dc92-8505-4c06-b70e-d5a10e1f1183
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160153434 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.4160153434
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.1525376566
Short name T907
Test name
Test status
Simulation time 2002401269 ps
CPU time 2.34 seconds
Started Jun 29 04:48:04 PM PDT 24
Finished Jun 29 04:48:07 PM PDT 24
Peak memory 198668 kb
Host smart-9e742d32-5ff3-4187-8d1e-26a394133e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525376566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.1525376566
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.1433720412
Short name T884
Test name
Test status
Simulation time 46047360338 ps
CPU time 16.18 seconds
Started Jun 29 04:48:06 PM PDT 24
Finished Jun 29 04:48:22 PM PDT 24
Peak memory 199848 kb
Host smart-31c08b7e-4e5a-4edb-ae36-b635ddc455ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433720412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1433720412
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.3202019507
Short name T544
Test name
Test status
Simulation time 127622467174 ps
CPU time 167.73 seconds
Started Jun 29 04:50:45 PM PDT 24
Finished Jun 29 04:53:33 PM PDT 24
Peak memory 199972 kb
Host smart-0e075ce7-7573-41d1-b5b9-1c5dd5722eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202019507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.3202019507
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.701548757
Short name T608
Test name
Test status
Simulation time 37075057233 ps
CPU time 52.21 seconds
Started Jun 29 04:50:38 PM PDT 24
Finished Jun 29 04:51:31 PM PDT 24
Peak memory 199644 kb
Host smart-14138380-6dea-44c9-b4f3-7bd10e706cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701548757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.701548757
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2507486455
Short name T61
Test name
Test status
Simulation time 311619204752 ps
CPU time 1134.75 seconds
Started Jun 29 04:50:42 PM PDT 24
Finished Jun 29 05:09:38 PM PDT 24
Peak memory 216552 kb
Host smart-95ce60e5-d849-418c-bc28-ecaf0b86bf92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507486455 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2507486455
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.211662928
Short name T979
Test name
Test status
Simulation time 85152425488 ps
CPU time 32.88 seconds
Started Jun 29 04:50:35 PM PDT 24
Finished Jun 29 04:51:08 PM PDT 24
Peak memory 199984 kb
Host smart-748a5feb-e73a-42a2-a0c1-a5a95f781b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211662928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.211662928
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.2068202106
Short name T249
Test name
Test status
Simulation time 340659195659 ps
CPU time 1069.08 seconds
Started Jun 29 04:50:36 PM PDT 24
Finished Jun 29 05:08:25 PM PDT 24
Peak memory 216580 kb
Host smart-428c6f99-de15-41e3-a674-1b9a9e8789ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068202106 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.2068202106
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.2174099618
Short name T157
Test name
Test status
Simulation time 48749669743 ps
CPU time 18.45 seconds
Started Jun 29 04:50:38 PM PDT 24
Finished Jun 29 04:50:57 PM PDT 24
Peak memory 200012 kb
Host smart-0a8eb257-597c-406d-b541-73c798b290ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174099618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2174099618
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.98777580
Short name T966
Test name
Test status
Simulation time 63006283378 ps
CPU time 62.44 seconds
Started Jun 29 04:50:37 PM PDT 24
Finished Jun 29 04:51:39 PM PDT 24
Peak memory 199928 kb
Host smart-6329db30-9fae-41e6-add1-93f8f82cdcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98777580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.98777580
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.3379809393
Short name T543
Test name
Test status
Simulation time 34557775635 ps
CPU time 102.67 seconds
Started Jun 29 04:50:37 PM PDT 24
Finished Jun 29 04:52:20 PM PDT 24
Peak memory 208304 kb
Host smart-1e28e7c6-a6bc-4916-9b11-fb61917d717a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379809393 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.3379809393
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.4276259068
Short name T766
Test name
Test status
Simulation time 37923999349 ps
CPU time 40.06 seconds
Started Jun 29 04:50:43 PM PDT 24
Finished Jun 29 04:51:24 PM PDT 24
Peak memory 199924 kb
Host smart-b1847112-04f9-42e8-8de6-5022fa1810f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276259068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.4276259068
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.3739639495
Short name T208
Test name
Test status
Simulation time 27926865617 ps
CPU time 64.12 seconds
Started Jun 29 04:50:39 PM PDT 24
Finished Jun 29 04:51:43 PM PDT 24
Peak memory 199952 kb
Host smart-2a7f01dd-0c46-4bf8-963a-94eabf80375d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739639495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3739639495
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.319876539
Short name T64
Test name
Test status
Simulation time 294635908393 ps
CPU time 754.06 seconds
Started Jun 29 04:50:37 PM PDT 24
Finished Jun 29 05:03:11 PM PDT 24
Peak memory 216492 kb
Host smart-48bc1829-936c-4ffa-9636-226da5a8bf80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319876539 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.319876539
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.3668336643
Short name T330
Test name
Test status
Simulation time 200592051251 ps
CPU time 49.78 seconds
Started Jun 29 04:50:36 PM PDT 24
Finished Jun 29 04:51:26 PM PDT 24
Peak memory 199924 kb
Host smart-12062711-9fe3-4896-ada8-d0bff9caff4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668336643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3668336643
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.675303248
Short name T886
Test name
Test status
Simulation time 75034034415 ps
CPU time 205 seconds
Started Jun 29 04:50:36 PM PDT 24
Finished Jun 29 04:54:01 PM PDT 24
Peak memory 208068 kb
Host smart-211be538-1e21-45ef-ad5a-3cd71467f762
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675303248 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.675303248
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2353159464
Short name T116
Test name
Test status
Simulation time 59876166459 ps
CPU time 58.63 seconds
Started Jun 29 04:50:39 PM PDT 24
Finished Jun 29 04:51:38 PM PDT 24
Peak memory 199904 kb
Host smart-33be40ee-8389-48c4-bc65-b2cd0d6b86d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353159464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2353159464
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.3857214181
Short name T243
Test name
Test status
Simulation time 168592274734 ps
CPU time 59.88 seconds
Started Jun 29 04:50:41 PM PDT 24
Finished Jun 29 04:51:41 PM PDT 24
Peak memory 200012 kb
Host smart-983918ca-cd2d-4ee2-a639-0d5412a057d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857214181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3857214181
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.1812282457
Short name T909
Test name
Test status
Simulation time 17880062998 ps
CPU time 220.18 seconds
Started Jun 29 04:50:48 PM PDT 24
Finished Jun 29 04:54:29 PM PDT 24
Peak memory 208332 kb
Host smart-7b2dd48c-ca71-4fec-a48a-850e38e3f58b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812282457 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.1812282457
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.1572855951
Short name T990
Test name
Test status
Simulation time 38440085 ps
CPU time 0.54 seconds
Started Jun 29 04:48:02 PM PDT 24
Finished Jun 29 04:48:04 PM PDT 24
Peak memory 194960 kb
Host smart-177c9289-e4cf-4982-999a-af2adf8d8247
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572855951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1572855951
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3360361777
Short name T929
Test name
Test status
Simulation time 143151510060 ps
CPU time 73.85 seconds
Started Jun 29 04:48:05 PM PDT 24
Finished Jun 29 04:49:20 PM PDT 24
Peak memory 199912 kb
Host smart-0e6f9fea-d1bd-4643-805b-ffcc0b20d6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360361777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3360361777
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.972217570
Short name T427
Test name
Test status
Simulation time 49807272861 ps
CPU time 16.23 seconds
Started Jun 29 04:48:05 PM PDT 24
Finished Jun 29 04:48:22 PM PDT 24
Peak memory 199996 kb
Host smart-76eebff0-dd09-4db7-903e-76ca837378b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972217570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.972217570
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.2924721158
Short name T1005
Test name
Test status
Simulation time 16192574448 ps
CPU time 6.36 seconds
Started Jun 29 04:48:00 PM PDT 24
Finished Jun 29 04:48:07 PM PDT 24
Peak memory 197516 kb
Host smart-37c595f3-b373-4495-9594-aa3b4e542adb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924721158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.2924721158
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.3525329945
Short name T765
Test name
Test status
Simulation time 74541249753 ps
CPU time 198.29 seconds
Started Jun 29 04:48:13 PM PDT 24
Finished Jun 29 04:51:32 PM PDT 24
Peak memory 199800 kb
Host smart-df3e3ae3-03ae-47cc-aa99-d8d39010f2c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3525329945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3525329945
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.1583496174
Short name T472
Test name
Test status
Simulation time 2273747365 ps
CPU time 5.16 seconds
Started Jun 29 04:48:05 PM PDT 24
Finished Jun 29 04:48:11 PM PDT 24
Peak memory 198836 kb
Host smart-48dcc75e-bc78-43e3-bb9f-82305263fb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583496174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1583496174
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.4246102148
Short name T1092
Test name
Test status
Simulation time 23620113629 ps
CPU time 20.66 seconds
Started Jun 29 04:48:00 PM PDT 24
Finished Jun 29 04:48:21 PM PDT 24
Peak memory 199992 kb
Host smart-b86ad2a6-5b9e-4599-91f6-df951c8687bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246102148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.4246102148
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.3667962024
Short name T442
Test name
Test status
Simulation time 6369501037 ps
CPU time 89.55 seconds
Started Jun 29 04:48:01 PM PDT 24
Finished Jun 29 04:49:31 PM PDT 24
Peak memory 199820 kb
Host smart-314a3e19-958d-4dc6-9da9-ccab526475ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3667962024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3667962024
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.351646844
Short name T407
Test name
Test status
Simulation time 3850854189 ps
CPU time 7.4 seconds
Started Jun 29 04:48:07 PM PDT 24
Finished Jun 29 04:48:15 PM PDT 24
Peak memory 198164 kb
Host smart-802ec557-16e0-4990-9c07-affedcc64114
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=351646844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.351646844
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.3763077880
Short name T845
Test name
Test status
Simulation time 178202056856 ps
CPU time 30.49 seconds
Started Jun 29 04:48:05 PM PDT 24
Finished Jun 29 04:48:36 PM PDT 24
Peak memory 199340 kb
Host smart-844db85f-2f90-41ff-8399-635d4626fe00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763077880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3763077880
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1511276319
Short name T1022
Test name
Test status
Simulation time 43148990462 ps
CPU time 7.57 seconds
Started Jun 29 04:48:10 PM PDT 24
Finished Jun 29 04:48:19 PM PDT 24
Peak memory 196228 kb
Host smart-7c340afe-2935-452e-b246-f53334b4b012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511276319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1511276319
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.451112534
Short name T1003
Test name
Test status
Simulation time 940454807 ps
CPU time 2.31 seconds
Started Jun 29 04:47:55 PM PDT 24
Finished Jun 29 04:47:59 PM PDT 24
Peak memory 198408 kb
Host smart-975b6bac-a0e9-47ee-befd-9b7fe870ecf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451112534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.451112534
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.51750033
Short name T1072
Test name
Test status
Simulation time 19180442692 ps
CPU time 336.23 seconds
Started Jun 29 04:48:08 PM PDT 24
Finished Jun 29 04:53:45 PM PDT 24
Peak memory 199788 kb
Host smart-86b7478e-483e-4e22-92c4-79738bccb7b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51750033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.51750033
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.1821458426
Short name T379
Test name
Test status
Simulation time 989906626 ps
CPU time 1.23 seconds
Started Jun 29 04:48:00 PM PDT 24
Finished Jun 29 04:48:02 PM PDT 24
Peak memory 198344 kb
Host smart-a49276bf-8d90-4dbc-8798-bc53ea34f0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821458426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1821458426
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.1506782705
Short name T487
Test name
Test status
Simulation time 62060180403 ps
CPU time 35.11 seconds
Started Jun 29 04:47:58 PM PDT 24
Finished Jun 29 04:48:34 PM PDT 24
Peak memory 199980 kb
Host smart-b839d829-a11d-40dc-a4f4-ae51f490b638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506782705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1506782705
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.429288207
Short name T238
Test name
Test status
Simulation time 57189290055 ps
CPU time 27.95 seconds
Started Jun 29 04:50:38 PM PDT 24
Finished Jun 29 04:51:06 PM PDT 24
Peak memory 199964 kb
Host smart-d7de9c49-386b-43f5-bbda-8417a4b64364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429288207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.429288207
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.3604320491
Short name T336
Test name
Test status
Simulation time 57541000026 ps
CPU time 731.01 seconds
Started Jun 29 04:50:48 PM PDT 24
Finished Jun 29 05:03:00 PM PDT 24
Peak memory 216492 kb
Host smart-b5e70b19-a119-4ec0-95db-1b585b39897e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604320491 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.3604320491
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2933444915
Short name T626
Test name
Test status
Simulation time 48335490592 ps
CPU time 74.48 seconds
Started Jun 29 04:50:45 PM PDT 24
Finished Jun 29 04:52:00 PM PDT 24
Peak memory 199928 kb
Host smart-4851140e-5588-4bcd-b338-fd18ccdef29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933444915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2933444915
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1903054442
Short name T109
Test name
Test status
Simulation time 66158311319 ps
CPU time 287.06 seconds
Started Jun 29 04:50:37 PM PDT 24
Finished Jun 29 04:55:25 PM PDT 24
Peak memory 216456 kb
Host smart-62388eba-b5f4-45f1-9aa6-22b83f26c73d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903054442 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1903054442
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.3654454126
Short name T444
Test name
Test status
Simulation time 39363345173 ps
CPU time 27.95 seconds
Started Jun 29 04:50:44 PM PDT 24
Finished Jun 29 04:51:13 PM PDT 24
Peak memory 199808 kb
Host smart-5e1c8d5a-99aa-48b2-b6ba-cf351aeb9a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654454126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3654454126
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.241610528
Short name T701
Test name
Test status
Simulation time 27599066419 ps
CPU time 45.08 seconds
Started Jun 29 04:50:36 PM PDT 24
Finished Jun 29 04:51:22 PM PDT 24
Peak memory 199944 kb
Host smart-91fa5c29-7034-4bdd-8843-c18ed2fde54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241610528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.241610528
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.3465419733
Short name T351
Test name
Test status
Simulation time 146250000064 ps
CPU time 56.62 seconds
Started Jun 29 04:50:42 PM PDT 24
Finished Jun 29 04:51:39 PM PDT 24
Peak memory 199844 kb
Host smart-25ae9d51-fe7f-414d-8ba6-de3b6d81c74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465419733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3465419733
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.156167203
Short name T183
Test name
Test status
Simulation time 7208094056 ps
CPU time 88.13 seconds
Started Jun 29 04:50:42 PM PDT 24
Finished Jun 29 04:52:11 PM PDT 24
Peak memory 216128 kb
Host smart-851ea6dd-8142-4178-bb46-0191f07bb184
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156167203 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.156167203
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.3979336446
Short name T266
Test name
Test status
Simulation time 51143600471 ps
CPU time 85.52 seconds
Started Jun 29 04:50:43 PM PDT 24
Finished Jun 29 04:52:09 PM PDT 24
Peak memory 199920 kb
Host smart-9b18c55e-0577-457b-b6ea-aea1829c1730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979336446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3979336446
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.57242433
Short name T33
Test name
Test status
Simulation time 81906954717 ps
CPU time 241.65 seconds
Started Jun 29 04:50:42 PM PDT 24
Finished Jun 29 04:54:44 PM PDT 24
Peak memory 216420 kb
Host smart-8b6a0bcc-e6c5-4ee3-820e-09bdbd3cfd11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57242433 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.57242433
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.3432541542
Short name T1023
Test name
Test status
Simulation time 25919470778 ps
CPU time 45.13 seconds
Started Jun 29 04:50:45 PM PDT 24
Finished Jun 29 04:51:31 PM PDT 24
Peak memory 199888 kb
Host smart-659756b7-6a6e-4047-a9aa-56bc8c898e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432541542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.3432541542
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.2901431901
Short name T908
Test name
Test status
Simulation time 83722041 ps
CPU time 0.54 seconds
Started Jun 29 04:48:07 PM PDT 24
Finished Jun 29 04:48:08 PM PDT 24
Peak memory 195304 kb
Host smart-7dc0a783-6426-4658-b348-e8c699b7c1f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901431901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2901431901
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.557910686
Short name T36
Test name
Test status
Simulation time 25271604276 ps
CPU time 36.98 seconds
Started Jun 29 04:48:03 PM PDT 24
Finished Jun 29 04:48:41 PM PDT 24
Peak memory 199932 kb
Host smart-5cda99aa-cc90-4358-9953-a5c544434a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557910686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.557910686
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.4049896329
Short name T267
Test name
Test status
Simulation time 76520142153 ps
CPU time 144.22 seconds
Started Jun 29 04:48:08 PM PDT 24
Finished Jun 29 04:50:33 PM PDT 24
Peak memory 199948 kb
Host smart-048dfd9b-f1d8-4bbf-b114-27c143ff5909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049896329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.4049896329
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.2588749776
Short name T613
Test name
Test status
Simulation time 51706909242 ps
CPU time 12.56 seconds
Started Jun 29 04:48:12 PM PDT 24
Finished Jun 29 04:48:26 PM PDT 24
Peak memory 199760 kb
Host smart-44c5b790-6975-4fbe-b368-dee0aff70252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588749776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2588749776
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.2921071513
Short name T384
Test name
Test status
Simulation time 34883326735 ps
CPU time 11.21 seconds
Started Jun 29 04:48:08 PM PDT 24
Finished Jun 29 04:48:20 PM PDT 24
Peak memory 198700 kb
Host smart-4ef072dc-44c7-4195-bb7e-1249dd6025e8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921071513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2921071513
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.45516777
Short name T1042
Test name
Test status
Simulation time 140700419702 ps
CPU time 343.58 seconds
Started Jun 29 04:48:02 PM PDT 24
Finished Jun 29 04:53:47 PM PDT 24
Peak memory 199916 kb
Host smart-432fb321-53cb-433e-a421-cdad32d258b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=45516777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.45516777
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.2800098619
Short name T745
Test name
Test status
Simulation time 2513793155 ps
CPU time 1.47 seconds
Started Jun 29 04:48:06 PM PDT 24
Finished Jun 29 04:48:08 PM PDT 24
Peak memory 195944 kb
Host smart-e5e504ab-d337-42a6-86cc-38d450fc7d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800098619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2800098619
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_perf.2779723371
Short name T806
Test name
Test status
Simulation time 25640632882 ps
CPU time 1209.95 seconds
Started Jun 29 04:48:11 PM PDT 24
Finished Jun 29 05:08:22 PM PDT 24
Peak memory 199844 kb
Host smart-26f74c36-c5cc-4c1d-9a71-a953e0f18f2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2779723371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2779723371
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.3338117856
Short name T640
Test name
Test status
Simulation time 2012250451 ps
CPU time 9.2 seconds
Started Jun 29 04:48:07 PM PDT 24
Finished Jun 29 04:48:16 PM PDT 24
Peak memory 198116 kb
Host smart-f2fef3aa-5ed9-45d8-946a-6595543f3075
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3338117856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3338117856
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.3282463759
Short name T174
Test name
Test status
Simulation time 104959558670 ps
CPU time 52.6 seconds
Started Jun 29 04:48:10 PM PDT 24
Finished Jun 29 04:49:04 PM PDT 24
Peak memory 199920 kb
Host smart-8a8a3c41-a9ac-41cd-89a2-c37ca2395c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282463759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.3282463759
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.1779865795
Short name T448
Test name
Test status
Simulation time 4465317223 ps
CPU time 7.16 seconds
Started Jun 29 04:48:00 PM PDT 24
Finished Jun 29 04:48:07 PM PDT 24
Peak memory 196036 kb
Host smart-f1a42ea8-5e68-4172-819e-39b121ac0ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779865795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1779865795
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.2644746652
Short name T937
Test name
Test status
Simulation time 985202004 ps
CPU time 2.39 seconds
Started Jun 29 04:48:08 PM PDT 24
Finished Jun 29 04:48:11 PM PDT 24
Peak memory 199704 kb
Host smart-b2e17675-e338-4930-b013-39f26190e5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644746652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.2644746652
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.1756515946
Short name T223
Test name
Test status
Simulation time 72322925080 ps
CPU time 1320.5 seconds
Started Jun 29 04:48:10 PM PDT 24
Finished Jun 29 05:10:11 PM PDT 24
Peak memory 224756 kb
Host smart-22270052-46f0-402f-91a0-1a742f687d15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756515946 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.1756515946
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.1850118524
Short name T410
Test name
Test status
Simulation time 7196746401 ps
CPU time 20.71 seconds
Started Jun 29 04:47:57 PM PDT 24
Finished Jun 29 04:48:18 PM PDT 24
Peak memory 199880 kb
Host smart-cdf4d81b-96ba-48d5-b9e8-734bec65b500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850118524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.1850118524
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.2404512425
Short name T957
Test name
Test status
Simulation time 55560197238 ps
CPU time 90.54 seconds
Started Jun 29 04:48:11 PM PDT 24
Finished Jun 29 04:49:42 PM PDT 24
Peak memory 199980 kb
Host smart-7bbf43ad-9c04-4114-ad58-d7b3a47aace3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404512425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2404512425
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.854569443
Short name T1077
Test name
Test status
Simulation time 86889697364 ps
CPU time 93.36 seconds
Started Jun 29 04:50:49 PM PDT 24
Finished Jun 29 04:52:23 PM PDT 24
Peak memory 199952 kb
Host smart-e1d06320-6a7a-463c-bf07-9b00a43356e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854569443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.854569443
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.2219017959
Short name T235
Test name
Test status
Simulation time 90932502899 ps
CPU time 1217.98 seconds
Started Jun 29 04:50:45 PM PDT 24
Finished Jun 29 05:11:04 PM PDT 24
Peak memory 216436 kb
Host smart-84c979ad-a424-4696-9f9e-0a0d1e3e11f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219017959 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.2219017959
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.1933492765
Short name T51
Test name
Test status
Simulation time 68412582604 ps
CPU time 28.1 seconds
Started Jun 29 04:50:43 PM PDT 24
Finished Jun 29 04:51:12 PM PDT 24
Peak memory 199904 kb
Host smart-4515ae0e-540a-49b2-bfb0-e250d8fd8373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933492765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1933492765
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.3180799056
Short name T831
Test name
Test status
Simulation time 9349219820 ps
CPU time 8.03 seconds
Started Jun 29 04:50:44 PM PDT 24
Finished Jun 29 04:50:52 PM PDT 24
Peak memory 199688 kb
Host smart-ab747697-cc5b-4a06-9145-65d2b4f48a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180799056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3180799056
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.2901347606
Short name T185
Test name
Test status
Simulation time 291145082341 ps
CPU time 292.73 seconds
Started Jun 29 04:50:46 PM PDT 24
Finished Jun 29 04:55:39 PM PDT 24
Peak memory 216556 kb
Host smart-a0e5fe92-4012-42aa-803c-8fc78f5c7270
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901347606 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.2901347606
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.2628288437
Short name T237
Test name
Test status
Simulation time 9803602412 ps
CPU time 18.42 seconds
Started Jun 29 04:50:42 PM PDT 24
Finished Jun 29 04:51:01 PM PDT 24
Peak memory 199924 kb
Host smart-9f551b60-4a59-48b2-8c58-11a1f5a3ccdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628288437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2628288437
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.408516979
Short name T614
Test name
Test status
Simulation time 28566762466 ps
CPU time 259.22 seconds
Started Jun 29 04:50:43 PM PDT 24
Finished Jun 29 04:55:03 PM PDT 24
Peak memory 208260 kb
Host smart-d7898ef9-52bc-4088-8549-eb64e27cb7fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408516979 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.408516979
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3511530380
Short name T560
Test name
Test status
Simulation time 86788386269 ps
CPU time 23.61 seconds
Started Jun 29 04:50:51 PM PDT 24
Finished Jun 29 04:51:15 PM PDT 24
Peak memory 199900 kb
Host smart-64b2f328-6eba-4a5d-8a31-2d0ba036cbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511530380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3511530380
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.2822633751
Short name T1054
Test name
Test status
Simulation time 53883632894 ps
CPU time 989.56 seconds
Started Jun 29 04:50:43 PM PDT 24
Finished Jun 29 05:07:14 PM PDT 24
Peak memory 216516 kb
Host smart-49110f85-f536-4a14-ae8c-a15eac66e018
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822633751 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.2822633751
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.2910593749
Short name T216
Test name
Test status
Simulation time 110337306038 ps
CPU time 155.09 seconds
Started Jun 29 04:50:45 PM PDT 24
Finished Jun 29 04:53:21 PM PDT 24
Peak memory 199988 kb
Host smart-f606efb9-b32e-4836-b5e1-a3408eec4e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910593749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2910593749
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.2518039437
Short name T191
Test name
Test status
Simulation time 107590086861 ps
CPU time 43.34 seconds
Started Jun 29 04:50:44 PM PDT 24
Finished Jun 29 04:51:28 PM PDT 24
Peak memory 199928 kb
Host smart-467d8676-2336-4d10-828b-aa4897568a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518039437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2518039437
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.813317142
Short name T641
Test name
Test status
Simulation time 20638543583 ps
CPU time 236.56 seconds
Started Jun 29 04:50:44 PM PDT 24
Finished Jun 29 04:54:41 PM PDT 24
Peak memory 216552 kb
Host smart-caa47c7e-849b-44eb-a85e-1bd564e7bf7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813317142 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.813317142
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.1277439755
Short name T337
Test name
Test status
Simulation time 46869320003 ps
CPU time 540.87 seconds
Started Jun 29 04:50:50 PM PDT 24
Finished Jun 29 04:59:51 PM PDT 24
Peak memory 212676 kb
Host smart-46502601-8e20-4f1b-866c-43d67a90b875
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277439755 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1277439755
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.850890387
Short name T168
Test name
Test status
Simulation time 104209311064 ps
CPU time 39.63 seconds
Started Jun 29 04:50:48 PM PDT 24
Finished Jun 29 04:51:28 PM PDT 24
Peak memory 199988 kb
Host smart-f4c5f5cd-7002-4b1f-a470-7a9f30ccdbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850890387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.850890387
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.1652368040
Short name T946
Test name
Test status
Simulation time 55553208127 ps
CPU time 401.69 seconds
Started Jun 29 04:50:45 PM PDT 24
Finished Jun 29 04:57:27 PM PDT 24
Peak memory 215664 kb
Host smart-b1b331a7-e198-4ebf-b274-714b7919279d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652368040 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.1652368040
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.175431885
Short name T169
Test name
Test status
Simulation time 172257981788 ps
CPU time 237.1 seconds
Started Jun 29 04:50:44 PM PDT 24
Finished Jun 29 04:54:41 PM PDT 24
Peak memory 199900 kb
Host smart-4655d812-0494-40ef-805a-320e5ae9267d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175431885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.175431885
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.706025562
Short name T63
Test name
Test status
Simulation time 107812599290 ps
CPU time 1012.33 seconds
Started Jun 29 04:50:45 PM PDT 24
Finished Jun 29 05:07:38 PM PDT 24
Peak memory 224612 kb
Host smart-ad2ced53-f91a-4ed2-8950-2221f52d8dc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706025562 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.706025562
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.539131233
Short name T727
Test name
Test status
Simulation time 22117991 ps
CPU time 0.55 seconds
Started Jun 29 04:48:16 PM PDT 24
Finished Jun 29 04:48:18 PM PDT 24
Peak memory 195256 kb
Host smart-fadbb9ca-8b12-43e9-808d-c80d0fa50033
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539131233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.539131233
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.4128543563
Short name T145
Test name
Test status
Simulation time 21559563388 ps
CPU time 18.49 seconds
Started Jun 29 04:48:05 PM PDT 24
Finished Jun 29 04:48:24 PM PDT 24
Peak memory 199936 kb
Host smart-eeb044c5-bbbd-4fd7-89f3-094b8efddb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128543563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.4128543563
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.2653757888
Short name T996
Test name
Test status
Simulation time 21820376830 ps
CPU time 37.38 seconds
Started Jun 29 04:47:54 PM PDT 24
Finished Jun 29 04:48:32 PM PDT 24
Peak memory 199900 kb
Host smart-8b8d1291-0e32-4259-9b88-10eaf0c51240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653757888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2653757888
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.203073974
Short name T196
Test name
Test status
Simulation time 25407840848 ps
CPU time 40.64 seconds
Started Jun 29 04:48:01 PM PDT 24
Finished Jun 29 04:48:42 PM PDT 24
Peak memory 199976 kb
Host smart-b0778fd0-c5a4-4e61-be25-67ba9902b5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203073974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.203073974
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.976138848
Short name T798
Test name
Test status
Simulation time 274391417695 ps
CPU time 351.59 seconds
Started Jun 29 04:48:02 PM PDT 24
Finished Jun 29 04:53:55 PM PDT 24
Peak memory 197356 kb
Host smart-f3958742-f02e-49bb-8fe4-6402d5e16864
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976138848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.976138848
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.1331901299
Short name T924
Test name
Test status
Simulation time 116690168381 ps
CPU time 563.54 seconds
Started Jun 29 04:48:10 PM PDT 24
Finished Jun 29 04:57:34 PM PDT 24
Peak memory 199972 kb
Host smart-ae0b2914-22f6-466b-b057-2147f726e933
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1331901299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1331901299
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.2755064288
Short name T790
Test name
Test status
Simulation time 6580804420 ps
CPU time 12.51 seconds
Started Jun 29 04:48:07 PM PDT 24
Finished Jun 29 04:48:20 PM PDT 24
Peak memory 199976 kb
Host smart-5181f884-d14a-4e79-8d61-d2ddfe02aace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755064288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2755064288
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_perf.3648092791
Short name T522
Test name
Test status
Simulation time 7071976828 ps
CPU time 357.04 seconds
Started Jun 29 04:48:03 PM PDT 24
Finished Jun 29 04:54:01 PM PDT 24
Peak memory 199944 kb
Host smart-a68a3e16-2256-4233-8c69-9a9cd876cfdd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3648092791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3648092791
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.1378070393
Short name T812
Test name
Test status
Simulation time 2444554558 ps
CPU time 19.55 seconds
Started Jun 29 04:48:00 PM PDT 24
Finished Jun 29 04:48:20 PM PDT 24
Peak memory 199484 kb
Host smart-f3df3f94-3e99-4997-ac1b-36e863e91ea2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1378070393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1378070393
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.1526418974
Short name T139
Test name
Test status
Simulation time 27220108404 ps
CPU time 47.61 seconds
Started Jun 29 04:48:09 PM PDT 24
Finished Jun 29 04:48:57 PM PDT 24
Peak memory 199924 kb
Host smart-4edae828-37bd-41be-828f-32533599eb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526418974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.1526418974
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.2630631207
Short name T447
Test name
Test status
Simulation time 49831967101 ps
CPU time 21.86 seconds
Started Jun 29 04:48:12 PM PDT 24
Finished Jun 29 04:48:35 PM PDT 24
Peak memory 195700 kb
Host smart-39140314-08ae-45f3-8811-7d7eefe218c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630631207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2630631207
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.3946397504
Short name T446
Test name
Test status
Simulation time 693144431 ps
CPU time 2.45 seconds
Started Jun 29 04:48:24 PM PDT 24
Finished Jun 29 04:48:27 PM PDT 24
Peak memory 198656 kb
Host smart-a9ee24f1-ec2a-4494-bdf7-26a548ecaf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946397504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3946397504
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.1673781449
Short name T977
Test name
Test status
Simulation time 87913512072 ps
CPU time 79.24 seconds
Started Jun 29 04:48:05 PM PDT 24
Finished Jun 29 04:49:24 PM PDT 24
Peak memory 199932 kb
Host smart-83d048ae-49b5-4377-9522-cff518f63b4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673781449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.1673781449
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.3190842339
Short name T688
Test name
Test status
Simulation time 907296993 ps
CPU time 4.16 seconds
Started Jun 29 04:48:11 PM PDT 24
Finished Jun 29 04:48:16 PM PDT 24
Peak memory 198288 kb
Host smart-ad3f5806-41b3-4e8b-89d5-02e5d88a8def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190842339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3190842339
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.1633962581
Short name T642
Test name
Test status
Simulation time 63263823722 ps
CPU time 33.07 seconds
Started Jun 29 04:48:17 PM PDT 24
Finished Jun 29 04:48:52 PM PDT 24
Peak memory 199980 kb
Host smart-fc105060-ca8f-4cfb-a852-7cb234699fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633962581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.1633962581
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2700697066
Short name T632
Test name
Test status
Simulation time 29141029350 ps
CPU time 42.34 seconds
Started Jun 29 04:50:48 PM PDT 24
Finished Jun 29 04:51:31 PM PDT 24
Peak memory 199984 kb
Host smart-6312e123-4582-4815-974f-6b0499eac233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700697066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2700697066
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.3320823755
Short name T34
Test name
Test status
Simulation time 304396455814 ps
CPU time 418.29 seconds
Started Jun 29 04:50:45 PM PDT 24
Finished Jun 29 04:57:43 PM PDT 24
Peak memory 216360 kb
Host smart-b47a442d-1215-407d-a82c-90720f502269
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320823755 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.3320823755
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.764491755
Short name T138
Test name
Test status
Simulation time 80785620486 ps
CPU time 25.35 seconds
Started Jun 29 04:50:45 PM PDT 24
Finished Jun 29 04:51:10 PM PDT 24
Peak memory 199952 kb
Host smart-7f5d4c76-f5f8-43e2-b2f0-0d3e5ec93d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764491755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.764491755
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.2498136069
Short name T99
Test name
Test status
Simulation time 98088877247 ps
CPU time 518.05 seconds
Started Jun 29 04:50:44 PM PDT 24
Finished Jun 29 04:59:22 PM PDT 24
Peak memory 216576 kb
Host smart-b49cac95-d60f-4645-87c2-b0bb3f016156
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498136069 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.2498136069
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.941142008
Short name T153
Test name
Test status
Simulation time 34135224535 ps
CPU time 29.69 seconds
Started Jun 29 04:50:50 PM PDT 24
Finished Jun 29 04:51:20 PM PDT 24
Peak memory 199988 kb
Host smart-24c4e392-8521-47ca-a833-51903f0d1d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941142008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.941142008
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.4155043167
Short name T986
Test name
Test status
Simulation time 39127460652 ps
CPU time 66.96 seconds
Started Jun 29 04:50:49 PM PDT 24
Finished Jun 29 04:51:57 PM PDT 24
Peak memory 199948 kb
Host smart-73477e8e-e64b-4dc4-aa9c-0bb8d258b798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155043167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.4155043167
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.3149139903
Short name T1076
Test name
Test status
Simulation time 120917256305 ps
CPU time 322.01 seconds
Started Jun 29 04:50:52 PM PDT 24
Finished Jun 29 04:56:15 PM PDT 24
Peak memory 209148 kb
Host smart-c7e116fb-caf7-4fb5-82ac-47192fdd76ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149139903 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.3149139903
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.2701947021
Short name T1078
Test name
Test status
Simulation time 109539587009 ps
CPU time 44.43 seconds
Started Jun 29 04:50:51 PM PDT 24
Finished Jun 29 04:51:36 PM PDT 24
Peak memory 199900 kb
Host smart-dc7d4c2e-a321-403c-b7ee-8504ad5438ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701947021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2701947021
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.2829761581
Short name T31
Test name
Test status
Simulation time 14631359855 ps
CPU time 78.85 seconds
Started Jun 29 04:50:51 PM PDT 24
Finished Jun 29 04:52:10 PM PDT 24
Peak memory 215320 kb
Host smart-7fe206fd-e172-470e-9f3d-364d05331454
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829761581 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.2829761581
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.2348662635
Short name T148
Test name
Test status
Simulation time 43275034251 ps
CPU time 23.38 seconds
Started Jun 29 04:50:51 PM PDT 24
Finished Jun 29 04:51:15 PM PDT 24
Peak memory 199980 kb
Host smart-b2075297-18b7-45d0-a2df-b86d713774d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348662635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.2348662635
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.1436128313
Short name T627
Test name
Test status
Simulation time 85049602307 ps
CPU time 301.83 seconds
Started Jun 29 04:50:50 PM PDT 24
Finished Jun 29 04:55:52 PM PDT 24
Peak memory 208708 kb
Host smart-3384df07-4bb4-4e9d-92a2-52411c7e3bc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436128313 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.1436128313
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.1400105755
Short name T894
Test name
Test status
Simulation time 69680146520 ps
CPU time 30.78 seconds
Started Jun 29 04:50:52 PM PDT 24
Finished Jun 29 04:51:23 PM PDT 24
Peak memory 199892 kb
Host smart-7b13e8b7-8fb3-4ac2-9f82-ebb03b993f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400105755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.1400105755
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.1342167908
Short name T203
Test name
Test status
Simulation time 75138622669 ps
CPU time 311.43 seconds
Started Jun 29 04:50:50 PM PDT 24
Finished Jun 29 04:56:02 PM PDT 24
Peak memory 216404 kb
Host smart-72366c91-9ffb-4753-a8b6-09fc39975112
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342167908 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1342167908
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.1366035111
Short name T865
Test name
Test status
Simulation time 35022015669 ps
CPU time 25.1 seconds
Started Jun 29 04:50:50 PM PDT 24
Finished Jun 29 04:51:16 PM PDT 24
Peak memory 199432 kb
Host smart-8667dd52-fc2b-4355-b1e1-6ca3071e036a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366035111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1366035111
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.2541386145
Short name T483
Test name
Test status
Simulation time 42397904121 ps
CPU time 30.04 seconds
Started Jun 29 04:50:52 PM PDT 24
Finished Jun 29 04:51:22 PM PDT 24
Peak memory 199952 kb
Host smart-1e829743-7caf-4cee-b405-21ede08ad45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541386145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.2541386145
Directory /workspace/99.uart_fifo_reset/latest
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