Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	96491	1			T1	50		T2	1		T3	603
all_values[1]	96491	1			T1	50		T2	1		T3	603
all_values[2]	96491	1			T1	50		T2	1		T3	603
all_values[3]	96491	1			T1	50		T2	1		T3	603
all_values[4]	96491	1			T1	50		T2	1		T3	603
all_values[5]	96491	1			T1	50		T2	1		T3	603
all_values[6]	96491	1			T1	50		T2	1		T3	603
all_values[7]	96491	1			T1	50		T2	1		T3	603
all_values[8]	96491	1			T1	50		T2	1		T3	603

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

435693

1

T1

240

T2

8

T3

2321

auto[1]

432726

1

T1

210

T2

1

T3

3106

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

797652

1

T1

368

T2

7

T3

5284

auto[1]

70767

1

T1

82

T2

2

T3

143

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	29845	1			T1	5		T3	170		T5	2
all_values[0]	auto[0]	auto[1]	19390	1			T1	10		T2	1		T3	32
all_values[0]	auto[1]	auto[0]	31805	1			T1	5		T3	373		T5	12
all_values[0]	auto[1]	auto[1]	15451	1			T1	30		T3	28		T5	23
all_values[1]	auto[0]	auto[0]	47459	1			T1	14		T3	115		T4	2
all_values[1]	auto[0]	auto[1]	1504	1			T9	34		T12	5		T13	4
all_values[1]	auto[1]	auto[0]	46373	1			T1	36		T2	1		T3	475
all_values[1]	auto[1]	auto[1]	1155	1			T3	13		T6	1		T9	6
all_values[2]	auto[0]	auto[0]	45728	1			T1	37		T2	1		T3	201
all_values[2]	auto[0]	auto[1]	2239	1			T1	3		T3	6		T4	1
all_values[2]	auto[1]	auto[0]	46491	1			T1	9		T3	387		T5	8
all_values[2]	auto[1]	auto[1]	2033	1			T1	1		T3	9		T6	5
all_values[3]	auto[0]	auto[0]	50095	1			T1	4		T2	1		T3	405
all_values[3]	auto[0]	auto[1]	271	1			T13	1		T14	5		T19	1
all_values[3]	auto[1]	auto[0]	45863	1			T1	46		T3	198		T5	16
all_values[3]	auto[1]	auto[1]	262	1			T12	1		T83	1		T175	3
all_values[4]	auto[0]	auto[0]	47380	1			T1	40		T2	1		T3	211
all_values[4]	auto[0]	auto[1]	393	1			T83	1		T15	1		T108	2
all_values[4]	auto[1]	auto[0]	48378	1			T1	10		T3	392		T5	18
all_values[4]	auto[1]	auto[1]	340	1			T9	1		T13	9		T15	3
all_values[5]	auto[0]	auto[0]	48953	1			T1	4		T2	1		T3	518
all_values[5]	auto[0]	auto[1]	154	1			T15	3		T16	1		T17	4
all_values[5]	auto[1]	auto[0]	47226	1			T1	46		T3	85		T5	30
all_values[5]	auto[1]	auto[1]	158	1			T16	3		T17	1		T126	2
all_values[6]	auto[0]	auto[0]	45242	1			T1	39		T2	1		T3	164
all_values[6]	auto[0]	auto[1]	161	1			T16	3		T17	1		T43	2
all_values[6]	auto[1]	auto[0]	50923	1			T1	11		T3	439		T5	9
all_values[6]	auto[1]	auto[1]	165	1			T17	5		T43	4		T126	1
all_values[7]	auto[0]	auto[0]	49122	1			T1	45		T2	1		T3	105
all_values[7]	auto[0]	auto[1]	333	1			T3	2		T13	9		T15	3
all_values[7]	auto[1]	auto[0]	46770	1			T1	5		T3	496		T5	8
all_values[7]	auto[1]	auto[1]	266	1			T9	2		T83	3		T15	1
all_values[8]	auto[0]	auto[0]	33378	1			T1	12		T3	368		T5	11
all_values[8]	auto[0]	auto[1]	14046	1			T1	27		T2	1		T3	24
all_values[8]	auto[1]	auto[0]	36621	1			T3	182		T5	3		T6	7
all_values[8]	auto[1]	auto[1]	12446	1			T1	11		T3	29		T5	1