Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv



Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 13 0 13 100.00
Crosses 22 0 22 100.00


Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dir 2 0 2 100.00 100 1 1 0
cp_rst_pos 11 0 11 100.00 100 1 1 0


Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
uart_reset_cg_cc 22 0 22 100.00 100 1 1 0


Summary for Variable cp_dir

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_dir

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UartTx] 2216 1 T1 3 T2 1 T3 11
auto[UartRx] 2216 1 T1 3 T2 1 T3 11



Summary for Variable cp_rst_pos

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 11 0 11 100.00


User Defined Bins for cp_rst_pos

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 4009 1 T1 6 T2 2 T3 11
values[1] 38 1 T3 1 T20 1 T29 1
values[2] 37 1 T3 2 T9 1 T15 2
values[3] 38 1 T3 2 T19 1 T16 1
values[4] 47 1 T9 1 T19 2 T20 4
values[5] 36 1 T3 1 T9 1 T19 4
values[6] 40 1 T9 1 T14 2 T19 1
values[7] 39 1 T3 1 T9 1 T19 2
values[8] 38 1 T3 1 T9 2 T14 1
values[9] 33 1 T19 1 T16 2 T29 1
values[10] 52 1 T3 2 T9 1 T14 1



Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 22 0 22 100.00


Automatically Generated Cross Bins for uart_reset_cg_cc

Bins
cp_dircp_rst_posCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UartTx] values[0] 2062 1 T1 3 T2 1 T3 8
auto[UartTx] values[1] 11 1 T20 1 T18 1 T36 1
auto[UartTx] values[2] 12 1 T3 1 T9 1 T16 1
auto[UartTx] values[3] 15 1 T19 1 T16 1 T29 1
auto[UartTx] values[4] 15 1 T9 1 T20 1 T29 1
auto[UartTx] values[5] 15 1 T3 1 T19 1 T29 1
auto[UartTx] values[6] 12 1 T9 1 T16 1 T109 1
auto[UartTx] values[7] 18 1 T19 2 T36 1 T46 1
auto[UartTx] values[8] 16 1 T3 1 T14 1 T20 1
auto[UartTx] values[9] 13 1 T16 1 T36 1 T110 1
auto[UartTx] values[10] 19 1 T20 1 T17 1 T109 1
auto[UartRx] values[0] 1947 1 T1 3 T2 1 T3 3
auto[UartRx] values[1] 27 1 T3 1 T29 1 T125 1
auto[UartRx] values[2] 25 1 T3 1 T15 2 T20 1
auto[UartRx] values[3] 23 1 T3 2 T43 1 T126 1
auto[UartRx] values[4] 32 1 T19 2 T20 3 T16 1
auto[UartRx] values[5] 21 1 T9 1 T19 3 T43 1
auto[UartRx] values[6] 28 1 T14 2 T19 1 T18 2
auto[UartRx] values[7] 21 1 T3 1 T9 1 T36 1
auto[UartRx] values[8] 22 1 T9 2 T20 1 T17 1
auto[UartRx] values[9] 20 1 T19 1 T16 1 T29 1
auto[UartRx] values[10] 33 1 T3 2 T9 1 T14 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%