Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1954	1			T2	14		T3	5		T5	2
auto[BaudRate115200]	1499	1			T1	3		T3	7		T5	2
auto[BaudRate230400]	1603	1			T1	2		T3	9		T7	2
auto[BaudRate128Kbps]	1500	1			T1	2		T3	4		T7	2
auto[BaudRate256Kbps]	1712	1			T1	1		T3	5		T4	1
auto[BaudRate1Mbps]	1581	1			T1	1		T3	5		T4	1
auto[BaudRate1p5Mbps]	1083	1			T1	2		T3	7		T5	3

---

Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1093	1			T175	7		T257	5		T28	9
freqs[25]	905	1			T2	14		T84	9		T119	5
freqs[48]	471	1			T83	1		T270	1		T100	8
freqs[50]	225	1			T6	9		T300	7		T275	2
freqs[100]	1239	1			T5	10		T14	14		T15	8

---

Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	151	1			T175	2		T257	2		T28	2
auto[BaudRate9600]	freqs[25]	196	1			T2	14		T84	9		T34	1
auto[BaudRate9600]	freqs[48]	59	1			T100	1		T101	3		T135	1
auto[BaudRate9600]	freqs[50]	28	1			T300	1		T275	1		T309	6
auto[BaudRate9600]	freqs[100]	247	1			T5	2		T14	5		T15	3
auto[BaudRate115200]	freqs[24]	172	1			T28	3		T118	1		T179	2
auto[BaudRate115200]	freqs[25]	101	1			T34	1		T242	2		T238	2
auto[BaudRate115200]	freqs[48]	85	1			T100	1		T101	3		T135	1
auto[BaudRate115200]	freqs[50]	17	1			T300	1		T309	3		T310	1
auto[BaudRate115200]	freqs[100]	152	1			T5	2		T14	2		T15	2
auto[BaudRate230400]	freqs[24]	167	1			T175	1		T257	1		T28	1
auto[BaudRate230400]	freqs[25]	146	1			T119	1		T242	4		T274	1
auto[BaudRate230400]	freqs[48]	76	1			T83	1		T100	3		T169	1
auto[BaudRate230400]	freqs[50]	24	1			T300	1		T73	1		T150	3
auto[BaudRate230400]	freqs[100]	146	1			T15	1		T249	2		T311	3
auto[BaudRate128Kbps]	freqs[24]	170	1			T175	1		T179	1		T312	1
auto[BaudRate128Kbps]	freqs[25]	108	1			T119	2		T34	2		T242	3
auto[BaudRate128Kbps]	freqs[48]	55	1			T270	1		T100	1		T101	1
auto[BaudRate128Kbps]	freqs[50]	17	1			T300	1		T309	6		T313	1
auto[BaudRate128Kbps]	freqs[100]	151	1			T14	2		T35	1		T249	3
auto[BaudRate256Kbps]	freqs[24]	158	1			T257	1		T118	1		T285	2
auto[BaudRate256Kbps]	freqs[25]	149	1			T119	1		T34	1		T238	1
auto[BaudRate256Kbps]	freqs[48]	72	1			T101	2		T135	1		T314	1
auto[BaudRate256Kbps]	freqs[50]	49	1			T6	1		T300	3		T315	4
auto[BaudRate256Kbps]	freqs[100]	187	1			T5	1		T249	2		T311	9
auto[BaudRate1Mbps]	freqs[24]	175	1			T175	3		T257	1		T28	2
auto[BaudRate1Mbps]	freqs[25]	144	1			T119	1		T34	2		T242	1
auto[BaudRate1Mbps]	freqs[48]	62	1			T135	3		T314	2		T169	1
auto[BaudRate1Mbps]	freqs[50]	48	1			T6	4		T275	1		T315	2
auto[BaudRate1Mbps]	freqs[100]	187	1			T5	2		T14	1		T15	1
auto[BaudRate1p5Mbps]	freqs[25]	61	1			T242	1		T274	1		T316	1
auto[BaudRate1p5Mbps]	freqs[48]	62	1			T100	2		T135	1		T314	1
auto[BaudRate1p5Mbps]	freqs[50]	42	1			T6	4		T73	1		T315	3
auto[BaudRate1p5Mbps]	freqs[100]	169	1			T5	3		T14	4		T15	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded