Group : uart_env_pkg::uart_env_cov::rx_break_err_cg
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Group : uart_env_pkg::uart_env_cov::rx_break_err_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_break_err_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group uart_env_pkg::uart_env_cov::rx_break_err_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_break_level 4 0 4 100.00 100 1 1 0


Summary for Variable cp_break_level

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_break_level

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 311 1 T15 3 T16 4 T17 6
all_levels[1] 17 1 T85 1 T312 1 T317 2
all_levels[2] 41 1 T13 2 T18 3 T289 1
all_levels[3] 24 1 T85 1 T43 1 T46 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%