Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	8	122	93.85

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	8	122	93.85	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	28444033	1			T1	950		T2	1		T3	201939
all_levels[1]	180315	1			T1	1		T3	94		T5	1
all_levels[2]	1528	1			T3	2		T7	1		T8	1
all_levels[3]	852	1			T1	1		T3	1		T7	2
all_levels[4]	526	1			T3	1		T5	1		T9	1
all_levels[5]	401	1			T3	1		T7	1		T9	2
all_levels[6]	372	1			T3	2		T7	1		T9	1
all_levels[7]	322	1			T1	2		T7	1		T9	1
all_levels[8]	247	1			T3	1		T8	1		T9	1
all_levels[9]	230	1			T30	2		T15	1		T33	2
all_levels[10]	173	1			T3	1		T9	2		T30	1
all_levels[11]	178	1			T1	1		T28	1		T19	1
all_levels[12]	153	1			T1	1		T3	1		T7	1
all_levels[13]	151	1			T3	5		T14	1		T123	4
all_levels[14]	105	1			T8	1		T12	1		T27	1
all_levels[15]	112	1			T3	3		T35	4		T106	1
all_levels[16]	113	1			T1	1		T30	1		T129	1
all_levels[17]	80	1			T1	2		T30	1		T14	1
all_levels[18]	84	1			T3	1		T9	1		T28	1
all_levels[19]	60	1			T130	1		T20	1		T100	1
all_levels[20]	81	1			T5	3		T30	1		T130	1
all_levels[21]	52	1			T9	1		T14	1		T123	1
all_levels[22]	43	1			T9	1		T20	1		T106	1
all_levels[23]	52	1			T30	1		T35	1		T124	2
all_levels[24]	51	1			T131	1		T123	3		T132	1
all_levels[25]	44	1			T3	1		T28	1		T133	2
all_levels[26]	44	1			T122	1		T133	3		T100	1
all_levels[27]	51	1			T118	1		T134	1		T135	1
all_levels[28]	42	1			T123	1		T124	1		T136	1
all_levels[29]	32	1			T14	1		T137	1		T138	2
all_levels[30]	35	1			T30	1		T19	1		T35	2
all_levels[31]	31	1			T28	3		T123	1		T17	1
all_levels[32]	33	1			T122	1		T123	1		T34	1
all_levels[33]	21	1			T130	2		T19	1		T17	1
all_levels[34]	28	1			T120	1		T139	1		T140	1
all_levels[35]	22	1			T123	1		T44	1		T141	1
all_levels[36]	18	1			T142	5		T74	1		T143	1
all_levels[37]	11	1			T15	1		T110	1		T143	1
all_levels[38]	22	1			T9	1		T107	1		T144	1
all_levels[39]	11	1			T47	1		T145	2		T146	1
all_levels[40]	12	1			T123	1		T34	1		T147	1
all_levels[41]	18	1			T34	1		T148	1		T46	1
all_levels[42]	12	1			T47	1		T70	1		T149	1
all_levels[43]	19	1			T3	1		T9	1		T122	1
all_levels[44]	14	1			T131	1		T19	1		T150	1
all_levels[45]	14	1			T100	1		T151	1		T74	1
all_levels[46]	15	1			T36	1		T152	1		T153	3
all_levels[47]	14	1			T132	1		T154	1		T155	1
all_levels[48]	17	1			T124	1		T156	1		T155	1
all_levels[49]	19	1			T136	1		T140	1		T157	1
all_levels[50]	20	1			T3	1		T126	1		T144	2
all_levels[51]	17	1			T145	1		T158	1		T159	1
all_levels[52]	8	1			T156	1		T160	3		T161	1
all_levels[53]	17	1			T3	1		T28	1		T44	2
all_levels[54]	4	1			T9	1		T12	1		T162	1
all_levels[55]	18	1			T41	1		T126	1		T148	5
all_levels[56]	14	1			T141	1		T145	4		T163	1
all_levels[57]	8	1			T9	2		T19	1		T118	1
all_levels[58]	4	1			T164	1		T165	1		T166	1
all_levels[59]	9	1			T9	1		T167	2		T168	1
all_levels[60]	9	1			T112	2		T169	1		T170	1
all_levels[61]	7	1			T9	1		T122	1		T70	2
all_levels[62]	5	1			T171	1		T172	2		T173	1
all_levels[63]	13	1			T72	1		T174	2		T159	1
all_levels[64]	99	1			T12	2		T14	1		T175	5

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28626974

1

T1

949

T3

202053

T5

38

auto[1]

4191

1

T1

10

T2

1

T3

3

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	8	122	93.85	8

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[33]]	[auto[1]]	0	1	1
[all_levels[37]]	[auto[1]]	0	1	1
[all_levels[39] , all_levels[40]]	[auto[1]]	--	--	2
[all_levels[42]]	[auto[1]]	0	1	1
[all_levels[45]]	[auto[1]]	0	1	1
[all_levels[54]]	[auto[1]]	0	1	1
[all_levels[58]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	28440265	1			T1	940		T3	201938		T5	35
all_levels[0]	auto[1]	3768	1			T1	10		T2	1		T3	1
all_levels[1]	auto[0]	180226	1			T1	1		T3	94		T5	1
all_levels[1]	auto[1]	89	1			T30	1		T12	3		T101	1
all_levels[2]	auto[0]	1509	1			T3	2		T7	1		T8	1
all_levels[2]	auto[1]	19	1			T40	1		T176	1		T177	1
all_levels[3]	auto[0]	826	1			T1	1		T3	1		T7	2
all_levels[3]	auto[1]	26	1			T130	2		T153	2		T178	2
all_levels[4]	auto[0]	502	1			T3	1		T5	1		T9	1
all_levels[4]	auto[1]	24	1			T100	4		T179	2		T180	1
all_levels[5]	auto[0]	391	1			T3	1		T7	1		T9	2
all_levels[5]	auto[1]	10	1			T130	1		T72	1		T181	2
all_levels[6]	auto[0]	360	1			T3	2		T7	1		T9	1
all_levels[6]	auto[1]	12	1			T12	1		T182	1		T183	1
all_levels[7]	auto[0]	303	1			T1	2		T7	1		T9	1
all_levels[7]	auto[1]	19	1			T179	1		T140	2		T184	1
all_levels[8]	auto[0]	240	1			T3	1		T8	1		T9	1
all_levels[8]	auto[1]	7	1			T120	1		T185	1		T186	1
all_levels[9]	auto[0]	222	1			T30	2		T15	1		T33	1
all_levels[9]	auto[1]	8	1			T33	1		T144	1		T187	1
all_levels[10]	auto[0]	159	1			T3	1		T9	2		T30	1
all_levels[10]	auto[1]	14	1			T12	1		T188	1		T187	1
all_levels[11]	auto[0]	168	1			T1	1		T28	1		T19	1
all_levels[11]	auto[1]	10	1			T189	2		T190	1		T191	1
all_levels[12]	auto[0]	145	1			T1	1		T3	1		T7	1
all_levels[12]	auto[1]	8	1			T185	3		T192	2		T193	1
all_levels[13]	auto[0]	134	1			T3	3		T14	1		T123	4
all_levels[13]	auto[1]	17	1			T3	2		T194	1		T143	1
all_levels[14]	auto[0]	100	1			T8	1		T12	1		T27	1
all_levels[14]	auto[1]	5	1			T38	1		T195	2		T196	1
all_levels[15]	auto[0]	105	1			T3	3		T35	4		T106	1
all_levels[15]	auto[1]	7	1			T178	2		T197	1		T198	1
all_levels[16]	auto[0]	108	1			T1	1		T30	1		T129	1
all_levels[16]	auto[1]	5	1			T199	1		T200	1		T201	1
all_levels[17]	auto[0]	74	1			T1	2		T30	1		T14	1
all_levels[17]	auto[1]	6	1			T155	1		T202	3		T203	2
all_levels[18]	auto[0]	78	1			T3	1		T9	1		T28	1
all_levels[18]	auto[1]	6	1			T43	1		T204	1		T168	2
all_levels[19]	auto[0]	56	1			T130	1		T20	1		T100	1
all_levels[19]	auto[1]	4	1			T188	1		T150	1		T205	1
all_levels[20]	auto[0]	71	1			T5	1		T30	1		T130	1
all_levels[20]	auto[1]	10	1			T5	2		T140	1		T206	2
all_levels[21]	auto[0]	49	1			T9	1		T14	1		T123	1
all_levels[21]	auto[1]	3	1			T207	3		-	-		-	-
all_levels[22]	auto[0]	38	1			T9	1		T20	1		T106	1
all_levels[22]	auto[1]	5	1			T152	1		T208	1		T209	1
all_levels[23]	auto[0]	44	1			T30	1		T35	1		T124	1
all_levels[23]	auto[1]	8	1			T124	1		T210	1		T209	1
all_levels[24]	auto[0]	48	1			T131	1		T123	3		T132	1
all_levels[24]	auto[1]	3	1			T211	1		T212	1		T213	1
all_levels[25]	auto[0]	41	1			T3	1		T28	1		T133	1
all_levels[25]	auto[1]	3	1			T133	1		T172	2		-	-
all_levels[26]	auto[0]	40	1			T122	1		T133	1		T100	1
all_levels[26]	auto[1]	4	1			T133	2		T40	2		-	-
all_levels[27]	auto[0]	46	1			T118	1		T134	1		T135	1
all_levels[27]	auto[1]	5	1			T214	2		T162	1		T215	1
all_levels[28]	auto[0]	37	1			T123	1		T124	1		T136	1
all_levels[28]	auto[1]	5	1			T180	2		T216	1		T217	2
all_levels[29]	auto[0]	30	1			T14	1		T137	1		T138	1
all_levels[29]	auto[1]	2	1			T138	1		T218	1		-	-
all_levels[30]	auto[0]	31	1			T30	1		T19	1		T35	2
all_levels[30]	auto[1]	4	1			T110	1		T219	1		T220	1
all_levels[31]	auto[0]	28	1			T28	2		T123	1		T17	1
all_levels[31]	auto[1]	3	1			T28	1		T203	1		T221	1
all_levels[32]	auto[0]	31	1			T122	1		T123	1		T34	1
all_levels[32]	auto[1]	2	1			T222	2		-	-		-	-
all_levels[33]	auto[0]	21	1			T130	2		T19	1		T17	1
all_levels[34]	auto[0]	23	1			T120	1		T139	1		T140	1
all_levels[34]	auto[1]	5	1			T223	4		T224	1		-	-
all_levels[35]	auto[0]	20	1			T123	1		T44	1		T141	1
all_levels[35]	auto[1]	2	1			T225	2		-	-		-	-
all_levels[36]	auto[0]	13	1			T142	1		T74	1		T143	1
all_levels[36]	auto[1]	5	1			T142	4		T226	1		-	-
all_levels[37]	auto[0]	11	1			T15	1		T110	1		T143	1
all_levels[38]	auto[0]	20	1			T9	1		T107	1		T144	1
all_levels[38]	auto[1]	2	1			T227	1		T228	1		-	-
all_levels[39]	auto[0]	11	1			T47	1		T145	2		T146	1
all_levels[40]	auto[0]	12	1			T123	1		T34	1		T147	1
all_levels[41]	auto[0]	16	1			T34	1		T148	1		T46	1
all_levels[41]	auto[1]	2	1			T229	1		T230	1		-	-
all_levels[42]	auto[0]	12	1			T47	1		T70	1		T149	1
all_levels[43]	auto[0]	18	1			T3	1		T9	1		T122	1
all_levels[43]	auto[1]	1	1			T177	1		-	-		-	-
all_levels[44]	auto[0]	13	1			T131	1		T19	1		T150	1
all_levels[44]	auto[1]	1	1			T231	1		-	-		-	-
all_levels[45]	auto[0]	14	1			T100	1		T151	1		T74	1
all_levels[46]	auto[0]	13	1			T36	1		T152	1		T153	1
all_levels[46]	auto[1]	2	1			T153	2		-	-		-	-
all_levels[47]	auto[0]	13	1			T132	1		T154	1		T155	1
all_levels[47]	auto[1]	1	1			T232	1		-	-		-	-
all_levels[48]	auto[0]	16	1			T124	1		T156	1		T155	1
all_levels[48]	auto[1]	1	1			T205	1		-	-		-	-
all_levels[49]	auto[0]	17	1			T136	1		T140	1		T157	1
all_levels[49]	auto[1]	2	1			T197	1		T233	1		-	-
all_levels[50]	auto[0]	18	1			T3	1		T126	1		T144	1
all_levels[50]	auto[1]	2	1			T144	1		T191	1		-	-
all_levels[51]	auto[0]	16	1			T145	1		T158	1		T159	1
all_levels[51]	auto[1]	1	1			T234	1		-	-		-	-
all_levels[52]	auto[0]	6	1			T156	1		T160	1		T161	1
all_levels[52]	auto[1]	2	1			T160	2		-	-		-	-
all_levels[53]	auto[0]	16	1			T3	1		T28	1		T44	1
all_levels[53]	auto[1]	1	1			T44	1		-	-		-	-
all_levels[54]	auto[0]	4	1			T9	1		T12	1		T162	1
all_levels[55]	auto[0]	12	1			T41	1		T126	1		T148	1
all_levels[55]	auto[1]	6	1			T148	4		T186	1		T235	1
all_levels[56]	auto[0]	9	1			T141	1		T145	1		T163	1
all_levels[56]	auto[1]	5	1			T145	3		T228	2		-	-
all_levels[57]	auto[0]	7	1			T9	2		T19	1		T118	1
all_levels[57]	auto[1]	1	1			T151	1		-	-		-	-
all_levels[58]	auto[0]	4	1			T164	1		T165	1		T166	1
all_levels[59]	auto[0]	7	1			T9	1		T167	1		T168	1
all_levels[59]	auto[1]	2	1			T167	1		T236	1		-	-
all_levels[60]	auto[0]	8	1			T112	1		T169	1		T170	1
all_levels[60]	auto[1]	1	1			T112	1		-	-		-	-
all_levels[61]	auto[0]	6	1			T9	1		T122	1		T70	1
all_levels[61]	auto[1]	1	1			T70	1		-	-		-	-
all_levels[62]	auto[0]	4	1			T171	1		T172	1		T173	1
all_levels[62]	auto[1]	1	1			T172	1		-	-		-	-
all_levels[63]	auto[0]	11	1			T72	1		T174	1		T159	1
all_levels[63]	auto[1]	2	1			T174	1		T201	1		-	-
all_levels[64]	auto[0]	78	1			T12	1		T14	1		T175	1
all_levels[64]	auto[1]	21	1			T12	1		T175	4		T41	2