Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	96491	1			T1	50		T2	1		T3	603
all_pins[1]	96491	1			T1	50		T2	1		T3	603
all_pins[2]	96491	1			T1	50		T2	1		T3	603
all_pins[3]	96491	1			T1	50		T2	1		T3	603
all_pins[4]	96491	1			T1	50		T2	1		T3	603
all_pins[5]	96491	1			T1	50		T2	1		T3	603
all_pins[6]	96491	1			T1	50		T2	1		T3	603
all_pins[7]	96491	1			T1	50		T2	1		T3	603
all_pins[8]	96491	1			T1	50		T2	1		T3	603

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	835408	1			T1	407		T2	9		T3	5348
values[0x1]	33011	1			T1	43		T3	79		T5	24
transitions[0x0=>0x1]	27068	1			T1	38		T3	73		T5	24
transitions[0x1=>0x0]	26862	1			T1	37		T3	73		T5	24

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	80962	1			T1	19		T2	1		T3	575
all_pins[0]	values[0x1]	15529	1			T1	31		T3	28		T5	23
all_pins[0]	transitions[0x0=>0x1]	15112	1			T1	31		T3	26		T5	23
all_pins[0]	transitions[0x1=>0x0]	738	1			T3	11		T6	1		T9	6
all_pins[1]	values[0x0]	95336	1			T1	50		T2	1		T3	590
all_pins[1]	values[0x1]	1155	1			T3	13		T6	1		T9	6
all_pins[1]	transitions[0x0=>0x1]	1071	1			T3	13		T6	1		T9	6
all_pins[1]	transitions[0x1=>0x0]	1996	1			T1	1		T3	9		T6	5
all_pins[2]	values[0x0]	94411	1			T1	49		T2	1		T3	594
all_pins[2]	values[0x1]	2080	1			T1	1		T3	9		T6	5
all_pins[2]	transitions[0x0=>0x1]	2034	1			T1	1		T3	9		T6	5
all_pins[2]	transitions[0x1=>0x0]	216	1			T83	1		T175	1		T133	2
all_pins[3]	values[0x0]	96229	1			T1	50		T2	1		T3	603
all_pins[3]	values[0x1]	262	1			T12	1		T83	1		T175	3
all_pins[3]	transitions[0x0=>0x1]	233	1			T12	1		T83	1		T175	3
all_pins[3]	transitions[0x1=>0x0]	311	1			T9	1		T13	9		T15	2
all_pins[4]	values[0x0]	96151	1			T1	50		T2	1		T3	603
all_pins[4]	values[0x1]	340	1			T9	1		T13	9		T15	3
all_pins[4]	transitions[0x0=>0x1]	291	1			T9	1		T13	9		T15	3
all_pins[4]	transitions[0x1=>0x0]	145	1			T16	3		T17	1		T85	1
all_pins[5]	values[0x0]	96297	1			T1	50		T2	1		T3	603
all_pins[5]	values[0x1]	194	1			T16	3		T17	2		T85	2
all_pins[5]	transitions[0x0=>0x1]	147	1			T16	3		T17	1		T85	2
all_pins[5]	transitions[0x1=>0x0]	622	1			T9	2		T27	1		T130	3
all_pins[6]	values[0x0]	95822	1			T1	50		T2	1		T3	603
all_pins[6]	values[0x1]	669	1			T9	2		T27	1		T130	3
all_pins[6]	transitions[0x0=>0x1]	628	1			T9	2		T27	1		T130	3
all_pins[6]	transitions[0x1=>0x0]	225	1			T9	2		T83	3		T15	1
all_pins[7]	values[0x0]	96225	1			T1	50		T2	1		T3	603
all_pins[7]	values[0x1]	266	1			T9	2		T83	3		T15	1
all_pins[7]	transitions[0x0=>0x1]	154	1			T83	3		T125	4		T157	1
all_pins[7]	transitions[0x1=>0x0]	12404	1			T1	11		T3	29		T5	1
all_pins[8]	values[0x0]	83975	1			T1	39		T2	1		T3	574
all_pins[8]	values[0x1]	12516	1			T1	11		T3	29		T5	1
all_pins[8]	transitions[0x0=>0x1]	7398	1			T1	6		T3	25		T5	1
all_pins[8]	transitions[0x1=>0x0]	10205	1			T1	25		T3	24		T5	23