Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	5716740	1			T1	19		T2	1		T3	60
all_levels[1]	1561820	1			T1	8		T3	18797		T6	98
all_levels[2]	210691	1			T1	909		T3	4		T6	87
all_levels[3]	172160	1			T3	4		T6	96		T9	2639
all_levels[4]	165556	1			T3	2		T6	105		T9	1713
all_levels[5]	151456	1			T3	3		T6	93		T9	2415
all_levels[6]	181332	1			T3	3		T6	83		T9	2349
all_levels[7]	311975	1			T3	2		T5	3		T6	90
all_levels[8]	296315	1			T3	7		T6	91		T7	1
all_levels[9]	149435	1			T3	1		T6	89		T9	2470
all_levels[10]	381878	1			T3	1		T6	91		T9	2318
all_levels[11]	158362	1			T3	1		T6	91		T7	2
all_levels[12]	155769	1			T3	6		T6	92		T7	5
all_levels[13]	248082	1			T3	2		T6	83		T9	24513
all_levels[14]	461416	1			T1	1		T3	4		T6	97
all_levels[15]	148567	1			T3	15		T6	82		T9	3108
all_levels[16]	222823	1			T3	3		T5	5		T6	83
all_levels[17]	151888	1			T3	1		T6	96		T7	1
all_levels[18]	151625	1			T1	1		T3	3		T6	86
all_levels[19]	253274	1			T3	5		T6	98		T9	2371
all_levels[20]	382504	1			T3	2		T6	89		T7	3
all_levels[21]	180652	1			T3	6		T6	100		T9	3079
all_levels[22]	150924	1			T1	2		T3	3		T6	86
all_levels[23]	146839	1			T3	1		T6	96		T9	3287
all_levels[24]	197546	1			T3	1		T6	90		T9	2959
all_levels[25]	141680	1			T1	3		T3	1		T6	105
all_levels[26]	601804	1			T3	2		T6	80		T9	3291
all_levels[27]	241937	1			T1	3		T3	1		T6	83
all_levels[28]	143500	1			T3	1		T6	90		T7	5
all_levels[29]	210814	1			T1	2		T3	3		T6	88
all_levels[30]	513782	1			T1	3		T3	2		T6	85
all_levels[31]	544308	1			T1	1		T3	6		T6	2521
all_levels[32]	13923458	1			T1	6		T3	183103		T5	5

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28626974

1

T1

949

T3

202053

T5

38

auto[1]

3938

1

T1

9

T2

1

T3

3

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	5714473	1			T1	14		T3	59		T5	29
all_levels[0]	auto[1]	2267	1			T1	5		T2	1		T3	1
all_levels[1]	auto[0]	1561516	1			T1	4		T3	18797		T6	98
all_levels[1]	auto[1]	304	1			T1	4		T8	7		T12	3
all_levels[2]	auto[0]	210644	1			T1	909		T3	4		T6	87
all_levels[2]	auto[1]	47	1			T40	2		T45	3		T184	1
all_levels[3]	auto[0]	172037	1			T3	4		T6	96		T9	2639
all_levels[3]	auto[1]	123	1			T30	2		T130	2		T106	1
all_levels[4]	auto[0]	165538	1			T3	2		T6	105		T9	1713
all_levels[4]	auto[1]	18	1			T28	3		T148	1		T256	1
all_levels[5]	auto[0]	151426	1			T3	3		T6	93		T9	2415
all_levels[5]	auto[1]	30	1			T133	1		T139	1		T266	1
all_levels[6]	auto[0]	181312	1			T3	3		T6	83		T9	2349
all_levels[6]	auto[1]	20	1			T43	1		T152	1		T313	1
all_levels[7]	auto[0]	311887	1			T3	2		T5	2		T6	90
all_levels[7]	auto[1]	88	1			T5	1		T13	2		T18	2
all_levels[8]	auto[0]	296292	1			T3	5		T6	91		T7	1
all_levels[8]	auto[1]	23	1			T3	2		T14	1		T238	1
all_levels[9]	auto[0]	149412	1			T3	1		T6	89		T9	2470
all_levels[9]	auto[1]	23	1			T30	1		T185	1		T153	2
all_levels[10]	auto[0]	381856	1			T3	1		T6	91		T9	2318
all_levels[10]	auto[1]	22	1			T110	1		T282	1		T318	3
all_levels[11]	auto[0]	158336	1			T3	1		T6	91		T7	2
all_levels[11]	auto[1]	26	1			T120	1		T100	2		T40	1
all_levels[12]	auto[0]	155758	1			T3	6		T6	92		T7	5
all_levels[12]	auto[1]	11	1			T144	1		T186	2		T319	1
all_levels[13]	auto[0]	248059	1			T3	2		T6	83		T9	24513
all_levels[13]	auto[1]	23	1			T101	1		T124	3		T185	2
all_levels[14]	auto[0]	461402	1			T1	1		T3	4		T6	97
all_levels[14]	auto[1]	14	1			T43	1		T316	1		T320	1
all_levels[15]	auto[0]	148455	1			T3	15		T6	82		T9	3108
all_levels[15]	auto[1]	112	1			T13	5		T83	7		T279	8
all_levels[16]	auto[0]	222809	1			T3	3		T5	3		T6	83
all_levels[16]	auto[1]	14	1			T5	2		T238	1		T44	2
all_levels[17]	auto[0]	151875	1			T3	1		T6	96		T7	1
all_levels[17]	auto[1]	13	1			T185	1		T137	1		T265	1
all_levels[18]	auto[0]	151606	1			T1	1		T3	3		T6	86
all_levels[18]	auto[1]	19	1			T143	3		T298	2		T183	1
all_levels[19]	auto[0]	253262	1			T3	5		T6	98		T9	2371
all_levels[19]	auto[1]	12	1			T249	1		T194	1		T171	1
all_levels[20]	auto[0]	382483	1			T3	2		T6	89		T7	3
all_levels[20]	auto[1]	21	1			T30	1		T129	2		T136	1
all_levels[21]	auto[0]	180638	1			T3	6		T6	100		T9	3079
all_levels[21]	auto[1]	14	1			T281	1		T147	3		T200	2
all_levels[22]	auto[0]	150899	1			T1	2		T3	3		T6	86
all_levels[22]	auto[1]	25	1			T72	1		T265	1		T181	1
all_levels[23]	auto[0]	146824	1			T3	1		T6	96		T9	3287
all_levels[23]	auto[1]	15	1			T38	4		T206	1		T132	1
all_levels[24]	auto[0]	197526	1			T3	1		T6	90		T9	2959
all_levels[24]	auto[1]	20	1			T43	1		T45	1		T140	2
all_levels[25]	auto[0]	141653	1			T1	3		T3	1		T6	105
all_levels[25]	auto[1]	27	1			T45	1		T148	1		T195	2
all_levels[26]	auto[0]	601781	1			T3	2		T6	80		T9	3291
all_levels[26]	auto[1]	23	1			T27	4		T245	1		T188	2
all_levels[27]	auto[0]	241915	1			T1	3		T3	1		T6	83
all_levels[27]	auto[1]	22	1			T133	2		T124	1		T251	1
all_levels[28]	auto[0]	143488	1			T3	1		T6	90		T7	4
all_levels[28]	auto[1]	12	1			T7	1		T8	1		T195	2
all_levels[29]	auto[0]	210795	1			T1	2		T3	3		T6	88
all_levels[29]	auto[1]	19	1			T175	2		T189	2		T45	1
all_levels[30]	auto[0]	513759	1			T1	3		T3	2		T6	85
all_levels[30]	auto[1]	23	1			T129	1		T120	2		T261	1
all_levels[31]	auto[0]	544296	1			T1	1		T3	6		T6	2521
all_levels[31]	auto[1]	12	1			T101	1		T16	1		T149	1
all_levels[32]	auto[0]	13922962	1			T1	6		T3	183103		T5	4
all_levels[32]	auto[1]	496	1			T5	1		T6	1		T30	2