Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	661	1			T15	4		T16	4		T17	7
all_values[1]	661	1			T15	4		T16	4		T17	7
all_values[2]	661	1			T15	4		T16	4		T17	7
all_values[3]	661	1			T15	4		T16	4		T17	7
all_values[4]	661	1			T15	4		T16	4		T17	7
all_values[5]	661	1			T15	4		T16	4		T17	7
all_values[6]	661	1			T15	4		T16	4		T17	7
all_values[7]	661	1			T15	4		T16	4		T17	7
all_values[8]	661	1			T15	4		T16	4		T17	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3280

1

T15

19

T16

22

T17

39

auto[1]

2669

1

T15

17

T16

14

T17

24

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1927

1

T15

11

T16

15

T17

20

auto[1]

4022

1

T15

25

T16

21

T17

43

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3506

1

T15

22

T16

24

T17

37

auto[1]

2443

1

T15

14

T16

12

T17

26

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	210	1			T15	3		T16	2		T17	2
all_values[0]	auto[0]	auto[1]	auto[1]	188	1			T16	1		T17	3		T43	3
all_values[0]	auto[1]	auto[0]	auto[1]	149	1			T16	1		T17	1		T43	2
all_values[0]	auto[1]	auto[1]	auto[1]	114	1			T15	1		T17	1		T43	1
all_values[1]	auto[0]	auto[0]	auto[0]	210	1			T16	1		T17	3		T43	1
all_values[1]	auto[0]	auto[1]	auto[0]	170	1			T15	2		T16	1		T17	1
all_values[1]	auto[1]	auto[0]	auto[1]	150	1			T15	1		T17	2		T43	1
all_values[1]	auto[1]	auto[1]	auto[1]	131	1			T15	1		T16	2		T17	1
all_values[2]	auto[0]	auto[0]	auto[0]	169	1			T15	1		T16	3		T17	3
all_values[2]	auto[0]	auto[0]	auto[1]	60	1			T125	3		T46	1		T47	1
all_values[2]	auto[0]	auto[1]	auto[0]	118	1			T16	1		T43	2		T46	2
all_values[2]	auto[0]	auto[1]	auto[1]	52	1			T15	1		T17	1		T43	2
all_values[2]	auto[1]	auto[0]	auto[1]	144	1			T17	2		T126	3		T125	1
all_values[2]	auto[1]	auto[1]	auto[1]	118	1			T15	2		T17	1		T43	2
all_values[3]	auto[0]	auto[0]	auto[0]	164	1			T15	1		T16	1		T17	3
all_values[3]	auto[0]	auto[0]	auto[1]	76	1			T125	1		T110	1		T47	3
all_values[3]	auto[0]	auto[1]	auto[0]	102	1			T15	2		T17	2		T43	2
all_values[3]	auto[0]	auto[1]	auto[1]	64	1			T16	1		T43	1		T126	2
all_values[3]	auto[1]	auto[0]	auto[1]	141	1			T17	1		T43	1		T126	1
all_values[3]	auto[1]	auto[1]	auto[1]	114	1			T15	1		T16	2		T17	1
all_values[4]	auto[0]	auto[0]	auto[0]	148	1			T16	1		T17	1		T126	1
all_values[4]	auto[0]	auto[0]	auto[1]	66	1			T17	1		T126	3		T47	2
all_values[4]	auto[0]	auto[1]	auto[0]	103	1			T16	2		T17	2		T43	3
all_values[4]	auto[0]	auto[1]	auto[1]	65	1			T15	2		T43	1		T125	1
all_values[4]	auto[1]	auto[0]	auto[1]	152	1			T15	1		T16	1		T17	3
all_values[4]	auto[1]	auto[1]	auto[1]	127	1			T15	1		T43	3		T125	2
all_values[5]	auto[0]	auto[0]	auto[0]	139	1			T15	1		T17	1		T43	1
all_values[5]	auto[0]	auto[0]	auto[1]	60	1			T15	1		T16	1		T17	2
all_values[5]	auto[0]	auto[1]	auto[0]	105	1			T125	1		T46	2		T47	1
all_values[5]	auto[0]	auto[1]	auto[1]	70	1			T16	2		T126	1		T47	4
all_values[5]	auto[1]	auto[0]	auto[1]	152	1			T15	2		T17	2		T43	4
all_values[5]	auto[1]	auto[1]	auto[1]	135	1			T16	1		T17	2		T126	2
all_values[6]	auto[0]	auto[0]	auto[0]	135	1			T15	2		T16	1		T126	2
all_values[6]	auto[0]	auto[0]	auto[1]	65	1			T16	1		T17	1		T43	2
all_values[6]	auto[0]	auto[1]	auto[0]	100	1			T15	2		T125	1		T46	1
all_values[6]	auto[0]	auto[1]	auto[1]	73	1			T17	2		T43	2		T110	1
all_values[6]	auto[1]	auto[0]	auto[1]	159	1			T16	2		T17	1		T43	3
all_values[6]	auto[1]	auto[1]	auto[1]	129	1			T17	3		T125	1		T110	2
all_values[7]	auto[0]	auto[0]	auto[0]	147	1			T16	3		T17	4		T43	4
all_values[7]	auto[0]	auto[0]	auto[1]	77	1			T15	1		T17	1		T110	2
all_values[7]	auto[0]	auto[1]	auto[0]	117	1			T16	1		T126	2		T46	2
all_values[7]	auto[0]	auto[1]	auto[1]	58	1			T126	1		T125	1		T46	1
all_values[7]	auto[1]	auto[0]	auto[1]	160	1			T15	2		T17	2		T43	3
all_values[7]	auto[1]	auto[1]	auto[1]	102	1			T15	1		T125	1		T46	2
all_values[8]	auto[0]	auto[0]	auto[1]	189	1			T15	2		T16	1		T17	1
all_values[8]	auto[0]	auto[1]	auto[1]	206	1			T15	1		T17	3		T43	1
all_values[8]	auto[1]	auto[0]	auto[1]	158	1			T15	1		T16	3		T17	2
all_values[8]	auto[1]	auto[1]	auto[1]	108	1			T17	1		T43	1		T126	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal