Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.12 99.10 97.65 100.00 98.38 100.00 99.59


Total test records in report: 1231
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T1039 /workspace/coverage/default/13.uart_rx_start_bit_filter.3554043155 Jun 30 05:07:05 PM PDT 24 Jun 30 05:08:08 PM PDT 24 44425936563 ps
T1040 /workspace/coverage/default/23.uart_stress_all.2561244066 Jun 30 05:07:56 PM PDT 24 Jun 30 05:08:36 PM PDT 24 277107679371 ps
T1041 /workspace/coverage/default/251.uart_fifo_reset.3336137601 Jun 30 05:12:15 PM PDT 24 Jun 30 05:20:05 PM PDT 24 238194748469 ps
T1042 /workspace/coverage/default/17.uart_fifo_reset.820107425 Jun 30 05:07:33 PM PDT 24 Jun 30 05:07:49 PM PDT 24 47571427792 ps
T1043 /workspace/coverage/default/294.uart_fifo_reset.4187943629 Jun 30 05:12:23 PM PDT 24 Jun 30 05:15:09 PM PDT 24 191660364537 ps
T1044 /workspace/coverage/default/28.uart_loopback.4040345259 Jun 30 05:08:25 PM PDT 24 Jun 30 05:08:40 PM PDT 24 5117285006 ps
T1045 /workspace/coverage/default/8.uart_stress_all_with_rand_reset.1283473770 Jun 30 05:06:51 PM PDT 24 Jun 30 05:09:16 PM PDT 24 68697960165 ps
T1046 /workspace/coverage/default/241.uart_fifo_reset.1216030996 Jun 30 05:12:02 PM PDT 24 Jun 30 05:14:42 PM PDT 24 109846059607 ps
T1047 /workspace/coverage/default/48.uart_intr.62327674 Jun 30 05:10:12 PM PDT 24 Jun 30 05:11:07 PM PDT 24 82923287914 ps
T1048 /workspace/coverage/default/46.uart_rx_oversample.976736112 Jun 30 05:10:04 PM PDT 24 Jun 30 05:10:51 PM PDT 24 4339427696 ps
T1049 /workspace/coverage/default/37.uart_rx_parity_err.56817827 Jun 30 05:09:15 PM PDT 24 Jun 30 05:10:23 PM PDT 24 50199393957 ps
T1050 /workspace/coverage/default/2.uart_rx_oversample.759071978 Jun 30 05:06:30 PM PDT 24 Jun 30 05:07:27 PM PDT 24 6066469129 ps
T1051 /workspace/coverage/default/14.uart_tx_ovrd.3874540391 Jun 30 05:07:06 PM PDT 24 Jun 30 05:07:10 PM PDT 24 2103199452 ps
T1052 /workspace/coverage/default/28.uart_alert_test.792838321 Jun 30 05:08:26 PM PDT 24 Jun 30 05:08:27 PM PDT 24 44275028 ps
T1053 /workspace/coverage/default/5.uart_loopback.3767590473 Jun 30 05:06:47 PM PDT 24 Jun 30 05:07:08 PM PDT 24 10823888026 ps
T1054 /workspace/coverage/default/10.uart_rx_parity_err.1746016179 Jun 30 05:06:59 PM PDT 24 Jun 30 05:08:23 PM PDT 24 143827921636 ps
T1055 /workspace/coverage/default/263.uart_fifo_reset.83567221 Jun 30 05:12:14 PM PDT 24 Jun 30 05:12:35 PM PDT 24 74996510944 ps
T1056 /workspace/coverage/default/31.uart_perf.661444814 Jun 30 05:08:43 PM PDT 24 Jun 30 05:21:36 PM PDT 24 14030163419 ps
T1057 /workspace/coverage/default/12.uart_stress_all.2346634297 Jun 30 05:07:06 PM PDT 24 Jun 30 05:07:30 PM PDT 24 52054058196 ps
T1058 /workspace/coverage/default/26.uart_fifo_overflow.376744140 Jun 30 05:08:09 PM PDT 24 Jun 30 05:08:28 PM PDT 24 42844138267 ps
T51 /workspace/coverage/default/14.uart_stress_all_with_rand_reset.1163032798 Jun 30 05:07:22 PM PDT 24 Jun 30 05:11:50 PM PDT 24 151736270654 ps
T1059 /workspace/coverage/default/30.uart_intr.854109088 Jun 30 05:08:33 PM PDT 24 Jun 30 05:08:42 PM PDT 24 18002238592 ps
T1060 /workspace/coverage/default/35.uart_alert_test.2597249444 Jun 30 05:09:04 PM PDT 24 Jun 30 05:09:06 PM PDT 24 13644422 ps
T1061 /workspace/coverage/default/5.uart_rx_start_bit_filter.2769095347 Jun 30 05:06:34 PM PDT 24 Jun 30 05:07:51 PM PDT 24 52289631912 ps
T1062 /workspace/coverage/default/151.uart_fifo_reset.1893496795 Jun 30 05:11:20 PM PDT 24 Jun 30 05:11:40 PM PDT 24 43513129916 ps
T213 /workspace/coverage/default/183.uart_fifo_reset.3435638405 Jun 30 05:11:34 PM PDT 24 Jun 30 05:12:04 PM PDT 24 85963740665 ps
T1063 /workspace/coverage/default/42.uart_alert_test.2614407150 Jun 30 05:09:51 PM PDT 24 Jun 30 05:09:52 PM PDT 24 30886033 ps
T1064 /workspace/coverage/default/13.uart_rx_oversample.1516353057 Jun 30 05:07:06 PM PDT 24 Jun 30 05:07:14 PM PDT 24 2936582497 ps
T1065 /workspace/coverage/default/49.uart_fifo_overflow.4057366051 Jun 30 05:10:18 PM PDT 24 Jun 30 05:12:12 PM PDT 24 75975464580 ps
T1066 /workspace/coverage/default/46.uart_intr.1222203811 Jun 30 05:10:06 PM PDT 24 Jun 30 05:10:22 PM PDT 24 48619736163 ps
T1067 /workspace/coverage/default/139.uart_fifo_reset.4257157610 Jun 30 05:11:12 PM PDT 24 Jun 30 05:11:30 PM PDT 24 23554017261 ps
T1068 /workspace/coverage/default/9.uart_smoke.857491334 Jun 30 05:06:53 PM PDT 24 Jun 30 05:06:55 PM PDT 24 865981428 ps
T1069 /workspace/coverage/default/227.uart_fifo_reset.1794165521 Jun 30 05:11:56 PM PDT 24 Jun 30 05:14:26 PM PDT 24 109668488827 ps
T1070 /workspace/coverage/default/33.uart_smoke.614913768 Jun 30 05:08:49 PM PDT 24 Jun 30 05:08:51 PM PDT 24 467016228 ps
T1071 /workspace/coverage/default/4.uart_rx_oversample.3353181276 Jun 30 05:06:37 PM PDT 24 Jun 30 05:06:53 PM PDT 24 6520095797 ps
T1072 /workspace/coverage/default/35.uart_loopback.122331065 Jun 30 05:09:03 PM PDT 24 Jun 30 05:09:09 PM PDT 24 2517400106 ps
T225 /workspace/coverage/default/16.uart_fifo_reset.3099011651 Jun 30 05:07:29 PM PDT 24 Jun 30 05:07:52 PM PDT 24 12706438355 ps
T1073 /workspace/coverage/default/167.uart_fifo_reset.2337478218 Jun 30 05:11:31 PM PDT 24 Jun 30 05:13:13 PM PDT 24 61222283415 ps
T1074 /workspace/coverage/default/4.uart_fifo_reset.785931342 Jun 30 05:06:38 PM PDT 24 Jun 30 05:07:21 PM PDT 24 30213826480 ps
T1075 /workspace/coverage/default/0.uart_rx_parity_err.2389022672 Jun 30 05:06:20 PM PDT 24 Jun 30 05:07:03 PM PDT 24 25806558542 ps
T1076 /workspace/coverage/default/24.uart_stress_all_with_rand_reset.2065409124 Jun 30 05:08:09 PM PDT 24 Jun 30 05:12:20 PM PDT 24 21310958681 ps
T1077 /workspace/coverage/default/34.uart_perf.2720791963 Jun 30 05:08:57 PM PDT 24 Jun 30 05:24:17 PM PDT 24 17772347622 ps
T1078 /workspace/coverage/default/298.uart_fifo_reset.3169203297 Jun 30 05:12:36 PM PDT 24 Jun 30 05:12:47 PM PDT 24 6426597404 ps
T1079 /workspace/coverage/default/19.uart_perf.1818781929 Jun 30 05:07:41 PM PDT 24 Jun 30 05:09:19 PM PDT 24 6586052211 ps
T1080 /workspace/coverage/default/284.uart_fifo_reset.3381319443 Jun 30 05:12:16 PM PDT 24 Jun 30 05:12:33 PM PDT 24 42919648889 ps
T1081 /workspace/coverage/default/32.uart_rx_oversample.684454074 Jun 30 05:08:43 PM PDT 24 Jun 30 05:08:50 PM PDT 24 3616269190 ps
T1082 /workspace/coverage/default/36.uart_rx_parity_err.1510159501 Jun 30 05:09:02 PM PDT 24 Jun 30 05:09:59 PM PDT 24 35310894647 ps
T1083 /workspace/coverage/default/41.uart_intr.199579072 Jun 30 05:09:34 PM PDT 24 Jun 30 05:09:38 PM PDT 24 8528962752 ps
T1084 /workspace/coverage/default/22.uart_rx_start_bit_filter.1795073510 Jun 30 05:07:51 PM PDT 24 Jun 30 05:07:55 PM PDT 24 1567220523 ps
T1085 /workspace/coverage/default/37.uart_loopback.2796665950 Jun 30 05:09:14 PM PDT 24 Jun 30 05:09:16 PM PDT 24 2756850482 ps
T1086 /workspace/coverage/default/89.uart_fifo_reset.593185613 Jun 30 05:10:51 PM PDT 24 Jun 30 05:11:31 PM PDT 24 51534268017 ps
T1087 /workspace/coverage/default/13.uart_fifo_overflow.1963236657 Jun 30 05:07:05 PM PDT 24 Jun 30 05:07:23 PM PDT 24 20356261154 ps
T1088 /workspace/coverage/default/112.uart_fifo_reset.2914651993 Jun 30 05:11:05 PM PDT 24 Jun 30 05:12:31 PM PDT 24 120418383492 ps
T1089 /workspace/coverage/default/23.uart_rx_start_bit_filter.392935330 Jun 30 05:07:56 PM PDT 24 Jun 30 05:07:58 PM PDT 24 537798368 ps
T1090 /workspace/coverage/default/24.uart_rx_oversample.3111678822 Jun 30 05:07:57 PM PDT 24 Jun 30 05:08:35 PM PDT 24 4926823733 ps
T1091 /workspace/coverage/default/60.uart_fifo_reset.2163681436 Jun 30 05:10:34 PM PDT 24 Jun 30 05:12:40 PM PDT 24 76315700203 ps
T1092 /workspace/coverage/default/31.uart_rx_parity_err.4257554301 Jun 30 05:08:40 PM PDT 24 Jun 30 05:08:56 PM PDT 24 10840736882 ps
T1093 /workspace/coverage/default/39.uart_long_xfer_wo_dly.2435246174 Jun 30 05:09:27 PM PDT 24 Jun 30 05:15:22 PM PDT 24 138845092909 ps
T1094 /workspace/coverage/default/41.uart_rx_parity_err.3964700940 Jun 30 05:09:38 PM PDT 24 Jun 30 05:10:07 PM PDT 24 16302784308 ps
T1095 /workspace/coverage/default/37.uart_fifo_reset.679475867 Jun 30 05:09:12 PM PDT 24 Jun 30 05:09:52 PM PDT 24 94258594671 ps
T1096 /workspace/coverage/default/27.uart_loopback.2771369505 Jun 30 05:08:17 PM PDT 24 Jun 30 05:08:29 PM PDT 24 6794159404 ps
T1097 /workspace/coverage/default/30.uart_rx_start_bit_filter.1562144006 Jun 30 05:08:33 PM PDT 24 Jun 30 05:09:17 PM PDT 24 29908785687 ps
T1098 /workspace/coverage/default/218.uart_fifo_reset.3261908846 Jun 30 05:11:55 PM PDT 24 Jun 30 05:13:07 PM PDT 24 54303047682 ps
T1099 /workspace/coverage/default/3.uart_rx_parity_err.4224298944 Jun 30 05:06:32 PM PDT 24 Jun 30 05:07:55 PM PDT 24 220639281661 ps
T1100 /workspace/coverage/default/33.uart_perf.1838676019 Jun 30 05:08:45 PM PDT 24 Jun 30 05:24:46 PM PDT 24 17337462787 ps
T52 /workspace/coverage/default/36.uart_stress_all_with_rand_reset.3313248953 Jun 30 05:09:13 PM PDT 24 Jun 30 05:21:58 PM PDT 24 234068101955 ps
T53 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3631512700 Jun 30 04:56:02 PM PDT 24 Jun 30 04:56:03 PM PDT 24 18119651 ps
T1101 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2378102358 Jun 30 04:56:06 PM PDT 24 Jun 30 04:56:07 PM PDT 24 99814084 ps
T86 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.4070922274 Jun 30 04:56:21 PM PDT 24 Jun 30 04:56:24 PM PDT 24 351319669 ps
T1102 /workspace/coverage/cover_reg_top/19.uart_tl_errors.579956788 Jun 30 04:56:29 PM PDT 24 Jun 30 04:56:30 PM PDT 24 230533063 ps
T1103 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1250166838 Jun 30 04:56:16 PM PDT 24 Jun 30 04:56:17 PM PDT 24 87818390 ps
T1104 /workspace/coverage/cover_reg_top/11.uart_intr_test.3981126680 Jun 30 04:56:20 PM PDT 24 Jun 30 04:56:21 PM PDT 24 13569366 ps
T1105 /workspace/coverage/cover_reg_top/6.uart_tl_errors.1128367635 Jun 30 04:56:13 PM PDT 24 Jun 30 04:56:17 PM PDT 24 157316043 ps
T1106 /workspace/coverage/cover_reg_top/14.uart_intr_test.474251223 Jun 30 04:56:23 PM PDT 24 Jun 30 04:56:24 PM PDT 24 24408762 ps
T1107 /workspace/coverage/cover_reg_top/18.uart_tl_errors.2972233206 Jun 30 04:56:31 PM PDT 24 Jun 30 04:56:34 PM PDT 24 253072602 ps
T54 /workspace/coverage/cover_reg_top/19.uart_csr_rw.1124480940 Jun 30 04:56:29 PM PDT 24 Jun 30 04:56:30 PM PDT 24 42155915 ps
T1108 /workspace/coverage/cover_reg_top/31.uart_intr_test.702997077 Jun 30 04:56:33 PM PDT 24 Jun 30 04:56:34 PM PDT 24 15568761 ps
T55 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.157514629 Jun 30 04:56:07 PM PDT 24 Jun 30 04:56:08 PM PDT 24 69438784 ps
T1109 /workspace/coverage/cover_reg_top/45.uart_intr_test.4134797636 Jun 30 04:56:33 PM PDT 24 Jun 30 04:56:34 PM PDT 24 44285732 ps
T87 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2271842338 Jun 30 04:56:28 PM PDT 24 Jun 30 04:56:30 PM PDT 24 541408579 ps
T1110 /workspace/coverage/cover_reg_top/16.uart_tl_errors.3102684004 Jun 30 04:56:28 PM PDT 24 Jun 30 04:56:30 PM PDT 24 89301524 ps
T75 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.218050570 Jun 30 04:56:29 PM PDT 24 Jun 30 04:56:31 PM PDT 24 66248966 ps
T76 /workspace/coverage/cover_reg_top/11.uart_csr_rw.33679176 Jun 30 04:56:23 PM PDT 24 Jun 30 04:56:25 PM PDT 24 13739884 ps
T1111 /workspace/coverage/cover_reg_top/43.uart_intr_test.2191392629 Jun 30 04:56:34 PM PDT 24 Jun 30 04:56:35 PM PDT 24 40235527 ps
T1112 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.123349694 Jun 30 04:56:22 PM PDT 24 Jun 30 04:56:24 PM PDT 24 96225852 ps
T1113 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1457654201 Jun 30 04:56:22 PM PDT 24 Jun 30 04:56:24 PM PDT 24 203350778 ps
T1114 /workspace/coverage/cover_reg_top/2.uart_intr_test.2925734186 Jun 30 04:55:58 PM PDT 24 Jun 30 04:55:59 PM PDT 24 14320189 ps
T1115 /workspace/coverage/cover_reg_top/20.uart_intr_test.497004864 Jun 30 04:56:37 PM PDT 24 Jun 30 04:56:38 PM PDT 24 13754520 ps
T1116 /workspace/coverage/cover_reg_top/38.uart_intr_test.3964314777 Jun 30 04:56:34 PM PDT 24 Jun 30 04:56:35 PM PDT 24 25531099 ps
T56 /workspace/coverage/cover_reg_top/18.uart_csr_rw.3178941030 Jun 30 04:56:28 PM PDT 24 Jun 30 04:56:30 PM PDT 24 13771134 ps
T1117 /workspace/coverage/cover_reg_top/16.uart_intr_test.3443138416 Jun 30 04:56:29 PM PDT 24 Jun 30 04:56:31 PM PDT 24 34741477 ps
T1118 /workspace/coverage/cover_reg_top/14.uart_tl_errors.1123791115 Jun 30 04:56:20 PM PDT 24 Jun 30 04:56:22 PM PDT 24 23997263 ps
T88 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2643273975 Jun 30 04:56:25 PM PDT 24 Jun 30 04:56:26 PM PDT 24 594440345 ps
T57 /workspace/coverage/cover_reg_top/0.uart_csr_rw.1535692023 Jun 30 04:55:57 PM PDT 24 Jun 30 04:55:58 PM PDT 24 14899879 ps
T77 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1159104776 Jun 30 04:56:23 PM PDT 24 Jun 30 04:56:24 PM PDT 24 18240980 ps
T1119 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2949512840 Jun 30 04:56:28 PM PDT 24 Jun 30 04:56:29 PM PDT 24 19677221 ps
T1120 /workspace/coverage/cover_reg_top/26.uart_intr_test.4080644366 Jun 30 04:56:36 PM PDT 24 Jun 30 04:56:37 PM PDT 24 15950907 ps
T94 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.4070879790 Jun 30 04:56:00 PM PDT 24 Jun 30 04:56:01 PM PDT 24 78888289 ps
T78 /workspace/coverage/cover_reg_top/9.uart_csr_rw.4034848288 Jun 30 04:56:12 PM PDT 24 Jun 30 04:56:13 PM PDT 24 169445793 ps
T1121 /workspace/coverage/cover_reg_top/12.uart_intr_test.2872250836 Jun 30 04:56:20 PM PDT 24 Jun 30 04:56:21 PM PDT 24 43201823 ps
T89 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3478189974 Jun 30 04:56:11 PM PDT 24 Jun 30 04:56:13 PM PDT 24 396297759 ps
T1122 /workspace/coverage/cover_reg_top/42.uart_intr_test.3817726487 Jun 30 04:56:34 PM PDT 24 Jun 30 04:56:36 PM PDT 24 12758867 ps
T79 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3994205777 Jun 30 04:56:23 PM PDT 24 Jun 30 04:56:24 PM PDT 24 122547665 ps
T1123 /workspace/coverage/cover_reg_top/19.uart_intr_test.3415627057 Jun 30 04:56:29 PM PDT 24 Jun 30 04:56:31 PM PDT 24 44974408 ps
T80 /workspace/coverage/cover_reg_top/17.uart_csr_rw.1052185871 Jun 30 04:56:28 PM PDT 24 Jun 30 04:56:30 PM PDT 24 20391524 ps
T1124 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.78415830 Jun 30 04:56:11 PM PDT 24 Jun 30 04:56:12 PM PDT 24 226678563 ps
T81 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2978718047 Jun 30 04:56:06 PM PDT 24 Jun 30 04:56:07 PM PDT 24 19261755 ps
T1125 /workspace/coverage/cover_reg_top/1.uart_intr_test.1468489993 Jun 30 04:55:58 PM PDT 24 Jun 30 04:55:59 PM PDT 24 53306799 ps
T1126 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.981181292 Jun 30 04:56:20 PM PDT 24 Jun 30 04:56:22 PM PDT 24 17853515 ps
T1127 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2010724145 Jun 30 04:56:08 PM PDT 24 Jun 30 04:56:09 PM PDT 24 54896729 ps
T82 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1186636476 Jun 30 04:56:13 PM PDT 24 Jun 30 04:56:14 PM PDT 24 17662118 ps
T58 /workspace/coverage/cover_reg_top/1.uart_csr_rw.398104553 Jun 30 04:55:59 PM PDT 24 Jun 30 04:56:00 PM PDT 24 42452570 ps
T1128 /workspace/coverage/cover_reg_top/28.uart_intr_test.3091874580 Jun 30 04:56:36 PM PDT 24 Jun 30 04:56:37 PM PDT 24 41801316 ps
T90 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.4276000932 Jun 30 04:56:30 PM PDT 24 Jun 30 04:56:32 PM PDT 24 109086244 ps
T1129 /workspace/coverage/cover_reg_top/3.uart_intr_test.1173023697 Jun 30 04:56:06 PM PDT 24 Jun 30 04:56:07 PM PDT 24 46393249 ps
T64 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3750990265 Jun 30 04:56:05 PM PDT 24 Jun 30 04:56:05 PM PDT 24 71635525 ps
T1130 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3433202435 Jun 30 04:56:06 PM PDT 24 Jun 30 04:56:07 PM PDT 24 43250893 ps
T1131 /workspace/coverage/cover_reg_top/10.uart_tl_errors.3513519646 Jun 30 04:56:15 PM PDT 24 Jun 30 04:56:17 PM PDT 24 32081506 ps
T1132 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2291490545 Jun 30 04:56:22 PM PDT 24 Jun 30 04:56:24 PM PDT 24 15866296 ps
T1133 /workspace/coverage/cover_reg_top/0.uart_tl_errors.372079537 Jun 30 04:55:52 PM PDT 24 Jun 30 04:55:55 PM PDT 24 124114908 ps
T1134 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3057759679 Jun 30 04:56:12 PM PDT 24 Jun 30 04:56:13 PM PDT 24 93464809 ps
T65 /workspace/coverage/cover_reg_top/8.uart_csr_rw.4089395266 Jun 30 04:56:15 PM PDT 24 Jun 30 04:56:16 PM PDT 24 46468024 ps
T92 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.742916395 Jun 30 04:56:23 PM PDT 24 Jun 30 04:56:25 PM PDT 24 177191931 ps
T1135 /workspace/coverage/cover_reg_top/32.uart_intr_test.2045082719 Jun 30 04:56:36 PM PDT 24 Jun 30 04:56:37 PM PDT 24 205631092 ps
T1136 /workspace/coverage/cover_reg_top/27.uart_intr_test.1971558229 Jun 30 04:56:36 PM PDT 24 Jun 30 04:56:37 PM PDT 24 32419649 ps
T1137 /workspace/coverage/cover_reg_top/33.uart_intr_test.579952329 Jun 30 04:56:36 PM PDT 24 Jun 30 04:56:37 PM PDT 24 44328880 ps
T1138 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3417376277 Jun 30 04:56:12 PM PDT 24 Jun 30 04:56:14 PM PDT 24 119860172 ps
T1139 /workspace/coverage/cover_reg_top/41.uart_intr_test.4274248255 Jun 30 04:56:34 PM PDT 24 Jun 30 04:56:35 PM PDT 24 43309684 ps
T1140 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.413496848 Jun 30 04:56:34 PM PDT 24 Jun 30 04:56:36 PM PDT 24 79641596 ps
T1141 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2476505834 Jun 30 04:55:58 PM PDT 24 Jun 30 04:55:59 PM PDT 24 69770600 ps
T1142 /workspace/coverage/cover_reg_top/6.uart_intr_test.1463221127 Jun 30 04:56:13 PM PDT 24 Jun 30 04:56:15 PM PDT 24 78482438 ps
T1143 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1528536037 Jun 30 04:56:01 PM PDT 24 Jun 30 04:56:03 PM PDT 24 30594986 ps
T1144 /workspace/coverage/cover_reg_top/49.uart_intr_test.759530383 Jun 30 04:56:39 PM PDT 24 Jun 30 04:56:40 PM PDT 24 12940741 ps
T1145 /workspace/coverage/cover_reg_top/7.uart_intr_test.1645734430 Jun 30 04:56:13 PM PDT 24 Jun 30 04:56:14 PM PDT 24 12976836 ps
T1146 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2214289170 Jun 30 04:56:13 PM PDT 24 Jun 30 04:56:14 PM PDT 24 16398971 ps
T1147 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1814045647 Jun 30 04:56:22 PM PDT 24 Jun 30 04:56:23 PM PDT 24 21363147 ps
T1148 /workspace/coverage/cover_reg_top/29.uart_intr_test.840302969 Jun 30 04:56:33 PM PDT 24 Jun 30 04:56:33 PM PDT 24 42164387 ps
T59 /workspace/coverage/cover_reg_top/3.uart_csr_rw.1846362452 Jun 30 04:56:06 PM PDT 24 Jun 30 04:56:07 PM PDT 24 43214206 ps
T1149 /workspace/coverage/cover_reg_top/7.uart_tl_errors.3160397491 Jun 30 04:56:13 PM PDT 24 Jun 30 04:56:16 PM PDT 24 633654854 ps
T1150 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3533259766 Jun 30 04:56:01 PM PDT 24 Jun 30 04:56:03 PM PDT 24 65453382 ps
T1151 /workspace/coverage/cover_reg_top/23.uart_intr_test.2217947989 Jun 30 04:56:33 PM PDT 24 Jun 30 04:56:34 PM PDT 24 53595449 ps
T1152 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3783059718 Jun 30 04:56:28 PM PDT 24 Jun 30 04:56:29 PM PDT 24 87830667 ps
T60 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.831838038 Jun 30 04:55:57 PM PDT 24 Jun 30 04:55:58 PM PDT 24 27397696 ps
T1153 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.227381842 Jun 30 04:56:06 PM PDT 24 Jun 30 04:56:07 PM PDT 24 68393090 ps
T1154 /workspace/coverage/cover_reg_top/11.uart_tl_errors.1156398127 Jun 30 04:56:20 PM PDT 24 Jun 30 04:56:23 PM PDT 24 101874947 ps
T1155 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3237414988 Jun 30 04:56:29 PM PDT 24 Jun 30 04:56:31 PM PDT 24 30330950 ps
T1156 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2291843100 Jun 30 04:56:06 PM PDT 24 Jun 30 04:56:08 PM PDT 24 65676797 ps
T1157 /workspace/coverage/cover_reg_top/4.uart_intr_test.1851314984 Jun 30 04:56:06 PM PDT 24 Jun 30 04:56:07 PM PDT 24 10902606 ps
T1158 /workspace/coverage/cover_reg_top/30.uart_intr_test.1996202967 Jun 30 04:56:34 PM PDT 24 Jun 30 04:56:35 PM PDT 24 15603798 ps
T1159 /workspace/coverage/cover_reg_top/10.uart_csr_rw.1091658451 Jun 30 04:56:22 PM PDT 24 Jun 30 04:56:23 PM PDT 24 12426102 ps
T1160 /workspace/coverage/cover_reg_top/34.uart_intr_test.474636462 Jun 30 04:56:36 PM PDT 24 Jun 30 04:56:38 PM PDT 24 14876365 ps
T1161 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.676621877 Jun 30 04:56:28 PM PDT 24 Jun 30 04:56:29 PM PDT 24 45860019 ps
T1162 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2244365320 Jun 30 04:56:00 PM PDT 24 Jun 30 04:56:01 PM PDT 24 35032374 ps
T1163 /workspace/coverage/cover_reg_top/37.uart_intr_test.1423504421 Jun 30 04:56:34 PM PDT 24 Jun 30 04:56:34 PM PDT 24 42490032 ps
T61 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2050872848 Jun 30 04:56:06 PM PDT 24 Jun 30 04:56:09 PM PDT 24 227786446 ps
T1164 /workspace/coverage/cover_reg_top/17.uart_intr_test.2749898280 Jun 30 04:56:27 PM PDT 24 Jun 30 04:56:28 PM PDT 24 17926177 ps
T95 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.923278027 Jun 30 04:56:12 PM PDT 24 Jun 30 04:56:13 PM PDT 24 100655582 ps
T1165 /workspace/coverage/cover_reg_top/13.uart_intr_test.859248910 Jun 30 04:56:20 PM PDT 24 Jun 30 04:56:21 PM PDT 24 41107691 ps
T1166 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.705498722 Jun 30 04:56:28 PM PDT 24 Jun 30 04:56:30 PM PDT 24 25662166 ps
T1167 /workspace/coverage/cover_reg_top/13.uart_tl_errors.3580782242 Jun 30 04:56:22 PM PDT 24 Jun 30 04:56:24 PM PDT 24 89350685 ps
T1168 /workspace/coverage/cover_reg_top/9.uart_intr_test.2583621889 Jun 30 04:56:11 PM PDT 24 Jun 30 04:56:12 PM PDT 24 17233955 ps
T1169 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3335359857 Jun 30 04:56:00 PM PDT 24 Jun 30 04:56:02 PM PDT 24 62422834 ps
T1170 /workspace/coverage/cover_reg_top/48.uart_intr_test.1979082523 Jun 30 04:56:44 PM PDT 24 Jun 30 04:56:45 PM PDT 24 26466008 ps
T128 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2748451216 Jun 30 04:56:31 PM PDT 24 Jun 30 04:56:32 PM PDT 24 98689996 ps
T93 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3010804523 Jun 30 04:56:05 PM PDT 24 Jun 30 04:56:06 PM PDT 24 375285251 ps
T1171 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.81502628 Jun 30 04:56:30 PM PDT 24 Jun 30 04:56:32 PM PDT 24 170950340 ps
T1172 /workspace/coverage/cover_reg_top/8.uart_tl_errors.3499046033 Jun 30 04:56:13 PM PDT 24 Jun 30 04:56:15 PM PDT 24 61523838 ps
T127 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3592343546 Jun 30 04:56:23 PM PDT 24 Jun 30 04:56:24 PM PDT 24 279842180 ps
T1173 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3818766022 Jun 30 04:56:31 PM PDT 24 Jun 30 04:56:32 PM PDT 24 53747924 ps
T1174 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2697010227 Jun 30 04:56:13 PM PDT 24 Jun 30 04:56:15 PM PDT 24 49114542 ps
T1175 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1116817823 Jun 30 04:55:57 PM PDT 24 Jun 30 04:55:58 PM PDT 24 16502219 ps
T1176 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2046553045 Jun 30 04:56:01 PM PDT 24 Jun 30 04:56:02 PM PDT 24 187533208 ps
T1177 /workspace/coverage/cover_reg_top/5.uart_intr_test.3603566017 Jun 30 04:56:05 PM PDT 24 Jun 30 04:56:06 PM PDT 24 43152496 ps
T1178 /workspace/coverage/cover_reg_top/15.uart_intr_test.3826582847 Jun 30 04:56:28 PM PDT 24 Jun 30 04:56:29 PM PDT 24 25606351 ps
T1179 /workspace/coverage/cover_reg_top/46.uart_intr_test.3928215522 Jun 30 04:56:36 PM PDT 24 Jun 30 04:56:37 PM PDT 24 47072873 ps
T1180 /workspace/coverage/cover_reg_top/40.uart_intr_test.1779341516 Jun 30 04:56:35 PM PDT 24 Jun 30 04:56:36 PM PDT 24 11815286 ps
T1181 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1047393512 Jun 30 04:56:06 PM PDT 24 Jun 30 04:56:07 PM PDT 24 52761121 ps
T1182 /workspace/coverage/cover_reg_top/35.uart_intr_test.1133647173 Jun 30 04:56:36 PM PDT 24 Jun 30 04:56:38 PM PDT 24 15361156 ps
T1183 /workspace/coverage/cover_reg_top/15.uart_tl_errors.2286721195 Jun 30 04:56:30 PM PDT 24 Jun 30 04:56:32 PM PDT 24 58262822 ps
T1184 /workspace/coverage/cover_reg_top/12.uart_tl_errors.1221307620 Jun 30 04:56:19 PM PDT 24 Jun 30 04:56:22 PM PDT 24 124060369 ps
T62 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3685889889 Jun 30 04:55:58 PM PDT 24 Jun 30 04:56:01 PM PDT 24 1031650701 ps
T1185 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1075826996 Jun 30 04:56:12 PM PDT 24 Jun 30 04:56:13 PM PDT 24 16225413 ps
T1186 /workspace/coverage/cover_reg_top/7.uart_csr_rw.3445017176 Jun 30 04:56:13 PM PDT 24 Jun 30 04:56:15 PM PDT 24 27001804 ps
T1187 /workspace/coverage/cover_reg_top/14.uart_csr_rw.2165023881 Jun 30 04:56:20 PM PDT 24 Jun 30 04:56:22 PM PDT 24 18567047 ps
T1188 /workspace/coverage/cover_reg_top/21.uart_intr_test.2144623688 Jun 30 04:56:36 PM PDT 24 Jun 30 04:56:37 PM PDT 24 143865590 ps
T1189 /workspace/coverage/cover_reg_top/25.uart_intr_test.2108878718 Jun 30 04:56:33 PM PDT 24 Jun 30 04:56:34 PM PDT 24 14379679 ps
T1190 /workspace/coverage/cover_reg_top/10.uart_intr_test.3360061093 Jun 30 04:56:20 PM PDT 24 Jun 30 04:56:22 PM PDT 24 16095911 ps
T1191 /workspace/coverage/cover_reg_top/5.uart_csr_rw.3709060582 Jun 30 04:56:06 PM PDT 24 Jun 30 04:56:07 PM PDT 24 155924923 ps
T1192 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.617475862 Jun 30 04:55:58 PM PDT 24 Jun 30 04:55:59 PM PDT 24 73656931 ps
T96 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2697871166 Jun 30 04:56:19 PM PDT 24 Jun 30 04:56:21 PM PDT 24 137011999 ps
T1193 /workspace/coverage/cover_reg_top/18.uart_intr_test.3033890356 Jun 30 04:56:28 PM PDT 24 Jun 30 04:56:28 PM PDT 24 52256184 ps
T1194 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2529481688 Jun 30 04:56:31 PM PDT 24 Jun 30 04:56:32 PM PDT 24 30201123 ps
T1195 /workspace/coverage/cover_reg_top/39.uart_intr_test.975569535 Jun 30 04:56:36 PM PDT 24 Jun 30 04:56:37 PM PDT 24 14135739 ps
T91 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.784531146 Jun 30 04:56:00 PM PDT 24 Jun 30 04:56:01 PM PDT 24 362143326 ps
T1196 /workspace/coverage/cover_reg_top/2.uart_csr_rw.2306090098 Jun 30 04:55:59 PM PDT 24 Jun 30 04:56:00 PM PDT 24 48471569 ps
T1197 /workspace/coverage/cover_reg_top/13.uart_csr_rw.550596156 Jun 30 04:56:23 PM PDT 24 Jun 30 04:56:24 PM PDT 24 20194840 ps
T1198 /workspace/coverage/cover_reg_top/15.uart_csr_rw.1883332493 Jun 30 04:56:27 PM PDT 24 Jun 30 04:56:27 PM PDT 24 21560755 ps
T1199 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1207116397 Jun 30 04:56:00 PM PDT 24 Jun 30 04:56:02 PM PDT 24 142298892 ps
T1200 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1896373955 Jun 30 04:56:00 PM PDT 24 Jun 30 04:56:01 PM PDT 24 18033424 ps
T1201 /workspace/coverage/cover_reg_top/6.uart_csr_rw.1715495708 Jun 30 04:56:13 PM PDT 24 Jun 30 04:56:15 PM PDT 24 219842493 ps
T1202 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3047275076 Jun 30 04:56:20 PM PDT 24 Jun 30 04:56:22 PM PDT 24 20838301 ps
T1203 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3566692310 Jun 30 04:56:16 PM PDT 24 Jun 30 04:56:18 PM PDT 24 86314978 ps
T1204 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.872001047 Jun 30 04:56:21 PM PDT 24 Jun 30 04:56:22 PM PDT 24 44908836 ps
T1205 /workspace/coverage/cover_reg_top/4.uart_tl_errors.1941271446 Jun 30 04:56:06 PM PDT 24 Jun 30 04:56:08 PM PDT 24 39558450 ps
T1206 /workspace/coverage/cover_reg_top/2.uart_tl_errors.3672783444 Jun 30 04:56:00 PM PDT 24 Jun 30 04:56:02 PM PDT 24 383046242 ps
T1207 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1214631599 Jun 30 04:56:28 PM PDT 24 Jun 30 04:56:30 PM PDT 24 93507814 ps
T1208 /workspace/coverage/cover_reg_top/8.uart_intr_test.293197419 Jun 30 04:56:14 PM PDT 24 Jun 30 04:56:15 PM PDT 24 13109945 ps
T63 /workspace/coverage/cover_reg_top/4.uart_csr_rw.2964606005 Jun 30 04:56:07 PM PDT 24 Jun 30 04:56:08 PM PDT 24 18323235 ps
T1209 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.121400876 Jun 30 04:56:07 PM PDT 24 Jun 30 04:56:10 PM PDT 24 932072050 ps
T1210 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2351943868 Jun 30 04:56:13 PM PDT 24 Jun 30 04:56:14 PM PDT 24 64683292 ps
T1211 /workspace/coverage/cover_reg_top/1.uart_tl_errors.1537296067 Jun 30 04:55:58 PM PDT 24 Jun 30 04:55:59 PM PDT 24 26583287 ps
T1212 /workspace/coverage/cover_reg_top/0.uart_intr_test.4202301685 Jun 30 04:55:57 PM PDT 24 Jun 30 04:55:58 PM PDT 24 47233486 ps
T1213 /workspace/coverage/cover_reg_top/17.uart_tl_errors.1467777812 Jun 30 04:56:30 PM PDT 24 Jun 30 04:56:31 PM PDT 24 174096698 ps
T1214 /workspace/coverage/cover_reg_top/3.uart_tl_errors.2544011978 Jun 30 04:56:00 PM PDT 24 Jun 30 04:56:02 PM PDT 24 175529466 ps
T1215 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2843494663 Jun 30 04:55:59 PM PDT 24 Jun 30 04:56:00 PM PDT 24 15053324 ps
T1216 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1508208903 Jun 30 04:56:16 PM PDT 24 Jun 30 04:56:17 PM PDT 24 35494394 ps
T1217 /workspace/coverage/cover_reg_top/36.uart_intr_test.2754131410 Jun 30 04:56:35 PM PDT 24 Jun 30 04:56:36 PM PDT 24 14300568 ps
T1218 /workspace/coverage/cover_reg_top/16.uart_csr_rw.2148748493 Jun 30 04:56:27 PM PDT 24 Jun 30 04:56:28 PM PDT 24 26035226 ps
T1219 /workspace/coverage/cover_reg_top/5.uart_tl_errors.1248794976 Jun 30 04:56:05 PM PDT 24 Jun 30 04:56:06 PM PDT 24 31477345 ps
T1220 /workspace/coverage/cover_reg_top/24.uart_intr_test.740750055 Jun 30 04:56:34 PM PDT 24 Jun 30 04:56:34 PM PDT 24 14076621 ps
T1221 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1841636702 Jun 30 04:56:01 PM PDT 24 Jun 30 04:56:02 PM PDT 24 33678736 ps
T1222 /workspace/coverage/cover_reg_top/47.uart_intr_test.3347849066 Jun 30 04:56:40 PM PDT 24 Jun 30 04:56:41 PM PDT 24 16304391 ps
T1223 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1189992182 Jun 30 04:56:22 PM PDT 24 Jun 30 04:56:24 PM PDT 24 23512772 ps
T1224 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3974035279 Jun 30 04:56:12 PM PDT 24 Jun 30 04:56:13 PM PDT 24 47344767 ps
T1225 /workspace/coverage/cover_reg_top/44.uart_intr_test.2052565405 Jun 30 04:56:34 PM PDT 24 Jun 30 04:56:36 PM PDT 24 16554675 ps
T1226 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3548607466 Jun 30 04:56:01 PM PDT 24 Jun 30 04:56:03 PM PDT 24 13446468 ps
T1227 /workspace/coverage/cover_reg_top/22.uart_intr_test.176506804 Jun 30 04:56:35 PM PDT 24 Jun 30 04:56:36 PM PDT 24 35378110 ps
T1228 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3481418567 Jun 30 04:56:30 PM PDT 24 Jun 30 04:56:32 PM PDT 24 1086641963 ps
T1229 /workspace/coverage/cover_reg_top/12.uart_csr_rw.2001211497 Jun 30 04:56:21 PM PDT 24 Jun 30 04:56:23 PM PDT 24 15033112 ps
T1230 /workspace/coverage/cover_reg_top/9.uart_tl_errors.1935339948 Jun 30 04:56:13 PM PDT 24 Jun 30 04:56:15 PM PDT 24 173447774 ps
T1231 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2752032804 Jun 30 04:55:58 PM PDT 24 Jun 30 04:55:59 PM PDT 24 153336217 ps

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.733192752
Short name T9
Test name
Test status
Simulation time 90622228207 ps
CPU time 1031.4 seconds
Started Jun 30 05:09:57 PM PDT 24
Finished Jun 30 05:27:09 PM PDT 24
Peak memory 216424 kb
Host smart-ff94e6dd-99ac-4ad1-a044-9936d7a1154a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733192752 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.733192752
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.2267983365
Short name T47
Test name
Test status
Simulation time 107354820007 ps
CPU time 1425.35 seconds
Started Jun 30 05:10:40 PM PDT 24
Finished Jun 30 05:34:27 PM PDT 24
Peak memory 226072 kb
Host smart-dbc2f5eb-c080-471b-ab72-15dd99ed8bc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267983365 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.2267983365
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.936788075
Short name T19
Test name
Test status
Simulation time 136963392604 ps
CPU time 654.9 seconds
Started Jun 30 05:10:25 PM PDT 24
Finished Jun 30 05:21:20 PM PDT 24
Peak memory 216400 kb
Host smart-d8e1e811-b043-4685-b7bf-c7715ff86c08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936788075 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.936788075
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.1957413324
Short name T16
Test name
Test status
Simulation time 112271699020 ps
CPU time 981.28 seconds
Started Jun 30 05:10:52 PM PDT 24
Finished Jun 30 05:27:13 PM PDT 24
Peak memory 226844 kb
Host smart-8366a93f-dc7b-4f81-9c90-c746478aaa86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957413324 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.1957413324
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.411604941
Short name T241
Test name
Test status
Simulation time 65777640977 ps
CPU time 437.89 seconds
Started Jun 30 05:06:27 PM PDT 24
Finished Jun 30 05:13:47 PM PDT 24
Peak memory 199896 kb
Host smart-dd799524-3acb-4ff3-89ab-ee7fa7f88a86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=411604941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.411604941
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1059761817
Short name T3
Test name
Test status
Simulation time 119796443090 ps
CPU time 719.99 seconds
Started Jun 30 05:10:32 PM PDT 24
Finished Jun 30 05:22:33 PM PDT 24
Peak memory 214680 kb
Host smart-7db75fd5-ac4b-4738-8291-3a4e0d754316
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059761817 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1059761817
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.2319265445
Short name T247
Test name
Test status
Simulation time 87647694125 ps
CPU time 486.51 seconds
Started Jun 30 05:07:46 PM PDT 24
Finished Jun 30 05:15:53 PM PDT 24
Peak memory 199820 kb
Host smart-61b95c1a-e9a5-4e3c-a96f-4a74f51c7a7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2319265445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.2319265445
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_stress_all.2933853220
Short name T148
Test name
Test status
Simulation time 571755993231 ps
CPU time 287.1 seconds
Started Jun 30 05:09:15 PM PDT 24
Finished Jun 30 05:14:03 PM PDT 24
Peak memory 199816 kb
Host smart-a88d5946-1edf-49b0-9b93-e6f220331a17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933853220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2933853220
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_sec_cm.2492252333
Short name T24
Test name
Test status
Simulation time 118653692 ps
CPU time 0.78 seconds
Started Jun 30 05:06:36 PM PDT 24
Finished Jun 30 05:06:38 PM PDT 24
Peak memory 218164 kb
Host smart-29da1b14-1045-45c6-9741-f70c00f7160b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492252333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.2492252333
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.3129899656
Short name T43
Test name
Test status
Simulation time 93241191503 ps
CPU time 952.62 seconds
Started Jun 30 05:06:34 PM PDT 24
Finished Jun 30 05:22:27 PM PDT 24
Peak memory 216448 kb
Host smart-e333b0ca-c0f7-431d-a19e-2e0a2f817fef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129899656 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.3129899656
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_fifo_full.2547222963
Short name T268
Test name
Test status
Simulation time 475889312395 ps
CPU time 574.48 seconds
Started Jun 30 05:09:21 PM PDT 24
Finished Jun 30 05:18:56 PM PDT 24
Peak memory 199936 kb
Host smart-c1545852-2cc1-48c7-881b-218ab0e7428d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547222963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2547222963
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.2870259591
Short name T44
Test name
Test status
Simulation time 146616057267 ps
CPU time 38.77 seconds
Started Jun 30 05:10:41 PM PDT 24
Finished Jun 30 05:11:20 PM PDT 24
Peak memory 199884 kb
Host smart-c8e76821-aa56-4c81-b856-b573d97545d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870259591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2870259591
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.3104681743
Short name T12
Test name
Test status
Simulation time 174492155673 ps
CPU time 106 seconds
Started Jun 30 05:11:18 PM PDT 24
Finished Jun 30 05:13:05 PM PDT 24
Peak memory 199828 kb
Host smart-2cd5f5e5-940a-4819-ae97-c5347d3e33c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104681743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.3104681743
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.3674924393
Short name T45
Test name
Test status
Simulation time 136423111812 ps
CPU time 402.86 seconds
Started Jun 30 05:11:10 PM PDT 24
Finished Jun 30 05:17:54 PM PDT 24
Peak memory 199784 kb
Host smart-3821bc5f-7fa2-4f5f-b210-7ede69dc13f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674924393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3674924393
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_tx_rx.2629708103
Short name T249
Test name
Test status
Simulation time 101366035442 ps
CPU time 167.91 seconds
Started Jun 30 05:08:21 PM PDT 24
Finished Jun 30 05:11:10 PM PDT 24
Peak memory 200120 kb
Host smart-4ea59dea-cfc7-45fe-8610-30e51d1fe4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629708103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.2629708103
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3178941030
Short name T56
Test name
Test status
Simulation time 13771134 ps
CPU time 0.61 seconds
Started Jun 30 04:56:28 PM PDT 24
Finished Jun 30 04:56:30 PM PDT 24
Peak memory 195808 kb
Host smart-36304a2b-22b3-45f2-a51d-c6007417d745
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178941030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3178941030
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.1878744719
Short name T27
Test name
Test status
Simulation time 593204507203 ps
CPU time 52.58 seconds
Started Jun 30 05:12:15 PM PDT 24
Finished Jun 30 05:13:08 PM PDT 24
Peak memory 199876 kb
Host smart-6bc592b3-8c45-4450-a90c-fd6ce9310ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878744719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.1878744719
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.4070922274
Short name T86
Test name
Test status
Simulation time 351319669 ps
CPU time 1.29 seconds
Started Jun 30 04:56:21 PM PDT 24
Finished Jun 30 04:56:24 PM PDT 24
Peak memory 199688 kb
Host smart-74a2b96f-be1e-464f-b91e-b709470641dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070922274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.4070922274
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/default/3.uart_fifo_full.68262294
Short name T34
Test name
Test status
Simulation time 116327830982 ps
CPU time 128.32 seconds
Started Jun 30 05:06:30 PM PDT 24
Finished Jun 30 05:08:39 PM PDT 24
Peak memory 199884 kb
Host smart-e1526191-22d9-43f6-b281-ec5ef5527f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68262294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.68262294
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_stress_all.3469170878
Short name T149
Test name
Test status
Simulation time 427726306863 ps
CPU time 221.24 seconds
Started Jun 30 05:09:57 PM PDT 24
Finished Jun 30 05:13:39 PM PDT 24
Peak memory 199836 kb
Host smart-f0a6e7e6-d3c4-4e6d-a228-e52401676bbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469170878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.3469170878
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.3607795334
Short name T20
Test name
Test status
Simulation time 48582051496 ps
CPU time 468.31 seconds
Started Jun 30 05:10:41 PM PDT 24
Finished Jun 30 05:18:30 PM PDT 24
Peak memory 212380 kb
Host smart-2b402fc0-ade6-472e-a411-907e7c03145a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607795334 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3607795334
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.917165999
Short name T425
Test name
Test status
Simulation time 11483823 ps
CPU time 0.56 seconds
Started Jun 30 05:07:21 PM PDT 24
Finished Jun 30 05:07:22 PM PDT 24
Peak memory 195220 kb
Host smart-acea721f-c7de-4fbb-8220-268ccadd1341
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917165999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.917165999
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.3613886472
Short name T134
Test name
Test status
Simulation time 14922399183 ps
CPU time 32.45 seconds
Started Jun 30 05:07:52 PM PDT 24
Finished Jun 30 05:08:25 PM PDT 24
Peak memory 200204 kb
Host smart-3f5bad78-c0c7-4699-b734-91834082d8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613886472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3613886472
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_perf.3523630928
Short name T244
Test name
Test status
Simulation time 20116866142 ps
CPU time 997.53 seconds
Started Jun 30 05:07:42 PM PDT 24
Finished Jun 30 05:24:20 PM PDT 24
Peak memory 199900 kb
Host smart-e133a07e-4041-48ef-b9c5-dc09308feaa1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3523630928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3523630928
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.4050952858
Short name T112
Test name
Test status
Simulation time 70913273621 ps
CPU time 896.84 seconds
Started Jun 30 05:07:41 PM PDT 24
Finished Jun 30 05:22:38 PM PDT 24
Peak memory 225420 kb
Host smart-9a516d21-0abf-40cc-b9fa-6910e29c4fc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050952858 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.4050952858
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.3337446018
Short name T48
Test name
Test status
Simulation time 419641711314 ps
CPU time 1298.04 seconds
Started Jun 30 05:10:41 PM PDT 24
Finished Jun 30 05:32:20 PM PDT 24
Peak memory 216484 kb
Host smart-5120f234-9a83-4414-8e61-5a197ca60816
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337446018 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3337446018
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_stress_all.1801761980
Short name T159
Test name
Test status
Simulation time 483652634129 ps
CPU time 139.69 seconds
Started Jun 30 05:08:44 PM PDT 24
Finished Jun 30 05:11:04 PM PDT 24
Peak memory 199812 kb
Host smart-b58f5c84-d8c4-480d-a05c-b89923059c38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801761980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.1801761980
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.984265333
Short name T111
Test name
Test status
Simulation time 149523710042 ps
CPU time 652.1 seconds
Started Jun 30 05:10:48 PM PDT 24
Finished Jun 30 05:21:41 PM PDT 24
Peak memory 216436 kb
Host smart-8d8eb4e1-9b8a-433c-a0d1-519792c858b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984265333 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.984265333
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.1641873038
Short name T155
Test name
Test status
Simulation time 365806242430 ps
CPU time 75.2 seconds
Started Jun 30 05:11:06 PM PDT 24
Finished Jun 30 05:12:22 PM PDT 24
Peak memory 199888 kb
Host smart-9d9a6cc1-58f5-411a-bd64-187185a4b943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641873038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1641873038
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.1167879446
Short name T135
Test name
Test status
Simulation time 100277930998 ps
CPU time 77.86 seconds
Started Jun 30 05:09:12 PM PDT 24
Finished Jun 30 05:10:30 PM PDT 24
Peak memory 199912 kb
Host smart-0bddf317-7063-4749-b3d3-88ebcfddcc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167879446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1167879446
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.4276000932
Short name T90
Test name
Test status
Simulation time 109086244 ps
CPU time 1.32 seconds
Started Jun 30 04:56:30 PM PDT 24
Finished Jun 30 04:56:32 PM PDT 24
Peak memory 199648 kb
Host smart-15080218-d6ec-4de9-987a-565f3369b314
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276000932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.4276000932
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.3487459476
Short name T153
Test name
Test status
Simulation time 104073797187 ps
CPU time 58.6 seconds
Started Jun 30 05:11:32 PM PDT 24
Finished Jun 30 05:12:31 PM PDT 24
Peak memory 199888 kb
Host smart-aab48fb3-400e-43c3-a3b2-9941f51f05fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487459476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3487459476
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.1315235313
Short name T70
Test name
Test status
Simulation time 78658711091 ps
CPU time 21.43 seconds
Started Jun 30 05:11:04 PM PDT 24
Finished Jun 30 05:11:26 PM PDT 24
Peak memory 199916 kb
Host smart-ae06f0d9-4924-4db7-b4f2-31fc430608b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315235313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1315235313
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.2545407234
Short name T661
Test name
Test status
Simulation time 35917546259 ps
CPU time 30.11 seconds
Started Jun 30 05:12:13 PM PDT 24
Finished Jun 30 05:12:43 PM PDT 24
Peak memory 199844 kb
Host smart-0669681b-f3d1-4e96-8a6e-8d8b869e9f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545407234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2545407234
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.347465460
Short name T315
Test name
Test status
Simulation time 116439888085 ps
CPU time 443.17 seconds
Started Jun 30 05:08:55 PM PDT 24
Finished Jun 30 05:16:19 PM PDT 24
Peak memory 199812 kb
Host smart-a5028ca3-2115-41a8-bad8-8721982400fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=347465460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.347465460
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.4136829426
Short name T142
Test name
Test status
Simulation time 39549666567 ps
CPU time 17.08 seconds
Started Jun 30 05:10:51 PM PDT 24
Finished Jun 30 05:11:09 PM PDT 24
Peak memory 199884 kb
Host smart-9cc9ae99-db88-47cc-94a9-844974f93625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136829426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.4136829426
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.4083991019
Short name T265
Test name
Test status
Simulation time 102954362211 ps
CPU time 178.21 seconds
Started Jun 30 05:07:06 PM PDT 24
Finished Jun 30 05:10:06 PM PDT 24
Peak memory 199896 kb
Host smart-4d919fd9-9038-44ce-920a-67a10260f138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083991019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.4083991019
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.2779556559
Short name T133
Test name
Test status
Simulation time 16070592696 ps
CPU time 27.82 seconds
Started Jun 30 05:10:48 PM PDT 24
Finished Jun 30 05:11:16 PM PDT 24
Peak memory 199916 kb
Host smart-479d2c04-8e72-4e26-9609-adc0b2f37d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779556559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2779556559
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.3073187937
Short name T393
Test name
Test status
Simulation time 148681120361 ps
CPU time 647.43 seconds
Started Jun 30 05:07:23 PM PDT 24
Finished Jun 30 05:18:11 PM PDT 24
Peak memory 199880 kb
Host smart-602ef687-5dc6-449c-8f15-6db77f7f73fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073187937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3073187937
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3431600819
Short name T228
Test name
Test status
Simulation time 90275270338 ps
CPU time 78.38 seconds
Started Jun 30 05:11:49 PM PDT 24
Finished Jun 30 05:13:08 PM PDT 24
Peak memory 199804 kb
Host smart-ccea5580-a4af-47eb-aca0-13074cff6288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431600819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3431600819
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.3398748940
Short name T164
Test name
Test status
Simulation time 31661347852 ps
CPU time 6.24 seconds
Started Jun 30 05:09:50 PM PDT 24
Finished Jun 30 05:09:57 PM PDT 24
Peak memory 199876 kb
Host smart-bae52bf1-15b0-41ff-8201-9bbd6124ba1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398748940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.3398748940
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.3679959083
Short name T110
Test name
Test status
Simulation time 38355745704 ps
CPU time 324.17 seconds
Started Jun 30 05:10:49 PM PDT 24
Finished Jun 30 05:16:14 PM PDT 24
Peak memory 216516 kb
Host smart-3e1a8ea0-6862-43ef-a227-d8bb5046ad1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679959083 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.3679959083
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3357077233
Short name T761
Test name
Test status
Simulation time 154766365504 ps
CPU time 52.72 seconds
Started Jun 30 05:10:57 PM PDT 24
Finished Jun 30 05:11:50 PM PDT 24
Peak memory 199888 kb
Host smart-61b2e876-c345-4f25-8a2b-8b65c63ec5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357077233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3357077233
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.3089385802
Short name T847
Test name
Test status
Simulation time 24170202562 ps
CPU time 48.04 seconds
Started Jun 30 05:11:03 PM PDT 24
Finished Jun 30 05:11:51 PM PDT 24
Peak memory 199884 kb
Host smart-0d4bb8b0-8dbe-4410-8325-02c0c556ecd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089385802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.3089385802
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.4281735017
Short name T144
Test name
Test status
Simulation time 31544949281 ps
CPU time 34.58 seconds
Started Jun 30 05:11:34 PM PDT 24
Finished Jun 30 05:12:09 PM PDT 24
Peak memory 199904 kb
Host smart-ee98b51d-04d3-43df-8e29-ab3cf6bd1aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281735017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.4281735017
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.2493236427
Short name T28
Test name
Test status
Simulation time 75851380258 ps
CPU time 38.42 seconds
Started Jun 30 05:12:02 PM PDT 24
Finished Jun 30 05:12:41 PM PDT 24
Peak memory 199920 kb
Host smart-46c58694-3520-4b5c-a3dc-e48801b96cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493236427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2493236427
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.1987662025
Short name T162
Test name
Test status
Simulation time 130752785240 ps
CPU time 199.47 seconds
Started Jun 30 05:12:17 PM PDT 24
Finished Jun 30 05:15:37 PM PDT 24
Peak memory 199916 kb
Host smart-106aacc6-0f69-417b-8bd3-588f59974839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987662025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1987662025
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.2489805370
Short name T172
Test name
Test status
Simulation time 61755071983 ps
CPU time 23.63 seconds
Started Jun 30 05:06:53 PM PDT 24
Finished Jun 30 05:07:17 PM PDT 24
Peak memory 199904 kb
Host smart-431e037c-f481-462e-b71b-0ef6ac2be009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489805370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.2489805370
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3754669922
Short name T208
Test name
Test status
Simulation time 228451888446 ps
CPU time 606.6 seconds
Started Jun 30 05:10:58 PM PDT 24
Finished Jun 30 05:21:05 PM PDT 24
Peak memory 213980 kb
Host smart-3abaaab2-aaac-42fc-9a79-2a6fb1836a27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754669922 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3754669922
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.525610602
Short name T233
Test name
Test status
Simulation time 41542679135 ps
CPU time 56.6 seconds
Started Jun 30 05:06:32 PM PDT 24
Finished Jun 30 05:07:29 PM PDT 24
Peak memory 199736 kb
Host smart-82feff12-4eae-4013-96a9-b78e8a94cbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525610602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.525610602
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.1840411017
Short name T201
Test name
Test status
Simulation time 205862240555 ps
CPU time 158.26 seconds
Started Jun 30 05:11:57 PM PDT 24
Finished Jun 30 05:14:35 PM PDT 24
Peak memory 199864 kb
Host smart-e3ccd145-0ab5-4935-ac55-86a97970bb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840411017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.1840411017
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.2342162609
Short name T350
Test name
Test status
Simulation time 9455833182 ps
CPU time 8.61 seconds
Started Jun 30 05:11:54 PM PDT 24
Finished Jun 30 05:12:03 PM PDT 24
Peak memory 199900 kb
Host smart-cf0ad812-f2dc-4871-b50a-bf1d6681ad6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342162609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2342162609
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.1535381607
Short name T129
Test name
Test status
Simulation time 31410145870 ps
CPU time 26.23 seconds
Started Jun 30 05:12:16 PM PDT 24
Finished Jun 30 05:12:42 PM PDT 24
Peak memory 199840 kb
Host smart-aa8619c9-e186-4c69-b594-c11adbaef43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535381607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1535381607
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.3236271278
Short name T205
Test name
Test status
Simulation time 155023940231 ps
CPU time 120.39 seconds
Started Jun 30 05:12:24 PM PDT 24
Finished Jun 30 05:14:25 PM PDT 24
Peak memory 199884 kb
Host smart-a46dca4c-ab15-4636-97b0-c3576bf2bc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236271278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3236271278
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2678018112
Short name T185
Test name
Test status
Simulation time 24751991224 ps
CPU time 22.94 seconds
Started Jun 30 05:10:47 PM PDT 24
Finished Jun 30 05:11:11 PM PDT 24
Peak memory 199864 kb
Host smart-7224baba-bb06-445d-a4b4-2efddd6c3063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678018112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2678018112
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.3160693583
Short name T123
Test name
Test status
Simulation time 19508863203 ps
CPU time 29.05 seconds
Started Jun 30 05:06:59 PM PDT 24
Finished Jun 30 05:07:29 PM PDT 24
Peak memory 199900 kb
Host smart-b2aee778-3cfb-46fe-b73c-1ce5d8a5cbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160693583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3160693583
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.3494117339
Short name T177
Test name
Test status
Simulation time 139546940029 ps
CPU time 101.87 seconds
Started Jun 30 05:10:58 PM PDT 24
Finished Jun 30 05:12:40 PM PDT 24
Peak memory 199920 kb
Host smart-92dbb318-5fc3-47fb-b1f6-03c6f04c1c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494117339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.3494117339
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.3343154678
Short name T180
Test name
Test status
Simulation time 9691246151 ps
CPU time 15.77 seconds
Started Jun 30 05:10:57 PM PDT 24
Finished Jun 30 05:11:13 PM PDT 24
Peak memory 199836 kb
Host smart-c8c9bf14-24d0-4a9a-b276-fb73b4346624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343154678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3343154678
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.1961074336
Short name T160
Test name
Test status
Simulation time 38755706500 ps
CPU time 33.39 seconds
Started Jun 30 05:11:04 PM PDT 24
Finished Jun 30 05:11:38 PM PDT 24
Peak memory 199920 kb
Host smart-874cb706-fba6-444c-919c-76b0c03fdc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961074336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1961074336
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.632087833
Short name T189
Test name
Test status
Simulation time 65455714130 ps
CPU time 45.63 seconds
Started Jun 30 05:11:03 PM PDT 24
Finished Jun 30 05:11:49 PM PDT 24
Peak memory 199884 kb
Host smart-94915416-3b3a-42a9-81b8-8d790ef0f2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632087833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.632087833
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.1394300303
Short name T232
Test name
Test status
Simulation time 118500012288 ps
CPU time 82.64 seconds
Started Jun 30 05:11:12 PM PDT 24
Finished Jun 30 05:12:35 PM PDT 24
Peak memory 199856 kb
Host smart-2e7713b6-518b-4de0-bbdf-4e652bc753f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394300303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.1394300303
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.1738372417
Short name T151
Test name
Test status
Simulation time 38186891852 ps
CPU time 17.22 seconds
Started Jun 30 05:11:12 PM PDT 24
Finished Jun 30 05:11:30 PM PDT 24
Peak memory 199860 kb
Host smart-fd79a0f4-edc6-4ff7-8690-3e9e3fa0384b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738372417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1738372417
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.2929351026
Short name T224
Test name
Test status
Simulation time 91664189346 ps
CPU time 45.52 seconds
Started Jun 30 05:11:19 PM PDT 24
Finished Jun 30 05:12:04 PM PDT 24
Peak memory 199828 kb
Host smart-7d6a2640-b10e-4309-8361-3fc80acde3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929351026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2929351026
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.2476285498
Short name T656
Test name
Test status
Simulation time 58544102714 ps
CPU time 74.58 seconds
Started Jun 30 05:07:11 PM PDT 24
Finished Jun 30 05:08:26 PM PDT 24
Peak memory 199792 kb
Host smart-d3cc8115-e05a-49e7-bc8c-8a758062b75a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476285498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2476285498
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3975788644
Short name T167
Test name
Test status
Simulation time 87784945324 ps
CPU time 118.16 seconds
Started Jun 30 05:11:29 PM PDT 24
Finished Jun 30 05:13:28 PM PDT 24
Peak memory 199808 kb
Host smart-2cf1d4db-0585-4e10-982e-5c61a3d9aea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975788644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3975788644
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2894027192
Short name T212
Test name
Test status
Simulation time 115459755882 ps
CPU time 63.34 seconds
Started Jun 30 05:11:32 PM PDT 24
Finished Jun 30 05:12:35 PM PDT 24
Peak memory 199336 kb
Host smart-1e62cfdc-a567-4f96-b91d-87473dec2cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894027192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2894027192
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.3099011651
Short name T225
Test name
Test status
Simulation time 12706438355 ps
CPU time 22.57 seconds
Started Jun 30 05:07:29 PM PDT 24
Finished Jun 30 05:07:52 PM PDT 24
Peak memory 199812 kb
Host smart-5385530e-4c1d-495c-8001-251d2f6b3fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099011651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3099011651
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.2219375262
Short name T229
Test name
Test status
Simulation time 74394062911 ps
CPU time 31.21 seconds
Started Jun 30 05:11:29 PM PDT 24
Finished Jun 30 05:12:01 PM PDT 24
Peak memory 199780 kb
Host smart-0a927fde-5b01-48f8-8e2c-a5f46f2ba831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219375262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.2219375262
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1302664896
Short name T222
Test name
Test status
Simulation time 94795361888 ps
CPU time 60.81 seconds
Started Jun 30 05:11:31 PM PDT 24
Finished Jun 30 05:12:32 PM PDT 24
Peak memory 199804 kb
Host smart-08e1b4af-ee6c-43ee-b685-a1e5267bd9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302664896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1302664896
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.1589161178
Short name T218
Test name
Test status
Simulation time 73958019558 ps
CPU time 8.07 seconds
Started Jun 30 05:11:33 PM PDT 24
Finished Jun 30 05:11:41 PM PDT 24
Peak memory 199876 kb
Host smart-6d9abb0b-cb1c-4ece-8e7e-6550ad6a61b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589161178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.1589161178
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.1279920582
Short name T207
Test name
Test status
Simulation time 109078458496 ps
CPU time 60.69 seconds
Started Jun 30 05:11:42 PM PDT 24
Finished Jun 30 05:12:43 PM PDT 24
Peak memory 199920 kb
Host smart-f83f8a38-647e-4f91-b722-5d6acce330ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279920582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1279920582
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.2915747146
Short name T234
Test name
Test status
Simulation time 121059197219 ps
CPU time 84.04 seconds
Started Jun 30 05:11:47 PM PDT 24
Finished Jun 30 05:13:12 PM PDT 24
Peak memory 199844 kb
Host smart-08c95f5a-f45a-4724-8de2-fbbb1b786418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915747146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2915747146
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1734298327
Short name T195
Test name
Test status
Simulation time 251337937648 ps
CPU time 337.64 seconds
Started Jun 30 05:11:49 PM PDT 24
Finished Jun 30 05:17:27 PM PDT 24
Peak memory 199920 kb
Host smart-f0746bbd-6e79-44ed-a4d9-6a90a6ae6c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734298327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1734298327
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.1270834139
Short name T231
Test name
Test status
Simulation time 28383424677 ps
CPU time 26 seconds
Started Jun 30 05:12:12 PM PDT 24
Finished Jun 30 05:12:39 PM PDT 24
Peak memory 199920 kb
Host smart-da166516-08aa-467f-994a-41e69f9c9e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270834139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1270834139
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3548607466
Short name T1226
Test name
Test status
Simulation time 13446468 ps
CPU time 0.66 seconds
Started Jun 30 04:56:01 PM PDT 24
Finished Jun 30 04:56:03 PM PDT 24
Peak memory 195820 kb
Host smart-55029c96-0333-4a1a-8b67-7e21aaaf0065
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548607466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3548607466
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2046553045
Short name T1176
Test name
Test status
Simulation time 187533208 ps
CPU time 1.43 seconds
Started Jun 30 04:56:01 PM PDT 24
Finished Jun 30 04:56:02 PM PDT 24
Peak memory 197904 kb
Host smart-5b32cceb-0071-4f45-a295-a2b6156c2c75
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046553045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2046553045
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3631512700
Short name T53
Test name
Test status
Simulation time 18119651 ps
CPU time 0.6 seconds
Started Jun 30 04:56:02 PM PDT 24
Finished Jun 30 04:56:03 PM PDT 24
Peak memory 195784 kb
Host smart-181225e3-1f4b-4561-8816-8d5cfe288b3b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631512700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.3631512700
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1116817823
Short name T1175
Test name
Test status
Simulation time 16502219 ps
CPU time 0.62 seconds
Started Jun 30 04:55:57 PM PDT 24
Finished Jun 30 04:55:58 PM PDT 24
Peak memory 197748 kb
Host smart-57204677-77ae-43a8-b74e-173c73b45648
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116817823 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.1116817823
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.1535692023
Short name T57
Test name
Test status
Simulation time 14899879 ps
CPU time 0.59 seconds
Started Jun 30 04:55:57 PM PDT 24
Finished Jun 30 04:55:58 PM PDT 24
Peak memory 195968 kb
Host smart-f22caf8f-11e1-4fc2-916c-2270a4404f65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535692023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1535692023
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.4202301685
Short name T1212
Test name
Test status
Simulation time 47233486 ps
CPU time 0.58 seconds
Started Jun 30 04:55:57 PM PDT 24
Finished Jun 30 04:55:58 PM PDT 24
Peak memory 194704 kb
Host smart-c8faaa60-b603-48ce-a3de-2ccde8df1a37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202301685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.4202301685
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.617475862
Short name T1192
Test name
Test status
Simulation time 73656931 ps
CPU time 0.65 seconds
Started Jun 30 04:55:58 PM PDT 24
Finished Jun 30 04:55:59 PM PDT 24
Peak memory 194996 kb
Host smart-ba0b2dd8-e61b-4f40-83b9-b27327b6126f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617475862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_
outstanding.617475862
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.372079537
Short name T1133
Test name
Test status
Simulation time 124114908 ps
CPU time 2.47 seconds
Started Jun 30 04:55:52 PM PDT 24
Finished Jun 30 04:55:55 PM PDT 24
Peak memory 200400 kb
Host smart-bde16318-8f24-4778-b1d5-b4334ae3dc76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372079537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.372079537
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1207116397
Short name T1199
Test name
Test status
Simulation time 142298892 ps
CPU time 0.95 seconds
Started Jun 30 04:56:00 PM PDT 24
Finished Jun 30 04:56:02 PM PDT 24
Peak memory 199652 kb
Host smart-6b9ae513-91da-4326-8754-b236f10bdc1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207116397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.1207116397
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.831838038
Short name T60
Test name
Test status
Simulation time 27397696 ps
CPU time 0.74 seconds
Started Jun 30 04:55:57 PM PDT 24
Finished Jun 30 04:55:58 PM PDT 24
Peak memory 196632 kb
Host smart-ce73ca81-6ddd-4c6c-b4c9-ad08e2ce59c4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831838038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.831838038
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3685889889
Short name T62
Test name
Test status
Simulation time 1031650701 ps
CPU time 2.43 seconds
Started Jun 30 04:55:58 PM PDT 24
Finished Jun 30 04:56:01 PM PDT 24
Peak memory 197936 kb
Host smart-4f1e2f7c-fc36-42fe-aa1b-f234f5973940
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685889889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3685889889
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2752032804
Short name T1231
Test name
Test status
Simulation time 153336217 ps
CPU time 0.6 seconds
Started Jun 30 04:55:58 PM PDT 24
Finished Jun 30 04:55:59 PM PDT 24
Peak memory 195760 kb
Host smart-120542a3-1262-40ce-bee5-392e3c039a6a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752032804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2752032804
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1528536037
Short name T1143
Test name
Test status
Simulation time 30594986 ps
CPU time 0.76 seconds
Started Jun 30 04:56:01 PM PDT 24
Finished Jun 30 04:56:03 PM PDT 24
Peak memory 199304 kb
Host smart-87e9e2f3-3709-4786-ba18-4b09e32e6315
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528536037 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1528536037
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.398104553
Short name T58
Test name
Test status
Simulation time 42452570 ps
CPU time 0.64 seconds
Started Jun 30 04:55:59 PM PDT 24
Finished Jun 30 04:56:00 PM PDT 24
Peak memory 195768 kb
Host smart-e498b41e-444c-472c-aa27-a24f414556d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398104553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.398104553
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.1468489993
Short name T1125
Test name
Test status
Simulation time 53306799 ps
CPU time 0.59 seconds
Started Jun 30 04:55:58 PM PDT 24
Finished Jun 30 04:55:59 PM PDT 24
Peak memory 195028 kb
Host smart-64d46b09-0396-4ce5-9f27-b4c014029d7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468489993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1468489993
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1896373955
Short name T1200
Test name
Test status
Simulation time 18033424 ps
CPU time 0.64 seconds
Started Jun 30 04:56:00 PM PDT 24
Finished Jun 30 04:56:01 PM PDT 24
Peak memory 196160 kb
Host smart-530860c8-49ab-4c3e-b5a5-136abf50fa00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896373955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.1896373955
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.1537296067
Short name T1211
Test name
Test status
Simulation time 26583287 ps
CPU time 1.29 seconds
Started Jun 30 04:55:58 PM PDT 24
Finished Jun 30 04:55:59 PM PDT 24
Peak memory 200396 kb
Host smart-5a7c5d33-e24b-4cba-bf07-7fe3664ce998
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537296067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1537296067
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.4070879790
Short name T94
Test name
Test status
Simulation time 78888289 ps
CPU time 0.9 seconds
Started Jun 30 04:56:00 PM PDT 24
Finished Jun 30 04:56:01 PM PDT 24
Peak memory 198940 kb
Host smart-b3d517b6-b1c9-4e1e-a7ff-a28d845154b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070879790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.4070879790
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2291490545
Short name T1132
Test name
Test status
Simulation time 15866296 ps
CPU time 0.82 seconds
Started Jun 30 04:56:22 PM PDT 24
Finished Jun 30 04:56:24 PM PDT 24
Peak memory 200156 kb
Host smart-59a73f6e-622d-48c1-a0d9-ed699e814760
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291490545 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.2291490545
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.1091658451
Short name T1159
Test name
Test status
Simulation time 12426102 ps
CPU time 0.57 seconds
Started Jun 30 04:56:22 PM PDT 24
Finished Jun 30 04:56:23 PM PDT 24
Peak memory 195724 kb
Host smart-bac8f17a-3c74-41e3-910f-adfb5d4a4d75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091658451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.1091658451
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.3360061093
Short name T1190
Test name
Test status
Simulation time 16095911 ps
CPU time 0.6 seconds
Started Jun 30 04:56:20 PM PDT 24
Finished Jun 30 04:56:22 PM PDT 24
Peak memory 194780 kb
Host smart-2102a557-4774-4f6d-bc6e-28b417542aee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360061093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3360061093
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1189992182
Short name T1223
Test name
Test status
Simulation time 23512772 ps
CPU time 0.68 seconds
Started Jun 30 04:56:22 PM PDT 24
Finished Jun 30 04:56:24 PM PDT 24
Peak memory 196284 kb
Host smart-86b852b7-7bee-479f-9964-a3d4847873c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189992182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.1189992182
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3513519646
Short name T1131
Test name
Test status
Simulation time 32081506 ps
CPU time 1.62 seconds
Started Jun 30 04:56:15 PM PDT 24
Finished Jun 30 04:56:17 PM PDT 24
Peak memory 200424 kb
Host smart-87d9534f-5624-4c27-9991-312e053b04cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513519646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3513519646
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.872001047
Short name T1204
Test name
Test status
Simulation time 44908836 ps
CPU time 0.71 seconds
Started Jun 30 04:56:21 PM PDT 24
Finished Jun 30 04:56:22 PM PDT 24
Peak memory 198096 kb
Host smart-d4b3467c-726f-408b-9995-dc5dc2231949
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872001047 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.872001047
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.33679176
Short name T76
Test name
Test status
Simulation time 13739884 ps
CPU time 0.58 seconds
Started Jun 30 04:56:23 PM PDT 24
Finished Jun 30 04:56:25 PM PDT 24
Peak memory 195784 kb
Host smart-ef3aa23a-bf5d-42cb-88f8-06abc8ecf850
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33679176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.33679176
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.3981126680
Short name T1104
Test name
Test status
Simulation time 13569366 ps
CPU time 0.58 seconds
Started Jun 30 04:56:20 PM PDT 24
Finished Jun 30 04:56:21 PM PDT 24
Peak memory 194784 kb
Host smart-15e9f9a5-f3b0-4464-85ed-a8ceb0e60d7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981126680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3981126680
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1814045647
Short name T1147
Test name
Test status
Simulation time 21363147 ps
CPU time 0.61 seconds
Started Jun 30 04:56:22 PM PDT 24
Finished Jun 30 04:56:23 PM PDT 24
Peak memory 196040 kb
Host smart-aae86bf2-d599-46f3-8aa0-447ce61ccf19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814045647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1814045647
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.1156398127
Short name T1154
Test name
Test status
Simulation time 101874947 ps
CPU time 2.16 seconds
Started Jun 30 04:56:20 PM PDT 24
Finished Jun 30 04:56:23 PM PDT 24
Peak memory 200376 kb
Host smart-82244e0c-c6a5-4ee5-8971-6dd5e706c916
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156398127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.1156398127
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.742916395
Short name T92
Test name
Test status
Simulation time 177191931 ps
CPU time 0.92 seconds
Started Jun 30 04:56:23 PM PDT 24
Finished Jun 30 04:56:25 PM PDT 24
Peak memory 199012 kb
Host smart-0d5c6eb7-d70b-4f63-affd-048de65f6798
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742916395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.742916395
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.981181292
Short name T1126
Test name
Test status
Simulation time 17853515 ps
CPU time 0.84 seconds
Started Jun 30 04:56:20 PM PDT 24
Finished Jun 30 04:56:22 PM PDT 24
Peak memory 200176 kb
Host smart-26ea3193-afe7-4a44-ac51-d359fd6a5490
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981181292 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.981181292
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2001211497
Short name T1229
Test name
Test status
Simulation time 15033112 ps
CPU time 0.55 seconds
Started Jun 30 04:56:21 PM PDT 24
Finished Jun 30 04:56:23 PM PDT 24
Peak memory 195796 kb
Host smart-5abe2654-3f47-42ea-8d66-b7d9adbc9e9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001211497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2001211497
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2872250836
Short name T1121
Test name
Test status
Simulation time 43201823 ps
CPU time 0.56 seconds
Started Jun 30 04:56:20 PM PDT 24
Finished Jun 30 04:56:21 PM PDT 24
Peak memory 194704 kb
Host smart-9ada408d-e7c4-4fbc-a61e-cbe04d8bc903
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872250836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2872250836
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1159104776
Short name T77
Test name
Test status
Simulation time 18240980 ps
CPU time 0.64 seconds
Started Jun 30 04:56:23 PM PDT 24
Finished Jun 30 04:56:24 PM PDT 24
Peak memory 196008 kb
Host smart-41f022e5-f94e-4282-bed2-993164e2d3c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159104776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.1159104776
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1221307620
Short name T1184
Test name
Test status
Simulation time 124060369 ps
CPU time 2.28 seconds
Started Jun 30 04:56:19 PM PDT 24
Finished Jun 30 04:56:22 PM PDT 24
Peak memory 200440 kb
Host smart-bfe0a667-dac1-42c3-8602-b989740e9bed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221307620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1221307620
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3592343546
Short name T127
Test name
Test status
Simulation time 279842180 ps
CPU time 0.88 seconds
Started Jun 30 04:56:23 PM PDT 24
Finished Jun 30 04:56:24 PM PDT 24
Peak memory 199260 kb
Host smart-b302f95b-942d-498a-82cb-16662e59bc23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592343546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3592343546
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1457654201
Short name T1113
Test name
Test status
Simulation time 203350778 ps
CPU time 1.05 seconds
Started Jun 30 04:56:22 PM PDT 24
Finished Jun 30 04:56:24 PM PDT 24
Peak memory 200204 kb
Host smart-e520460b-02e2-4cc8-91c2-245587e1e96e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457654201 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1457654201
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.550596156
Short name T1197
Test name
Test status
Simulation time 20194840 ps
CPU time 0.57 seconds
Started Jun 30 04:56:23 PM PDT 24
Finished Jun 30 04:56:24 PM PDT 24
Peak memory 195748 kb
Host smart-c3931f07-ded4-4d06-9586-ef812d812a5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550596156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.550596156
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.859248910
Short name T1165
Test name
Test status
Simulation time 41107691 ps
CPU time 0.58 seconds
Started Jun 30 04:56:20 PM PDT 24
Finished Jun 30 04:56:21 PM PDT 24
Peak memory 194740 kb
Host smart-44ac2133-4bed-44c0-bb39-ca0c9cf8f93d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859248910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.859248910
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3047275076
Short name T1202
Test name
Test status
Simulation time 20838301 ps
CPU time 0.65 seconds
Started Jun 30 04:56:20 PM PDT 24
Finished Jun 30 04:56:22 PM PDT 24
Peak memory 195900 kb
Host smart-18c9710e-f01c-4b89-814e-516b992c2c4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047275076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.3047275076
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3580782242
Short name T1167
Test name
Test status
Simulation time 89350685 ps
CPU time 1.21 seconds
Started Jun 30 04:56:22 PM PDT 24
Finished Jun 30 04:56:24 PM PDT 24
Peak memory 200340 kb
Host smart-281bc6c5-7e87-438f-bd8f-99305df02920
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580782242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3580782242
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2643273975
Short name T88
Test name
Test status
Simulation time 594440345 ps
CPU time 1.23 seconds
Started Jun 30 04:56:25 PM PDT 24
Finished Jun 30 04:56:26 PM PDT 24
Peak memory 199372 kb
Host smart-19ec0163-d170-4de9-be0b-997419997bdc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643273975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2643273975
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.123349694
Short name T1112
Test name
Test status
Simulation time 96225852 ps
CPU time 0.81 seconds
Started Jun 30 04:56:22 PM PDT 24
Finished Jun 30 04:56:24 PM PDT 24
Peak memory 200132 kb
Host smart-72040104-ae12-49da-8728-c97dd1b8df80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123349694 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.123349694
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.2165023881
Short name T1187
Test name
Test status
Simulation time 18567047 ps
CPU time 0.56 seconds
Started Jun 30 04:56:20 PM PDT 24
Finished Jun 30 04:56:22 PM PDT 24
Peak memory 195720 kb
Host smart-42d67ad7-69a2-4756-94a3-c6c2e27caef7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165023881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2165023881
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.474251223
Short name T1106
Test name
Test status
Simulation time 24408762 ps
CPU time 0.57 seconds
Started Jun 30 04:56:23 PM PDT 24
Finished Jun 30 04:56:24 PM PDT 24
Peak memory 194780 kb
Host smart-caf84697-8c7a-4c69-b39d-9dd979bfb580
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474251223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.474251223
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3994205777
Short name T79
Test name
Test status
Simulation time 122547665 ps
CPU time 0.74 seconds
Started Jun 30 04:56:23 PM PDT 24
Finished Jun 30 04:56:24 PM PDT 24
Peak memory 197308 kb
Host smart-05f71ce4-1da3-4c45-a06f-2395f8d3775b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994205777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.3994205777
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1123791115
Short name T1118
Test name
Test status
Simulation time 23997263 ps
CPU time 1.21 seconds
Started Jun 30 04:56:20 PM PDT 24
Finished Jun 30 04:56:22 PM PDT 24
Peak memory 200408 kb
Host smart-a8a5e7dc-7201-4d0a-98d3-34c025f45486
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123791115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1123791115
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2697871166
Short name T96
Test name
Test status
Simulation time 137011999 ps
CPU time 1.27 seconds
Started Jun 30 04:56:19 PM PDT 24
Finished Jun 30 04:56:21 PM PDT 24
Peak memory 199664 kb
Host smart-917e26d3-d06c-41cf-8493-198c98537bd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697871166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.2697871166
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.676621877
Short name T1161
Test name
Test status
Simulation time 45860019 ps
CPU time 0.79 seconds
Started Jun 30 04:56:28 PM PDT 24
Finished Jun 30 04:56:29 PM PDT 24
Peak memory 198612 kb
Host smart-58a81c89-ec64-4820-85aa-f61c3ad6730b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676621877 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.676621877
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1883332493
Short name T1198
Test name
Test status
Simulation time 21560755 ps
CPU time 0.6 seconds
Started Jun 30 04:56:27 PM PDT 24
Finished Jun 30 04:56:27 PM PDT 24
Peak memory 195820 kb
Host smart-e5ba0cf6-1a41-4c44-9e54-9f4a6792a0dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883332493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1883332493
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.3826582847
Short name T1178
Test name
Test status
Simulation time 25606351 ps
CPU time 0.58 seconds
Started Jun 30 04:56:28 PM PDT 24
Finished Jun 30 04:56:29 PM PDT 24
Peak memory 194744 kb
Host smart-6ed091f3-0873-436c-b112-f4ea6dcabcc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826582847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3826582847
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.705498722
Short name T1166
Test name
Test status
Simulation time 25662166 ps
CPU time 0.69 seconds
Started Jun 30 04:56:28 PM PDT 24
Finished Jun 30 04:56:30 PM PDT 24
Peak memory 197132 kb
Host smart-f0a55062-4386-49ed-ae0d-c1c06b7e3cdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705498722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr
_outstanding.705498722
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.2286721195
Short name T1183
Test name
Test status
Simulation time 58262822 ps
CPU time 1.34 seconds
Started Jun 30 04:56:30 PM PDT 24
Finished Jun 30 04:56:32 PM PDT 24
Peak memory 200384 kb
Host smart-0637cfad-1dc3-4f18-ae70-4f15bcb76508
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286721195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2286721195
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3818766022
Short name T1173
Test name
Test status
Simulation time 53747924 ps
CPU time 0.65 seconds
Started Jun 30 04:56:31 PM PDT 24
Finished Jun 30 04:56:32 PM PDT 24
Peak memory 197960 kb
Host smart-185a70cf-200f-47b1-8bad-8022669210d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818766022 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.3818766022
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.2148748493
Short name T1218
Test name
Test status
Simulation time 26035226 ps
CPU time 0.58 seconds
Started Jun 30 04:56:27 PM PDT 24
Finished Jun 30 04:56:28 PM PDT 24
Peak memory 195760 kb
Host smart-6701a8ab-d7ec-4225-9984-3492303ff464
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148748493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.2148748493
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.3443138416
Short name T1117
Test name
Test status
Simulation time 34741477 ps
CPU time 0.56 seconds
Started Jun 30 04:56:29 PM PDT 24
Finished Jun 30 04:56:31 PM PDT 24
Peak memory 194692 kb
Host smart-4430fd83-8445-4476-9cd3-923e2bc7b25a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443138416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3443138416
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.218050570
Short name T75
Test name
Test status
Simulation time 66248966 ps
CPU time 0.71 seconds
Started Jun 30 04:56:29 PM PDT 24
Finished Jun 30 04:56:31 PM PDT 24
Peak memory 197148 kb
Host smart-ddfdae1f-f696-46d9-a05e-ce7067c042b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218050570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr
_outstanding.218050570
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.3102684004
Short name T1110
Test name
Test status
Simulation time 89301524 ps
CPU time 1.26 seconds
Started Jun 30 04:56:28 PM PDT 24
Finished Jun 30 04:56:30 PM PDT 24
Peak memory 200276 kb
Host smart-d6950e5b-9782-4746-822e-47d5ffc407b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102684004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3102684004
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2748451216
Short name T128
Test name
Test status
Simulation time 98689996 ps
CPU time 0.89 seconds
Started Jun 30 04:56:31 PM PDT 24
Finished Jun 30 04:56:32 PM PDT 24
Peak memory 198868 kb
Host smart-145de9f2-c1b0-490d-9366-e45be0454c51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748451216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2748451216
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3237414988
Short name T1155
Test name
Test status
Simulation time 30330950 ps
CPU time 0.85 seconds
Started Jun 30 04:56:29 PM PDT 24
Finished Jun 30 04:56:31 PM PDT 24
Peak memory 200196 kb
Host smart-36553581-7c60-48a7-9479-617a9d34af66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237414988 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.3237414988
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.1052185871
Short name T80
Test name
Test status
Simulation time 20391524 ps
CPU time 0.61 seconds
Started Jun 30 04:56:28 PM PDT 24
Finished Jun 30 04:56:30 PM PDT 24
Peak memory 195764 kb
Host smart-997ddbb0-0628-4db2-b721-fc5b6b94e454
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052185871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.1052185871
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.2749898280
Short name T1164
Test name
Test status
Simulation time 17926177 ps
CPU time 0.63 seconds
Started Jun 30 04:56:27 PM PDT 24
Finished Jun 30 04:56:28 PM PDT 24
Peak memory 194796 kb
Host smart-e3dc0f0f-cc7a-404e-aa10-c6b3f8b9aa15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749898280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2749898280
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2529481688
Short name T1194
Test name
Test status
Simulation time 30201123 ps
CPU time 0.78 seconds
Started Jun 30 04:56:31 PM PDT 24
Finished Jun 30 04:56:32 PM PDT 24
Peak memory 197412 kb
Host smart-d1bb0785-d769-4be9-a2fb-f15407d52153
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529481688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2529481688
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.1467777812
Short name T1213
Test name
Test status
Simulation time 174096698 ps
CPU time 1.04 seconds
Started Jun 30 04:56:30 PM PDT 24
Finished Jun 30 04:56:31 PM PDT 24
Peak memory 200152 kb
Host smart-c3db74b6-481e-4d8b-8d68-d813bf1b8a3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467777812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1467777812
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3481418567
Short name T1228
Test name
Test status
Simulation time 1086641963 ps
CPU time 1.3 seconds
Started Jun 30 04:56:30 PM PDT 24
Finished Jun 30 04:56:32 PM PDT 24
Peak memory 199576 kb
Host smart-bcc85549-9004-4002-96e4-37de7f48c8db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481418567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3481418567
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2949512840
Short name T1119
Test name
Test status
Simulation time 19677221 ps
CPU time 0.71 seconds
Started Jun 30 04:56:28 PM PDT 24
Finished Jun 30 04:56:29 PM PDT 24
Peak memory 197620 kb
Host smart-801cd7df-0f90-4ecd-b977-bacb93784566
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949512840 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.2949512840
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3033890356
Short name T1193
Test name
Test status
Simulation time 52256184 ps
CPU time 0.58 seconds
Started Jun 30 04:56:28 PM PDT 24
Finished Jun 30 04:56:28 PM PDT 24
Peak memory 194804 kb
Host smart-41e87e76-7d29-414f-a165-c74efacdc2e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033890356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3033890356
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3783059718
Short name T1152
Test name
Test status
Simulation time 87830667 ps
CPU time 0.72 seconds
Started Jun 30 04:56:28 PM PDT 24
Finished Jun 30 04:56:29 PM PDT 24
Peak memory 197152 kb
Host smart-1c32bd1f-405c-48a6-b72d-7309f6ce511c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783059718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3783059718
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2972233206
Short name T1107
Test name
Test status
Simulation time 253072602 ps
CPU time 2.21 seconds
Started Jun 30 04:56:31 PM PDT 24
Finished Jun 30 04:56:34 PM PDT 24
Peak memory 200400 kb
Host smart-b5eb0c18-45b1-4b5f-9a77-ba07123aca0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972233206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2972233206
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1214631599
Short name T1207
Test name
Test status
Simulation time 93507814 ps
CPU time 1.39 seconds
Started Jun 30 04:56:28 PM PDT 24
Finished Jun 30 04:56:30 PM PDT 24
Peak memory 199720 kb
Host smart-c3e001bb-3772-42a6-bdb5-1f6f3dd5d8d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214631599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1214631599
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.413496848
Short name T1140
Test name
Test status
Simulation time 79641596 ps
CPU time 0.79 seconds
Started Jun 30 04:56:34 PM PDT 24
Finished Jun 30 04:56:36 PM PDT 24
Peak memory 199804 kb
Host smart-42d37b09-e900-479f-bd66-303d3684b563
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413496848 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.413496848
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1124480940
Short name T54
Test name
Test status
Simulation time 42155915 ps
CPU time 0.59 seconds
Started Jun 30 04:56:29 PM PDT 24
Finished Jun 30 04:56:30 PM PDT 24
Peak memory 195796 kb
Host smart-f7bfd431-00a0-472c-9e4f-5022ce401cfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124480940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1124480940
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.3415627057
Short name T1123
Test name
Test status
Simulation time 44974408 ps
CPU time 0.54 seconds
Started Jun 30 04:56:29 PM PDT 24
Finished Jun 30 04:56:31 PM PDT 24
Peak memory 194704 kb
Host smart-dc1fbcc8-f2b6-48a0-adb7-184e3ebddb1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415627057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3415627057
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.81502628
Short name T1171
Test name
Test status
Simulation time 170950340 ps
CPU time 0.79 seconds
Started Jun 30 04:56:30 PM PDT 24
Finished Jun 30 04:56:32 PM PDT 24
Peak memory 196488 kb
Host smart-3a880945-a501-4b42-8d81-0f4c3834c25f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81502628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr_
outstanding.81502628
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.579956788
Short name T1102
Test name
Test status
Simulation time 230533063 ps
CPU time 1.2 seconds
Started Jun 30 04:56:29 PM PDT 24
Finished Jun 30 04:56:30 PM PDT 24
Peak memory 200428 kb
Host smart-606bc8d5-1dc0-4338-95ca-cff8e79c3d9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579956788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.579956788
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2271842338
Short name T87
Test name
Test status
Simulation time 541408579 ps
CPU time 0.9 seconds
Started Jun 30 04:56:28 PM PDT 24
Finished Jun 30 04:56:30 PM PDT 24
Peak memory 199364 kb
Host smart-4bbfbdb5-0e9d-4047-afb8-88513a1862a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271842338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2271842338
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2244365320
Short name T1162
Test name
Test status
Simulation time 35032374 ps
CPU time 0.69 seconds
Started Jun 30 04:56:00 PM PDT 24
Finished Jun 30 04:56:01 PM PDT 24
Peak memory 195292 kb
Host smart-af120d67-f28b-4097-8f45-4da5befe7628
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244365320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2244365320
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3335359857
Short name T1169
Test name
Test status
Simulation time 62422834 ps
CPU time 1.44 seconds
Started Jun 30 04:56:00 PM PDT 24
Finished Jun 30 04:56:02 PM PDT 24
Peak memory 198264 kb
Host smart-07794e72-e6ee-4bfb-be6f-e688cf7a461b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335359857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3335359857
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2843494663
Short name T1215
Test name
Test status
Simulation time 15053324 ps
CPU time 0.63 seconds
Started Jun 30 04:55:59 PM PDT 24
Finished Jun 30 04:56:00 PM PDT 24
Peak memory 195788 kb
Host smart-e066d20e-2be3-405a-a509-796bf710849f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843494663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2843494663
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2476505834
Short name T1141
Test name
Test status
Simulation time 69770600 ps
CPU time 0.68 seconds
Started Jun 30 04:55:58 PM PDT 24
Finished Jun 30 04:55:59 PM PDT 24
Peak memory 198168 kb
Host smart-5c4015e3-1b47-49d3-ad32-aef1da7c352a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476505834 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.2476505834
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.2306090098
Short name T1196
Test name
Test status
Simulation time 48471569 ps
CPU time 0.59 seconds
Started Jun 30 04:55:59 PM PDT 24
Finished Jun 30 04:56:00 PM PDT 24
Peak memory 195784 kb
Host smart-f39dd7df-5314-43eb-bfe2-034a6434d45f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306090098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2306090098
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.2925734186
Short name T1114
Test name
Test status
Simulation time 14320189 ps
CPU time 0.6 seconds
Started Jun 30 04:55:58 PM PDT 24
Finished Jun 30 04:55:59 PM PDT 24
Peak memory 194740 kb
Host smart-206feb4d-0a4c-41d4-9ac5-4e27bae1d0b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925734186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2925734186
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1841636702
Short name T1221
Test name
Test status
Simulation time 33678736 ps
CPU time 0.77 seconds
Started Jun 30 04:56:01 PM PDT 24
Finished Jun 30 04:56:02 PM PDT 24
Peak memory 196468 kb
Host smart-35df5979-1adb-4d2e-9ea5-172baeef5750
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841636702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.1841636702
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.3672783444
Short name T1206
Test name
Test status
Simulation time 383046242 ps
CPU time 1.95 seconds
Started Jun 30 04:56:00 PM PDT 24
Finished Jun 30 04:56:02 PM PDT 24
Peak memory 200440 kb
Host smart-5fb509fc-5fe5-46dd-9f76-d6bbd079f5b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672783444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.3672783444
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.784531146
Short name T91
Test name
Test status
Simulation time 362143326 ps
CPU time 0.9 seconds
Started Jun 30 04:56:00 PM PDT 24
Finished Jun 30 04:56:01 PM PDT 24
Peak memory 199140 kb
Host smart-e14a6462-9825-4ebb-aa4a-6852d19f5d2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784531146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.784531146
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.497004864
Short name T1115
Test name
Test status
Simulation time 13754520 ps
CPU time 0.6 seconds
Started Jun 30 04:56:37 PM PDT 24
Finished Jun 30 04:56:38 PM PDT 24
Peak memory 194716 kb
Host smart-befd3db6-6035-4c66-9ead-5f94c55578fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497004864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.497004864
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.2144623688
Short name T1188
Test name
Test status
Simulation time 143865590 ps
CPU time 0.55 seconds
Started Jun 30 04:56:36 PM PDT 24
Finished Jun 30 04:56:37 PM PDT 24
Peak memory 194604 kb
Host smart-5637f9b6-540b-4333-97b5-8f059395487e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144623688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2144623688
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.176506804
Short name T1227
Test name
Test status
Simulation time 35378110 ps
CPU time 0.59 seconds
Started Jun 30 04:56:35 PM PDT 24
Finished Jun 30 04:56:36 PM PDT 24
Peak memory 194776 kb
Host smart-64e5e00d-dfa6-4191-aa46-f84db2d9a2fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176506804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.176506804
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2217947989
Short name T1151
Test name
Test status
Simulation time 53595449 ps
CPU time 0.56 seconds
Started Jun 30 04:56:33 PM PDT 24
Finished Jun 30 04:56:34 PM PDT 24
Peak memory 194788 kb
Host smart-3c4eae1a-358b-4759-8df5-9be6196977fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217947989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2217947989
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.740750055
Short name T1220
Test name
Test status
Simulation time 14076621 ps
CPU time 0.55 seconds
Started Jun 30 04:56:34 PM PDT 24
Finished Jun 30 04:56:34 PM PDT 24
Peak memory 194580 kb
Host smart-bf00923a-79a8-4534-b583-9f4b583a1afb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740750055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.740750055
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.2108878718
Short name T1189
Test name
Test status
Simulation time 14379679 ps
CPU time 0.57 seconds
Started Jun 30 04:56:33 PM PDT 24
Finished Jun 30 04:56:34 PM PDT 24
Peak memory 194764 kb
Host smart-22192916-d479-4ea0-a345-eadbb76d3e04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108878718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2108878718
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.4080644366
Short name T1120
Test name
Test status
Simulation time 15950907 ps
CPU time 0.61 seconds
Started Jun 30 04:56:36 PM PDT 24
Finished Jun 30 04:56:37 PM PDT 24
Peak memory 194772 kb
Host smart-10fa204f-4e2b-4f9f-84a5-323cb8650d66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080644366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.4080644366
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.1971558229
Short name T1136
Test name
Test status
Simulation time 32419649 ps
CPU time 0.57 seconds
Started Jun 30 04:56:36 PM PDT 24
Finished Jun 30 04:56:37 PM PDT 24
Peak memory 194708 kb
Host smart-02592b8a-8f36-4035-865c-65b09a45f77f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971558229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1971558229
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.3091874580
Short name T1128
Test name
Test status
Simulation time 41801316 ps
CPU time 0.57 seconds
Started Jun 30 04:56:36 PM PDT 24
Finished Jun 30 04:56:37 PM PDT 24
Peak memory 194676 kb
Host smart-e384e7e0-7420-414c-ba68-266c4355e3cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091874580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3091874580
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.840302969
Short name T1148
Test name
Test status
Simulation time 42164387 ps
CPU time 0.56 seconds
Started Jun 30 04:56:33 PM PDT 24
Finished Jun 30 04:56:33 PM PDT 24
Peak memory 194716 kb
Host smart-ca7da3a4-391b-4328-8e23-d47968a4eead
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840302969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.840302969
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3750990265
Short name T64
Test name
Test status
Simulation time 71635525 ps
CPU time 0.65 seconds
Started Jun 30 04:56:05 PM PDT 24
Finished Jun 30 04:56:05 PM PDT 24
Peak memory 195324 kb
Host smart-181d9782-00e5-46c1-bc4d-1c8114bb5590
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750990265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3750990265
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.121400876
Short name T1209
Test name
Test status
Simulation time 932072050 ps
CPU time 2.59 seconds
Started Jun 30 04:56:07 PM PDT 24
Finished Jun 30 04:56:10 PM PDT 24
Peak memory 198240 kb
Host smart-4f6c2da6-cead-4444-8890-a0fa520dd824
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121400876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.121400876
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3433202435
Short name T1130
Test name
Test status
Simulation time 43250893 ps
CPU time 0.62 seconds
Started Jun 30 04:56:06 PM PDT 24
Finished Jun 30 04:56:07 PM PDT 24
Peak memory 195784 kb
Host smart-13f02c17-eb1a-4f3d-9c6e-819918852b46
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433202435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3433202435
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1047393512
Short name T1181
Test name
Test status
Simulation time 52761121 ps
CPU time 0.88 seconds
Started Jun 30 04:56:06 PM PDT 24
Finished Jun 30 04:56:07 PM PDT 24
Peak memory 200204 kb
Host smart-44aa5cae-dc57-4736-86aa-4c77a2ed4e0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047393512 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.1047393512
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.1846362452
Short name T59
Test name
Test status
Simulation time 43214206 ps
CPU time 0.59 seconds
Started Jun 30 04:56:06 PM PDT 24
Finished Jun 30 04:56:07 PM PDT 24
Peak memory 195780 kb
Host smart-9e3fa396-96f2-4e1b-b121-8316f544bdd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846362452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.1846362452
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.1173023697
Short name T1129
Test name
Test status
Simulation time 46393249 ps
CPU time 0.56 seconds
Started Jun 30 04:56:06 PM PDT 24
Finished Jun 30 04:56:07 PM PDT 24
Peak memory 194784 kb
Host smart-0f3c3e39-1586-48cf-9522-761915a4eb01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173023697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1173023697
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.227381842
Short name T1153
Test name
Test status
Simulation time 68393090 ps
CPU time 0.67 seconds
Started Jun 30 04:56:06 PM PDT 24
Finished Jun 30 04:56:07 PM PDT 24
Peak memory 196872 kb
Host smart-e08d3ff6-92ce-4ae4-a2f1-30947255596a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227381842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_
outstanding.227381842
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2544011978
Short name T1214
Test name
Test status
Simulation time 175529466 ps
CPU time 1.65 seconds
Started Jun 30 04:56:00 PM PDT 24
Finished Jun 30 04:56:02 PM PDT 24
Peak memory 200348 kb
Host smart-b2d596e1-fcd6-49d4-b437-58b89ce0d0de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544011978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2544011978
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3533259766
Short name T1150
Test name
Test status
Simulation time 65453382 ps
CPU time 1.3 seconds
Started Jun 30 04:56:01 PM PDT 24
Finished Jun 30 04:56:03 PM PDT 24
Peak memory 199536 kb
Host smart-c45d4c94-e888-4901-b99d-04fe0bb08fc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533259766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3533259766
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.1996202967
Short name T1158
Test name
Test status
Simulation time 15603798 ps
CPU time 0.57 seconds
Started Jun 30 04:56:34 PM PDT 24
Finished Jun 30 04:56:35 PM PDT 24
Peak memory 194740 kb
Host smart-852d14da-ba4b-4c92-aa70-98a505aaf4ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996202967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1996202967
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.702997077
Short name T1108
Test name
Test status
Simulation time 15568761 ps
CPU time 0.57 seconds
Started Jun 30 04:56:33 PM PDT 24
Finished Jun 30 04:56:34 PM PDT 24
Peak memory 194748 kb
Host smart-ed6c5b33-abfd-4eab-b04d-822c7fb5f98c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702997077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.702997077
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.2045082719
Short name T1135
Test name
Test status
Simulation time 205631092 ps
CPU time 0.58 seconds
Started Jun 30 04:56:36 PM PDT 24
Finished Jun 30 04:56:37 PM PDT 24
Peak memory 194740 kb
Host smart-cb40d2da-433d-43fd-bb26-0faafa5249b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045082719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2045082719
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.579952329
Short name T1137
Test name
Test status
Simulation time 44328880 ps
CPU time 0.57 seconds
Started Jun 30 04:56:36 PM PDT 24
Finished Jun 30 04:56:37 PM PDT 24
Peak memory 194640 kb
Host smart-8f51daae-430e-4a4e-958e-05cf0420d12f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579952329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.579952329
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.474636462
Short name T1160
Test name
Test status
Simulation time 14876365 ps
CPU time 0.58 seconds
Started Jun 30 04:56:36 PM PDT 24
Finished Jun 30 04:56:38 PM PDT 24
Peak memory 194672 kb
Host smart-f773236a-8339-4fc0-9961-8ad5e004f1a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474636462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.474636462
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1133647173
Short name T1182
Test name
Test status
Simulation time 15361156 ps
CPU time 0.57 seconds
Started Jun 30 04:56:36 PM PDT 24
Finished Jun 30 04:56:38 PM PDT 24
Peak memory 194668 kb
Host smart-a9e7f4c7-16c5-4fb6-9f80-e0e519bd9cd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133647173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1133647173
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2754131410
Short name T1217
Test name
Test status
Simulation time 14300568 ps
CPU time 0.56 seconds
Started Jun 30 04:56:35 PM PDT 24
Finished Jun 30 04:56:36 PM PDT 24
Peak memory 194684 kb
Host smart-acb8ba77-942b-4ef2-b933-7322132df13a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754131410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2754131410
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1423504421
Short name T1163
Test name
Test status
Simulation time 42490032 ps
CPU time 0.55 seconds
Started Jun 30 04:56:34 PM PDT 24
Finished Jun 30 04:56:34 PM PDT 24
Peak memory 194732 kb
Host smart-dc2163fd-719f-4daf-a4b1-c20fb48663a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423504421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1423504421
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.3964314777
Short name T1116
Test name
Test status
Simulation time 25531099 ps
CPU time 0.59 seconds
Started Jun 30 04:56:34 PM PDT 24
Finished Jun 30 04:56:35 PM PDT 24
Peak memory 194756 kb
Host smart-03a30202-bbc3-46f9-8186-35085ecd2e63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964314777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3964314777
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.975569535
Short name T1195
Test name
Test status
Simulation time 14135739 ps
CPU time 0.59 seconds
Started Jun 30 04:56:36 PM PDT 24
Finished Jun 30 04:56:37 PM PDT 24
Peak memory 194772 kb
Host smart-e220de24-7b65-4eb7-b35b-7fe0f997c3b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975569535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.975569535
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2378102358
Short name T1101
Test name
Test status
Simulation time 99814084 ps
CPU time 0.78 seconds
Started Jun 30 04:56:06 PM PDT 24
Finished Jun 30 04:56:07 PM PDT 24
Peak memory 196784 kb
Host smart-3c4e69a0-04a2-41b6-bd4f-9670a20f5f06
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378102358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2378102358
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2050872848
Short name T61
Test name
Test status
Simulation time 227786446 ps
CPU time 2.22 seconds
Started Jun 30 04:56:06 PM PDT 24
Finished Jun 30 04:56:09 PM PDT 24
Peak memory 198064 kb
Host smart-b511f1ae-a7b1-4205-867b-3be62fd00552
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050872848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.2050872848
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.157514629
Short name T55
Test name
Test status
Simulation time 69438784 ps
CPU time 0.58 seconds
Started Jun 30 04:56:07 PM PDT 24
Finished Jun 30 04:56:08 PM PDT 24
Peak memory 195792 kb
Host smart-34671c56-46e3-477f-b642-696775d38ebf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157514629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.157514629
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2010724145
Short name T1127
Test name
Test status
Simulation time 54896729 ps
CPU time 0.85 seconds
Started Jun 30 04:56:08 PM PDT 24
Finished Jun 30 04:56:09 PM PDT 24
Peak memory 200184 kb
Host smart-dab29a64-027d-4c27-8788-eebf8c96df25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010724145 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2010724145
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2964606005
Short name T63
Test name
Test status
Simulation time 18323235 ps
CPU time 0.57 seconds
Started Jun 30 04:56:07 PM PDT 24
Finished Jun 30 04:56:08 PM PDT 24
Peak memory 195796 kb
Host smart-8daf0a33-ee83-4274-b722-0bf3473b306b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964606005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2964606005
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.1851314984
Short name T1157
Test name
Test status
Simulation time 10902606 ps
CPU time 0.56 seconds
Started Jun 30 04:56:06 PM PDT 24
Finished Jun 30 04:56:07 PM PDT 24
Peak memory 194680 kb
Host smart-abf9f7aa-228a-4a5b-9d31-3dde33b0196e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851314984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.1851314984
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2978718047
Short name T81
Test name
Test status
Simulation time 19261755 ps
CPU time 0.64 seconds
Started Jun 30 04:56:06 PM PDT 24
Finished Jun 30 04:56:07 PM PDT 24
Peak memory 196004 kb
Host smart-5031f432-c796-4d3a-9dd2-0052bced0857
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978718047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.2978718047
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.1941271446
Short name T1205
Test name
Test status
Simulation time 39558450 ps
CPU time 1.79 seconds
Started Jun 30 04:56:06 PM PDT 24
Finished Jun 30 04:56:08 PM PDT 24
Peak memory 200424 kb
Host smart-0ed2841b-57af-4881-bcc1-53edae248645
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941271446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1941271446
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3010804523
Short name T93
Test name
Test status
Simulation time 375285251 ps
CPU time 0.99 seconds
Started Jun 30 04:56:05 PM PDT 24
Finished Jun 30 04:56:06 PM PDT 24
Peak memory 199400 kb
Host smart-550f8e9d-ff8d-47fb-bc64-2fb2da9257ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010804523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3010804523
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.1779341516
Short name T1180
Test name
Test status
Simulation time 11815286 ps
CPU time 0.59 seconds
Started Jun 30 04:56:35 PM PDT 24
Finished Jun 30 04:56:36 PM PDT 24
Peak memory 194752 kb
Host smart-a5e0a9d8-2c2f-40e3-b431-95732d5da042
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779341516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1779341516
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.4274248255
Short name T1139
Test name
Test status
Simulation time 43309684 ps
CPU time 0.56 seconds
Started Jun 30 04:56:34 PM PDT 24
Finished Jun 30 04:56:35 PM PDT 24
Peak memory 194676 kb
Host smart-92364562-650c-4921-a766-c4747a845139
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274248255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.4274248255
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.3817726487
Short name T1122
Test name
Test status
Simulation time 12758867 ps
CPU time 0.55 seconds
Started Jun 30 04:56:34 PM PDT 24
Finished Jun 30 04:56:36 PM PDT 24
Peak memory 194640 kb
Host smart-b02eabe4-cb14-45df-916e-6a5e2ecfa260
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817726487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.3817726487
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.2191392629
Short name T1111
Test name
Test status
Simulation time 40235527 ps
CPU time 0.56 seconds
Started Jun 30 04:56:34 PM PDT 24
Finished Jun 30 04:56:35 PM PDT 24
Peak memory 194664 kb
Host smart-1805930b-ca69-488b-bdc3-6e6381e1e925
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191392629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2191392629
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.2052565405
Short name T1225
Test name
Test status
Simulation time 16554675 ps
CPU time 0.61 seconds
Started Jun 30 04:56:34 PM PDT 24
Finished Jun 30 04:56:36 PM PDT 24
Peak memory 194756 kb
Host smart-21e7355b-4381-4acf-89f6-7f3fc917daea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052565405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2052565405
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.4134797636
Short name T1109
Test name
Test status
Simulation time 44285732 ps
CPU time 0.61 seconds
Started Jun 30 04:56:33 PM PDT 24
Finished Jun 30 04:56:34 PM PDT 24
Peak memory 194784 kb
Host smart-001eb33a-a62c-44a5-b914-39be291ecd2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134797636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.4134797636
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.3928215522
Short name T1179
Test name
Test status
Simulation time 47072873 ps
CPU time 0.57 seconds
Started Jun 30 04:56:36 PM PDT 24
Finished Jun 30 04:56:37 PM PDT 24
Peak memory 194676 kb
Host smart-a9dbae97-28c8-44a6-ae75-14d3575ac394
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928215522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3928215522
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.3347849066
Short name T1222
Test name
Test status
Simulation time 16304391 ps
CPU time 0.59 seconds
Started Jun 30 04:56:40 PM PDT 24
Finished Jun 30 04:56:41 PM PDT 24
Peak memory 194744 kb
Host smart-1d01f4a2-da8f-40a9-bbc2-eeb60d0c06ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347849066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3347849066
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.1979082523
Short name T1170
Test name
Test status
Simulation time 26466008 ps
CPU time 0.56 seconds
Started Jun 30 04:56:44 PM PDT 24
Finished Jun 30 04:56:45 PM PDT 24
Peak memory 194664 kb
Host smart-3dece196-e7fa-43d7-aff5-b4fb02eb7157
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979082523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.1979082523
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.759530383
Short name T1144
Test name
Test status
Simulation time 12940741 ps
CPU time 0.57 seconds
Started Jun 30 04:56:39 PM PDT 24
Finished Jun 30 04:56:40 PM PDT 24
Peak memory 195016 kb
Host smart-25e36354-c932-43b6-b429-5487717199f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759530383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.759530383
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3417376277
Short name T1138
Test name
Test status
Simulation time 119860172 ps
CPU time 0.92 seconds
Started Jun 30 04:56:12 PM PDT 24
Finished Jun 30 04:56:14 PM PDT 24
Peak memory 200212 kb
Host smart-ff47283d-f71c-4782-a1f3-ae2a1c9422b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417376277 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3417376277
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.3709060582
Short name T1191
Test name
Test status
Simulation time 155924923 ps
CPU time 0.6 seconds
Started Jun 30 04:56:06 PM PDT 24
Finished Jun 30 04:56:07 PM PDT 24
Peak memory 195948 kb
Host smart-788e80dc-5348-4dcf-815d-8a29bc42dee3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709060582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3709060582
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3603566017
Short name T1177
Test name
Test status
Simulation time 43152496 ps
CPU time 0.55 seconds
Started Jun 30 04:56:05 PM PDT 24
Finished Jun 30 04:56:06 PM PDT 24
Peak memory 194672 kb
Host smart-17bec68d-5d6e-4c63-a921-81f0ce3ef158
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603566017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3603566017
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.1075826996
Short name T1185
Test name
Test status
Simulation time 16225413 ps
CPU time 0.73 seconds
Started Jun 30 04:56:12 PM PDT 24
Finished Jun 30 04:56:13 PM PDT 24
Peak memory 197324 kb
Host smart-68696ab8-e8de-4b9e-9ec8-2796012d5d41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075826996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.1075826996
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.1248794976
Short name T1219
Test name
Test status
Simulation time 31477345 ps
CPU time 1.48 seconds
Started Jun 30 04:56:05 PM PDT 24
Finished Jun 30 04:56:06 PM PDT 24
Peak memory 200432 kb
Host smart-e9e86687-5407-4c58-ad86-c98ccaa32bc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248794976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1248794976
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2291843100
Short name T1156
Test name
Test status
Simulation time 65676797 ps
CPU time 0.94 seconds
Started Jun 30 04:56:06 PM PDT 24
Finished Jun 30 04:56:08 PM PDT 24
Peak memory 199208 kb
Host smart-435293ca-3f9b-4d65-b341-571764c9df77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291843100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.2291843100
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2351943868
Short name T1210
Test name
Test status
Simulation time 64683292 ps
CPU time 0.75 seconds
Started Jun 30 04:56:13 PM PDT 24
Finished Jun 30 04:56:14 PM PDT 24
Peak memory 198580 kb
Host smart-b77375e8-62ac-4519-9ea3-8bc2af11be5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351943868 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.2351943868
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.1715495708
Short name T1201
Test name
Test status
Simulation time 219842493 ps
CPU time 0.61 seconds
Started Jun 30 04:56:13 PM PDT 24
Finished Jun 30 04:56:15 PM PDT 24
Peak memory 195844 kb
Host smart-a103e329-17b3-497a-8f39-b35b331b343d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715495708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1715495708
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1463221127
Short name T1142
Test name
Test status
Simulation time 78482438 ps
CPU time 0.57 seconds
Started Jun 30 04:56:13 PM PDT 24
Finished Jun 30 04:56:15 PM PDT 24
Peak memory 194772 kb
Host smart-9e95d6e8-b9b5-47a9-94b0-7726c6223221
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463221127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1463221127
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1186636476
Short name T82
Test name
Test status
Simulation time 17662118 ps
CPU time 0.73 seconds
Started Jun 30 04:56:13 PM PDT 24
Finished Jun 30 04:56:14 PM PDT 24
Peak memory 197180 kb
Host smart-fa74ce69-dc69-4df4-a069-fbc82ca0dd34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186636476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.1186636476
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1128367635
Short name T1105
Test name
Test status
Simulation time 157316043 ps
CPU time 2.57 seconds
Started Jun 30 04:56:13 PM PDT 24
Finished Jun 30 04:56:17 PM PDT 24
Peak memory 200384 kb
Host smart-32b2b386-455a-4497-923b-0284f035e010
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128367635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1128367635
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3974035279
Short name T1224
Test name
Test status
Simulation time 47344767 ps
CPU time 0.92 seconds
Started Jun 30 04:56:12 PM PDT 24
Finished Jun 30 04:56:13 PM PDT 24
Peak memory 199412 kb
Host smart-3d4004b7-4bb2-4007-a17f-f192e5024607
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974035279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3974035279
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1250166838
Short name T1103
Test name
Test status
Simulation time 87818390 ps
CPU time 0.79 seconds
Started Jun 30 04:56:16 PM PDT 24
Finished Jun 30 04:56:17 PM PDT 24
Peak memory 199136 kb
Host smart-c9bf5905-b3e8-498f-bdfd-f28ae3efad54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250166838 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.1250166838
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.3445017176
Short name T1186
Test name
Test status
Simulation time 27001804 ps
CPU time 0.61 seconds
Started Jun 30 04:56:13 PM PDT 24
Finished Jun 30 04:56:15 PM PDT 24
Peak memory 195844 kb
Host smart-91858dbb-d38d-40b1-bea8-60f31e857608
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445017176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3445017176
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1645734430
Short name T1145
Test name
Test status
Simulation time 12976836 ps
CPU time 0.55 seconds
Started Jun 30 04:56:13 PM PDT 24
Finished Jun 30 04:56:14 PM PDT 24
Peak memory 194772 kb
Host smart-6b3d4082-4d76-411f-b518-5c1e4e69109a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645734430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1645734430
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1508208903
Short name T1216
Test name
Test status
Simulation time 35494394 ps
CPU time 0.66 seconds
Started Jun 30 04:56:16 PM PDT 24
Finished Jun 30 04:56:17 PM PDT 24
Peak memory 196804 kb
Host smart-1959f6f6-be90-498d-8426-db689d9429d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508208903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1508208903
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.3160397491
Short name T1149
Test name
Test status
Simulation time 633654854 ps
CPU time 2.39 seconds
Started Jun 30 04:56:13 PM PDT 24
Finished Jun 30 04:56:16 PM PDT 24
Peak memory 200396 kb
Host smart-a0de94f5-636e-447d-8224-e76888372b34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160397491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.3160397491
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.923278027
Short name T95
Test name
Test status
Simulation time 100655582 ps
CPU time 0.98 seconds
Started Jun 30 04:56:12 PM PDT 24
Finished Jun 30 04:56:13 PM PDT 24
Peak memory 199348 kb
Host smart-2b413b01-7208-41f5-89d1-1232ec9124a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923278027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.923278027
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3057759679
Short name T1134
Test name
Test status
Simulation time 93464809 ps
CPU time 0.65 seconds
Started Jun 30 04:56:12 PM PDT 24
Finished Jun 30 04:56:13 PM PDT 24
Peak memory 197244 kb
Host smart-8eb882e5-0a44-4208-91f0-0ce6aa1dd1ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057759679 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.3057759679
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.4089395266
Short name T65
Test name
Test status
Simulation time 46468024 ps
CPU time 0.62 seconds
Started Jun 30 04:56:15 PM PDT 24
Finished Jun 30 04:56:16 PM PDT 24
Peak memory 195748 kb
Host smart-1a01a1cd-48ce-4967-931e-67505fcb43f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089395266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.4089395266
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.293197419
Short name T1208
Test name
Test status
Simulation time 13109945 ps
CPU time 0.65 seconds
Started Jun 30 04:56:14 PM PDT 24
Finished Jun 30 04:56:15 PM PDT 24
Peak memory 194704 kb
Host smart-52a39624-72c3-4f70-8fa6-51b8cf52ae2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293197419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.293197419
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2214289170
Short name T1146
Test name
Test status
Simulation time 16398971 ps
CPU time 0.68 seconds
Started Jun 30 04:56:13 PM PDT 24
Finished Jun 30 04:56:14 PM PDT 24
Peak memory 197272 kb
Host smart-e1fb2398-f6a8-4012-80c2-66e785868f67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214289170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.2214289170
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.3499046033
Short name T1172
Test name
Test status
Simulation time 61523838 ps
CPU time 0.83 seconds
Started Jun 30 04:56:13 PM PDT 24
Finished Jun 30 04:56:15 PM PDT 24
Peak memory 198712 kb
Host smart-6a67f4bd-e6bd-4d96-afe3-0f970ae5e55b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499046033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.3499046033
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3478189974
Short name T89
Test name
Test status
Simulation time 396297759 ps
CPU time 1.46 seconds
Started Jun 30 04:56:11 PM PDT 24
Finished Jun 30 04:56:13 PM PDT 24
Peak memory 199676 kb
Host smart-5fe2bb5c-f3b8-4120-bb53-81874a82c41b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478189974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3478189974
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.78415830
Short name T1124
Test name
Test status
Simulation time 226678563 ps
CPU time 0.87 seconds
Started Jun 30 04:56:11 PM PDT 24
Finished Jun 30 04:56:12 PM PDT 24
Peak memory 200208 kb
Host smart-e082e7eb-f53a-4abf-a97c-1565887e9c54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78415830 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.78415830
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.4034848288
Short name T78
Test name
Test status
Simulation time 169445793 ps
CPU time 0.63 seconds
Started Jun 30 04:56:12 PM PDT 24
Finished Jun 30 04:56:13 PM PDT 24
Peak memory 196012 kb
Host smart-3ef6dfe8-5fa8-471a-bbe9-bac7397374fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034848288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.4034848288
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.2583621889
Short name T1168
Test name
Test status
Simulation time 17233955 ps
CPU time 0.57 seconds
Started Jun 30 04:56:11 PM PDT 24
Finished Jun 30 04:56:12 PM PDT 24
Peak memory 194696 kb
Host smart-d490862f-6245-4276-8a0e-5fd1c44debd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583621889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2583621889
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2697010227
Short name T1174
Test name
Test status
Simulation time 49114542 ps
CPU time 0.72 seconds
Started Jun 30 04:56:13 PM PDT 24
Finished Jun 30 04:56:15 PM PDT 24
Peak memory 197304 kb
Host smart-94f8eab9-d43e-4477-b83a-046c9d4a2cd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697010227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.2697010227
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1935339948
Short name T1230
Test name
Test status
Simulation time 173447774 ps
CPU time 1.19 seconds
Started Jun 30 04:56:13 PM PDT 24
Finished Jun 30 04:56:15 PM PDT 24
Peak memory 200408 kb
Host smart-d47fb574-df45-4720-883b-c276b5e312f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935339948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1935339948
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3566692310
Short name T1203
Test name
Test status
Simulation time 86314978 ps
CPU time 1.31 seconds
Started Jun 30 04:56:16 PM PDT 24
Finished Jun 30 04:56:18 PM PDT 24
Peak memory 199620 kb
Host smart-4a5e59b7-23ba-42f3-b650-ff05e523598a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566692310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3566692310
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2644029095
Short name T721
Test name
Test status
Simulation time 16008660 ps
CPU time 0.57 seconds
Started Jun 30 05:06:23 PM PDT 24
Finished Jun 30 05:06:24 PM PDT 24
Peak memory 195232 kb
Host smart-aaa58a65-d7cc-4a60-82fc-0fc8dbfa231d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644029095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2644029095
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.2751520983
Short name T478
Test name
Test status
Simulation time 38151662654 ps
CPU time 52.09 seconds
Started Jun 30 05:06:23 PM PDT 24
Finished Jun 30 05:07:16 PM PDT 24
Peak memory 199892 kb
Host smart-c0f2fa9f-b3d2-4845-87e1-6a50434deb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751520983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2751520983
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.2871933605
Short name T239
Test name
Test status
Simulation time 214340072178 ps
CPU time 227.09 seconds
Started Jun 30 05:06:19 PM PDT 24
Finished Jun 30 05:10:07 PM PDT 24
Peak memory 199896 kb
Host smart-8d317514-6fc3-483d-85df-775d562e765d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871933605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.2871933605
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.1579987011
Short name T100
Test name
Test status
Simulation time 42330103929 ps
CPU time 32.37 seconds
Started Jun 30 05:06:20 PM PDT 24
Finished Jun 30 05:06:53 PM PDT 24
Peak memory 199900 kb
Host smart-4edf8fc7-4759-4278-bd5b-33ae244de055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579987011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.1579987011
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.856239160
Short name T590
Test name
Test status
Simulation time 23830774281 ps
CPU time 8.39 seconds
Started Jun 30 05:06:22 PM PDT 24
Finished Jun 30 05:06:32 PM PDT 24
Peak memory 198488 kb
Host smart-c9fb81b5-e231-4d8c-b1de-6a4fa71947e1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856239160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.856239160
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.2881211108
Short name T740
Test name
Test status
Simulation time 146175578012 ps
CPU time 714.42 seconds
Started Jun 30 05:06:20 PM PDT 24
Finished Jun 30 05:18:15 PM PDT 24
Peak memory 199828 kb
Host smart-3c332a34-a34e-47c2-9e13-294ab7ec1211
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2881211108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2881211108
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.1143042071
Short name T649
Test name
Test status
Simulation time 7901100523 ps
CPU time 4.42 seconds
Started Jun 30 05:06:24 PM PDT 24
Finished Jun 30 05:06:29 PM PDT 24
Peak memory 199900 kb
Host smart-67cc6416-2332-4525-812b-e53e00fd2404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143042071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1143042071
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_perf.2224388555
Short name T745
Test name
Test status
Simulation time 11119735868 ps
CPU time 313.06 seconds
Started Jun 30 05:06:22 PM PDT 24
Finished Jun 30 05:11:36 PM PDT 24
Peak memory 199832 kb
Host smart-085ed9d0-639d-41fe-9778-54731c5a75cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2224388555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2224388555
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.1805695637
Short name T545
Test name
Test status
Simulation time 4470523607 ps
CPU time 9.29 seconds
Started Jun 30 05:06:25 PM PDT 24
Finished Jun 30 05:06:35 PM PDT 24
Peak memory 199228 kb
Host smart-d420ec7a-6456-4c71-a390-3443ff38c5c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1805695637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.1805695637
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2389022672
Short name T1075
Test name
Test status
Simulation time 25806558542 ps
CPU time 42.57 seconds
Started Jun 30 05:06:20 PM PDT 24
Finished Jun 30 05:07:03 PM PDT 24
Peak memory 199916 kb
Host smart-cbf23d75-6af9-4dc5-b16f-14510f9b186c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389022672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2389022672
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.355899186
Short name T360
Test name
Test status
Simulation time 754505347 ps
CPU time 0.92 seconds
Started Jun 30 05:06:20 PM PDT 24
Finished Jun 30 05:06:22 PM PDT 24
Peak memory 195544 kb
Host smart-35720723-0667-491c-87d3-4e60bba98870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355899186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.355899186
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2970899703
Short name T98
Test name
Test status
Simulation time 113554467 ps
CPU time 0.9 seconds
Started Jun 30 05:06:22 PM PDT 24
Finished Jun 30 05:06:24 PM PDT 24
Peak memory 218200 kb
Host smart-be86785e-8692-48de-8d35-924b8de304e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970899703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2970899703
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.2938910920
Short name T349
Test name
Test status
Simulation time 773542544 ps
CPU time 1.21 seconds
Started Jun 30 05:06:21 PM PDT 24
Finished Jun 30 05:06:24 PM PDT 24
Peak memory 198580 kb
Host smart-27a28a68-8f7e-4ab5-bb9a-d1645cf91d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938910920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.2938910920
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.292747379
Short name T958
Test name
Test status
Simulation time 44585502528 ps
CPU time 763.26 seconds
Started Jun 30 05:06:21 PM PDT 24
Finished Jun 30 05:19:05 PM PDT 24
Peak memory 199904 kb
Host smart-94073748-8364-4681-be03-ef78f75b571d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292747379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.292747379
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.3365562024
Short name T18
Test name
Test status
Simulation time 21891602378 ps
CPU time 166.65 seconds
Started Jun 30 05:06:22 PM PDT 24
Finished Jun 30 05:09:10 PM PDT 24
Peak memory 215460 kb
Host smart-1101b7ea-aab3-4f6f-93b6-15c1ef702140
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365562024 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.3365562024
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.1939769461
Short name T886
Test name
Test status
Simulation time 8573829406 ps
CPU time 16.29 seconds
Started Jun 30 05:06:22 PM PDT 24
Finished Jun 30 05:06:40 PM PDT 24
Peak memory 199808 kb
Host smart-3877c649-cc28-4634-bf8b-00cc4f73a68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939769461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1939769461
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.116971531
Short name T737
Test name
Test status
Simulation time 101756142187 ps
CPU time 48.05 seconds
Started Jun 30 05:06:20 PM PDT 24
Finished Jun 30 05:07:09 PM PDT 24
Peak memory 199792 kb
Host smart-eb10965c-7d6e-4937-bfdf-e5e028fe775a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116971531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.116971531
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.3472214594
Short name T806
Test name
Test status
Simulation time 27152880 ps
CPU time 0.55 seconds
Started Jun 30 05:06:27 PM PDT 24
Finished Jun 30 05:06:29 PM PDT 24
Peak memory 195500 kb
Host smart-5c9be941-f568-4e11-a228-3fcdafc12b27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472214594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3472214594
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.3581004277
Short name T681
Test name
Test status
Simulation time 173669323965 ps
CPU time 37.23 seconds
Started Jun 30 05:06:34 PM PDT 24
Finished Jun 30 05:07:12 PM PDT 24
Peak memory 199948 kb
Host smart-effa06a1-6dcb-4c1e-91cc-fe0ad9cefcdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581004277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3581004277
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.1637823248
Short name T553
Test name
Test status
Simulation time 24778776357 ps
CPU time 10.84 seconds
Started Jun 30 05:06:30 PM PDT 24
Finished Jun 30 05:06:42 PM PDT 24
Peak memory 199892 kb
Host smart-13c6f2cb-fe91-44c1-9156-57932712b841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637823248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.1637823248
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.1722502648
Short name T294
Test name
Test status
Simulation time 27458986396 ps
CPU time 11.46 seconds
Started Jun 30 05:06:28 PM PDT 24
Finished Jun 30 05:06:41 PM PDT 24
Peak memory 199852 kb
Host smart-94da409e-2d66-4384-9b77-386f39d69253
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722502648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1722502648
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_loopback.736254273
Short name T1006
Test name
Test status
Simulation time 4515118102 ps
CPU time 8.42 seconds
Started Jun 30 05:06:28 PM PDT 24
Finished Jun 30 05:06:38 PM PDT 24
Peak memory 198888 kb
Host smart-83deee5c-7b47-402b-a814-bf7e5c99e750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736254273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.736254273
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_perf.163020306
Short name T42
Test name
Test status
Simulation time 28529073971 ps
CPU time 352.17 seconds
Started Jun 30 05:06:27 PM PDT 24
Finished Jun 30 05:12:21 PM PDT 24
Peak memory 199828 kb
Host smart-8fd901c8-e55c-4ee8-8e2f-3ce5b87e20ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=163020306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.163020306
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.2904930029
Short name T1003
Test name
Test status
Simulation time 6721549483 ps
CPU time 29.66 seconds
Started Jun 30 05:06:30 PM PDT 24
Finished Jun 30 05:07:01 PM PDT 24
Peak memory 198852 kb
Host smart-da47aab8-339d-45c3-a9c2-25cd36338b88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2904930029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2904930029
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.2349373456
Short name T832
Test name
Test status
Simulation time 33167300318 ps
CPU time 13.47 seconds
Started Jun 30 05:06:32 PM PDT 24
Finished Jun 30 05:06:46 PM PDT 24
Peak memory 199892 kb
Host smart-6f0e5886-7085-481f-bceb-e01ab8549cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349373456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2349373456
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.1563939557
Short name T631
Test name
Test status
Simulation time 48422926624 ps
CPU time 11.93 seconds
Started Jun 30 05:06:27 PM PDT 24
Finished Jun 30 05:06:40 PM PDT 24
Peak memory 195848 kb
Host smart-ede6c93d-d4fc-4091-9d10-c2d3cdf863f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563939557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1563939557
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.1798096729
Short name T26
Test name
Test status
Simulation time 324630244 ps
CPU time 0.83 seconds
Started Jun 30 05:06:27 PM PDT 24
Finished Jun 30 05:06:29 PM PDT 24
Peak memory 218364 kb
Host smart-7fdd89a8-247b-4869-8ddd-efabf9feaa3f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798096729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1798096729
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.3691549915
Short name T559
Test name
Test status
Simulation time 624390267 ps
CPU time 2.6 seconds
Started Jun 30 05:06:30 PM PDT 24
Finished Jun 30 05:06:34 PM PDT 24
Peak memory 198660 kb
Host smart-1236d607-881f-4ef6-ae38-6b338b6cea49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691549915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3691549915
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.4211594641
Short name T884
Test name
Test status
Simulation time 366365090844 ps
CPU time 617.19 seconds
Started Jun 30 05:06:27 PM PDT 24
Finished Jun 30 05:16:46 PM PDT 24
Peak memory 199900 kb
Host smart-93ff2e1e-8d8c-44ca-8073-ca8f941aeb31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211594641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.4211594641
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.259462809
Short name T322
Test name
Test status
Simulation time 1679794306 ps
CPU time 2.05 seconds
Started Jun 30 05:06:34 PM PDT 24
Finished Jun 30 05:06:37 PM PDT 24
Peak memory 199288 kb
Host smart-1b7e873c-9e68-46c4-be00-65e0d0c13421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259462809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.259462809
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.1165563637
Short name T876
Test name
Test status
Simulation time 42699306219 ps
CPU time 64.66 seconds
Started Jun 30 05:06:29 PM PDT 24
Finished Jun 30 05:07:35 PM PDT 24
Peak memory 199716 kb
Host smart-a5f61d0a-f0e5-4e84-a55f-317dae111f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165563637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1165563637
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.2971473704
Short name T792
Test name
Test status
Simulation time 14596976 ps
CPU time 0.57 seconds
Started Jun 30 05:06:58 PM PDT 24
Finished Jun 30 05:07:00 PM PDT 24
Peak memory 195236 kb
Host smart-39fc55de-8227-465b-8c9a-316eb0dc995b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971473704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2971473704
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.1818656617
Short name T364
Test name
Test status
Simulation time 27903194327 ps
CPU time 42.1 seconds
Started Jun 30 05:06:58 PM PDT 24
Finished Jun 30 05:07:40 PM PDT 24
Peak memory 199932 kb
Host smart-598041d5-8197-482c-929e-6116a75ab550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818656617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.1818656617
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.3460832848
Short name T367
Test name
Test status
Simulation time 80888603124 ps
CPU time 34.6 seconds
Started Jun 30 05:06:58 PM PDT 24
Finished Jun 30 05:07:34 PM PDT 24
Peak memory 199772 kb
Host smart-a7a15f93-f3fc-4872-baf2-0c1dc2182f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460832848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3460832848
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.3473100523
Short name T299
Test name
Test status
Simulation time 57380472563 ps
CPU time 23.65 seconds
Started Jun 30 05:06:59 PM PDT 24
Finished Jun 30 05:07:23 PM PDT 24
Peak memory 199816 kb
Host smart-43e171cd-22ec-4616-8158-0791fac9da11
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473100523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3473100523
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2016579754
Short name T495
Test name
Test status
Simulation time 100432630563 ps
CPU time 531.77 seconds
Started Jun 30 05:07:01 PM PDT 24
Finished Jun 30 05:15:53 PM PDT 24
Peak memory 199872 kb
Host smart-5509eec1-e058-495e-9b7e-356615790d48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2016579754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2016579754
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.1605049467
Short name T309
Test name
Test status
Simulation time 7406373758 ps
CPU time 7.71 seconds
Started Jun 30 05:07:05 PM PDT 24
Finished Jun 30 05:07:14 PM PDT 24
Peak memory 198576 kb
Host smart-ffd65bfc-e4a4-43e7-ab45-dd89dff45ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605049467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.1605049467
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_perf.388621211
Short name T980
Test name
Test status
Simulation time 18981572320 ps
CPU time 891.65 seconds
Started Jun 30 05:07:00 PM PDT 24
Finished Jun 30 05:21:52 PM PDT 24
Peak memory 199916 kb
Host smart-723e4d53-2d38-43e4-85f3-06bafac2e3d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=388621211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.388621211
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.1952402062
Short name T357
Test name
Test status
Simulation time 2520704534 ps
CPU time 8.92 seconds
Started Jun 30 05:06:56 PM PDT 24
Finished Jun 30 05:07:05 PM PDT 24
Peak memory 197928 kb
Host smart-5fdc0c15-cec0-4b19-a969-f08fe0041e83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1952402062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.1952402062
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.1746016179
Short name T1054
Test name
Test status
Simulation time 143827921636 ps
CPU time 83.43 seconds
Started Jun 30 05:06:59 PM PDT 24
Finished Jun 30 05:08:23 PM PDT 24
Peak memory 199768 kb
Host smart-b0f90478-db6e-4218-9649-d534905fdc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746016179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1746016179
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.1497994404
Short name T713
Test name
Test status
Simulation time 34609674789 ps
CPU time 6.67 seconds
Started Jun 30 05:07:02 PM PDT 24
Finished Jun 30 05:07:10 PM PDT 24
Peak memory 195676 kb
Host smart-b4010a63-f201-4e58-adca-7e730d703ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497994404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1497994404
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.238546981
Short name T401
Test name
Test status
Simulation time 785333307 ps
CPU time 1.16 seconds
Started Jun 30 05:06:56 PM PDT 24
Finished Jun 30 05:06:57 PM PDT 24
Peak memory 198236 kb
Host smart-2593a5a1-ac77-487d-a15d-e8b2a813ef90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238546981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.238546981
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.3705068191
Short name T983
Test name
Test status
Simulation time 11085232022 ps
CPU time 127.43 seconds
Started Jun 30 05:06:58 PM PDT 24
Finished Jun 30 05:09:06 PM PDT 24
Peak memory 208572 kb
Host smart-2c8bcdfe-a813-4a89-a1f2-da0e9948c1b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705068191 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.3705068191
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.287836682
Short name T285
Test name
Test status
Simulation time 795219606 ps
CPU time 1.6 seconds
Started Jun 30 05:06:58 PM PDT 24
Finished Jun 30 05:07:00 PM PDT 24
Peak memory 198728 kb
Host smart-49b292ef-9fbd-4042-9e2c-854229a94d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287836682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.287836682
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3837908124
Short name T908
Test name
Test status
Simulation time 26091460829 ps
CPU time 19.47 seconds
Started Jun 30 05:06:51 PM PDT 24
Finished Jun 30 05:07:10 PM PDT 24
Peak memory 199816 kb
Host smart-7de2a0b7-1d95-44ab-be36-87744c48fb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837908124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3837908124
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.1321858837
Short name T704
Test name
Test status
Simulation time 16014775905 ps
CPU time 32.31 seconds
Started Jun 30 05:10:57 PM PDT 24
Finished Jun 30 05:11:30 PM PDT 24
Peak memory 199816 kb
Host smart-de6343c8-8e9e-490a-bb5a-6601c7c35692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321858837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1321858837
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.743227524
Short name T785
Test name
Test status
Simulation time 97432820300 ps
CPU time 36.81 seconds
Started Jun 30 05:10:59 PM PDT 24
Finished Jun 30 05:11:36 PM PDT 24
Peak memory 199792 kb
Host smart-bd4130c0-ba74-424c-bdbc-12436336b7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743227524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.743227524
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.2564343374
Short name T870
Test name
Test status
Simulation time 57216983478 ps
CPU time 199.76 seconds
Started Jun 30 05:11:04 PM PDT 24
Finished Jun 30 05:14:25 PM PDT 24
Peak memory 199864 kb
Host smart-548596b8-a84d-4ff6-b346-96b869b2d4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564343374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.2564343374
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1643817364
Short name T238
Test name
Test status
Simulation time 57671916194 ps
CPU time 24.35 seconds
Started Jun 30 05:11:06 PM PDT 24
Finished Jun 30 05:11:31 PM PDT 24
Peak memory 199820 kb
Host smart-c5ef0759-da60-42a4-9f56-ae7fd3f46d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643817364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1643817364
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1729068076
Short name T889
Test name
Test status
Simulation time 67267263587 ps
CPU time 174.62 seconds
Started Jun 30 05:11:03 PM PDT 24
Finished Jun 30 05:13:58 PM PDT 24
Peak memory 199928 kb
Host smart-ee9787b7-6552-43c4-bc28-16666539e9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729068076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1729068076
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.542600549
Short name T8
Test name
Test status
Simulation time 7059343647 ps
CPU time 12.74 seconds
Started Jun 30 05:11:06 PM PDT 24
Finished Jun 30 05:11:20 PM PDT 24
Peak memory 199832 kb
Host smart-0371a4e9-2618-4f46-97ee-6c2883c311d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542600549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.542600549
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2486528892
Short name T552
Test name
Test status
Simulation time 22337337 ps
CPU time 0.62 seconds
Started Jun 30 05:07:02 PM PDT 24
Finished Jun 30 05:07:04 PM PDT 24
Peak memory 195516 kb
Host smart-2417545d-0212-4379-85b2-9ea0c3c8c2e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486528892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2486528892
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.3561010021
Short name T531
Test name
Test status
Simulation time 64083408003 ps
CPU time 87.17 seconds
Started Jun 30 05:07:02 PM PDT 24
Finished Jun 30 05:08:30 PM PDT 24
Peak memory 199856 kb
Host smart-44e6b211-69a4-422a-8df9-b31d521dfdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561010021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3561010021
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.528442542
Short name T161
Test name
Test status
Simulation time 189458893642 ps
CPU time 97.78 seconds
Started Jun 30 05:07:01 PM PDT 24
Finished Jun 30 05:08:39 PM PDT 24
Peak memory 199856 kb
Host smart-ffa51e3e-93e3-46af-a75c-a88f00ce48a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528442542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.528442542
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.427631883
Short name T1015
Test name
Test status
Simulation time 108309786968 ps
CPU time 52.95 seconds
Started Jun 30 05:06:59 PM PDT 24
Finished Jun 30 05:07:53 PM PDT 24
Peak memory 199904 kb
Host smart-483aed21-57a2-476a-9956-f96dc2086a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427631883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.427631883
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.3591255058
Short name T627
Test name
Test status
Simulation time 54494333630 ps
CPU time 84.2 seconds
Started Jun 30 05:07:02 PM PDT 24
Finished Jun 30 05:08:27 PM PDT 24
Peak memory 199840 kb
Host smart-3ebba06a-5b83-40fb-ab26-7ab707bccf1c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591255058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.3591255058
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.1961717595
Short name T338
Test name
Test status
Simulation time 69898505558 ps
CPU time 545.79 seconds
Started Jun 30 05:07:05 PM PDT 24
Finished Jun 30 05:16:12 PM PDT 24
Peak memory 199840 kb
Host smart-51396418-1e43-4ef7-9527-eaaa15701db1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1961717595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.1961717595
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.3623102417
Short name T620
Test name
Test status
Simulation time 2145930319 ps
CPU time 2.81 seconds
Started Jun 30 05:06:59 PM PDT 24
Finished Jun 30 05:07:03 PM PDT 24
Peak memory 198676 kb
Host smart-1946d4f8-4987-40a1-a4e0-263d3b91cefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623102417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.3623102417
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_perf.1137973115
Short name T687
Test name
Test status
Simulation time 11213490703 ps
CPU time 74.6 seconds
Started Jun 30 05:07:01 PM PDT 24
Finished Jun 30 05:08:16 PM PDT 24
Peak memory 199820 kb
Host smart-8407e40b-0d86-48cd-8fab-767c10434470
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1137973115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1137973115
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.1352119463
Short name T540
Test name
Test status
Simulation time 4362918151 ps
CPU time 22.7 seconds
Started Jun 30 05:06:59 PM PDT 24
Finished Jun 30 05:07:22 PM PDT 24
Peak memory 198196 kb
Host smart-f0291bd8-b1ed-4eca-83dd-4ebd8c93bbca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1352119463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1352119463
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.3244469789
Short name T887
Test name
Test status
Simulation time 77444265786 ps
CPU time 41.3 seconds
Started Jun 30 05:07:02 PM PDT 24
Finished Jun 30 05:07:44 PM PDT 24
Peak memory 199912 kb
Host smart-c9fee04d-a151-44eb-bbf9-5a7db82801b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244469789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3244469789
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.3480108991
Short name T659
Test name
Test status
Simulation time 41208850487 ps
CPU time 15.92 seconds
Started Jun 30 05:06:59 PM PDT 24
Finished Jun 30 05:07:15 PM PDT 24
Peak memory 195836 kb
Host smart-8029b4bc-f6a7-459b-969d-6def5af23e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480108991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.3480108991
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.3127507228
Short name T882
Test name
Test status
Simulation time 5995410059 ps
CPU time 11.37 seconds
Started Jun 30 05:06:59 PM PDT 24
Finished Jun 30 05:07:11 PM PDT 24
Peak memory 199200 kb
Host smart-8f614bf8-e958-4988-9197-272cc073e0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127507228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3127507228
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.550074185
Short name T862
Test name
Test status
Simulation time 251701867213 ps
CPU time 262.28 seconds
Started Jun 30 05:07:00 PM PDT 24
Finished Jun 30 05:11:22 PM PDT 24
Peak memory 199904 kb
Host smart-79b05d8c-2cd6-4708-b5e6-5fe4b394c12d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550074185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.550074185
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.2588933077
Short name T15
Test name
Test status
Simulation time 14677853850 ps
CPU time 179.95 seconds
Started Jun 30 05:07:01 PM PDT 24
Finished Jun 30 05:10:02 PM PDT 24
Peak memory 208220 kb
Host smart-a404f23f-b2c7-4454-87af-0afa192e0981
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588933077 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.2588933077
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.673201295
Short name T510
Test name
Test status
Simulation time 136936800 ps
CPU time 0.99 seconds
Started Jun 30 05:06:59 PM PDT 24
Finished Jun 30 05:07:01 PM PDT 24
Peak memory 197116 kb
Host smart-a8f3bb1b-0a00-4b2e-af55-a432f97492b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673201295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.673201295
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.2059404704
Short name T850
Test name
Test status
Simulation time 23596717691 ps
CPU time 49.4 seconds
Started Jun 30 05:06:59 PM PDT 24
Finished Jun 30 05:07:49 PM PDT 24
Peak memory 199872 kb
Host smart-74144971-15a7-465b-8ba5-fc8745603da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059404704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2059404704
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.2604481357
Short name T316
Test name
Test status
Simulation time 20340514824 ps
CPU time 8.92 seconds
Started Jun 30 05:11:07 PM PDT 24
Finished Jun 30 05:11:16 PM PDT 24
Peak memory 199340 kb
Host smart-79db0cec-6a9c-4f05-8ecb-dd985439abb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604481357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.2604481357
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.967438974
Short name T40
Test name
Test status
Simulation time 25088247858 ps
CPU time 21.8 seconds
Started Jun 30 05:11:07 PM PDT 24
Finished Jun 30 05:11:29 PM PDT 24
Peak memory 199864 kb
Host smart-4225a66e-961a-47f6-8103-24bafb9db3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967438974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.967438974
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.2914651993
Short name T1088
Test name
Test status
Simulation time 120418383492 ps
CPU time 85.92 seconds
Started Jun 30 05:11:05 PM PDT 24
Finished Jun 30 05:12:31 PM PDT 24
Peak memory 199836 kb
Host smart-9e89671e-5b77-4c49-b54e-a253cf5c1b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914651993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.2914651993
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.2717742340
Short name T451
Test name
Test status
Simulation time 46506902476 ps
CPU time 24.96 seconds
Started Jun 30 05:11:04 PM PDT 24
Finished Jun 30 05:11:29 PM PDT 24
Peak memory 199932 kb
Host smart-8bc77c43-3571-4de6-b7b3-bfe5df4987ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717742340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2717742340
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.4200734044
Short name T187
Test name
Test status
Simulation time 46487542290 ps
CPU time 34.67 seconds
Started Jun 30 05:11:03 PM PDT 24
Finished Jun 30 05:11:38 PM PDT 24
Peak memory 199840 kb
Host smart-15857f40-bd48-42e1-a421-b79bf6df386f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200734044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.4200734044
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.3441159722
Short name T252
Test name
Test status
Simulation time 159115187410 ps
CPU time 250.27 seconds
Started Jun 30 05:11:07 PM PDT 24
Finished Jun 30 05:15:17 PM PDT 24
Peak memory 199912 kb
Host smart-030169bf-5843-4ed9-b92f-c2f51c19e1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441159722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.3441159722
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.4028705522
Short name T957
Test name
Test status
Simulation time 181691616831 ps
CPU time 54.28 seconds
Started Jun 30 05:11:07 PM PDT 24
Finished Jun 30 05:12:02 PM PDT 24
Peak memory 199768 kb
Host smart-25ec2d7f-5454-48de-9d87-86a14be1d267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028705522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.4028705522
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.1653217005
Short name T566
Test name
Test status
Simulation time 45228994357 ps
CPU time 72.59 seconds
Started Jun 30 05:11:06 PM PDT 24
Finished Jun 30 05:12:19 PM PDT 24
Peak memory 199920 kb
Host smart-57c1e668-6113-45a5-9acd-dc5a73aa1ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653217005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1653217005
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.93694206
Short name T857
Test name
Test status
Simulation time 15249364 ps
CPU time 0.55 seconds
Started Jun 30 05:07:07 PM PDT 24
Finished Jun 30 05:07:08 PM PDT 24
Peak memory 195244 kb
Host smart-17b5a248-d128-4e8d-b744-98117080e792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93694206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.93694206
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2537398744
Short name T462
Test name
Test status
Simulation time 10012280792 ps
CPU time 14.84 seconds
Started Jun 30 05:06:58 PM PDT 24
Finished Jun 30 05:07:13 PM PDT 24
Peak memory 199872 kb
Host smart-485884b1-72e1-44b7-8f86-8a9f6b0970cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537398744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2537398744
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.547001634
Short name T131
Test name
Test status
Simulation time 33005584207 ps
CPU time 46.89 seconds
Started Jun 30 05:06:59 PM PDT 24
Finished Jun 30 05:07:47 PM PDT 24
Peak memory 199840 kb
Host smart-b9ebbdc5-ab5a-4099-89cc-b4718e0f11c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547001634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.547001634
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2305397211
Short name T995
Test name
Test status
Simulation time 50186225838 ps
CPU time 75.86 seconds
Started Jun 30 05:06:59 PM PDT 24
Finished Jun 30 05:08:15 PM PDT 24
Peak memory 199652 kb
Host smart-abb42301-caac-49fc-9cc6-4266a78fa181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305397211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2305397211
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.1477801548
Short name T916
Test name
Test status
Simulation time 10158109853 ps
CPU time 5.39 seconds
Started Jun 30 05:07:03 PM PDT 24
Finished Jun 30 05:07:08 PM PDT 24
Peak memory 196532 kb
Host smart-62235841-88ce-4fbc-a2cf-9f3f36ba948b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477801548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1477801548
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.862611284
Short name T592
Test name
Test status
Simulation time 104151245266 ps
CPU time 244.64 seconds
Started Jun 30 05:07:05 PM PDT 24
Finished Jun 30 05:11:11 PM PDT 24
Peak memory 199864 kb
Host smart-5c8e9592-0df9-4e7d-84aa-6f5d427e97db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=862611284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.862611284
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.3344347252
Short name T842
Test name
Test status
Simulation time 6608682491 ps
CPU time 12.67 seconds
Started Jun 30 05:07:00 PM PDT 24
Finished Jun 30 05:07:14 PM PDT 24
Peak memory 198936 kb
Host smart-d3de3de4-6b75-487f-88d8-126c7c27ffab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344347252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3344347252
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_perf.3105681316
Short name T651
Test name
Test status
Simulation time 19968489535 ps
CPU time 1243.51 seconds
Started Jun 30 05:07:02 PM PDT 24
Finished Jun 30 05:27:46 PM PDT 24
Peak memory 199896 kb
Host smart-4beded32-f28d-43ca-8b4c-60b480c7d8b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3105681316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3105681316
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.4278350553
Short name T321
Test name
Test status
Simulation time 6548513814 ps
CPU time 7.53 seconds
Started Jun 30 05:07:01 PM PDT 24
Finished Jun 30 05:07:09 PM PDT 24
Peak memory 197760 kb
Host smart-8032d898-eb7f-42d0-85b5-f061409e86f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4278350553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.4278350553
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.995731334
Short name T300
Test name
Test status
Simulation time 70287749406 ps
CPU time 66.64 seconds
Started Jun 30 05:06:58 PM PDT 24
Finished Jun 30 05:08:05 PM PDT 24
Peak memory 199792 kb
Host smart-9501717c-daae-44a7-87e8-3aafa7d39471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995731334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.995731334
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.486554027
Short name T558
Test name
Test status
Simulation time 4365110264 ps
CPU time 2.12 seconds
Started Jun 30 05:06:58 PM PDT 24
Finished Jun 30 05:07:00 PM PDT 24
Peak memory 196136 kb
Host smart-71a02498-b7f3-4dc2-be93-792845eeb5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486554027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.486554027
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.4111258333
Short name T539
Test name
Test status
Simulation time 5765080122 ps
CPU time 35.34 seconds
Started Jun 30 05:07:00 PM PDT 24
Finished Jun 30 05:07:36 PM PDT 24
Peak memory 199116 kb
Host smart-9958a58e-3e87-4ab9-b5f4-42574a473381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111258333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.4111258333
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.2346634297
Short name T1057
Test name
Test status
Simulation time 52054058196 ps
CPU time 22.94 seconds
Started Jun 30 05:07:06 PM PDT 24
Finished Jun 30 05:07:30 PM PDT 24
Peak memory 199884 kb
Host smart-f8dd3575-b443-4241-a449-393518f105ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346634297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.2346634297
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.4153963064
Short name T521
Test name
Test status
Simulation time 953845188 ps
CPU time 1.87 seconds
Started Jun 30 05:06:59 PM PDT 24
Finished Jun 30 05:07:02 PM PDT 24
Peak memory 198256 kb
Host smart-f3bbceea-5d2b-44e8-8376-515a4fe8e787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153963064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.4153963064
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.902479311
Short name T773
Test name
Test status
Simulation time 35188160486 ps
CPU time 16.92 seconds
Started Jun 30 05:06:59 PM PDT 24
Finished Jun 30 05:07:17 PM PDT 24
Peak memory 199872 kb
Host smart-6e528b25-261f-424e-a3bd-5d8fa93df596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902479311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.902479311
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.2205238008
Short name T795
Test name
Test status
Simulation time 128820335506 ps
CPU time 53.57 seconds
Started Jun 30 05:11:06 PM PDT 24
Finished Jun 30 05:12:00 PM PDT 24
Peak memory 199868 kb
Host smart-8cd1ea07-06a7-43c7-871e-07e79952737b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205238008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2205238008
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.3603261374
Short name T658
Test name
Test status
Simulation time 75208939611 ps
CPU time 175.78 seconds
Started Jun 30 05:11:04 PM PDT 24
Finished Jun 30 05:14:00 PM PDT 24
Peak memory 199820 kb
Host smart-cc3d6abe-9b18-4beb-97ab-221c051be64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603261374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3603261374
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.3339362947
Short name T526
Test name
Test status
Simulation time 125313131318 ps
CPU time 227.74 seconds
Started Jun 30 05:11:04 PM PDT 24
Finished Jun 30 05:14:53 PM PDT 24
Peak memory 200148 kb
Host smart-be7cbca6-f129-464a-9a16-ad934055e679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339362947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3339362947
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.2004931646
Short name T468
Test name
Test status
Simulation time 35121495894 ps
CPU time 16.03 seconds
Started Jun 30 05:11:06 PM PDT 24
Finished Jun 30 05:11:23 PM PDT 24
Peak memory 199768 kb
Host smart-5c576db5-b2e5-4ad7-8126-f1a34ec793c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004931646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2004931646
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.3258795961
Short name T282
Test name
Test status
Simulation time 84557951498 ps
CPU time 227.56 seconds
Started Jun 30 05:11:04 PM PDT 24
Finished Jun 30 05:14:52 PM PDT 24
Peak memory 199852 kb
Host smart-669c0198-2192-4ca2-a7fa-d3b4f6763c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258795961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3258795961
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.3340843875
Short name T178
Test name
Test status
Simulation time 125859473459 ps
CPU time 64.18 seconds
Started Jun 30 05:11:07 PM PDT 24
Finished Jun 30 05:12:11 PM PDT 24
Peak memory 199904 kb
Host smart-ccaad38c-f235-4957-b698-4dd587f2141b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340843875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.3340843875
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.1226836549
Short name T194
Test name
Test status
Simulation time 18056904392 ps
CPU time 17.44 seconds
Started Jun 30 05:11:11 PM PDT 24
Finished Jun 30 05:11:29 PM PDT 24
Peak memory 199776 kb
Host smart-1433c679-d5bd-4b19-a2f7-a3e0442fcb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226836549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1226836549
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.412827035
Short name T796
Test name
Test status
Simulation time 14649484 ps
CPU time 0.57 seconds
Started Jun 30 05:07:11 PM PDT 24
Finished Jun 30 05:07:11 PM PDT 24
Peak memory 195416 kb
Host smart-2082a509-d7c5-4e30-b71a-847ad03ae025
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412827035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.412827035
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.650399110
Short name T920
Test name
Test status
Simulation time 219780010659 ps
CPU time 110.81 seconds
Started Jun 30 05:07:05 PM PDT 24
Finished Jun 30 05:08:56 PM PDT 24
Peak memory 199936 kb
Host smart-b78a3928-aae3-489f-9285-0e9ce1b5ec4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650399110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.650399110
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.1963236657
Short name T1087
Test name
Test status
Simulation time 20356261154 ps
CPU time 17.23 seconds
Started Jun 30 05:07:05 PM PDT 24
Finished Jun 30 05:07:23 PM PDT 24
Peak memory 199896 kb
Host smart-ad456309-bd75-46e6-991b-0081ab024524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963236657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.1963236657
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1082110781
Short name T902
Test name
Test status
Simulation time 235475423554 ps
CPU time 85.11 seconds
Started Jun 30 05:07:06 PM PDT 24
Finished Jun 30 05:08:32 PM PDT 24
Peak memory 199816 kb
Host smart-b2ec651c-12f2-44d6-9566-9297457a91b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082110781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1082110781
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.3474550785
Short name T774
Test name
Test status
Simulation time 284722769604 ps
CPU time 519.16 seconds
Started Jun 30 05:07:05 PM PDT 24
Finished Jun 30 05:15:46 PM PDT 24
Peak memory 199684 kb
Host smart-c1c4dd34-187a-4173-bdc8-e915ed7922c2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474550785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3474550785
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3659487168
Short name T6
Test name
Test status
Simulation time 98362115195 ps
CPU time 515.32 seconds
Started Jun 30 05:07:05 PM PDT 24
Finished Jun 30 05:15:40 PM PDT 24
Peak memory 199848 kb
Host smart-2f7c99f9-8038-4d41-8ce5-e3314b8150d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3659487168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3659487168
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.882039046
Short name T858
Test name
Test status
Simulation time 15416036757 ps
CPU time 8.09 seconds
Started Jun 30 05:07:07 PM PDT 24
Finished Jun 30 05:07:16 PM PDT 24
Peak memory 199848 kb
Host smart-986b2b83-5c46-4c85-a76a-cc11eafb8e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882039046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.882039046
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_perf.2129323361
Short name T442
Test name
Test status
Simulation time 8219174279 ps
CPU time 100.61 seconds
Started Jun 30 05:07:06 PM PDT 24
Finished Jun 30 05:08:48 PM PDT 24
Peak memory 199836 kb
Host smart-c43f7099-93ad-4c6a-9c04-96642e1b6515
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2129323361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2129323361
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.1516353057
Short name T1064
Test name
Test status
Simulation time 2936582497 ps
CPU time 7.47 seconds
Started Jun 30 05:07:06 PM PDT 24
Finished Jun 30 05:07:14 PM PDT 24
Peak memory 198524 kb
Host smart-7f52634b-53c6-4c7a-aae4-ad4aecd5ba14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1516353057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.1516353057
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.2550294795
Short name T68
Test name
Test status
Simulation time 123014073453 ps
CPU time 9.24 seconds
Started Jun 30 05:07:04 PM PDT 24
Finished Jun 30 05:07:14 PM PDT 24
Peak memory 199856 kb
Host smart-fa1eef32-8855-470c-bfde-97a10174f87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550294795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2550294795
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.3554043155
Short name T1039
Test name
Test status
Simulation time 44425936563 ps
CPU time 61.82 seconds
Started Jun 30 05:07:05 PM PDT 24
Finished Jun 30 05:08:08 PM PDT 24
Peak memory 195892 kb
Host smart-c5e1e2be-02f7-4d0f-a706-7ff218d480dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554043155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3554043155
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.2751744933
Short name T933
Test name
Test status
Simulation time 5482086928 ps
CPU time 11.41 seconds
Started Jun 30 05:07:04 PM PDT 24
Finished Jun 30 05:07:16 PM PDT 24
Peak memory 199620 kb
Host smart-4134eeaa-c19b-439f-9b2a-37b100a263c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751744933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.2751744933
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.1525165775
Short name T516
Test name
Test status
Simulation time 182735628470 ps
CPU time 2438.7 seconds
Started Jun 30 05:07:03 PM PDT 24
Finished Jun 30 05:47:42 PM PDT 24
Peak memory 199832 kb
Host smart-717fae6b-4d1d-4c2c-960b-63120fa75964
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525165775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1525165775
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.3240698088
Short name T14
Test name
Test status
Simulation time 19581592216 ps
CPU time 237.61 seconds
Started Jun 30 05:07:03 PM PDT 24
Finished Jun 30 05:11:01 PM PDT 24
Peak memory 215700 kb
Host smart-b6e7e40d-9c91-433a-ae96-50f995b64761
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240698088 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.3240698088
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.3299632161
Short name T416
Test name
Test status
Simulation time 1035021257 ps
CPU time 2.93 seconds
Started Jun 30 05:07:05 PM PDT 24
Finished Jun 30 05:07:08 PM PDT 24
Peak memory 199136 kb
Host smart-95f3842b-6fbe-42ec-8b8b-f405e325962b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299632161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3299632161
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.2340806423
Short name T932
Test name
Test status
Simulation time 153379841873 ps
CPU time 103.87 seconds
Started Jun 30 05:07:06 PM PDT 24
Finished Jun 30 05:08:51 PM PDT 24
Peak memory 199848 kb
Host smart-bb045179-376e-4501-a466-57cc092589f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340806423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2340806423
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.3579960638
Short name T711
Test name
Test status
Simulation time 100909034273 ps
CPU time 46.49 seconds
Started Jun 30 05:11:10 PM PDT 24
Finished Jun 30 05:11:57 PM PDT 24
Peak memory 199924 kb
Host smart-7998728d-61db-467e-9c63-48e06af68bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579960638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3579960638
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.2354405819
Short name T648
Test name
Test status
Simulation time 112394601239 ps
CPU time 159.38 seconds
Started Jun 30 05:11:12 PM PDT 24
Finished Jun 30 05:13:51 PM PDT 24
Peak memory 199808 kb
Host smart-1057d719-3ebd-47e7-b73b-22d9b34e1b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354405819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2354405819
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.771827860
Short name T917
Test name
Test status
Simulation time 105566979768 ps
CPU time 195.95 seconds
Started Jun 30 05:11:12 PM PDT 24
Finished Jun 30 05:14:28 PM PDT 24
Peak memory 199924 kb
Host smart-476edd01-bcdd-4a1e-8ab8-7be4cbf36eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771827860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.771827860
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.2832987497
Short name T780
Test name
Test status
Simulation time 64648854899 ps
CPU time 373 seconds
Started Jun 30 05:11:13 PM PDT 24
Finished Jun 30 05:17:27 PM PDT 24
Peak memory 199888 kb
Host smart-69824a1a-0cc5-432e-b85b-8c3fcc506dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832987497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2832987497
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.3314281512
Short name T435
Test name
Test status
Simulation time 28374351345 ps
CPU time 39.77 seconds
Started Jun 30 05:11:13 PM PDT 24
Finished Jun 30 05:11:53 PM PDT 24
Peak memory 199844 kb
Host smart-855bdea3-796b-4b9e-8ccf-bf44e0758172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314281512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3314281512
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.3802071426
Short name T871
Test name
Test status
Simulation time 29622841847 ps
CPU time 38.18 seconds
Started Jun 30 05:11:12 PM PDT 24
Finished Jun 30 05:11:50 PM PDT 24
Peak memory 199920 kb
Host smart-e4f4c28a-57e9-4a28-adcb-69c276421f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802071426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3802071426
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.2814413303
Short name T33
Test name
Test status
Simulation time 18514201797 ps
CPU time 30.08 seconds
Started Jun 30 05:11:13 PM PDT 24
Finished Jun 30 05:11:43 PM PDT 24
Peak memory 199880 kb
Host smart-62be378d-4aa9-4d56-9b4e-85232772f931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814413303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2814413303
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2733736831
Short name T866
Test name
Test status
Simulation time 28391048837 ps
CPU time 24.41 seconds
Started Jun 30 05:11:13 PM PDT 24
Finished Jun 30 05:11:38 PM PDT 24
Peak memory 199760 kb
Host smart-b1ad6d17-4fa1-46cd-9a5f-634f9be83b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733736831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2733736831
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.4257157610
Short name T1067
Test name
Test status
Simulation time 23554017261 ps
CPU time 17.75 seconds
Started Jun 30 05:11:12 PM PDT 24
Finished Jun 30 05:11:30 PM PDT 24
Peak memory 199916 kb
Host smart-fe0196ce-ca72-48c7-842f-1b2951485a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257157610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.4257157610
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.3836739360
Short name T967
Test name
Test status
Simulation time 14077457 ps
CPU time 0.55 seconds
Started Jun 30 05:07:23 PM PDT 24
Finished Jun 30 05:07:25 PM PDT 24
Peak memory 195192 kb
Host smart-b383ccb0-e1b2-49c2-bfdb-6d6692df97b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836739360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3836739360
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.4251338248
Short name T743
Test name
Test status
Simulation time 51577361312 ps
CPU time 57.96 seconds
Started Jun 30 05:07:06 PM PDT 24
Finished Jun 30 05:08:05 PM PDT 24
Peak memory 199892 kb
Host smart-827252cc-180d-43e1-a58e-fe87cd9f8bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251338248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.4251338248
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.513823849
Short name T789
Test name
Test status
Simulation time 17224775693 ps
CPU time 32.07 seconds
Started Jun 30 05:07:06 PM PDT 24
Finished Jun 30 05:07:39 PM PDT 24
Peak memory 199840 kb
Host smart-063b1974-91ab-4611-9778-6d94b887f50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513823849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.513823849
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_intr.3743057571
Short name T317
Test name
Test status
Simulation time 13954680773 ps
CPU time 23.08 seconds
Started Jun 30 05:07:07 PM PDT 24
Finished Jun 30 05:07:31 PM PDT 24
Peak memory 197616 kb
Host smart-f9f8bd1a-655d-44a0-8dec-190daec9c1d7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743057571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3743057571
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.877867530
Short name T825
Test name
Test status
Simulation time 122686036509 ps
CPU time 173.5 seconds
Started Jun 30 05:07:05 PM PDT 24
Finished Jun 30 05:10:00 PM PDT 24
Peak memory 199832 kb
Host smart-02849b56-b8c5-4bd9-bdab-a88096593e38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=877867530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.877867530
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.1453752624
Short name T678
Test name
Test status
Simulation time 1861741218 ps
CPU time 1.7 seconds
Started Jun 30 05:07:07 PM PDT 24
Finished Jun 30 05:07:09 PM PDT 24
Peak memory 197924 kb
Host smart-d7f0dd1a-7606-49ce-b4b4-2c77eb7a215a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453752624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.1453752624
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_perf.862333654
Short name T258
Test name
Test status
Simulation time 19087058532 ps
CPU time 176.08 seconds
Started Jun 30 05:07:05 PM PDT 24
Finished Jun 30 05:10:03 PM PDT 24
Peak memory 199904 kb
Host smart-a29ef893-ec28-41c6-b052-88494926d24a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=862333654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.862333654
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.541767448
Short name T554
Test name
Test status
Simulation time 1480325746 ps
CPU time 5.56 seconds
Started Jun 30 05:07:05 PM PDT 24
Finished Jun 30 05:07:11 PM PDT 24
Peak memory 196700 kb
Host smart-6f3e6ce1-6ad4-4200-bb73-a1152330fdbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=541767448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.541767448
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.223514040
Short name T696
Test name
Test status
Simulation time 80406105454 ps
CPU time 34.49 seconds
Started Jun 30 05:07:07 PM PDT 24
Finished Jun 30 05:07:42 PM PDT 24
Peak memory 199784 kb
Host smart-9121f09c-b00e-488e-994c-570ebdef8454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223514040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.223514040
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.2008661041
Short name T434
Test name
Test status
Simulation time 5508168634 ps
CPU time 5.08 seconds
Started Jun 30 05:07:05 PM PDT 24
Finished Jun 30 05:07:10 PM PDT 24
Peak memory 196364 kb
Host smart-d4ff58f1-0f19-401b-9e08-a4c3989e2288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008661041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.2008661041
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.4091247382
Short name T629
Test name
Test status
Simulation time 468195853 ps
CPU time 1.18 seconds
Started Jun 30 05:07:05 PM PDT 24
Finished Jun 30 05:07:08 PM PDT 24
Peak memory 198400 kb
Host smart-6db4ec27-a37c-49a5-8df4-c497b6960ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091247382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.4091247382
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.603759950
Short name T534
Test name
Test status
Simulation time 86072586916 ps
CPU time 242.58 seconds
Started Jun 30 05:07:22 PM PDT 24
Finished Jun 30 05:11:25 PM PDT 24
Peak memory 199892 kb
Host smart-4ae4deb6-0a3a-4356-bcb7-d6d8b35bb31e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603759950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.603759950
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.1163032798
Short name T51
Test name
Test status
Simulation time 151736270654 ps
CPU time 268.06 seconds
Started Jun 30 05:07:22 PM PDT 24
Finished Jun 30 05:11:50 PM PDT 24
Peak memory 215844 kb
Host smart-feb18acf-3efe-4801-bfad-754ce0dd15c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163032798 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.1163032798
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.3874540391
Short name T1051
Test name
Test status
Simulation time 2103199452 ps
CPU time 2.91 seconds
Started Jun 30 05:07:06 PM PDT 24
Finished Jun 30 05:07:10 PM PDT 24
Peak memory 198384 kb
Host smart-897b5129-5055-49d6-abf9-8a6cce577d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874540391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.3874540391
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.886016831
Short name T266
Test name
Test status
Simulation time 65711626741 ps
CPU time 51.53 seconds
Started Jun 30 05:07:05 PM PDT 24
Finished Jun 30 05:07:58 PM PDT 24
Peak memory 199924 kb
Host smart-fcca13a6-6487-48db-829d-fdf2e5f29b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886016831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.886016831
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.759062071
Short name T499
Test name
Test status
Simulation time 116666070637 ps
CPU time 201.33 seconds
Started Jun 30 05:11:10 PM PDT 24
Finished Jun 30 05:14:31 PM PDT 24
Peak memory 199876 kb
Host smart-08760a02-ed99-4b2c-a053-62c2e95c4d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759062071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.759062071
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.539620871
Short name T1035
Test name
Test status
Simulation time 42530959808 ps
CPU time 29.58 seconds
Started Jun 30 05:11:12 PM PDT 24
Finished Jun 30 05:11:42 PM PDT 24
Peak memory 199808 kb
Host smart-970c33e2-da0e-46ff-8e8c-620f3fa43ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539620871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.539620871
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.813459695
Short name T953
Test name
Test status
Simulation time 20677055039 ps
CPU time 31.06 seconds
Started Jun 30 05:11:13 PM PDT 24
Finished Jun 30 05:11:45 PM PDT 24
Peak memory 199816 kb
Host smart-58d4784c-0350-4029-b1da-308838340d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813459695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.813459695
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.1280373397
Short name T1021
Test name
Test status
Simulation time 120653712094 ps
CPU time 68.4 seconds
Started Jun 30 05:11:11 PM PDT 24
Finished Jun 30 05:12:20 PM PDT 24
Peak memory 199824 kb
Host smart-2f3f9375-1000-4d17-86d2-46a9ba178cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280373397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.1280373397
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.3272506061
Short name T772
Test name
Test status
Simulation time 102354046678 ps
CPU time 210.23 seconds
Started Jun 30 05:11:10 PM PDT 24
Finished Jun 30 05:14:41 PM PDT 24
Peak memory 199864 kb
Host smart-b20e89e2-fb4f-49e8-b869-ec0bcac5fdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272506061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3272506061
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.1708960722
Short name T152
Test name
Test status
Simulation time 58891502927 ps
CPU time 90.61 seconds
Started Jun 30 05:11:18 PM PDT 24
Finished Jun 30 05:12:49 PM PDT 24
Peak memory 199916 kb
Host smart-8455c013-f5bb-4452-b305-b9e11f2a3fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708960722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1708960722
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.1551355911
Short name T927
Test name
Test status
Simulation time 360621149743 ps
CPU time 74.6 seconds
Started Jun 30 05:11:19 PM PDT 24
Finished Jun 30 05:12:34 PM PDT 24
Peak memory 199920 kb
Host smart-14915df1-c1d8-4af0-8bea-2f0dc95d2428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551355911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1551355911
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2856384289
Short name T308
Test name
Test status
Simulation time 95259020964 ps
CPU time 140.04 seconds
Started Jun 30 05:07:23 PM PDT 24
Finished Jun 30 05:09:44 PM PDT 24
Peak memory 199896 kb
Host smart-16d2a44b-60cc-461f-94b0-5ea077072f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856384289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2856384289
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1454413534
Short name T984
Test name
Test status
Simulation time 130546159486 ps
CPU time 267.45 seconds
Started Jun 30 05:07:14 PM PDT 24
Finished Jun 30 05:11:42 PM PDT 24
Peak memory 199852 kb
Host smart-b5a03bee-6b4d-44d4-a7a3-a747e4de8368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454413534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1454413534
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.1249559579
Short name T1036
Test name
Test status
Simulation time 59801160648 ps
CPU time 18.97 seconds
Started Jun 30 05:07:22 PM PDT 24
Finished Jun 30 05:07:42 PM PDT 24
Peak memory 199864 kb
Host smart-15258f81-edaa-4fac-bc1a-0dbcd43da894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249559579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.1249559579
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.518584149
Short name T1024
Test name
Test status
Simulation time 126146053555 ps
CPU time 781.15 seconds
Started Jun 30 05:07:24 PM PDT 24
Finished Jun 30 05:20:26 PM PDT 24
Peak memory 199836 kb
Host smart-cb38e607-d321-4bea-8824-b77bf999c8fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=518584149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.518584149
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.2778872883
Short name T1027
Test name
Test status
Simulation time 9854100463 ps
CPU time 6.66 seconds
Started Jun 30 05:07:24 PM PDT 24
Finished Jun 30 05:07:32 PM PDT 24
Peak memory 199816 kb
Host smart-34af370c-3246-4682-808e-ca87711c0e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778872883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2778872883
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_perf.3836773267
Short name T337
Test name
Test status
Simulation time 24958329923 ps
CPU time 138.83 seconds
Started Jun 30 05:07:22 PM PDT 24
Finished Jun 30 05:09:42 PM PDT 24
Peak memory 199832 kb
Host smart-8fe87fac-48d9-4b63-a26d-24442e3406e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3836773267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3836773267
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.2026991726
Short name T529
Test name
Test status
Simulation time 5061835240 ps
CPU time 9.16 seconds
Started Jun 30 05:07:12 PM PDT 24
Finished Jun 30 05:07:21 PM PDT 24
Peak memory 198360 kb
Host smart-8dcfbb40-c18f-4809-bbe9-74bf7c3f80c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2026991726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2026991726
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.1391371446
Short name T471
Test name
Test status
Simulation time 100097309413 ps
CPU time 34.79 seconds
Started Jun 30 05:07:13 PM PDT 24
Finished Jun 30 05:07:48 PM PDT 24
Peak memory 199792 kb
Host smart-f6cd0028-f50f-4625-9707-398d8ea35510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391371446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1391371446
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.3113557979
Short name T525
Test name
Test status
Simulation time 674546404 ps
CPU time 0.78 seconds
Started Jun 30 05:07:30 PM PDT 24
Finished Jun 30 05:07:32 PM PDT 24
Peak memory 195252 kb
Host smart-be85a780-b90d-4525-b07b-673e0105a2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113557979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3113557979
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.2166856247
Short name T538
Test name
Test status
Simulation time 530665832 ps
CPU time 0.9 seconds
Started Jun 30 05:07:22 PM PDT 24
Finished Jun 30 05:07:24 PM PDT 24
Peak memory 198124 kb
Host smart-12827922-fd3c-4963-b504-ad54f34c804a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166856247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.2166856247
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.1095417768
Short name T798
Test name
Test status
Simulation time 218438879572 ps
CPU time 297.62 seconds
Started Jun 30 05:07:29 PM PDT 24
Finished Jun 30 05:12:27 PM PDT 24
Peak memory 199792 kb
Host smart-c4d385de-b92f-4ebe-9cff-3e6e0662f8dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095417768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1095417768
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.723670254
Short name T456
Test name
Test status
Simulation time 2153647216 ps
CPU time 2.94 seconds
Started Jun 30 05:07:24 PM PDT 24
Finished Jun 30 05:07:27 PM PDT 24
Peak memory 199260 kb
Host smart-c9809461-569f-48ee-aadb-b2cfaeff5ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723670254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.723670254
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.950537823
Short name T397
Test name
Test status
Simulation time 40742720699 ps
CPU time 59.5 seconds
Started Jun 30 05:07:23 PM PDT 24
Finished Jun 30 05:08:24 PM PDT 24
Peak memory 199872 kb
Host smart-912cdc43-0071-450f-915b-d6043692ec02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950537823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.950537823
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.2102701135
Short name T446
Test name
Test status
Simulation time 68267159639 ps
CPU time 56.54 seconds
Started Jun 30 05:11:19 PM PDT 24
Finished Jun 30 05:12:16 PM PDT 24
Peak memory 199916 kb
Host smart-8056dc08-e8ed-4c0b-8a08-589356f05250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102701135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.2102701135
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.1893496795
Short name T1062
Test name
Test status
Simulation time 43513129916 ps
CPU time 19.43 seconds
Started Jun 30 05:11:20 PM PDT 24
Finished Jun 30 05:11:40 PM PDT 24
Peak memory 199920 kb
Host smart-cb965aab-93da-4398-97ff-76ad11b073e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893496795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1893496795
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.4188911914
Short name T464
Test name
Test status
Simulation time 331454907266 ps
CPU time 46.72 seconds
Started Jun 30 05:11:19 PM PDT 24
Finished Jun 30 05:12:06 PM PDT 24
Peak memory 199892 kb
Host smart-5110e254-0223-4b3a-bb1c-c5553a74563b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188911914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.4188911914
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.3876674205
Short name T904
Test name
Test status
Simulation time 56965412145 ps
CPU time 43.27 seconds
Started Jun 30 05:11:30 PM PDT 24
Finished Jun 30 05:12:13 PM PDT 24
Peak memory 199920 kb
Host smart-51290e3d-a4ed-4a47-831b-c947f86b4118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876674205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3876674205
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.215894504
Short name T175
Test name
Test status
Simulation time 86397338764 ps
CPU time 35.59 seconds
Started Jun 30 05:11:31 PM PDT 24
Finished Jun 30 05:12:07 PM PDT 24
Peak memory 199828 kb
Host smart-4d0739c5-61f6-4f00-8f67-4363479e18ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215894504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.215894504
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.3141339380
Short name T423
Test name
Test status
Simulation time 39180558413 ps
CPU time 16.4 seconds
Started Jun 30 05:11:31 PM PDT 24
Finished Jun 30 05:11:48 PM PDT 24
Peak memory 199752 kb
Host smart-e0f3dfdf-e7fa-4397-bd72-bd8797560a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141339380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3141339380
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.232966702
Short name T754
Test name
Test status
Simulation time 39698341894 ps
CPU time 90.68 seconds
Started Jun 30 05:11:30 PM PDT 24
Finished Jun 30 05:13:01 PM PDT 24
Peak memory 199908 kb
Host smart-52e5b7cc-ff39-4479-9d22-4f473afaf5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232966702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.232966702
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.633667928
Short name T219
Test name
Test status
Simulation time 11967737227 ps
CPU time 14.71 seconds
Started Jun 30 05:11:30 PM PDT 24
Finished Jun 30 05:11:45 PM PDT 24
Peak memory 199608 kb
Host smart-e833af57-5383-46c7-a107-28faafcaa4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633667928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.633667928
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.2828522515
Short name T517
Test name
Test status
Simulation time 23672657 ps
CPU time 0.55 seconds
Started Jun 30 05:07:24 PM PDT 24
Finished Jun 30 05:07:26 PM PDT 24
Peak memory 194160 kb
Host smart-e9bd518e-3da5-4430-92a9-7b6b8e2dcf92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828522515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2828522515
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.3434848492
Short name T836
Test name
Test status
Simulation time 35874011214 ps
CPU time 54.49 seconds
Started Jun 30 05:07:22 PM PDT 24
Finished Jun 30 05:08:17 PM PDT 24
Peak memory 199920 kb
Host smart-cbd9a8a6-52d0-4baa-8808-cf6eb2ee1e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434848492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3434848492
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.2286141982
Short name T849
Test name
Test status
Simulation time 38732227172 ps
CPU time 48.84 seconds
Started Jun 30 05:07:30 PM PDT 24
Finished Jun 30 05:08:19 PM PDT 24
Peak memory 199728 kb
Host smart-56a736d2-22d5-48a2-8944-583d400168b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286141982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2286141982
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_intr.2132718257
Short name T966
Test name
Test status
Simulation time 257587211691 ps
CPU time 200.31 seconds
Started Jun 30 05:07:25 PM PDT 24
Finished Jun 30 05:10:46 PM PDT 24
Peak memory 198080 kb
Host smart-56487b62-464d-4f2c-af75-0e8cc1049845
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132718257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2132718257
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.3148809564
Short name T852
Test name
Test status
Simulation time 69997941189 ps
CPU time 348.29 seconds
Started Jun 30 05:07:22 PM PDT 24
Finished Jun 30 05:13:12 PM PDT 24
Peak memory 199900 kb
Host smart-e1de0e07-6366-4bcb-9006-17c105e9eaa0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3148809564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3148809564
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.2629093259
Short name T1022
Test name
Test status
Simulation time 47166466 ps
CPU time 0.61 seconds
Started Jun 30 05:07:23 PM PDT 24
Finished Jun 30 05:07:25 PM PDT 24
Peak memory 195836 kb
Host smart-ae38f562-c23a-4fa0-a53a-a060d02daf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629093259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2629093259
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_perf.2254738799
Short name T504
Test name
Test status
Simulation time 10676001061 ps
CPU time 114.5 seconds
Started Jun 30 05:07:34 PM PDT 24
Finished Jun 30 05:09:30 PM PDT 24
Peak memory 199896 kb
Host smart-39683a88-d837-4816-9d3e-17425461dcc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2254738799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2254738799
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.1778436539
Short name T561
Test name
Test status
Simulation time 4025432863 ps
CPU time 18.16 seconds
Started Jun 30 05:07:24 PM PDT 24
Finished Jun 30 05:07:43 PM PDT 24
Peak memory 198956 kb
Host smart-64b42ca5-69c9-4aa5-9eca-9fbf9df01ff1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1778436539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1778436539
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.2343835474
Short name T472
Test name
Test status
Simulation time 1660867350 ps
CPU time 1.39 seconds
Started Jun 30 05:07:23 PM PDT 24
Finished Jun 30 05:07:26 PM PDT 24
Peak memory 195328 kb
Host smart-a7a2cc3c-dd5c-47e8-ad39-00d9af75b6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343835474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.2343835474
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.379133403
Short name T396
Test name
Test status
Simulation time 523235154 ps
CPU time 1.58 seconds
Started Jun 30 05:07:22 PM PDT 24
Finished Jun 30 05:07:24 PM PDT 24
Peak memory 198464 kb
Host smart-c8839fc3-794a-406b-932e-68aa96d0302d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379133403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.379133403
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.2420286921
Short name T720
Test name
Test status
Simulation time 504974343 ps
CPU time 1.73 seconds
Started Jun 30 05:07:22 PM PDT 24
Finished Jun 30 05:07:24 PM PDT 24
Peak memory 198576 kb
Host smart-7ee86dc7-c94f-4935-8ca3-5f535df0c8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420286921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2420286921
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.1199475383
Short name T7
Test name
Test status
Simulation time 84180374317 ps
CPU time 29.04 seconds
Started Jun 30 05:07:24 PM PDT 24
Finished Jun 30 05:07:54 PM PDT 24
Peak memory 199888 kb
Host smart-2812148c-2869-47d4-929d-69ac13bbdaf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199475383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1199475383
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.3796060662
Short name T837
Test name
Test status
Simulation time 90374834811 ps
CPU time 127.51 seconds
Started Jun 30 05:11:31 PM PDT 24
Finished Jun 30 05:13:39 PM PDT 24
Peak memory 199924 kb
Host smart-af3447b9-c301-49dd-b515-1959f89b8c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796060662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3796060662
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.3233960234
Short name T973
Test name
Test status
Simulation time 85867412922 ps
CPU time 53 seconds
Started Jun 30 05:11:30 PM PDT 24
Finished Jun 30 05:12:23 PM PDT 24
Peak memory 199828 kb
Host smart-77fe61ba-4601-476b-933f-38759cfd3811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233960234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3233960234
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3621097804
Short name T708
Test name
Test status
Simulation time 77022062508 ps
CPU time 42.23 seconds
Started Jun 30 05:11:33 PM PDT 24
Finished Jun 30 05:12:15 PM PDT 24
Peak memory 199888 kb
Host smart-c0ab2cc8-1519-4187-8f93-8c857f5b8eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621097804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3621097804
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1355663665
Short name T821
Test name
Test status
Simulation time 100058647793 ps
CPU time 87.45 seconds
Started Jun 30 05:11:31 PM PDT 24
Finished Jun 30 05:12:59 PM PDT 24
Peak memory 199864 kb
Host smart-dbabac6b-159b-4fe3-9682-bab69ceefe94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355663665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1355663665
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.4288904472
Short name T379
Test name
Test status
Simulation time 27436524977 ps
CPU time 23.92 seconds
Started Jun 30 05:11:31 PM PDT 24
Finished Jun 30 05:11:56 PM PDT 24
Peak memory 199820 kb
Host smart-ae7db096-6cc3-4160-8bdc-e189c1e19767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288904472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.4288904472
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2337478218
Short name T1073
Test name
Test status
Simulation time 61222283415 ps
CPU time 101.34 seconds
Started Jun 30 05:11:31 PM PDT 24
Finished Jun 30 05:13:13 PM PDT 24
Peak memory 199880 kb
Host smart-31defc31-f70b-4713-80e7-d62e779d078d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337478218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2337478218
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1199623736
Short name T485
Test name
Test status
Simulation time 21885612379 ps
CPU time 38.08 seconds
Started Jun 30 05:11:33 PM PDT 24
Finished Jun 30 05:12:12 PM PDT 24
Peak memory 199880 kb
Host smart-4783cd92-2ddb-4d93-bd3e-e9ccafd6cc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199623736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1199623736
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.1389717765
Short name T203
Test name
Test status
Simulation time 84533062052 ps
CPU time 37.37 seconds
Started Jun 30 05:11:30 PM PDT 24
Finished Jun 30 05:12:08 PM PDT 24
Peak memory 199896 kb
Host smart-530e0492-bdf2-43c8-a405-b3a6ed7e0435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389717765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.1389717765
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.3072424479
Short name T400
Test name
Test status
Simulation time 27075100 ps
CPU time 0.56 seconds
Started Jun 30 05:07:27 PM PDT 24
Finished Jun 30 05:07:28 PM PDT 24
Peak memory 194160 kb
Host smart-10f53667-b67f-4af4-89e0-45d06ba2df1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072424479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3072424479
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.3621552223
Short name T1001
Test name
Test status
Simulation time 54739352427 ps
CPU time 91.74 seconds
Started Jun 30 05:07:25 PM PDT 24
Finished Jun 30 05:08:57 PM PDT 24
Peak memory 199844 kb
Host smart-738b5a34-ebba-4295-a902-f50e58112ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621552223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3621552223
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.1361677448
Short name T650
Test name
Test status
Simulation time 39235211189 ps
CPU time 18.35 seconds
Started Jun 30 05:07:23 PM PDT 24
Finished Jun 30 05:07:42 PM PDT 24
Peak memory 199912 kb
Host smart-f853df77-bb75-4769-8e01-f9cdd6c6d1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361677448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1361677448
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.820107425
Short name T1042
Test name
Test status
Simulation time 47571427792 ps
CPU time 14.63 seconds
Started Jun 30 05:07:33 PM PDT 24
Finished Jun 30 05:07:49 PM PDT 24
Peak memory 199860 kb
Host smart-64e5394f-fdf6-4071-8189-6cd01406b144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820107425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.820107425
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.3613890433
Short name T779
Test name
Test status
Simulation time 56749287118 ps
CPU time 14.88 seconds
Started Jun 30 05:07:34 PM PDT 24
Finished Jun 30 05:07:50 PM PDT 24
Peak memory 199460 kb
Host smart-9602294b-4d9d-4d0d-81c2-949fe0fb1f1a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613890433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3613890433
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.3267710218
Short name T483
Test name
Test status
Simulation time 198936478255 ps
CPU time 978.09 seconds
Started Jun 30 05:07:30 PM PDT 24
Finished Jun 30 05:23:49 PM PDT 24
Peak memory 200156 kb
Host smart-f65ebd74-4a6d-4d78-8da5-320f3c1e09eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3267710218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3267710218
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.3115370482
Short name T524
Test name
Test status
Simulation time 10810768531 ps
CPU time 6.4 seconds
Started Jun 30 05:07:27 PM PDT 24
Finished Jun 30 05:07:34 PM PDT 24
Peak memory 199816 kb
Host smart-fcc585c7-4235-4d97-bb14-b3da9a8ce7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115370482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.3115370482
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_perf.797021530
Short name T948
Test name
Test status
Simulation time 5809362080 ps
CPU time 84.12 seconds
Started Jun 30 05:07:29 PM PDT 24
Finished Jun 30 05:08:54 PM PDT 24
Peak memory 199824 kb
Host smart-e11f86e2-7c40-424b-8810-d7c48e11486c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=797021530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.797021530
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.1855572882
Short name T84
Test name
Test status
Simulation time 3789086897 ps
CPU time 7.62 seconds
Started Jun 30 05:07:34 PM PDT 24
Finished Jun 30 05:07:43 PM PDT 24
Peak memory 198984 kb
Host smart-8c3382f6-bdea-4476-bc9e-da32b20e73fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1855572882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.1855572882
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.365676431
Short name T671
Test name
Test status
Simulation time 149472540647 ps
CPU time 55.67 seconds
Started Jun 30 05:07:29 PM PDT 24
Finished Jun 30 05:08:25 PM PDT 24
Peak memory 199892 kb
Host smart-38acbcd0-1592-49fa-bf0d-938fc1cbb07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365676431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.365676431
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.3594978309
Short name T802
Test name
Test status
Simulation time 38374679902 ps
CPU time 29.25 seconds
Started Jun 30 05:07:28 PM PDT 24
Finished Jun 30 05:07:58 PM PDT 24
Peak memory 195992 kb
Host smart-55dbbcbc-7fd7-491c-b906-de0e6bdb8a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594978309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3594978309
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.2841406955
Short name T888
Test name
Test status
Simulation time 514957278 ps
CPU time 1.52 seconds
Started Jun 30 05:07:23 PM PDT 24
Finished Jun 30 05:07:26 PM PDT 24
Peak memory 198976 kb
Host smart-1b01cdd9-0049-489f-9dad-8ae1ae3523ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841406955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.2841406955
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.2573784792
Short name T794
Test name
Test status
Simulation time 60830407632 ps
CPU time 615.26 seconds
Started Jun 30 05:07:27 PM PDT 24
Finished Jun 30 05:17:43 PM PDT 24
Peak memory 199888 kb
Host smart-50a6bf4f-36b6-4eb0-9fd4-ffe5da375638
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573784792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2573784792
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.1000084605
Short name T960
Test name
Test status
Simulation time 372102814263 ps
CPU time 943.14 seconds
Started Jun 30 05:07:34 PM PDT 24
Finished Jun 30 05:23:19 PM PDT 24
Peak memory 216092 kb
Host smart-e629f813-f54f-411e-92ca-20783a86adcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000084605 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.1000084605
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1009331742
Short name T450
Test name
Test status
Simulation time 672314765 ps
CPU time 2.61 seconds
Started Jun 30 05:07:30 PM PDT 24
Finished Jun 30 05:07:33 PM PDT 24
Peak memory 199080 kb
Host smart-0efaaa56-9c98-4791-9723-0f6ddc37c127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009331742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1009331742
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.2227399048
Short name T918
Test name
Test status
Simulation time 129824058725 ps
CPU time 82.77 seconds
Started Jun 30 05:07:33 PM PDT 24
Finished Jun 30 05:08:58 PM PDT 24
Peak memory 199924 kb
Host smart-628e8061-5595-47c4-9463-e6af69b2135a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227399048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2227399048
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.1538184029
Short name T611
Test name
Test status
Simulation time 58377046761 ps
CPU time 75.66 seconds
Started Jun 30 05:11:31 PM PDT 24
Finished Jun 30 05:12:47 PM PDT 24
Peak memory 199880 kb
Host smart-ed91ab1c-cb26-42e8-b80b-74baad70b534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538184029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1538184029
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3169459722
Short name T880
Test name
Test status
Simulation time 47338477004 ps
CPU time 35.95 seconds
Started Jun 30 05:11:31 PM PDT 24
Finished Jun 30 05:12:07 PM PDT 24
Peak memory 199860 kb
Host smart-d065e2c8-280a-4b0c-8887-c5308524a7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169459722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3169459722
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.3295868727
Short name T417
Test name
Test status
Simulation time 39542986271 ps
CPU time 52.21 seconds
Started Jun 30 05:11:36 PM PDT 24
Finished Jun 30 05:12:29 PM PDT 24
Peak memory 199896 kb
Host smart-ae833b2e-932f-4555-ad23-36ffbdaf077c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295868727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3295868727
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.1893302119
Short name T652
Test name
Test status
Simulation time 39934537579 ps
CPU time 57.56 seconds
Started Jun 30 05:11:37 PM PDT 24
Finished Jun 30 05:12:35 PM PDT 24
Peak memory 199824 kb
Host smart-24d0a71c-460b-4246-99b6-3bd93104b651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893302119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1893302119
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.67267430
Short name T214
Test name
Test status
Simulation time 28804504501 ps
CPU time 12.54 seconds
Started Jun 30 05:11:34 PM PDT 24
Finished Jun 30 05:11:47 PM PDT 24
Peak memory 199888 kb
Host smart-4d89cded-13f0-450a-9228-65f22af35686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67267430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.67267430
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3304055815
Short name T513
Test name
Test status
Simulation time 117230441678 ps
CPU time 41.8 seconds
Started Jun 30 05:11:32 PM PDT 24
Finished Jun 30 05:12:14 PM PDT 24
Peak memory 199756 kb
Host smart-d30adc94-ebdd-4cde-a9a7-357f0a9fdb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304055815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3304055815
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.2822190441
Short name T202
Test name
Test status
Simulation time 187626734415 ps
CPU time 50.19 seconds
Started Jun 30 05:11:35 PM PDT 24
Finished Jun 30 05:12:25 PM PDT 24
Peak memory 199904 kb
Host smart-47b64ef5-1051-439c-8f31-1fdc4e07d1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822190441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2822190441
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.2048002547
Short name T409
Test name
Test status
Simulation time 146080899010 ps
CPU time 46.47 seconds
Started Jun 30 05:11:33 PM PDT 24
Finished Jun 30 05:12:20 PM PDT 24
Peak memory 199832 kb
Host smart-e80d6d43-7b73-462a-a87a-5e057efa4063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048002547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.2048002547
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.1793165001
Short name T438
Test name
Test status
Simulation time 43984623 ps
CPU time 0.57 seconds
Started Jun 30 05:07:33 PM PDT 24
Finished Jun 30 05:07:34 PM PDT 24
Peak memory 195228 kb
Host smart-96fc7256-9326-4fd4-a598-2da19e203aad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793165001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1793165001
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3629122165
Short name T146
Test name
Test status
Simulation time 27957402142 ps
CPU time 46.75 seconds
Started Jun 30 05:07:28 PM PDT 24
Finished Jun 30 05:08:15 PM PDT 24
Peak memory 199820 kb
Host smart-771c7de0-01c5-483c-84f7-9174a5e040e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629122165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3629122165
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.1475368700
Short name T505
Test name
Test status
Simulation time 32970872944 ps
CPU time 33.76 seconds
Started Jun 30 05:07:31 PM PDT 24
Finished Jun 30 05:08:05 PM PDT 24
Peak memory 199936 kb
Host smart-c4c870d4-47eb-4856-ab17-2c02fa0a40a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475368700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1475368700
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.2012252681
Short name T646
Test name
Test status
Simulation time 97533457893 ps
CPU time 153.04 seconds
Started Jun 30 05:07:33 PM PDT 24
Finished Jun 30 05:10:07 PM PDT 24
Peak memory 199852 kb
Host smart-d5ad5898-49e6-47c2-ba74-a920e084ab1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012252681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2012252681
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.652509468
Short name T329
Test name
Test status
Simulation time 6963186400 ps
CPU time 13.94 seconds
Started Jun 30 05:07:36 PM PDT 24
Finished Jun 30 05:07:51 PM PDT 24
Peak memory 199780 kb
Host smart-50bcf62c-2cf5-4a8e-a857-8dbefc393d85
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652509468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.652509468
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.4095392425
Short name T489
Test name
Test status
Simulation time 90860346703 ps
CPU time 525.01 seconds
Started Jun 30 05:07:34 PM PDT 24
Finished Jun 30 05:16:21 PM PDT 24
Peak memory 199900 kb
Host smart-4bb2ba3f-1976-4bef-b199-b42ea042dd8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4095392425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.4095392425
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.3623133781
Short name T770
Test name
Test status
Simulation time 13327909927 ps
CPU time 11.09 seconds
Started Jun 30 05:07:34 PM PDT 24
Finished Jun 30 05:07:46 PM PDT 24
Peak memory 199656 kb
Host smart-cf385058-f4c6-4885-9224-1135b2935b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623133781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.3623133781
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_perf.298693798
Short name T588
Test name
Test status
Simulation time 12312286793 ps
CPU time 485.02 seconds
Started Jun 30 05:07:37 PM PDT 24
Finished Jun 30 05:15:42 PM PDT 24
Peak memory 199860 kb
Host smart-031b07ec-b0a8-43e6-a3dd-45fc778bb398
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=298693798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.298693798
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.47010048
Short name T603
Test name
Test status
Simulation time 4085400290 ps
CPU time 30.73 seconds
Started Jun 30 05:07:34 PM PDT 24
Finished Jun 30 05:08:06 PM PDT 24
Peak memory 197992 kb
Host smart-37029b53-d023-46e5-8e45-557b8d14525d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=47010048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.47010048
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.4083672632
Short name T844
Test name
Test status
Simulation time 124066665862 ps
CPU time 55.17 seconds
Started Jun 30 05:07:33 PM PDT 24
Finished Jun 30 05:08:30 PM PDT 24
Peak memory 199864 kb
Host smart-85cef926-bd0e-42ab-877b-8c4c4e5d6046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083672632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.4083672632
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.4005644103
Short name T839
Test name
Test status
Simulation time 31574757682 ps
CPU time 47.49 seconds
Started Jun 30 05:07:33 PM PDT 24
Finished Jun 30 05:08:22 PM PDT 24
Peak memory 195728 kb
Host smart-596acbd7-b2c6-404d-8864-b86437b78385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005644103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.4005644103
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2808574982
Short name T474
Test name
Test status
Simulation time 717142182 ps
CPU time 3.35 seconds
Started Jun 30 05:07:26 PM PDT 24
Finished Jun 30 05:07:30 PM PDT 24
Peak memory 198616 kb
Host smart-024a189d-d938-4b42-86b8-05fd4808f435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808574982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2808574982
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.1031870460
Short name T542
Test name
Test status
Simulation time 190517703093 ps
CPU time 103.67 seconds
Started Jun 30 05:07:34 PM PDT 24
Finished Jun 30 05:09:19 PM PDT 24
Peak memory 199888 kb
Host smart-4f82a57a-0cd7-474a-b38f-aa264f53623e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031870460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.1031870460
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.3030902893
Short name T358
Test name
Test status
Simulation time 6397634463 ps
CPU time 13.37 seconds
Started Jun 30 05:07:34 PM PDT 24
Finished Jun 30 05:07:49 PM PDT 24
Peak memory 199704 kb
Host smart-f70e9443-aadd-41a9-a87f-c76073a5a87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030902893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3030902893
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.2861743119
Short name T507
Test name
Test status
Simulation time 12298490998 ps
CPU time 7.57 seconds
Started Jun 30 05:07:26 PM PDT 24
Finished Jun 30 05:07:34 PM PDT 24
Peak memory 197800 kb
Host smart-189a3145-6799-4874-bb61-fb9e7691181a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861743119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2861743119
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.1875921374
Short name T132
Test name
Test status
Simulation time 92633011401 ps
CPU time 106.55 seconds
Started Jun 30 05:11:34 PM PDT 24
Finished Jun 30 05:13:20 PM PDT 24
Peak memory 199868 kb
Host smart-04066228-9bc4-41ff-9673-d6642089f967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875921374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.1875921374
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.827484634
Short name T41
Test name
Test status
Simulation time 180811385374 ps
CPU time 27.82 seconds
Started Jun 30 05:11:37 PM PDT 24
Finished Jun 30 05:12:05 PM PDT 24
Peak memory 199756 kb
Host smart-da23392c-fd6e-4369-8b01-8f0cb919838b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827484634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.827484634
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.3435638405
Short name T213
Test name
Test status
Simulation time 85963740665 ps
CPU time 29.88 seconds
Started Jun 30 05:11:34 PM PDT 24
Finished Jun 30 05:12:04 PM PDT 24
Peak memory 199892 kb
Host smart-1f75fb52-8459-475e-8b41-b45858d9973b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435638405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3435638405
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.1145709327
Short name T304
Test name
Test status
Simulation time 102225588556 ps
CPU time 58.85 seconds
Started Jun 30 05:11:40 PM PDT 24
Finished Jun 30 05:12:40 PM PDT 24
Peak memory 199860 kb
Host smart-23ec2f8e-a546-4802-8d72-8f7fd6ed0882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145709327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.1145709327
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1845803748
Short name T419
Test name
Test status
Simulation time 102036817616 ps
CPU time 38.11 seconds
Started Jun 30 05:11:41 PM PDT 24
Finished Jun 30 05:12:19 PM PDT 24
Peak memory 199916 kb
Host smart-d3dada3c-a84e-4213-b3c0-9b79fcbcc175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845803748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1845803748
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.2531742655
Short name T677
Test name
Test status
Simulation time 156652560629 ps
CPU time 24.4 seconds
Started Jun 30 05:11:41 PM PDT 24
Finished Jun 30 05:12:06 PM PDT 24
Peak memory 199868 kb
Host smart-fb07d472-c900-4acb-96eb-a4d8e1d9ad1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531742655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2531742655
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.4054215574
Short name T619
Test name
Test status
Simulation time 93071116277 ps
CPU time 37.46 seconds
Started Jun 30 05:11:41 PM PDT 24
Finished Jun 30 05:12:19 PM PDT 24
Peak memory 199804 kb
Host smart-d3cfb741-dcb9-423d-aab7-779c702d57d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054215574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.4054215574
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3174525812
Short name T764
Test name
Test status
Simulation time 48353951721 ps
CPU time 91.5 seconds
Started Jun 30 05:11:40 PM PDT 24
Finished Jun 30 05:13:12 PM PDT 24
Peak memory 199860 kb
Host smart-7fb98709-b8de-49ac-91a2-02f6a18d5493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174525812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3174525812
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2463063463
Short name T22
Test name
Test status
Simulation time 11827905 ps
CPU time 0.58 seconds
Started Jun 30 05:07:45 PM PDT 24
Finished Jun 30 05:07:46 PM PDT 24
Peak memory 195220 kb
Host smart-55897531-edb6-4a64-93be-0ff0eeb3b5dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463063463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2463063463
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.1587687656
Short name T303
Test name
Test status
Simulation time 175036946240 ps
CPU time 191.77 seconds
Started Jun 30 05:07:33 PM PDT 24
Finished Jun 30 05:10:47 PM PDT 24
Peak memory 199808 kb
Host smart-052949b2-b78e-4224-87e1-477ba39d63a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587687656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1587687656
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.542057914
Short name T1010
Test name
Test status
Simulation time 67353489539 ps
CPU time 203.09 seconds
Started Jun 30 05:07:35 PM PDT 24
Finished Jun 30 05:10:59 PM PDT 24
Peak memory 199856 kb
Host smart-0585dee8-1593-4f84-9b1f-1636089a1978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542057914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.542057914
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.547333287
Short name T506
Test name
Test status
Simulation time 103793578889 ps
CPU time 139.24 seconds
Started Jun 30 05:07:36 PM PDT 24
Finished Jun 30 05:09:56 PM PDT 24
Peak memory 199864 kb
Host smart-8dfdc3eb-72cd-46b0-af9b-d0ad98e95452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547333287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.547333287
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.2004433663
Short name T579
Test name
Test status
Simulation time 250703211584 ps
CPU time 484.27 seconds
Started Jun 30 05:07:40 PM PDT 24
Finished Jun 30 05:15:45 PM PDT 24
Peak memory 199816 kb
Host smart-fd283476-4d19-4295-aa69-de9aea4538b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2004433663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2004433663
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.3650007481
Short name T405
Test name
Test status
Simulation time 10357024549 ps
CPU time 13.74 seconds
Started Jun 30 05:07:36 PM PDT 24
Finished Jun 30 05:07:51 PM PDT 24
Peak memory 198396 kb
Host smart-a0f66aa1-0c1c-417e-833a-6f02fc092e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650007481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3650007481
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.2032290888
Short name T630
Test name
Test status
Simulation time 45676559838 ps
CPU time 67.98 seconds
Started Jun 30 05:07:35 PM PDT 24
Finished Jun 30 05:08:44 PM PDT 24
Peak memory 199904 kb
Host smart-6a8a9d8f-ce06-441e-80c4-08e1958f8519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032290888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2032290888
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.1818781929
Short name T1079
Test name
Test status
Simulation time 6586052211 ps
CPU time 96.94 seconds
Started Jun 30 05:07:41 PM PDT 24
Finished Jun 30 05:09:19 PM PDT 24
Peak memory 199884 kb
Host smart-38ed42fc-836f-44ab-b26d-ae78939e8e4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1818781929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1818781929
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.3753444573
Short name T31
Test name
Test status
Simulation time 3360574817 ps
CPU time 22.39 seconds
Started Jun 30 05:07:35 PM PDT 24
Finished Jun 30 05:07:58 PM PDT 24
Peak memory 198304 kb
Host smart-a16d6da0-cb88-4d1d-8384-3b4b5d8527d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3753444573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3753444573
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.3063936492
Short name T365
Test name
Test status
Simulation time 38413219817 ps
CPU time 18.5 seconds
Started Jun 30 05:07:35 PM PDT 24
Finished Jun 30 05:07:55 PM PDT 24
Peak memory 199864 kb
Host smart-873667dd-aa97-48f8-9e69-0643e82d3a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063936492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3063936492
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.3463594422
Short name T336
Test name
Test status
Simulation time 3644316599 ps
CPU time 1.29 seconds
Started Jun 30 05:07:33 PM PDT 24
Finished Jun 30 05:07:35 PM PDT 24
Peak memory 196368 kb
Host smart-f4c0fa6e-e903-40a6-b5c8-e907043c761e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463594422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3463594422
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.3802354201
Short name T455
Test name
Test status
Simulation time 5578011800 ps
CPU time 10.05 seconds
Started Jun 30 05:07:34 PM PDT 24
Finished Jun 30 05:07:46 PM PDT 24
Peak memory 199924 kb
Host smart-1f7896f9-f4d8-421c-9671-f1171668fb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802354201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.3802354201
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.2575237779
Short name T936
Test name
Test status
Simulation time 139576222880 ps
CPU time 566.74 seconds
Started Jun 30 05:07:42 PM PDT 24
Finished Jun 30 05:17:10 PM PDT 24
Peak memory 199952 kb
Host smart-1f553887-9496-486d-920d-0fbfd87f9e25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575237779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2575237779
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.3601190619
Short name T32
Test name
Test status
Simulation time 1212281546 ps
CPU time 2.43 seconds
Started Jun 30 05:07:36 PM PDT 24
Finished Jun 30 05:07:39 PM PDT 24
Peak memory 198252 kb
Host smart-6004ad0b-1128-47ca-aaf2-b01861eb588a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601190619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3601190619
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.2732085323
Short name T686
Test name
Test status
Simulation time 7830407725 ps
CPU time 3.28 seconds
Started Jun 30 05:07:34 PM PDT 24
Finished Jun 30 05:07:38 PM PDT 24
Peak memory 199820 kb
Host smart-cdc4c530-52d9-47f1-bd5d-3ea5037c4323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732085323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2732085323
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.141625411
Short name T171
Test name
Test status
Simulation time 119009005694 ps
CPU time 70.23 seconds
Started Jun 30 05:11:40 PM PDT 24
Finished Jun 30 05:12:51 PM PDT 24
Peak memory 199864 kb
Host smart-c08a3fee-7367-4049-9026-d996c96ea87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141625411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.141625411
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.1519690620
Short name T437
Test name
Test status
Simulation time 8925424735 ps
CPU time 13.67 seconds
Started Jun 30 05:11:42 PM PDT 24
Finished Jun 30 05:11:56 PM PDT 24
Peak memory 199824 kb
Host smart-c2adcc26-bbdf-4e14-9931-c5fc0ee9a596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519690620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.1519690620
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.3808701650
Short name T217
Test name
Test status
Simulation time 36770877230 ps
CPU time 58.17 seconds
Started Jun 30 05:11:41 PM PDT 24
Finished Jun 30 05:12:39 PM PDT 24
Peak memory 199832 kb
Host smart-e2fd37ac-c9f8-4f7a-a82e-3e2f316b0581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808701650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.3808701650
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.141902247
Short name T846
Test name
Test status
Simulation time 76008765035 ps
CPU time 8.37 seconds
Started Jun 30 05:11:42 PM PDT 24
Finished Jun 30 05:11:50 PM PDT 24
Peak memory 199888 kb
Host smart-d654821f-c88d-4d33-b60a-d832cb58fdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141902247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.141902247
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.3819906860
Short name T204
Test name
Test status
Simulation time 68980592273 ps
CPU time 73.42 seconds
Started Jun 30 05:11:47 PM PDT 24
Finished Jun 30 05:13:01 PM PDT 24
Peak memory 199852 kb
Host smart-455ac53b-f942-43fb-ba13-7055d3d1a1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819906860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3819906860
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.3013569267
Short name T136
Test name
Test status
Simulation time 6708219271 ps
CPU time 12.92 seconds
Started Jun 30 05:11:47 PM PDT 24
Finished Jun 30 05:12:01 PM PDT 24
Peak memory 199900 kb
Host smart-a90efff8-a1ba-4ec4-acbf-f9dc10ccbf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013569267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.3013569267
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2511002072
Short name T147
Test name
Test status
Simulation time 10318861366 ps
CPU time 17.04 seconds
Started Jun 30 05:11:48 PM PDT 24
Finished Jun 30 05:12:05 PM PDT 24
Peak memory 199936 kb
Host smart-c7923f28-ad92-40e2-8fa3-4ca0765e0024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511002072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2511002072
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.1680230112
Short name T885
Test name
Test status
Simulation time 71818383811 ps
CPU time 37.1 seconds
Started Jun 30 05:11:48 PM PDT 24
Finished Jun 30 05:12:25 PM PDT 24
Peak memory 199912 kb
Host smart-cd96ac5a-5f46-4dbb-8b1c-76e71fc32afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680230112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1680230112
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.4236727445
Short name T106
Test name
Test status
Simulation time 20311919672 ps
CPU time 38.69 seconds
Started Jun 30 05:11:47 PM PDT 24
Finished Jun 30 05:12:27 PM PDT 24
Peak memory 199844 kb
Host smart-47f3616a-f78d-4ae0-9447-b38ba482c35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236727445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.4236727445
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.2326577132
Short name T738
Test name
Test status
Simulation time 10875309 ps
CPU time 0.55 seconds
Started Jun 30 05:06:28 PM PDT 24
Finished Jun 30 05:06:30 PM PDT 24
Peak memory 194212 kb
Host smart-a6f7d836-bf67-428c-b199-f7bf370604eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326577132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.2326577132
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.1687577477
Short name T426
Test name
Test status
Simulation time 175233063236 ps
CPU time 666.69 seconds
Started Jun 30 05:06:29 PM PDT 24
Finished Jun 30 05:17:38 PM PDT 24
Peak memory 199896 kb
Host smart-b37cb24e-0d7e-42a2-b814-e31390d184eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687577477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1687577477
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3226129686
Short name T465
Test name
Test status
Simulation time 122864444162 ps
CPU time 174 seconds
Started Jun 30 05:06:28 PM PDT 24
Finished Jun 30 05:09:24 PM PDT 24
Peak memory 199732 kb
Host smart-3b0c7b57-f93c-418b-afcb-54e7f80ab5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226129686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3226129686
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.1880479281
Short name T812
Test name
Test status
Simulation time 154071143195 ps
CPU time 81.46 seconds
Started Jun 30 05:06:27 PM PDT 24
Finished Jun 30 05:07:50 PM PDT 24
Peak memory 199852 kb
Host smart-6008c930-3908-414a-891d-b7dd37eda087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880479281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1880479281
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.1387100840
Short name T698
Test name
Test status
Simulation time 11814640649 ps
CPU time 33.42 seconds
Started Jun 30 05:06:28 PM PDT 24
Finished Jun 30 05:07:03 PM PDT 24
Peak memory 199516 kb
Host smart-65a613a8-c127-4214-8c2e-0368ad0470f9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387100840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1387100840
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.570151331
Short name T246
Test name
Test status
Simulation time 95597896665 ps
CPU time 491.3 seconds
Started Jun 30 05:06:34 PM PDT 24
Finished Jun 30 05:14:46 PM PDT 24
Peak memory 199864 kb
Host smart-8d68400e-826a-476f-9c2a-6edd1841d47d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=570151331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.570151331
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.3149269607
Short name T374
Test name
Test status
Simulation time 9049139824 ps
CPU time 16.16 seconds
Started Jun 30 05:06:27 PM PDT 24
Finished Jun 30 05:06:45 PM PDT 24
Peak memory 199868 kb
Host smart-f7ae26f1-b8cc-4f45-97e8-7cbb10b6381f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149269607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.3149269607
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_perf.2284258253
Short name T414
Test name
Test status
Simulation time 19302174182 ps
CPU time 139.3 seconds
Started Jun 30 05:06:28 PM PDT 24
Finished Jun 30 05:08:49 PM PDT 24
Peak memory 199892 kb
Host smart-115baef4-ff93-48db-9b7c-4c6d6f0b1f0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2284258253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2284258253
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.759071978
Short name T1050
Test name
Test status
Simulation time 6066469129 ps
CPU time 55.16 seconds
Started Jun 30 05:06:30 PM PDT 24
Finished Jun 30 05:07:27 PM PDT 24
Peak memory 198712 kb
Host smart-15e43507-6cd0-4a8f-ab57-aca8580ced92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=759071978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.759071978
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1923946316
Short name T675
Test name
Test status
Simulation time 32842262524 ps
CPU time 49.05 seconds
Started Jun 30 05:06:31 PM PDT 24
Finished Jun 30 05:07:21 PM PDT 24
Peak memory 199920 kb
Host smart-5f958086-cd01-4897-a413-230c761a3af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923946316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1923946316
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.4175345192
Short name T528
Test name
Test status
Simulation time 25154285063 ps
CPU time 14.26 seconds
Started Jun 30 05:06:29 PM PDT 24
Finished Jun 30 05:06:45 PM PDT 24
Peak memory 196116 kb
Host smart-497d9a51-95e0-4144-807e-b6f8824b37c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175345192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.4175345192
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.4001903702
Short name T99
Test name
Test status
Simulation time 111532210 ps
CPU time 0.88 seconds
Started Jun 30 05:06:31 PM PDT 24
Finished Jun 30 05:06:33 PM PDT 24
Peak memory 218208 kb
Host smart-3260c775-dd3e-4ee4-8d3e-408f134bed07
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001903702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.4001903702
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.1800060991
Short name T523
Test name
Test status
Simulation time 5760654970 ps
CPU time 11.69 seconds
Started Jun 30 05:06:28 PM PDT 24
Finished Jun 30 05:06:42 PM PDT 24
Peak memory 199224 kb
Host smart-be561e97-7c14-42ad-84b1-c9c33c32d3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800060991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1800060991
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.3031787240
Short name T221
Test name
Test status
Simulation time 147651979104 ps
CPU time 255.87 seconds
Started Jun 30 05:06:29 PM PDT 24
Finished Jun 30 05:10:46 PM PDT 24
Peak memory 199908 kb
Host smart-555d3173-6b68-40a0-b374-45c8e7698847
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031787240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3031787240
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.752100844
Short name T46
Test name
Test status
Simulation time 46984759030 ps
CPU time 563.92 seconds
Started Jun 30 05:06:33 PM PDT 24
Finished Jun 30 05:15:57 PM PDT 24
Peak memory 216420 kb
Host smart-fbb85da5-5eb2-4798-8b5d-646ca2bcf4ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752100844 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.752100844
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.2020851751
Short name T879
Test name
Test status
Simulation time 1403918941 ps
CPU time 2.58 seconds
Started Jun 30 05:06:33 PM PDT 24
Finished Jun 30 05:06:36 PM PDT 24
Peak memory 199864 kb
Host smart-00445c3e-8f5c-4654-9229-26547f8b650f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020851751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.2020851751
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3187960780
Short name T248
Test name
Test status
Simulation time 79869327910 ps
CPU time 281.77 seconds
Started Jun 30 05:06:29 PM PDT 24
Finished Jun 30 05:11:12 PM PDT 24
Peak memory 199884 kb
Host smart-78d82ee4-3e4c-4477-ab16-47aea2ae0648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187960780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3187960780
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.1979774428
Short name T424
Test name
Test status
Simulation time 43891682 ps
CPU time 0.55 seconds
Started Jun 30 05:07:46 PM PDT 24
Finished Jun 30 05:07:47 PM PDT 24
Peak memory 195516 kb
Host smart-1624fc3f-fbb3-447e-a521-83028b7db944
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979774428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1979774428
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.3474685532
Short name T731
Test name
Test status
Simulation time 148860236622 ps
CPU time 62.37 seconds
Started Jun 30 05:07:44 PM PDT 24
Finished Jun 30 05:08:47 PM PDT 24
Peak memory 199900 kb
Host smart-61c4cf6a-470e-4ecb-8f42-c8ac92f4d601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474685532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3474685532
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.1778560140
Short name T647
Test name
Test status
Simulation time 27176445902 ps
CPU time 21.69 seconds
Started Jun 30 05:07:45 PM PDT 24
Finished Jun 30 05:08:08 PM PDT 24
Peak memory 199920 kb
Host smart-a8d9dd0c-5341-4b6b-aa30-2f2b38a88a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778560140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1778560140
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.253060055
Short name T586
Test name
Test status
Simulation time 68542840191 ps
CPU time 105.66 seconds
Started Jun 30 05:07:41 PM PDT 24
Finished Jun 30 05:09:27 PM PDT 24
Peak memory 199852 kb
Host smart-50c78428-85b9-4320-9a26-ee9bdf10d767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253060055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.253060055
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.2298553121
Short name T657
Test name
Test status
Simulation time 426066659637 ps
CPU time 616.07 seconds
Started Jun 30 05:07:42 PM PDT 24
Finished Jun 30 05:17:59 PM PDT 24
Peak memory 198644 kb
Host smart-db72add9-9ebb-4100-a649-911d706fdb2f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298553121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.2298553121
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_loopback.3847847825
Short name T762
Test name
Test status
Simulation time 4990420415 ps
CPU time 3.41 seconds
Started Jun 30 05:07:41 PM PDT 24
Finished Jun 30 05:07:45 PM PDT 24
Peak memory 199056 kb
Host smart-d118b5f9-210e-4814-a3ef-6eedaa91720a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847847825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.3847847825
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.3596697875
Short name T672
Test name
Test status
Simulation time 53776754447 ps
CPU time 52.16 seconds
Started Jun 30 05:07:42 PM PDT 24
Finished Jun 30 05:08:34 PM PDT 24
Peak memory 199924 kb
Host smart-8499f9fb-7ca4-4eb5-bc56-9184edc0a63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596697875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3596697875
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.3434865514
Short name T642
Test name
Test status
Simulation time 5386084316 ps
CPU time 43.4 seconds
Started Jun 30 05:07:40 PM PDT 24
Finished Jun 30 05:08:24 PM PDT 24
Peak memory 199248 kb
Host smart-96545c3f-46f6-4b4b-a706-9228ce1a8786
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3434865514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.3434865514
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.4216812851
Short name T74
Test name
Test status
Simulation time 38425811342 ps
CPU time 20.31 seconds
Started Jun 30 05:07:42 PM PDT 24
Finished Jun 30 05:08:03 PM PDT 24
Peak memory 199808 kb
Host smart-36df8bc3-f4bb-4d79-b1de-d2c0e6658b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216812851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.4216812851
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.2173978941
Short name T822
Test name
Test status
Simulation time 4511798146 ps
CPU time 1.58 seconds
Started Jun 30 05:07:46 PM PDT 24
Finished Jun 30 05:07:48 PM PDT 24
Peak memory 196172 kb
Host smart-ab3b6236-415f-4093-b612-1407d8d6722d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173978941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2173978941
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.1451929864
Short name T1023
Test name
Test status
Simulation time 740930853 ps
CPU time 1.71 seconds
Started Jun 30 05:07:41 PM PDT 24
Finished Jun 30 05:07:43 PM PDT 24
Peak memory 198248 kb
Host smart-5a1f1808-3c91-4411-8cb7-55545324eeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451929864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1451929864
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.243435742
Short name T154
Test name
Test status
Simulation time 49522406376 ps
CPU time 260.05 seconds
Started Jun 30 05:07:42 PM PDT 24
Finished Jun 30 05:12:03 PM PDT 24
Peak memory 199748 kb
Host smart-a49c2df3-9a45-41db-98bb-eb88846c7d09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243435742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.243435742
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.3120380424
Short name T492
Test name
Test status
Simulation time 7599738583 ps
CPU time 6.01 seconds
Started Jun 30 05:07:40 PM PDT 24
Finished Jun 30 05:07:47 PM PDT 24
Peak memory 199872 kb
Host smart-878aa80b-f27c-4df6-b41f-b70b6a641ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120380424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3120380424
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.1061279848
Short name T786
Test name
Test status
Simulation time 35902086768 ps
CPU time 162.77 seconds
Started Jun 30 05:07:45 PM PDT 24
Finished Jun 30 05:10:28 PM PDT 24
Peak memory 199920 kb
Host smart-e8a0872f-7245-4759-b550-10ad9c2ad138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061279848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.1061279848
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.4265928244
Short name T138
Test name
Test status
Simulation time 91040773299 ps
CPU time 36.26 seconds
Started Jun 30 05:11:47 PM PDT 24
Finished Jun 30 05:12:24 PM PDT 24
Peak memory 199920 kb
Host smart-46b5d6e6-4b0f-4588-9e9f-06d0a73b7f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265928244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.4265928244
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.229141561
Short name T145
Test name
Test status
Simulation time 28554536857 ps
CPU time 78.52 seconds
Started Jun 30 05:11:46 PM PDT 24
Finished Jun 30 05:13:06 PM PDT 24
Peak memory 199924 kb
Host smart-5b6df7c9-87f9-4de5-b504-41129f088f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229141561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.229141561
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1774823654
Short name T236
Test name
Test status
Simulation time 84993839106 ps
CPU time 35.56 seconds
Started Jun 30 05:11:48 PM PDT 24
Finished Jun 30 05:12:24 PM PDT 24
Peak memory 199836 kb
Host smart-75fe1401-fadb-4d3a-861e-042a1e90d2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774823654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1774823654
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.1997877987
Short name T411
Test name
Test status
Simulation time 30945990189 ps
CPU time 34.33 seconds
Started Jun 30 05:11:47 PM PDT 24
Finished Jun 30 05:12:22 PM PDT 24
Peak memory 199824 kb
Host smart-717dffe2-e210-4b6a-9a4e-c7f7156488bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997877987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.1997877987
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.1092180866
Short name T963
Test name
Test status
Simulation time 13890266805 ps
CPU time 24.39 seconds
Started Jun 30 05:11:46 PM PDT 24
Finished Jun 30 05:12:12 PM PDT 24
Peak memory 199840 kb
Host smart-bad21e77-1a82-4c08-833c-9f6ab3f36039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092180866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1092180866
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.1461702881
Short name T1005
Test name
Test status
Simulation time 20602599443 ps
CPU time 33.97 seconds
Started Jun 30 05:11:48 PM PDT 24
Finished Jun 30 05:12:23 PM PDT 24
Peak memory 199888 kb
Host smart-59d7e914-35c9-4b88-816d-fc5fd3e78375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461702881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1461702881
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.3545910688
Short name T997
Test name
Test status
Simulation time 13849599574 ps
CPU time 12.29 seconds
Started Jun 30 05:11:48 PM PDT 24
Finished Jun 30 05:12:00 PM PDT 24
Peak memory 200136 kb
Host smart-10d5cfe2-3ca8-4543-9cad-598619d204c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545910688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.3545910688
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.490499664
Short name T403
Test name
Test status
Simulation time 290709407749 ps
CPU time 29.13 seconds
Started Jun 30 05:11:49 PM PDT 24
Finished Jun 30 05:12:19 PM PDT 24
Peak memory 199828 kb
Host smart-15f5806f-afef-43b4-b2c3-258db624ae33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490499664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.490499664
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.1854008695
Short name T578
Test name
Test status
Simulation time 13945344 ps
CPU time 0.56 seconds
Started Jun 30 05:07:51 PM PDT 24
Finished Jun 30 05:07:52 PM PDT 24
Peak memory 195520 kb
Host smart-27a65dfd-41c6-4d1a-9902-1dfe8b251b9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854008695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1854008695
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.1239786914
Short name T122
Test name
Test status
Simulation time 72783467554 ps
CPU time 26.91 seconds
Started Jun 30 05:07:41 PM PDT 24
Finished Jun 30 05:08:09 PM PDT 24
Peak memory 199844 kb
Host smart-a5a8a4c5-eec6-4886-8995-5f5bbde0a6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239786914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.1239786914
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.1285217551
Short name T982
Test name
Test status
Simulation time 37458272091 ps
CPU time 29.49 seconds
Started Jun 30 05:07:49 PM PDT 24
Finished Jun 30 05:08:20 PM PDT 24
Peak memory 199832 kb
Host smart-74f55f61-8be2-417c-8dff-463f0e87b87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285217551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.1285217551
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.1095675716
Short name T407
Test name
Test status
Simulation time 7345649793 ps
CPU time 3.83 seconds
Started Jun 30 05:07:49 PM PDT 24
Finished Jun 30 05:07:53 PM PDT 24
Peak memory 196732 kb
Host smart-95c65bfe-e288-4478-94c0-433aa66afa50
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095675716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1095675716
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.2951910653
Short name T950
Test name
Test status
Simulation time 103208047069 ps
CPU time 522.23 seconds
Started Jun 30 05:07:49 PM PDT 24
Finished Jun 30 05:16:33 PM PDT 24
Peak memory 199880 kb
Host smart-4bd1683f-c8c7-462e-83ab-99c201ce844e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2951910653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2951910653
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.1295917770
Short name T914
Test name
Test status
Simulation time 3729414477 ps
CPU time 8.11 seconds
Started Jun 30 05:07:50 PM PDT 24
Finished Jun 30 05:07:59 PM PDT 24
Peak memory 199392 kb
Host smart-379e91bf-e7e7-4732-929e-4d02da0ebc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295917770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1295917770
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_perf.1399552588
Short name T37
Test name
Test status
Simulation time 30476750924 ps
CPU time 1449.74 seconds
Started Jun 30 05:07:50 PM PDT 24
Finished Jun 30 05:32:01 PM PDT 24
Peak memory 199844 kb
Host smart-48ec2e4d-4231-419b-b9f5-00ba9ad5b6cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1399552588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1399552588
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.628726725
Short name T872
Test name
Test status
Simulation time 2022729035 ps
CPU time 2.68 seconds
Started Jun 30 05:07:50 PM PDT 24
Finished Jun 30 05:07:54 PM PDT 24
Peak memory 198064 kb
Host smart-fe2e8339-0367-4985-8e6c-b2a01af9307d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=628726725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.628726725
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.2839191154
Short name T441
Test name
Test status
Simulation time 189723698651 ps
CPU time 332.94 seconds
Started Jun 30 05:07:49 PM PDT 24
Finished Jun 30 05:13:24 PM PDT 24
Peak memory 199836 kb
Host smart-03ac20f2-3f4d-43df-94f9-a9c484275ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839191154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2839191154
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2005101271
Short name T736
Test name
Test status
Simulation time 34628761796 ps
CPU time 14.81 seconds
Started Jun 30 05:07:48 PM PDT 24
Finished Jun 30 05:08:04 PM PDT 24
Peak memory 196336 kb
Host smart-a7a7de6e-8f5c-42ee-afdc-4c74e14e268e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005101271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2005101271
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.426048028
Short name T267
Test name
Test status
Simulation time 138181231 ps
CPU time 0.85 seconds
Started Jun 30 05:07:45 PM PDT 24
Finished Jun 30 05:07:46 PM PDT 24
Peak memory 197836 kb
Host smart-2d5be53d-6ea4-4bb1-8545-9fc02bc07f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426048028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.426048028
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.3965884450
Short name T296
Test name
Test status
Simulation time 210294807851 ps
CPU time 772.1 seconds
Started Jun 30 05:07:49 PM PDT 24
Finished Jun 30 05:20:42 PM PDT 24
Peak memory 215380 kb
Host smart-6616498e-71d9-4419-9eb3-b4b52e329f77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965884450 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.3965884450
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2724278297
Short name T670
Test name
Test status
Simulation time 877481075 ps
CPU time 1.65 seconds
Started Jun 30 05:07:51 PM PDT 24
Finished Jun 30 05:07:54 PM PDT 24
Peak memory 198712 kb
Host smart-365c48f6-7b31-47ae-99a4-814dead97c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724278297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2724278297
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.1560721947
Short name T66
Test name
Test status
Simulation time 4464308177 ps
CPU time 6.79 seconds
Started Jun 30 05:07:45 PM PDT 24
Finished Jun 30 05:07:53 PM PDT 24
Peak memory 196952 kb
Host smart-78f1d886-8174-4a9e-98da-0445d723d884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560721947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1560721947
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1079962650
Short name T179
Test name
Test status
Simulation time 158932988416 ps
CPU time 57.74 seconds
Started Jun 30 05:11:50 PM PDT 24
Finished Jun 30 05:12:48 PM PDT 24
Peak memory 199908 kb
Host smart-0a3c63c6-15c2-4cd2-a6c2-e51c686ee076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079962650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1079962650
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.3889382778
Short name T72
Test name
Test status
Simulation time 37262441035 ps
CPU time 15.37 seconds
Started Jun 30 05:11:49 PM PDT 24
Finished Jun 30 05:12:05 PM PDT 24
Peak memory 199820 kb
Host smart-06697aef-65f4-49e1-be9d-f471ec9836d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889382778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3889382778
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.3548493255
Short name T546
Test name
Test status
Simulation time 164434992300 ps
CPU time 286.23 seconds
Started Jun 30 05:11:48 PM PDT 24
Finished Jun 30 05:16:35 PM PDT 24
Peak memory 199788 kb
Host smart-a8779f87-f699-497c-b0f6-6865fc7dd94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548493255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.3548493255
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.1308253569
Short name T278
Test name
Test status
Simulation time 18256866093 ps
CPU time 17.11 seconds
Started Jun 30 05:11:53 PM PDT 24
Finished Jun 30 05:12:11 PM PDT 24
Peak memory 199884 kb
Host smart-06ec2fdb-e3f9-4720-89b3-6b2ae2a84e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308253569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.1308253569
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2908613238
Short name T140
Test name
Test status
Simulation time 113360542919 ps
CPU time 165.98 seconds
Started Jun 30 05:11:55 PM PDT 24
Finished Jun 30 05:14:41 PM PDT 24
Peak memory 199920 kb
Host smart-53ae8f39-8a6a-4421-b66a-a2d7579e2534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908613238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2908613238
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.522705752
Short name T829
Test name
Test status
Simulation time 167349465466 ps
CPU time 65.3 seconds
Started Jun 30 05:11:57 PM PDT 24
Finished Jun 30 05:13:02 PM PDT 24
Peak memory 199856 kb
Host smart-d1c58129-70b8-4285-b070-62f51caf8793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522705752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.522705752
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1913244574
Short name T170
Test name
Test status
Simulation time 531977163226 ps
CPU time 64.51 seconds
Started Jun 30 05:11:54 PM PDT 24
Finished Jun 30 05:12:59 PM PDT 24
Peak memory 199760 kb
Host smart-8a980786-d092-4414-b0e7-0013128ce73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913244574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1913244574
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.3261908846
Short name T1098
Test name
Test status
Simulation time 54303047682 ps
CPU time 71.95 seconds
Started Jun 30 05:11:55 PM PDT 24
Finished Jun 30 05:13:07 PM PDT 24
Peak memory 199800 kb
Host smart-8bba5970-8aa4-489e-808c-306cb3e03a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261908846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.3261908846
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2688126543
Short name T439
Test name
Test status
Simulation time 40030758551 ps
CPU time 18.74 seconds
Started Jun 30 05:11:56 PM PDT 24
Finished Jun 30 05:12:15 PM PDT 24
Peak memory 200060 kb
Host smart-5adf5a84-549d-4e30-859d-c0e2eec0c233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688126543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2688126543
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.752131953
Short name T392
Test name
Test status
Simulation time 18414330 ps
CPU time 0.58 seconds
Started Jun 30 05:07:48 PM PDT 24
Finished Jun 30 05:07:50 PM PDT 24
Peak memory 195532 kb
Host smart-e00e74b4-5467-488d-a570-e993bd71cd87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752131953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.752131953
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.1019109589
Short name T173
Test name
Test status
Simulation time 282859677623 ps
CPU time 108.97 seconds
Started Jun 30 05:07:47 PM PDT 24
Finished Jun 30 05:09:37 PM PDT 24
Peak memory 199732 kb
Host smart-844f96c2-0604-4be3-94c1-50824a8fb8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019109589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1019109589
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.4042925369
Short name T255
Test name
Test status
Simulation time 123408082172 ps
CPU time 186.02 seconds
Started Jun 30 05:07:49 PM PDT 24
Finished Jun 30 05:10:56 PM PDT 24
Peak memory 199912 kb
Host smart-8abb7d62-d5b8-4831-b9b7-620914d439e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042925369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.4042925369
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.2022655819
Short name T533
Test name
Test status
Simulation time 46754745003 ps
CPU time 25.02 seconds
Started Jun 30 05:07:51 PM PDT 24
Finished Jun 30 05:08:17 PM PDT 24
Peak memory 199956 kb
Host smart-a51468f7-95ad-4c8c-b94b-8ac7df9d4bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022655819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2022655819
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.1209875949
Short name T382
Test name
Test status
Simulation time 41298990916 ps
CPU time 17.24 seconds
Started Jun 30 05:07:48 PM PDT 24
Finished Jun 30 05:08:06 PM PDT 24
Peak memory 199828 kb
Host smart-3827de7b-8aef-4bfd-80ce-2fb41cfdbb14
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209875949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1209875949
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.1245565894
Short name T701
Test name
Test status
Simulation time 265069807732 ps
CPU time 213.71 seconds
Started Jun 30 05:07:50 PM PDT 24
Finished Jun 30 05:11:25 PM PDT 24
Peak memory 199840 kb
Host smart-ab88495c-2a10-4a20-ad8f-0a0554af279d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1245565894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1245565894
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.3663993043
Short name T951
Test name
Test status
Simulation time 6881309326 ps
CPU time 13.16 seconds
Started Jun 30 05:07:52 PM PDT 24
Finished Jun 30 05:08:06 PM PDT 24
Peak memory 197956 kb
Host smart-e6a292b3-ada6-4ec9-a5ed-80c726f2eafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663993043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3663993043
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.3387574985
Short name T854
Test name
Test status
Simulation time 153019608913 ps
CPU time 141.55 seconds
Started Jun 30 05:07:48 PM PDT 24
Finished Jun 30 05:10:11 PM PDT 24
Peak memory 199940 kb
Host smart-1baef997-669b-4e55-9f34-bf1c79715c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387574985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.3387574985
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.2549989400
Short name T432
Test name
Test status
Simulation time 14283508985 ps
CPU time 691.3 seconds
Started Jun 30 05:07:50 PM PDT 24
Finished Jun 30 05:19:23 PM PDT 24
Peak memory 199900 kb
Host smart-6037a0fb-9842-4631-8b27-a88ca04388fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2549989400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2549989400
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.4156178347
Short name T1004
Test name
Test status
Simulation time 2832256170 ps
CPU time 18.04 seconds
Started Jun 30 05:07:49 PM PDT 24
Finished Jun 30 05:08:08 PM PDT 24
Peak memory 198088 kb
Host smart-c057aa72-057a-4fd5-92f0-af11791bf213
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4156178347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.4156178347
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.4011032932
Short name T682
Test name
Test status
Simulation time 51525581768 ps
CPU time 83.82 seconds
Started Jun 30 05:07:50 PM PDT 24
Finished Jun 30 05:09:15 PM PDT 24
Peak memory 199896 kb
Host smart-8f24624c-961b-4d2a-8e0e-ae24d6f64728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011032932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.4011032932
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.1795073510
Short name T1084
Test name
Test status
Simulation time 1567220523 ps
CPU time 2.99 seconds
Started Jun 30 05:07:51 PM PDT 24
Finished Jun 30 05:07:55 PM PDT 24
Peak memory 195376 kb
Host smart-7c723104-95d6-46d3-8bee-db94ad47f2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795073510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1795073510
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.3804353011
Short name T334
Test name
Test status
Simulation time 248743353 ps
CPU time 1.37 seconds
Started Jun 30 05:07:50 PM PDT 24
Finished Jun 30 05:07:52 PM PDT 24
Peak memory 198204 kb
Host smart-a0726a96-233c-4708-bbde-f99d1497659e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804353011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3804353011
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.2479481597
Short name T784
Test name
Test status
Simulation time 146477685513 ps
CPU time 758.8 seconds
Started Jun 30 05:07:51 PM PDT 24
Finished Jun 30 05:20:31 PM PDT 24
Peak memory 199840 kb
Host smart-a1f9a4e5-e13e-4e24-a2a0-edcc30b049b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479481597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.2479481597
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.1700732740
Short name T782
Test name
Test status
Simulation time 48724160331 ps
CPU time 880.34 seconds
Started Jun 30 05:07:51 PM PDT 24
Finished Jun 30 05:22:32 PM PDT 24
Peak memory 214916 kb
Host smart-47064196-a014-42f6-a464-c52f97df168c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700732740 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.1700732740
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.3496720900
Short name T287
Test name
Test status
Simulation time 8625656014 ps
CPU time 5.87 seconds
Started Jun 30 05:07:50 PM PDT 24
Finished Jun 30 05:07:57 PM PDT 24
Peak memory 199204 kb
Host smart-9f458a8b-fc38-4bca-abde-defe40c88bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496720900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.3496720900
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3001075276
Short name T102
Test name
Test status
Simulation time 42972683060 ps
CPU time 18.51 seconds
Started Jun 30 05:07:52 PM PDT 24
Finished Jun 30 05:08:11 PM PDT 24
Peak memory 199796 kb
Host smart-929db39a-ba0a-4e18-80cc-6ba223752604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001075276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3001075276
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1296227661
Short name T875
Test name
Test status
Simulation time 95480551288 ps
CPU time 159.46 seconds
Started Jun 30 05:11:55 PM PDT 24
Finished Jun 30 05:14:35 PM PDT 24
Peak memory 199796 kb
Host smart-4e3c97a6-65c1-443a-a58d-a3b4977bf572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296227661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1296227661
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.894999041
Short name T791
Test name
Test status
Simulation time 52337937923 ps
CPU time 69.67 seconds
Started Jun 30 05:11:56 PM PDT 24
Finished Jun 30 05:13:06 PM PDT 24
Peak memory 199860 kb
Host smart-7532efc2-d93b-49c0-8fc1-1095e53ac6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894999041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.894999041
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.1736639353
Short name T705
Test name
Test status
Simulation time 11738342559 ps
CPU time 17.1 seconds
Started Jun 30 05:11:54 PM PDT 24
Finished Jun 30 05:12:12 PM PDT 24
Peak memory 199940 kb
Host smart-4664720c-c5bd-44b6-b76a-3dd07dd2c960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736639353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.1736639353
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.2895913156
Short name T723
Test name
Test status
Simulation time 63226099958 ps
CPU time 93.93 seconds
Started Jun 30 05:11:56 PM PDT 24
Finished Jun 30 05:13:30 PM PDT 24
Peak memory 199876 kb
Host smart-a733b34e-a83e-4116-b902-8ea27d4dc9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895913156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2895913156
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.3384885539
Short name T209
Test name
Test status
Simulation time 58990999480 ps
CPU time 33.62 seconds
Started Jun 30 05:11:54 PM PDT 24
Finished Jun 30 05:12:28 PM PDT 24
Peak memory 199864 kb
Host smart-d0024131-65de-4488-83eb-6d40d7a0dc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384885539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3384885539
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3813094563
Short name T186
Test name
Test status
Simulation time 165930740862 ps
CPU time 107.52 seconds
Started Jun 30 05:11:55 PM PDT 24
Finished Jun 30 05:13:43 PM PDT 24
Peak memory 199852 kb
Host smart-0619c7f6-c729-4651-b928-47c151ee4b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813094563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3813094563
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.1794165521
Short name T1069
Test name
Test status
Simulation time 109668488827 ps
CPU time 150.17 seconds
Started Jun 30 05:11:56 PM PDT 24
Finished Jun 30 05:14:26 PM PDT 24
Peak memory 199820 kb
Host smart-fe4b88f7-751b-4e8e-80ee-fcb567181946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794165521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1794165521
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.74036860
Short name T712
Test name
Test status
Simulation time 47039805515 ps
CPU time 104.83 seconds
Started Jun 30 05:11:54 PM PDT 24
Finished Jun 30 05:13:40 PM PDT 24
Peak memory 199472 kb
Host smart-41e4291d-f639-4c8c-9e5d-f33c3c753d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74036860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.74036860
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.737910269
Short name T848
Test name
Test status
Simulation time 45915803227 ps
CPU time 92.07 seconds
Started Jun 30 05:11:56 PM PDT 24
Finished Jun 30 05:13:28 PM PDT 24
Peak memory 199904 kb
Host smart-072abb25-1bd3-4ba3-bf16-111614f838ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737910269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.737910269
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.401148153
Short name T21
Test name
Test status
Simulation time 20492146 ps
CPU time 0.58 seconds
Started Jun 30 05:08:00 PM PDT 24
Finished Jun 30 05:08:01 PM PDT 24
Peak memory 195228 kb
Host smart-91037405-0728-4f5d-a49a-130ab3e25e73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401148153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.401148153
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2850260614
Short name T141
Test name
Test status
Simulation time 257924762781 ps
CPU time 42.27 seconds
Started Jun 30 05:07:49 PM PDT 24
Finished Jun 30 05:08:33 PM PDT 24
Peak memory 199824 kb
Host smart-d4db3f56-74db-4de3-880d-19e9c48364dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850260614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2850260614
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.1059284222
Short name T965
Test name
Test status
Simulation time 21869678888 ps
CPU time 16.23 seconds
Started Jun 30 05:07:49 PM PDT 24
Finished Jun 30 05:08:07 PM PDT 24
Peak memory 199900 kb
Host smart-ffc89883-b694-4737-a691-18427a0091aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059284222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.1059284222
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.1397083920
Short name T729
Test name
Test status
Simulation time 31740264096 ps
CPU time 15.88 seconds
Started Jun 30 05:07:58 PM PDT 24
Finished Jun 30 05:08:14 PM PDT 24
Peak memory 200164 kb
Host smart-d324371e-e4b3-4131-bd23-036de5447d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397083920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.1397083920
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.3681607074
Short name T279
Test name
Test status
Simulation time 18709943103 ps
CPU time 41.16 seconds
Started Jun 30 05:07:56 PM PDT 24
Finished Jun 30 05:08:38 PM PDT 24
Peak memory 199912 kb
Host smart-8ce7290e-58a7-4d5c-9d19-abb0751e78eb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681607074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3681607074
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1615774942
Short name T1034
Test name
Test status
Simulation time 379118172015 ps
CPU time 79.31 seconds
Started Jun 30 05:07:57 PM PDT 24
Finished Jun 30 05:09:17 PM PDT 24
Peak memory 199868 kb
Host smart-c8d611f8-edde-4a04-883f-dd11fe3c401f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1615774942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1615774942
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.139577974
Short name T935
Test name
Test status
Simulation time 6468347910 ps
CPU time 10.8 seconds
Started Jun 30 05:07:56 PM PDT 24
Finished Jun 30 05:08:08 PM PDT 24
Peak memory 198320 kb
Host smart-258c2666-c7b6-43dc-b96f-83b32c3b4a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139577974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.139577974
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_perf.3077534205
Short name T240
Test name
Test status
Simulation time 30737471465 ps
CPU time 213.36 seconds
Started Jun 30 05:07:57 PM PDT 24
Finished Jun 30 05:11:31 PM PDT 24
Peak memory 199832 kb
Host smart-ad57b0dd-4dfe-47e5-8117-cc2bb2bf6fb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3077534205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3077534205
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1919294143
Short name T756
Test name
Test status
Simulation time 4834367944 ps
CPU time 37.91 seconds
Started Jun 30 05:07:56 PM PDT 24
Finished Jun 30 05:08:35 PM PDT 24
Peak memory 198084 kb
Host smart-c2bc18a2-c2b1-4ca5-b24f-cf456405bca2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1919294143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1919294143
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.4177578294
Short name T508
Test name
Test status
Simulation time 65320453535 ps
CPU time 118.37 seconds
Started Jun 30 05:08:00 PM PDT 24
Finished Jun 30 05:09:59 PM PDT 24
Peak memory 199920 kb
Host smart-4d10e741-958a-4e63-b6bd-f2cd75815397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177578294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.4177578294
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.392935330
Short name T1089
Test name
Test status
Simulation time 537798368 ps
CPU time 1.48 seconds
Started Jun 30 05:07:56 PM PDT 24
Finished Jun 30 05:07:58 PM PDT 24
Peak memory 195340 kb
Host smart-310f128a-78f9-445e-8696-54852bccaf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392935330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.392935330
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.3879497973
Short name T577
Test name
Test status
Simulation time 140148592 ps
CPU time 0.88 seconds
Started Jun 30 05:07:49 PM PDT 24
Finished Jun 30 05:07:51 PM PDT 24
Peak memory 196868 kb
Host smart-33711e72-2ad4-465b-b9de-de93d6143701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879497973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.3879497973
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.2561244066
Short name T1040
Test name
Test status
Simulation time 277107679371 ps
CPU time 38.99 seconds
Started Jun 30 05:07:56 PM PDT 24
Finished Jun 30 05:08:36 PM PDT 24
Peak memory 199808 kb
Host smart-a30b29d1-b4ce-4123-a673-9237c6456411
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561244066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.2561244066
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.2981129691
Short name T970
Test name
Test status
Simulation time 211358828360 ps
CPU time 1397.04 seconds
Started Jun 30 05:07:57 PM PDT 24
Finished Jun 30 05:31:15 PM PDT 24
Peak memory 216712 kb
Host smart-504b774b-119c-43c8-8baa-bf7ef58ef461
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981129691 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.2981129691
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.2502657189
Short name T883
Test name
Test status
Simulation time 2960410806 ps
CPU time 2.5 seconds
Started Jun 30 05:08:00 PM PDT 24
Finished Jun 30 05:08:02 PM PDT 24
Peak memory 198780 kb
Host smart-eab6ac0f-2445-4071-b47a-92bb5b59109c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502657189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2502657189
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.788561188
Short name T394
Test name
Test status
Simulation time 49667941718 ps
CPU time 14.43 seconds
Started Jun 30 05:07:48 PM PDT 24
Finished Jun 30 05:08:03 PM PDT 24
Peak memory 198148 kb
Host smart-61887b98-215c-4195-8b19-2b960bd99be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788561188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.788561188
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.3698765080
Short name T169
Test name
Test status
Simulation time 231509803464 ps
CPU time 163.47 seconds
Started Jun 30 05:12:04 PM PDT 24
Finished Jun 30 05:14:47 PM PDT 24
Peak memory 199840 kb
Host smart-53503b30-c6c9-4b1e-a699-3ddc27c8baef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698765080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.3698765080
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1671065344
Short name T174
Test name
Test status
Simulation time 115768536201 ps
CPU time 194.37 seconds
Started Jun 30 05:12:03 PM PDT 24
Finished Jun 30 05:15:18 PM PDT 24
Peak memory 199756 kb
Host smart-07c08f6b-40d1-4517-99f3-c87e1507fd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671065344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1671065344
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.1986421722
Short name T335
Test name
Test status
Simulation time 41042873678 ps
CPU time 31.51 seconds
Started Jun 30 05:12:03 PM PDT 24
Finished Jun 30 05:12:34 PM PDT 24
Peak memory 199884 kb
Host smart-67400384-4028-4480-9f32-8bbf0ea48a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986421722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1986421722
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.3236069693
Short name T38
Test name
Test status
Simulation time 44123259571 ps
CPU time 106.59 seconds
Started Jun 30 05:12:03 PM PDT 24
Finished Jun 30 05:13:50 PM PDT 24
Peak memory 199916 kb
Host smart-a95c8808-0e08-4a6e-897a-8b58fdf45283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236069693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3236069693
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2133145468
Short name T143
Test name
Test status
Simulation time 35202235050 ps
CPU time 30.89 seconds
Started Jun 30 05:12:02 PM PDT 24
Finished Jun 30 05:12:33 PM PDT 24
Peak memory 199844 kb
Host smart-21d3e65b-cb17-4926-b968-1a514389ec88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133145468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2133145468
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3548671380
Short name T192
Test name
Test status
Simulation time 42562254794 ps
CPU time 40.53 seconds
Started Jun 30 05:12:03 PM PDT 24
Finished Jun 30 05:12:43 PM PDT 24
Peak memory 199920 kb
Host smart-1441a482-5351-4fc0-b45a-94db2bc89be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548671380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3548671380
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.3821200893
Short name T584
Test name
Test status
Simulation time 94389091857 ps
CPU time 149.75 seconds
Started Jun 30 05:12:04 PM PDT 24
Finished Jun 30 05:14:34 PM PDT 24
Peak memory 199620 kb
Host smart-2f3ab49c-d637-408f-8210-90dd51d15d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821200893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.3821200893
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.1708671971
Short name T710
Test name
Test status
Simulation time 120531192501 ps
CPU time 270.64 seconds
Started Jun 30 05:12:01 PM PDT 24
Finished Jun 30 05:16:33 PM PDT 24
Peak memory 199828 kb
Host smart-cf2cfb7b-20ff-48e9-aefd-d7a4114d65a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708671971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1708671971
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.1679007501
Short name T137
Test name
Test status
Simulation time 35439287562 ps
CPU time 33.67 seconds
Started Jun 30 05:12:01 PM PDT 24
Finished Jun 30 05:12:35 PM PDT 24
Peak memory 199840 kb
Host smart-71da0f17-12dc-432d-89ce-4a278c55d70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679007501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.1679007501
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.3780578053
Short name T190
Test name
Test status
Simulation time 122020827709 ps
CPU time 175.46 seconds
Started Jun 30 05:12:03 PM PDT 24
Finished Jun 30 05:14:58 PM PDT 24
Peak memory 199916 kb
Host smart-3d8be308-83f1-4227-874e-263ecb2f222b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780578053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3780578053
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.4036625841
Short name T532
Test name
Test status
Simulation time 14734346 ps
CPU time 0.57 seconds
Started Jun 30 05:08:02 PM PDT 24
Finished Jun 30 05:08:04 PM PDT 24
Peak memory 195484 kb
Host smart-089db8d4-8e37-4a80-a5e4-5fc14d6e58ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036625841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.4036625841
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.2346983512
Short name T276
Test name
Test status
Simulation time 314222629062 ps
CPU time 1035.96 seconds
Started Jun 30 05:07:56 PM PDT 24
Finished Jun 30 05:25:13 PM PDT 24
Peak memory 199812 kb
Host smart-1ba85c2a-821a-44b0-bc42-d2f87625c8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346983512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2346983512
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.2758845390
Short name T609
Test name
Test status
Simulation time 25238707304 ps
CPU time 40.68 seconds
Started Jun 30 05:07:55 PM PDT 24
Finished Jun 30 05:08:36 PM PDT 24
Peak memory 197908 kb
Host smart-6ede4019-960f-43a1-b150-1cc485c65ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758845390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2758845390
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.1322110605
Short name T783
Test name
Test status
Simulation time 23435469766 ps
CPU time 39.08 seconds
Started Jun 30 05:08:00 PM PDT 24
Finished Jun 30 05:08:40 PM PDT 24
Peak memory 199904 kb
Host smart-74717935-6943-4f86-9e82-d3b594ca742c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322110605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1322110605
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.194263679
Short name T306
Test name
Test status
Simulation time 17362922136 ps
CPU time 25.66 seconds
Started Jun 30 05:07:57 PM PDT 24
Finished Jun 30 05:08:24 PM PDT 24
Peak memory 197480 kb
Host smart-6af8fdb3-5863-451d-be7c-544b926f9857
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194263679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.194263679
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.452916293
Short name T341
Test name
Test status
Simulation time 169744730283 ps
CPU time 1235.9 seconds
Started Jun 30 05:08:09 PM PDT 24
Finished Jun 30 05:28:46 PM PDT 24
Peak memory 200100 kb
Host smart-69a3a593-dbfd-4fd5-8b74-2f452a7440f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=452916293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.452916293
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.868885842
Short name T326
Test name
Test status
Simulation time 5377103271 ps
CPU time 8.4 seconds
Started Jun 30 05:08:04 PM PDT 24
Finished Jun 30 05:08:14 PM PDT 24
Peak memory 198020 kb
Host smart-0ac20c98-393c-4843-b77b-3007654e9dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868885842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.868885842
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_perf.2494500090
Short name T581
Test name
Test status
Simulation time 20674021049 ps
CPU time 607.36 seconds
Started Jun 30 05:08:03 PM PDT 24
Finished Jun 30 05:18:11 PM PDT 24
Peak memory 199796 kb
Host smart-9fe1fdca-2e83-4530-9640-e07135829a8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2494500090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2494500090
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.3111678822
Short name T1090
Test name
Test status
Simulation time 4926823733 ps
CPU time 37.95 seconds
Started Jun 30 05:07:57 PM PDT 24
Finished Jun 30 05:08:35 PM PDT 24
Peak memory 199288 kb
Host smart-2e559124-ab57-4313-ac68-762cc5850d60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3111678822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3111678822
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1912940674
Short name T901
Test name
Test status
Simulation time 43165072271 ps
CPU time 73.47 seconds
Started Jun 30 05:08:04 PM PDT 24
Finished Jun 30 05:09:19 PM PDT 24
Peak memory 199920 kb
Host smart-6d425802-dfaf-4ce6-bcc2-e1b6d00ab562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912940674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1912940674
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.3994063615
Short name T260
Test name
Test status
Simulation time 4821979960 ps
CPU time 5.98 seconds
Started Jun 30 05:08:03 PM PDT 24
Finished Jun 30 05:08:10 PM PDT 24
Peak memory 196136 kb
Host smart-8f35f7cf-7e97-4f95-aa78-21a3d9fea949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994063615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3994063615
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.2608383416
Short name T716
Test name
Test status
Simulation time 661160454 ps
CPU time 1.91 seconds
Started Jun 30 05:08:00 PM PDT 24
Finished Jun 30 05:08:03 PM PDT 24
Peak memory 198192 kb
Host smart-3987bbaf-8340-4474-bb14-7eee651b6e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608383416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2608383416
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.2065409124
Short name T1076
Test name
Test status
Simulation time 21310958681 ps
CPU time 249.31 seconds
Started Jun 30 05:08:09 PM PDT 24
Finished Jun 30 05:12:20 PM PDT 24
Peak memory 216308 kb
Host smart-36c0ef12-09c3-4908-8d80-d70fc43f7c55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065409124 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.2065409124
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.2713692375
Short name T749
Test name
Test status
Simulation time 1189405703 ps
CPU time 4.42 seconds
Started Jun 30 05:08:01 PM PDT 24
Finished Jun 30 05:08:06 PM PDT 24
Peak memory 198652 kb
Host smart-f91a0e1f-dad6-4680-b198-6b0adc0492f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713692375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2713692375
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.310541618
Short name T978
Test name
Test status
Simulation time 3196055399 ps
CPU time 5.8 seconds
Started Jun 30 05:07:57 PM PDT 24
Finished Jun 30 05:08:04 PM PDT 24
Peak memory 199492 kb
Host smart-a5cd40b8-7a67-4f5f-b6ed-3ec51305dd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310541618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.310541618
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.3572625209
Short name T591
Test name
Test status
Simulation time 29070461790 ps
CPU time 63.23 seconds
Started Jun 30 05:12:01 PM PDT 24
Finished Jun 30 05:13:04 PM PDT 24
Peak memory 199848 kb
Host smart-06585db3-d5c4-4120-aadd-08580e065d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572625209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3572625209
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.1216030996
Short name T1046
Test name
Test status
Simulation time 109846059607 ps
CPU time 160.12 seconds
Started Jun 30 05:12:02 PM PDT 24
Finished Jun 30 05:14:42 PM PDT 24
Peak memory 199828 kb
Host smart-03fc7301-21e6-40e7-a127-6e16d2d7e4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216030996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1216030996
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.86922507
Short name T286
Test name
Test status
Simulation time 277322616039 ps
CPU time 21.94 seconds
Started Jun 30 05:12:04 PM PDT 24
Finished Jun 30 05:12:26 PM PDT 24
Peak memory 199736 kb
Host smart-b2c3ef9d-d04f-40c1-92fe-fb0c105712d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86922507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.86922507
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.1519029893
Short name T874
Test name
Test status
Simulation time 139357706835 ps
CPU time 26.5 seconds
Started Jun 30 05:12:05 PM PDT 24
Finished Jun 30 05:12:32 PM PDT 24
Peak memory 199860 kb
Host smart-fea37162-d5a1-433b-adb2-be5385b5f698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519029893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.1519029893
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.1465939817
Short name T972
Test name
Test status
Simulation time 17279184871 ps
CPU time 27.81 seconds
Started Jun 30 05:12:04 PM PDT 24
Finished Jun 30 05:12:32 PM PDT 24
Peak memory 199820 kb
Host smart-b069a2bb-158c-40fb-b618-79a6b6879c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465939817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.1465939817
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.1191164540
Short name T230
Test name
Test status
Simulation time 21265649048 ps
CPU time 12.48 seconds
Started Jun 30 05:12:04 PM PDT 24
Finished Jun 30 05:12:17 PM PDT 24
Peak memory 199860 kb
Host smart-737f7156-30d2-47c5-95a7-50e3becb0df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191164540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1191164540
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.2037266058
Short name T384
Test name
Test status
Simulation time 48725803709 ps
CPU time 80.54 seconds
Started Jun 30 05:12:03 PM PDT 24
Finished Jun 30 05:13:24 PM PDT 24
Peak memory 199876 kb
Host smart-2dbc3b82-3a99-4a4a-9803-2462a5ae6b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037266058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2037266058
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.826051455
Short name T215
Test name
Test status
Simulation time 55191613015 ps
CPU time 23.08 seconds
Started Jun 30 05:12:11 PM PDT 24
Finished Jun 30 05:12:35 PM PDT 24
Peak memory 199208 kb
Host smart-9f6ba0cf-5876-4669-98f0-dd2ef8634c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826051455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.826051455
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2933223349
Short name T775
Test name
Test status
Simulation time 33661899762 ps
CPU time 31.73 seconds
Started Jun 30 05:12:11 PM PDT 24
Finished Jun 30 05:12:44 PM PDT 24
Peak memory 199896 kb
Host smart-3fc8a4ac-6289-405e-b4c0-3744bad36f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933223349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2933223349
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.2728180939
Short name T479
Test name
Test status
Simulation time 13170506 ps
CPU time 0.56 seconds
Started Jun 30 05:08:09 PM PDT 24
Finished Jun 30 05:08:11 PM PDT 24
Peak memory 195448 kb
Host smart-4ad78c83-f8a8-4961-a226-4d39cb728556
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728180939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2728180939
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.497647510
Short name T632
Test name
Test status
Simulation time 17569098773 ps
CPU time 30.55 seconds
Started Jun 30 05:08:04 PM PDT 24
Finished Jun 30 05:08:36 PM PDT 24
Peak memory 199848 kb
Host smart-e0ebafc4-dabc-45a0-9c93-73e6b36a98f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497647510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.497647510
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.938232512
Short name T949
Test name
Test status
Simulation time 41404918167 ps
CPU time 66.05 seconds
Started Jun 30 05:08:01 PM PDT 24
Finished Jun 30 05:09:08 PM PDT 24
Peak memory 199844 kb
Host smart-6758cf06-16aa-42ab-b47b-9482a1645cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938232512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.938232512
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.37285620
Short name T573
Test name
Test status
Simulation time 10273595574 ps
CPU time 17.47 seconds
Started Jun 30 05:08:03 PM PDT 24
Finished Jun 30 05:08:22 PM PDT 24
Peak memory 199856 kb
Host smart-f051d7fa-3787-4c84-b2e3-0a8dbf06281a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37285620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.37285620
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.2980524292
Short name T891
Test name
Test status
Simulation time 76505708650 ps
CPU time 577.38 seconds
Started Jun 30 05:08:02 PM PDT 24
Finished Jun 30 05:17:40 PM PDT 24
Peak memory 199904 kb
Host smart-fad3567f-d439-4772-a1d3-5cb80b3e00b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2980524292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2980524292
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.2364119289
Short name T327
Test name
Test status
Simulation time 1134097127 ps
CPU time 1.03 seconds
Started Jun 30 05:08:05 PM PDT 24
Finished Jun 30 05:08:07 PM PDT 24
Peak memory 195548 kb
Host smart-81aea738-33f8-453c-8991-cf4045d0286c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364119289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2364119289
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_perf.3918805961
Short name T332
Test name
Test status
Simulation time 1237750928 ps
CPU time 69.62 seconds
Started Jun 30 05:08:08 PM PDT 24
Finished Jun 30 05:09:18 PM PDT 24
Peak memory 200068 kb
Host smart-c1cbfddf-9a9e-4158-8f6b-6397cbbd386b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3918805961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3918805961
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.3016597159
Short name T615
Test name
Test status
Simulation time 3074097357 ps
CPU time 20.02 seconds
Started Jun 30 05:08:04 PM PDT 24
Finished Jun 30 05:08:25 PM PDT 24
Peak memory 198752 kb
Host smart-1ddd3312-5fb4-4c80-a18f-f4c2910be0e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3016597159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.3016597159
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.3068629547
Short name T840
Test name
Test status
Simulation time 107960193866 ps
CPU time 123.2 seconds
Started Jun 30 05:08:02 PM PDT 24
Finished Jun 30 05:10:07 PM PDT 24
Peak memory 199836 kb
Host smart-d0279887-19d9-4b14-920b-cbc8d34ab51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068629547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3068629547
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.3626622372
Short name T1016
Test name
Test status
Simulation time 1567793214 ps
CPU time 1.34 seconds
Started Jun 30 05:08:05 PM PDT 24
Finished Jun 30 05:08:08 PM PDT 24
Peak memory 195340 kb
Host smart-198070e3-51b4-474d-b3ea-8ec455bb3568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626622372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3626622372
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.3902108750
Short name T302
Test name
Test status
Simulation time 6081306969 ps
CPU time 17.81 seconds
Started Jun 30 05:08:03 PM PDT 24
Finished Jun 30 05:08:23 PM PDT 24
Peak memory 199864 kb
Host smart-b8613e24-695c-4c52-b3a6-d6642974d589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902108750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.3902108750
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.4090983652
Short name T938
Test name
Test status
Simulation time 769396556486 ps
CPU time 214.31 seconds
Started Jun 30 05:08:09 PM PDT 24
Finished Jun 30 05:11:44 PM PDT 24
Peak memory 199896 kb
Host smart-0848cd0b-2ecb-4cd5-a285-50f051da17da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090983652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.4090983652
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.4109338403
Short name T275
Test name
Test status
Simulation time 5810242267 ps
CPU time 20.61 seconds
Started Jun 30 05:08:04 PM PDT 24
Finished Jun 30 05:08:26 PM PDT 24
Peak memory 199588 kb
Host smart-c59308d5-4ac6-4bac-9317-280e0b21bf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109338403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.4109338403
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.822815324
Short name T269
Test name
Test status
Simulation time 17618077040 ps
CPU time 28.34 seconds
Started Jun 30 05:08:09 PM PDT 24
Finished Jun 30 05:08:38 PM PDT 24
Peak memory 199912 kb
Host smart-b9bd1ab1-1ec4-4758-a022-fad8eabbfed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822815324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.822815324
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.3709263889
Short name T831
Test name
Test status
Simulation time 19400210177 ps
CPU time 33.33 seconds
Started Jun 30 05:12:09 PM PDT 24
Finished Jun 30 05:12:43 PM PDT 24
Peak memory 199772 kb
Host smart-b483d6f5-4ede-4a7a-9b48-a78e1b376c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709263889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.3709263889
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.3336137601
Short name T1041
Test name
Test status
Simulation time 238194748469 ps
CPU time 470.45 seconds
Started Jun 30 05:12:15 PM PDT 24
Finished Jun 30 05:20:05 PM PDT 24
Peak memory 199916 kb
Host smart-8051bc54-1f8b-4885-946f-49f2ba3c9451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336137601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3336137601
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.290059564
Short name T1012
Test name
Test status
Simulation time 64510106144 ps
CPU time 100.91 seconds
Started Jun 30 05:12:12 PM PDT 24
Finished Jun 30 05:13:54 PM PDT 24
Peak memory 199824 kb
Host smart-64519661-9a14-4021-b547-35ba5024638a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290059564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.290059564
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.241142373
Short name T900
Test name
Test status
Simulation time 14958787490 ps
CPU time 20.51 seconds
Started Jun 30 05:12:11 PM PDT 24
Finished Jun 30 05:12:33 PM PDT 24
Peak memory 199572 kb
Host smart-d5b67e24-bfd2-45d1-b9e1-32f1a3b9aa5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241142373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.241142373
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.1973566221
Short name T589
Test name
Test status
Simulation time 66032344487 ps
CPU time 54.62 seconds
Started Jun 30 05:12:11 PM PDT 24
Finished Jun 30 05:13:07 PM PDT 24
Peak memory 199852 kb
Host smart-3737c0e2-4f28-4916-8700-bb5ac0cad29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973566221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1973566221
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2872982196
Short name T639
Test name
Test status
Simulation time 38590681911 ps
CPU time 35.12 seconds
Started Jun 30 05:12:10 PM PDT 24
Finished Jun 30 05:12:45 PM PDT 24
Peak memory 199808 kb
Host smart-a12cccb9-7135-471d-ae9e-935ff09bde2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872982196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2872982196
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.3834708583
Short name T748
Test name
Test status
Simulation time 19415104459 ps
CPU time 16.35 seconds
Started Jun 30 05:12:11 PM PDT 24
Finished Jun 30 05:12:28 PM PDT 24
Peak memory 199916 kb
Host smart-56f74f51-4335-446b-9fa0-e1d640f8c79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834708583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.3834708583
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.950582342
Short name T845
Test name
Test status
Simulation time 18227751408 ps
CPU time 15.2 seconds
Started Jun 30 05:12:13 PM PDT 24
Finished Jun 30 05:12:28 PM PDT 24
Peak memory 199872 kb
Host smart-654a20e5-ffdd-467b-a091-224bd3e9dbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950582342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.950582342
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.2849872764
Short name T560
Test name
Test status
Simulation time 54513373032 ps
CPU time 76.62 seconds
Started Jun 30 05:12:09 PM PDT 24
Finished Jun 30 05:13:27 PM PDT 24
Peak memory 199900 kb
Host smart-0cdb4bb7-42a7-41fc-a8ce-6d12435a8028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849872764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2849872764
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.1733130150
Short name T665
Test name
Test status
Simulation time 67456340351 ps
CPU time 31.87 seconds
Started Jun 30 05:12:12 PM PDT 24
Finished Jun 30 05:12:45 PM PDT 24
Peak memory 199824 kb
Host smart-b8f7d68c-ecab-4bf9-993b-5fdf1fa66d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733130150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1733130150
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.3203021027
Short name T376
Test name
Test status
Simulation time 33161704 ps
CPU time 0.54 seconds
Started Jun 30 05:08:17 PM PDT 24
Finished Jun 30 05:08:18 PM PDT 24
Peak memory 194212 kb
Host smart-c042cc7b-7b13-4466-8610-529002380cc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203021027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.3203021027
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.60340169
Short name T352
Test name
Test status
Simulation time 117426131531 ps
CPU time 177.35 seconds
Started Jun 30 05:08:10 PM PDT 24
Finished Jun 30 05:11:08 PM PDT 24
Peak memory 199908 kb
Host smart-3cc5bf34-cacc-4e63-b8cd-74916a434a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60340169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.60340169
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.376744140
Short name T1058
Test name
Test status
Simulation time 42844138267 ps
CPU time 17.18 seconds
Started Jun 30 05:08:09 PM PDT 24
Finished Jun 30 05:08:28 PM PDT 24
Peak memory 199396 kb
Host smart-74aa13b5-c1b7-4936-8f25-ab5576bbbfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376744140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.376744140
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.1825720091
Short name T188
Test name
Test status
Simulation time 43105977522 ps
CPU time 67.04 seconds
Started Jun 30 05:08:09 PM PDT 24
Finished Jun 30 05:09:18 PM PDT 24
Peak memory 199852 kb
Host smart-28c8f1b6-17d2-42ea-96a1-843ea34d166a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825720091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1825720091
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.152919661
Short name T907
Test name
Test status
Simulation time 57966231292 ps
CPU time 26.52 seconds
Started Jun 30 05:08:10 PM PDT 24
Finished Jun 30 05:08:38 PM PDT 24
Peak memory 199852 kb
Host smart-73fba118-42d5-4da9-a11d-837b895c4d82
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152919661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.152919661
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1266825325
Short name T813
Test name
Test status
Simulation time 202024691698 ps
CPU time 446.53 seconds
Started Jun 30 05:08:13 PM PDT 24
Finished Jun 30 05:15:40 PM PDT 24
Peak memory 199840 kb
Host smart-58e6cbf9-d111-4925-8d3f-2b75bb06763b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1266825325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1266825325
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.903808856
Short name T843
Test name
Test status
Simulation time 1780781083 ps
CPU time 1.78 seconds
Started Jun 30 05:08:12 PM PDT 24
Finished Jun 30 05:08:14 PM PDT 24
Peak memory 198084 kb
Host smart-9ab524f2-1f2d-4453-a6f8-e42b704b596b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903808856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.903808856
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_perf.2654731328
Short name T732
Test name
Test status
Simulation time 13516807043 ps
CPU time 54.06 seconds
Started Jun 30 05:08:10 PM PDT 24
Finished Jun 30 05:09:05 PM PDT 24
Peak memory 199816 kb
Host smart-0f684a66-f8a5-46d3-a96f-1f716e5b7c8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2654731328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.2654731328
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.3832994082
Short name T706
Test name
Test status
Simulation time 3736961945 ps
CPU time 4.15 seconds
Started Jun 30 05:08:10 PM PDT 24
Finished Jun 30 05:08:15 PM PDT 24
Peak memory 199344 kb
Host smart-58a901a5-0168-4110-88e9-e3c60d2b550c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3832994082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3832994082
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.306728109
Short name T903
Test name
Test status
Simulation time 72007400883 ps
CPU time 56.23 seconds
Started Jun 30 05:08:11 PM PDT 24
Finished Jun 30 05:09:08 PM PDT 24
Peak memory 199816 kb
Host smart-8bb98b4f-c0c0-4c27-a3c9-9f39ec7dacff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306728109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.306728109
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.1713394327
Short name T964
Test name
Test status
Simulation time 38484770944 ps
CPU time 16.39 seconds
Started Jun 30 05:08:10 PM PDT 24
Finished Jun 30 05:08:28 PM PDT 24
Peak memory 196008 kb
Host smart-f4ef939f-bcf3-489b-a97a-1b7805a012e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713394327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1713394327
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.3339871107
Short name T488
Test name
Test status
Simulation time 473664306 ps
CPU time 1.29 seconds
Started Jun 30 05:08:10 PM PDT 24
Finished Jun 30 05:08:13 PM PDT 24
Peak memory 198768 kb
Host smart-35eea777-b89a-47db-bef6-a23cbf6b9d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339871107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3339871107
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.582373344
Short name T420
Test name
Test status
Simulation time 28248236583 ps
CPU time 12.74 seconds
Started Jun 30 05:08:09 PM PDT 24
Finished Jun 30 05:08:24 PM PDT 24
Peak memory 199796 kb
Host smart-c9c9ea81-cd4c-4cdd-8224-7022168141d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582373344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.582373344
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.2778100701
Short name T572
Test name
Test status
Simulation time 63555755553 ps
CPU time 149.06 seconds
Started Jun 30 05:08:12 PM PDT 24
Finished Jun 30 05:10:41 PM PDT 24
Peak memory 216376 kb
Host smart-f039b119-1abc-423c-9d54-5d25bbc84f87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778100701 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.2778100701
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.3627669848
Short name T491
Test name
Test status
Simulation time 1352455097 ps
CPU time 1.61 seconds
Started Jun 30 05:08:09 PM PDT 24
Finished Jun 30 05:08:12 PM PDT 24
Peak memory 198224 kb
Host smart-d083798d-63a7-4079-9c5b-ecd4b7b4aa9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627669848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3627669848
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.396443726
Short name T666
Test name
Test status
Simulation time 217424572006 ps
CPU time 84.54 seconds
Started Jun 30 05:08:11 PM PDT 24
Finished Jun 30 05:09:36 PM PDT 24
Peak memory 199928 kb
Host smart-537182fd-618c-442e-962c-1b55eccba5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396443726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.396443726
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.3364763853
Short name T724
Test name
Test status
Simulation time 168730754133 ps
CPU time 25.58 seconds
Started Jun 30 05:12:12 PM PDT 24
Finished Jun 30 05:12:39 PM PDT 24
Peak memory 199864 kb
Host smart-456f71ad-38ab-4036-bd52-923383cb9a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364763853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.3364763853
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.83567221
Short name T1055
Test name
Test status
Simulation time 74996510944 ps
CPU time 21.1 seconds
Started Jun 30 05:12:14 PM PDT 24
Finished Jun 30 05:12:35 PM PDT 24
Peak memory 199864 kb
Host smart-dd3aa6a8-164b-46bd-8815-29da8cd347fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83567221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.83567221
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.2547237030
Short name T797
Test name
Test status
Simulation time 33351949303 ps
CPU time 21.93 seconds
Started Jun 30 05:12:10 PM PDT 24
Finished Jun 30 05:12:33 PM PDT 24
Peak memory 199892 kb
Host smart-09ab96dc-64d8-4c3d-bd7f-15a371020399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547237030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2547237030
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.3064063101
Short name T634
Test name
Test status
Simulation time 8441216727 ps
CPU time 13.44 seconds
Started Jun 30 05:12:11 PM PDT 24
Finished Jun 30 05:12:26 PM PDT 24
Peak memory 199756 kb
Host smart-7a7bada1-21c0-47ba-a6ff-7774ee695891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064063101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3064063101
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.2820030163
Short name T463
Test name
Test status
Simulation time 68733197583 ps
CPU time 70.78 seconds
Started Jun 30 05:12:11 PM PDT 24
Finished Jun 30 05:13:23 PM PDT 24
Peak memory 199860 kb
Host smart-aa0a533c-d854-4d6d-a275-e09ff9d1c089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820030163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2820030163
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.4062967997
Short name T206
Test name
Test status
Simulation time 109481314309 ps
CPU time 178.6 seconds
Started Jun 30 05:12:09 PM PDT 24
Finished Jun 30 05:15:08 PM PDT 24
Peak memory 199672 kb
Host smart-2a033583-250f-4632-a92f-f5062e7d95b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062967997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.4062967997
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.1005547906
Short name T929
Test name
Test status
Simulation time 13638195144 ps
CPU time 30.09 seconds
Started Jun 30 05:12:10 PM PDT 24
Finished Jun 30 05:12:41 PM PDT 24
Peak memory 199856 kb
Host smart-3b7efb2c-9d19-4474-9012-6ac38c78afce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005547906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.1005547906
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.3887168836
Short name T873
Test name
Test status
Simulation time 21428889 ps
CPU time 0.56 seconds
Started Jun 30 05:08:24 PM PDT 24
Finished Jun 30 05:08:25 PM PDT 24
Peak memory 194188 kb
Host smart-a9de00c2-175a-4eef-a981-b32117baf31d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887168836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3887168836
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.2040317764
Short name T583
Test name
Test status
Simulation time 187855882651 ps
CPU time 582.85 seconds
Started Jun 30 05:08:16 PM PDT 24
Finished Jun 30 05:17:59 PM PDT 24
Peak memory 199824 kb
Host smart-e0b10e00-3caf-49d9-bb82-64994f054f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040317764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.2040317764
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.255058606
Short name T35
Test name
Test status
Simulation time 21891257420 ps
CPU time 41.43 seconds
Started Jun 30 05:08:19 PM PDT 24
Finished Jun 30 05:09:01 PM PDT 24
Peak memory 199808 kb
Host smart-10fd79fb-4564-4640-a985-c7ed080445ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255058606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.255058606
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.246639736
Short name T163
Test name
Test status
Simulation time 120595791743 ps
CPU time 50.8 seconds
Started Jun 30 05:08:18 PM PDT 24
Finished Jun 30 05:09:09 PM PDT 24
Peak memory 199856 kb
Host smart-f2b4811d-0d6e-4755-bab0-e61789e613f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246639736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.246639736
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.228027703
Short name T312
Test name
Test status
Simulation time 13454546609 ps
CPU time 5.35 seconds
Started Jun 30 05:08:22 PM PDT 24
Finished Jun 30 05:08:27 PM PDT 24
Peak memory 197168 kb
Host smart-e4fea5b4-913d-4caa-8b79-2498c23f34f7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228027703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.228027703
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.3103519115
Short name T466
Test name
Test status
Simulation time 113487150430 ps
CPU time 187.17 seconds
Started Jun 30 05:08:17 PM PDT 24
Finished Jun 30 05:11:25 PM PDT 24
Peak memory 199904 kb
Host smart-8e3e0c2f-c982-41c0-86f2-b04b4bfdc08a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3103519115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.3103519115
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.2771369505
Short name T1096
Test name
Test status
Simulation time 6794159404 ps
CPU time 12.31 seconds
Started Jun 30 05:08:17 PM PDT 24
Finished Jun 30 05:08:29 PM PDT 24
Peak memory 198252 kb
Host smart-5cf62b27-0a28-4592-b3af-3b7dc4f823fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771369505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2771369505
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_perf.3820326442
Short name T251
Test name
Test status
Simulation time 14874160369 ps
CPU time 856.02 seconds
Started Jun 30 05:08:18 PM PDT 24
Finished Jun 30 05:22:34 PM PDT 24
Peak memory 199892 kb
Host smart-b304002f-9fbb-4c0e-8933-8b32361e1cc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3820326442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.3820326442
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.3308659103
Short name T835
Test name
Test status
Simulation time 6332727841 ps
CPU time 40.79 seconds
Started Jun 30 05:08:17 PM PDT 24
Finished Jun 30 05:08:59 PM PDT 24
Peak memory 198032 kb
Host smart-446c76fb-da88-4a9d-8e58-fe7c71e41b9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3308659103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3308659103
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.1855650672
Short name T363
Test name
Test status
Simulation time 113766171919 ps
CPU time 223.47 seconds
Started Jun 30 05:08:16 PM PDT 24
Finished Jun 30 05:12:00 PM PDT 24
Peak memory 199876 kb
Host smart-092ed0d5-b572-40c9-a8d6-1b597885bfff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855650672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1855650672
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.2088050471
Short name T733
Test name
Test status
Simulation time 3219965642 ps
CPU time 2.99 seconds
Started Jun 30 05:08:17 PM PDT 24
Finished Jun 30 05:08:21 PM PDT 24
Peak memory 195956 kb
Host smart-a61965fe-dace-4168-8913-3ad78106edb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088050471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.2088050471
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.776022651
Short name T767
Test name
Test status
Simulation time 709284901 ps
CPU time 2.25 seconds
Started Jun 30 05:08:19 PM PDT 24
Finished Jun 30 05:08:21 PM PDT 24
Peak memory 199312 kb
Host smart-3540ca5f-de60-4310-9e4a-3eef2c696017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776022651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.776022651
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.3950678199
Short name T913
Test name
Test status
Simulation time 1222381468 ps
CPU time 2.31 seconds
Started Jun 30 05:08:18 PM PDT 24
Finished Jun 30 05:08:21 PM PDT 24
Peak memory 198180 kb
Host smart-6856bb9e-da9b-4ccc-8159-85492607e21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950678199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.3950678199
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.1347078403
Short name T314
Test name
Test status
Simulation time 21087930313 ps
CPU time 15.25 seconds
Started Jun 30 05:12:19 PM PDT 24
Finished Jun 30 05:12:34 PM PDT 24
Peak memory 199848 kb
Host smart-f93ba5df-2fa2-4616-9bf8-bc95e6479d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347078403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1347078403
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.3127861885
Short name T899
Test name
Test status
Simulation time 287145752119 ps
CPU time 27.43 seconds
Started Jun 30 05:12:18 PM PDT 24
Finished Jun 30 05:12:46 PM PDT 24
Peak memory 199864 kb
Host smart-9c7de949-64cd-4cdb-b852-bcd757eb196b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127861885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3127861885
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1355790399
Short name T182
Test name
Test status
Simulation time 33492614117 ps
CPU time 27.45 seconds
Started Jun 30 05:12:15 PM PDT 24
Finished Jun 30 05:12:43 PM PDT 24
Peak memory 199628 kb
Host smart-d29236d3-a5af-43a2-a93b-6d04d7550069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355790399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1355790399
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.1283527421
Short name T757
Test name
Test status
Simulation time 101146450035 ps
CPU time 198.27 seconds
Started Jun 30 05:12:17 PM PDT 24
Finished Jun 30 05:15:35 PM PDT 24
Peak memory 199920 kb
Host smart-11ccec0c-0a5d-4a43-86e3-9c2f514e6b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283527421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1283527421
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.2863088029
Short name T718
Test name
Test status
Simulation time 80414713291 ps
CPU time 118.72 seconds
Started Jun 30 05:12:15 PM PDT 24
Finished Jun 30 05:14:14 PM PDT 24
Peak memory 199860 kb
Host smart-0bddc4be-5b21-42f6-8d60-953812791343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863088029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2863088029
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.2882725213
Short name T934
Test name
Test status
Simulation time 10182153412 ps
CPU time 15.6 seconds
Started Jun 30 05:12:15 PM PDT 24
Finished Jun 30 05:12:31 PM PDT 24
Peak memory 199488 kb
Host smart-a46b08ce-c091-4dde-8c2e-74fd7b5c8706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882725213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2882725213
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.1670208776
Short name T490
Test name
Test status
Simulation time 42293580733 ps
CPU time 61.58 seconds
Started Jun 30 05:12:17 PM PDT 24
Finished Jun 30 05:13:19 PM PDT 24
Peak memory 200084 kb
Host smart-3f85f35d-47ba-4c1a-81de-dfdef33cece6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670208776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1670208776
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.497613457
Short name T356
Test name
Test status
Simulation time 146129160241 ps
CPU time 274.04 seconds
Started Jun 30 05:12:17 PM PDT 24
Finished Jun 30 05:16:51 PM PDT 24
Peak memory 199868 kb
Host smart-f8df5550-79f6-4722-80ac-7a37ebe434b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497613457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.497613457
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.792838321
Short name T1052
Test name
Test status
Simulation time 44275028 ps
CPU time 0.53 seconds
Started Jun 30 05:08:26 PM PDT 24
Finished Jun 30 05:08:27 PM PDT 24
Peak memory 195512 kb
Host smart-815ced46-34ba-477c-aa86-c170911a2b5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792838321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.792838321
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.1771593999
Short name T494
Test name
Test status
Simulation time 82718032916 ps
CPU time 65.97 seconds
Started Jun 30 05:08:21 PM PDT 24
Finished Jun 30 05:09:28 PM PDT 24
Peak memory 199864 kb
Host smart-f292b438-2750-4c30-90c7-c7341c90e43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771593999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.1771593999
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.3849509305
Short name T512
Test name
Test status
Simulation time 88828372683 ps
CPU time 109.63 seconds
Started Jun 30 05:08:24 PM PDT 24
Finished Jun 30 05:10:14 PM PDT 24
Peak memory 199888 kb
Host smart-e7d012b2-1ee6-46e0-8eb6-c861c4f5110d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849509305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.3849509305
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.601579428
Short name T408
Test name
Test status
Simulation time 35103719109 ps
CPU time 11.21 seconds
Started Jun 30 05:08:23 PM PDT 24
Finished Jun 30 05:08:35 PM PDT 24
Peak memory 199828 kb
Host smart-068bca3f-c255-4dab-b692-924d80e9bb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601579428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.601579428
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.3704675824
Short name T83
Test name
Test status
Simulation time 5652237210 ps
CPU time 6.02 seconds
Started Jun 30 05:08:24 PM PDT 24
Finished Jun 30 05:08:31 PM PDT 24
Peak memory 199788 kb
Host smart-6424f65c-b078-42ce-8cda-c687312b93d9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704675824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3704675824
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.685040378
Short name T742
Test name
Test status
Simulation time 126101282385 ps
CPU time 503.17 seconds
Started Jun 30 05:08:22 PM PDT 24
Finished Jun 30 05:16:46 PM PDT 24
Peak memory 199900 kb
Host smart-c0ba98a3-2a85-46f9-b3b1-be7eeb2719c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=685040378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.685040378
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.4040345259
Short name T1044
Test name
Test status
Simulation time 5117285006 ps
CPU time 14 seconds
Started Jun 30 05:08:25 PM PDT 24
Finished Jun 30 05:08:40 PM PDT 24
Peak memory 199856 kb
Host smart-aa64b1b0-3d09-4dc9-a035-53884c34860c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040345259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.4040345259
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_perf.3863544335
Short name T975
Test name
Test status
Simulation time 16414966106 ps
CPU time 792.96 seconds
Started Jun 30 05:08:25 PM PDT 24
Finished Jun 30 05:21:38 PM PDT 24
Peak memory 199836 kb
Host smart-b099f967-af44-4c7f-a754-8bf00e49d8cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3863544335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.3863544335
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.963323828
Short name T702
Test name
Test status
Simulation time 4324326548 ps
CPU time 9.97 seconds
Started Jun 30 05:08:22 PM PDT 24
Finished Jun 30 05:08:33 PM PDT 24
Peak memory 199380 kb
Host smart-cbb69df2-11d2-4eee-86b1-e0bbb26bb3ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=963323828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.963323828
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.478245302
Short name T905
Test name
Test status
Simulation time 169315612779 ps
CPU time 297.05 seconds
Started Jun 30 05:08:23 PM PDT 24
Finished Jun 30 05:13:21 PM PDT 24
Peak memory 199840 kb
Host smart-51e3768f-7daf-40f2-a8f8-6ca370d1cf13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478245302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.478245302
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.263362796
Short name T575
Test name
Test status
Simulation time 46886379622 ps
CPU time 8.83 seconds
Started Jun 30 05:08:23 PM PDT 24
Finished Jun 30 05:08:32 PM PDT 24
Peak memory 196344 kb
Host smart-3796d522-79e0-4790-90c7-362915ce4f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263362796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.263362796
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.2303796550
Short name T381
Test name
Test status
Simulation time 280367138 ps
CPU time 1.54 seconds
Started Jun 30 05:08:23 PM PDT 24
Finished Jun 30 05:08:25 PM PDT 24
Peak memory 198372 kb
Host smart-fee7d382-1780-4606-90c7-cedd6e0844fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303796550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2303796550
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.1046659206
Short name T1037
Test name
Test status
Simulation time 230842457458 ps
CPU time 1894.67 seconds
Started Jun 30 05:08:24 PM PDT 24
Finished Jun 30 05:39:59 PM PDT 24
Peak memory 199832 kb
Host smart-54effe60-a3ef-46c8-9320-3e065db94f71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046659206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.1046659206
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.455253115
Short name T323
Test name
Test status
Simulation time 1623085817 ps
CPU time 4.02 seconds
Started Jun 30 05:08:23 PM PDT 24
Finished Jun 30 05:08:28 PM PDT 24
Peak memory 198804 kb
Host smart-ced8bf38-f3f0-4086-9cb4-827efc503932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455253115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.455253115
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.1182301515
Short name T242
Test name
Test status
Simulation time 79037809810 ps
CPU time 35.67 seconds
Started Jun 30 05:08:23 PM PDT 24
Finished Jun 30 05:08:59 PM PDT 24
Peak memory 199908 kb
Host smart-badcf952-057e-40b5-8df8-2d09d54e3930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182301515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1182301515
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.4280034392
Short name T256
Test name
Test status
Simulation time 17585956690 ps
CPU time 18.1 seconds
Started Jun 30 05:12:16 PM PDT 24
Finished Jun 30 05:12:35 PM PDT 24
Peak memory 199864 kb
Host smart-1599cd76-1432-46a1-82c9-6a6c235ebee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280034392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.4280034392
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.1590750651
Short name T1017
Test name
Test status
Simulation time 50808398356 ps
CPU time 20.67 seconds
Started Jun 30 05:12:18 PM PDT 24
Finished Jun 30 05:12:39 PM PDT 24
Peak memory 199900 kb
Host smart-31a23c79-f735-4e9f-859f-03ab699f7f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590750651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1590750651
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.3226643727
Short name T985
Test name
Test status
Simulation time 10765606732 ps
CPU time 9.58 seconds
Started Jun 30 05:12:16 PM PDT 24
Finished Jun 30 05:12:26 PM PDT 24
Peak memory 198444 kb
Host smart-8fb33d1d-d6a5-4bcf-b22f-8970477573c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226643727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3226643727
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.4233751351
Short name T165
Test name
Test status
Simulation time 26626793169 ps
CPU time 40.02 seconds
Started Jun 30 05:12:18 PM PDT 24
Finished Jun 30 05:12:58 PM PDT 24
Peak memory 199828 kb
Host smart-76ba5afd-b8d2-44c5-a950-7dc05a9c48ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233751351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.4233751351
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.3381319443
Short name T1080
Test name
Test status
Simulation time 42919648889 ps
CPU time 16.49 seconds
Started Jun 30 05:12:16 PM PDT 24
Finished Jun 30 05:12:33 PM PDT 24
Peak memory 199604 kb
Host smart-ed51b3b7-6ee5-4665-bd42-9c74edc6953c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381319443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3381319443
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.3412089373
Short name T741
Test name
Test status
Simulation time 48793997983 ps
CPU time 24.74 seconds
Started Jun 30 05:12:36 PM PDT 24
Finished Jun 30 05:13:01 PM PDT 24
Peak memory 199712 kb
Host smart-42fa63e9-ccb7-4b7c-9732-84e80a66c678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412089373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3412089373
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.1328106167
Short name T298
Test name
Test status
Simulation time 58710124109 ps
CPU time 60.65 seconds
Started Jun 30 05:12:24 PM PDT 24
Finished Jun 30 05:13:25 PM PDT 24
Peak memory 200140 kb
Host smart-ad0c353e-5c15-4187-a3a5-860bb900695b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328106167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1328106167
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.4286185834
Short name T726
Test name
Test status
Simulation time 14624672947 ps
CPU time 27.4 seconds
Started Jun 30 05:12:24 PM PDT 24
Finished Jun 30 05:12:52 PM PDT 24
Peak memory 199860 kb
Host smart-6c650897-4d9d-4727-b59e-6df72177f8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286185834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.4286185834
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.240615422
Short name T223
Test name
Test status
Simulation time 112587817287 ps
CPU time 10.77 seconds
Started Jun 30 05:12:24 PM PDT 24
Finished Jun 30 05:12:35 PM PDT 24
Peak memory 199908 kb
Host smart-54a91e15-2787-4f21-9d94-4307dbd18661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240615422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.240615422
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.1719686444
Short name T941
Test name
Test status
Simulation time 18623771 ps
CPU time 0.56 seconds
Started Jun 30 05:08:33 PM PDT 24
Finished Jun 30 05:08:35 PM PDT 24
Peak memory 195516 kb
Host smart-0cbb29b6-fd90-4fd2-9764-86c7a3152dec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719686444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1719686444
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3977667488
Short name T1029
Test name
Test status
Simulation time 214686812878 ps
CPU time 390.24 seconds
Started Jun 30 05:08:26 PM PDT 24
Finished Jun 30 05:14:56 PM PDT 24
Peak memory 199876 kb
Host smart-1aadb420-a935-455d-8e11-de66ab8e389f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977667488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3977667488
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.2815365135
Short name T412
Test name
Test status
Simulation time 12157614319 ps
CPU time 21.24 seconds
Started Jun 30 05:08:30 PM PDT 24
Finished Jun 30 05:08:52 PM PDT 24
Peak memory 199876 kb
Host smart-fe6e04de-6ac0-4cf3-9c77-f2a9b07bddaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815365135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2815365135
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.2093894164
Short name T750
Test name
Test status
Simulation time 7010246641 ps
CPU time 20.46 seconds
Started Jun 30 05:08:32 PM PDT 24
Finished Jun 30 05:08:54 PM PDT 24
Peak memory 199836 kb
Host smart-855e84f8-1711-4ce6-92d6-ca656b3976d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093894164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.2093894164
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.300357951
Short name T828
Test name
Test status
Simulation time 231973871723 ps
CPU time 208.41 seconds
Started Jun 30 05:08:33 PM PDT 24
Finished Jun 30 05:12:02 PM PDT 24
Peak memory 199844 kb
Host smart-74138c80-5920-431b-a075-18ba2861d062
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300357951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.300357951
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2159553249
Short name T1019
Test name
Test status
Simulation time 111309964935 ps
CPU time 253.09 seconds
Started Jun 30 05:08:32 PM PDT 24
Finished Jun 30 05:12:45 PM PDT 24
Peak memory 199744 kb
Host smart-d38d4b48-8f17-43be-8502-948e4adf4cad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2159553249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2159553249
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.383077415
Short name T461
Test name
Test status
Simulation time 34259094 ps
CPU time 0.6 seconds
Started Jun 30 05:08:32 PM PDT 24
Finished Jun 30 05:08:33 PM PDT 24
Peak memory 195688 kb
Host smart-ec319006-b5e8-4b54-a5c9-edaf42a32b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383077415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.383077415
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_perf.633458115
Short name T912
Test name
Test status
Simulation time 18511397521 ps
CPU time 1000.39 seconds
Started Jun 30 05:08:30 PM PDT 24
Finished Jun 30 05:25:11 PM PDT 24
Peak memory 199884 kb
Host smart-d22b5f00-2ed1-4dc8-9811-f4565ff64eb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=633458115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.633458115
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2733413451
Short name T683
Test name
Test status
Simulation time 7350969467 ps
CPU time 14.53 seconds
Started Jun 30 05:08:32 PM PDT 24
Finished Jun 30 05:08:47 PM PDT 24
Peak memory 199184 kb
Host smart-5d30f906-689d-4467-8ea7-3cf05b137ecf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2733413451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2733413451
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.199562743
Short name T406
Test name
Test status
Simulation time 33327101690 ps
CPU time 15.19 seconds
Started Jun 30 05:08:31 PM PDT 24
Finished Jun 30 05:08:47 PM PDT 24
Peak memory 199472 kb
Host smart-bb07ff77-85bc-4b17-b714-ff607ef24bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199562743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.199562743
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.51599181
Short name T402
Test name
Test status
Simulation time 32145246182 ps
CPU time 52.4 seconds
Started Jun 30 05:08:33 PM PDT 24
Finished Jun 30 05:09:26 PM PDT 24
Peak memory 195636 kb
Host smart-ea29fb69-a99a-4525-b12f-cb1572c06999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51599181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.51599181
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.2893703597
Short name T969
Test name
Test status
Simulation time 5883744725 ps
CPU time 12.82 seconds
Started Jun 30 05:08:23 PM PDT 24
Finished Jun 30 05:08:36 PM PDT 24
Peak memory 199900 kb
Host smart-5e2ede8a-1c8c-45c5-8190-19853970131d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893703597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.2893703597
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.1979635185
Short name T1
Test name
Test status
Simulation time 60669925435 ps
CPU time 68.38 seconds
Started Jun 30 05:08:33 PM PDT 24
Finished Jun 30 05:09:42 PM PDT 24
Peak memory 199872 kb
Host smart-8bde4e96-3c48-45dd-8fe2-2d28ecba0c50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979635185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.1979635185
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.3726956815
Short name T1013
Test name
Test status
Simulation time 645068531 ps
CPU time 3.47 seconds
Started Jun 30 05:08:32 PM PDT 24
Finished Jun 30 05:08:36 PM PDT 24
Peak memory 199600 kb
Host smart-50c00a2a-025b-4c3d-b479-af1c59e08198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726956815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3726956815
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.2164276397
Short name T509
Test name
Test status
Simulation time 8977362825 ps
CPU time 2.81 seconds
Started Jun 30 05:08:23 PM PDT 24
Finished Jun 30 05:08:27 PM PDT 24
Peak memory 196644 kb
Host smart-a7f41492-3c32-4075-af46-b4cd83b68d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164276397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.2164276397
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.4293524792
Short name T191
Test name
Test status
Simulation time 26373507769 ps
CPU time 45.65 seconds
Started Jun 30 05:12:25 PM PDT 24
Finished Jun 30 05:13:11 PM PDT 24
Peak memory 199912 kb
Host smart-cadd103c-de95-46aa-90b6-80ae5e2498d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293524792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.4293524792
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1412869767
Short name T707
Test name
Test status
Simulation time 76832274156 ps
CPU time 31.52 seconds
Started Jun 30 05:12:23 PM PDT 24
Finished Jun 30 05:12:55 PM PDT 24
Peak memory 199844 kb
Host smart-e17aac98-121d-43f4-9177-295f7fbfaa78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412869767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1412869767
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1898977169
Short name T210
Test name
Test status
Simulation time 25876463319 ps
CPU time 31.61 seconds
Started Jun 30 05:12:25 PM PDT 24
Finished Jun 30 05:12:57 PM PDT 24
Peak memory 199900 kb
Host smart-efe9a8cf-d0f3-43bc-aa97-abd315631c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898977169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1898977169
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.2302776330
Short name T734
Test name
Test status
Simulation time 16999745767 ps
CPU time 31 seconds
Started Jun 30 05:12:36 PM PDT 24
Finished Jun 30 05:13:08 PM PDT 24
Peak memory 199828 kb
Host smart-4675f5e4-5117-4500-8acb-ad0193775e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302776330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2302776330
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.4187943629
Short name T1043
Test name
Test status
Simulation time 191660364537 ps
CPU time 165.84 seconds
Started Jun 30 05:12:23 PM PDT 24
Finished Jun 30 05:15:09 PM PDT 24
Peak memory 199884 kb
Host smart-924f4128-bc08-4412-9612-23ead22f4204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187943629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.4187943629
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2047154387
Short name T937
Test name
Test status
Simulation time 45463568314 ps
CPU time 21.37 seconds
Started Jun 30 05:12:36 PM PDT 24
Finished Jun 30 05:12:58 PM PDT 24
Peak memory 199772 kb
Host smart-cd3b686d-1ee1-4d59-94fe-4c1351c1a8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047154387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2047154387
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.3906657738
Short name T342
Test name
Test status
Simulation time 35398058897 ps
CPU time 26.93 seconds
Started Jun 30 05:12:24 PM PDT 24
Finished Jun 30 05:12:51 PM PDT 24
Peak memory 199744 kb
Host smart-fd9ae76a-a23a-47f5-a749-5da79b54966a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906657738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3906657738
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.3444130611
Short name T830
Test name
Test status
Simulation time 15404672366 ps
CPU time 24.24 seconds
Started Jun 30 05:12:23 PM PDT 24
Finished Jun 30 05:12:47 PM PDT 24
Peak memory 199840 kb
Host smart-5fc5d73c-4047-4091-b1cf-f1b053a0c69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444130611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.3444130611
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.3169203297
Short name T1078
Test name
Test status
Simulation time 6426597404 ps
CPU time 10.26 seconds
Started Jun 30 05:12:36 PM PDT 24
Finished Jun 30 05:12:47 PM PDT 24
Peak memory 199356 kb
Host smart-487307ad-f4ed-4eda-b5fd-c943d25e6dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169203297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3169203297
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.610124453
Short name T220
Test name
Test status
Simulation time 94021837287 ps
CPU time 35.35 seconds
Started Jun 30 05:12:36 PM PDT 24
Finished Jun 30 05:13:12 PM PDT 24
Peak memory 199768 kb
Host smart-b4f98ea1-9615-4938-ae0e-e0dd9b5274e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610124453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.610124453
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.4140022774
Short name T366
Test name
Test status
Simulation time 142474674 ps
CPU time 0.56 seconds
Started Jun 30 05:06:38 PM PDT 24
Finished Jun 30 05:06:39 PM PDT 24
Peak memory 195516 kb
Host smart-d620184e-8392-4f23-bf13-1e3a961ad83a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140022774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.4140022774
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.3330733292
Short name T926
Test name
Test status
Simulation time 37292219882 ps
CPU time 14.24 seconds
Started Jun 30 05:06:28 PM PDT 24
Finished Jun 30 05:06:43 PM PDT 24
Peak memory 200140 kb
Host smart-eaf3f0e0-6383-4236-8ad0-d561516096e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330733292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3330733292
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.4258063041
Short name T930
Test name
Test status
Simulation time 102063053997 ps
CPU time 134.47 seconds
Started Jun 30 05:06:31 PM PDT 24
Finished Jun 30 05:08:47 PM PDT 24
Peak memory 199832 kb
Host smart-2a8a2da2-aebd-4e20-8d2e-2dcb4a66532a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258063041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.4258063041
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.2083503276
Short name T85
Test name
Test status
Simulation time 53438796519 ps
CPU time 96.48 seconds
Started Jun 30 05:06:30 PM PDT 24
Finished Jun 30 05:08:07 PM PDT 24
Peak memory 199904 kb
Host smart-2571c0e2-d232-40b4-803a-f691595266f3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083503276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2083503276
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.2725366179
Short name T947
Test name
Test status
Simulation time 94983176808 ps
CPU time 316.83 seconds
Started Jun 30 05:06:28 PM PDT 24
Finished Jun 30 05:11:46 PM PDT 24
Peak memory 199824 kb
Host smart-f3898d6f-58b2-4649-b1fe-c7bc5fafe323
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2725366179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.2725366179
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.3508674622
Short name T576
Test name
Test status
Simulation time 5607423636 ps
CPU time 8.48 seconds
Started Jun 30 05:06:28 PM PDT 24
Finished Jun 30 05:06:38 PM PDT 24
Peak memory 199576 kb
Host smart-bbf42871-22d1-4890-a7d5-8aa877cf612f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508674622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3508674622
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.1666995014
Short name T319
Test name
Test status
Simulation time 5867080557 ps
CPU time 5.08 seconds
Started Jun 30 05:06:29 PM PDT 24
Finished Jun 30 05:06:36 PM PDT 24
Peak memory 199624 kb
Host smart-136d6651-4937-4f80-b7b1-c9ba29f50a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666995014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.1666995014
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.1638346311
Short name T291
Test name
Test status
Simulation time 10459860652 ps
CPU time 246.9 seconds
Started Jun 30 05:06:30 PM PDT 24
Finished Jun 30 05:10:38 PM PDT 24
Peak memory 199904 kb
Host smart-5558a4c6-0adb-4cb1-be4f-464a2545337c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1638346311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1638346311
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.2266576310
Short name T946
Test name
Test status
Simulation time 6357965946 ps
CPU time 57.34 seconds
Started Jun 30 05:06:29 PM PDT 24
Finished Jun 30 05:07:28 PM PDT 24
Peak memory 197500 kb
Host smart-c70636e2-ac2c-41c4-8ebe-67c330174b9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2266576310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.2266576310
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.4224298944
Short name T1099
Test name
Test status
Simulation time 220639281661 ps
CPU time 82.47 seconds
Started Jun 30 05:06:32 PM PDT 24
Finished Jun 30 05:07:55 PM PDT 24
Peak memory 199652 kb
Host smart-9c7913ba-3c29-4fe5-ab5d-40424e96a6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224298944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.4224298944
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.3098345473
Short name T855
Test name
Test status
Simulation time 5404764327 ps
CPU time 8.68 seconds
Started Jun 30 05:06:30 PM PDT 24
Finished Jun 30 05:06:40 PM PDT 24
Peak memory 196704 kb
Host smart-81422bc5-0a08-4468-95ab-271cd545d357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098345473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.3098345473
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_smoke.438354446
Short name T636
Test name
Test status
Simulation time 459907983 ps
CPU time 1.9 seconds
Started Jun 30 05:06:26 PM PDT 24
Finished Jun 30 05:06:29 PM PDT 24
Peak memory 198848 kb
Host smart-0b20b44b-a2b8-46be-a0a4-7e3dfb764966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438354446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.438354446
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.2468093287
Short name T197
Test name
Test status
Simulation time 102387233484 ps
CPU time 56.04 seconds
Started Jun 30 05:06:30 PM PDT 24
Finished Jun 30 05:07:27 PM PDT 24
Peak memory 199880 kb
Host smart-423151e3-cf0c-4d34-8912-af2ced6ef652
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468093287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2468093287
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.4107092084
Short name T943
Test name
Test status
Simulation time 825342801 ps
CPU time 3.31 seconds
Started Jun 30 05:06:28 PM PDT 24
Finished Jun 30 05:06:32 PM PDT 24
Peak memory 199436 kb
Host smart-a27c5da5-3ab0-45c0-97ae-7c97f8315e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107092084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.4107092084
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.2753786606
Short name T105
Test name
Test status
Simulation time 21643467261 ps
CPU time 18.58 seconds
Started Jun 30 05:06:31 PM PDT 24
Finished Jun 30 05:06:51 PM PDT 24
Peak memory 199864 kb
Host smart-cd9a54f1-4d2c-4aa9-8bc6-47cbe50ce996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753786606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2753786606
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.2404116694
Short name T820
Test name
Test status
Simulation time 36868790 ps
CPU time 0.54 seconds
Started Jun 30 05:08:31 PM PDT 24
Finished Jun 30 05:08:32 PM PDT 24
Peak memory 195236 kb
Host smart-21517da4-0458-4b82-b826-96433cb4bf67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404116694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.2404116694
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.2799246757
Short name T679
Test name
Test status
Simulation time 125343993181 ps
CPU time 204.07 seconds
Started Jun 30 05:08:33 PM PDT 24
Finished Jun 30 05:11:58 PM PDT 24
Peak memory 199920 kb
Host smart-d16dd909-2233-4275-93d7-5ba81c16067e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799246757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.2799246757
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.996713242
Short name T618
Test name
Test status
Simulation time 114588246830 ps
CPU time 183.18 seconds
Started Jun 30 05:08:34 PM PDT 24
Finished Jun 30 05:11:38 PM PDT 24
Peak memory 199920 kb
Host smart-59594815-4146-4630-a6b3-8804de427a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996713242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.996713242
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.2194219591
Short name T755
Test name
Test status
Simulation time 11145702692 ps
CPU time 18.71 seconds
Started Jun 30 05:08:32 PM PDT 24
Finished Jun 30 05:08:52 PM PDT 24
Peak memory 198536 kb
Host smart-b4ac2934-751a-4ae1-ba9e-f02a218478ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194219591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2194219591
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.854109088
Short name T1059
Test name
Test status
Simulation time 18002238592 ps
CPU time 7.62 seconds
Started Jun 30 05:08:33 PM PDT 24
Finished Jun 30 05:08:42 PM PDT 24
Peak memory 197352 kb
Host smart-a8ae0aec-fec3-4c88-b624-f1f625059ec1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854109088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.854109088
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.3209841654
Short name T515
Test name
Test status
Simulation time 40888818015 ps
CPU time 228.69 seconds
Started Jun 30 05:08:33 PM PDT 24
Finished Jun 30 05:12:23 PM PDT 24
Peak memory 199848 kb
Host smart-17599c68-8def-4e10-ab58-f406d44bcbe0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3209841654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3209841654
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1007703882
Short name T496
Test name
Test status
Simulation time 58312630 ps
CPU time 0.73 seconds
Started Jun 30 05:08:32 PM PDT 24
Finished Jun 30 05:08:34 PM PDT 24
Peak memory 196036 kb
Host smart-01785a1f-2c8b-436c-9628-d5d255146758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007703882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1007703882
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_perf.1057607086
Short name T307
Test name
Test status
Simulation time 2735627852 ps
CPU time 40.5 seconds
Started Jun 30 05:08:32 PM PDT 24
Finished Jun 30 05:09:13 PM PDT 24
Peak memory 199912 kb
Host smart-ee48617e-c04b-47e8-b594-b584f18a7f04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1057607086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1057607086
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.4043250392
Short name T826
Test name
Test status
Simulation time 2489307094 ps
CPU time 1.59 seconds
Started Jun 30 05:08:33 PM PDT 24
Finished Jun 30 05:08:36 PM PDT 24
Peak memory 197408 kb
Host smart-c87ab120-910a-423d-804e-e6b18925fddc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4043250392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.4043250392
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.2498685098
Short name T599
Test name
Test status
Simulation time 75769533404 ps
CPU time 58.91 seconds
Started Jun 30 05:08:32 PM PDT 24
Finished Jun 30 05:09:32 PM PDT 24
Peak memory 199888 kb
Host smart-c0f9c5bc-d236-40af-b615-06fab3af1cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498685098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.2498685098
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.1562144006
Short name T1097
Test name
Test status
Simulation time 29908785687 ps
CPU time 42.77 seconds
Started Jun 30 05:08:33 PM PDT 24
Finished Jun 30 05:09:17 PM PDT 24
Peak memory 196692 kb
Host smart-58132465-f6de-46b6-a77e-d08899f4766e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562144006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1562144006
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.813307831
Short name T597
Test name
Test status
Simulation time 892333786 ps
CPU time 2.89 seconds
Started Jun 30 05:08:32 PM PDT 24
Finished Jun 30 05:08:36 PM PDT 24
Peak memory 199388 kb
Host smart-3fe46ebb-fb5d-47ea-9769-1bb796006968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813307831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.813307831
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.1498122475
Short name T313
Test name
Test status
Simulation time 123088035208 ps
CPU time 475.45 seconds
Started Jun 30 05:08:32 PM PDT 24
Finished Jun 30 05:16:29 PM PDT 24
Peak memory 199892 kb
Host smart-1e35e4dc-5615-4c45-86e5-ab21941f9575
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498122475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1498122475
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.3062403220
Short name T270
Test name
Test status
Simulation time 1495837555 ps
CPU time 4.05 seconds
Started Jun 30 05:08:33 PM PDT 24
Finished Jun 30 05:08:38 PM PDT 24
Peak memory 199504 kb
Host smart-56aaf670-c170-41ef-9ef3-5be541ef9995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062403220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3062403220
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.559658653
Short name T744
Test name
Test status
Simulation time 13946048866 ps
CPU time 12.53 seconds
Started Jun 30 05:08:30 PM PDT 24
Finished Jun 30 05:08:43 PM PDT 24
Peak memory 199804 kb
Host smart-67993182-b21b-4f47-95f3-a79f81f9357c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559658653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.559658653
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.3480829648
Short name T594
Test name
Test status
Simulation time 18432464 ps
CPU time 0.53 seconds
Started Jun 30 05:08:41 PM PDT 24
Finished Jun 30 05:08:42 PM PDT 24
Peak memory 194212 kb
Host smart-56787d18-163d-42c0-b376-3f4d1193407b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480829648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3480829648
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.259253824
Short name T470
Test name
Test status
Simulation time 179675908234 ps
CPU time 14.42 seconds
Started Jun 30 05:08:41 PM PDT 24
Finished Jun 30 05:08:56 PM PDT 24
Peak memory 199860 kb
Host smart-e32a46e4-8af2-44c9-95ad-3cc7663ee245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259253824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.259253824
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1037223352
Short name T355
Test name
Test status
Simulation time 161528311745 ps
CPU time 269.7 seconds
Started Jun 30 05:08:38 PM PDT 24
Finished Jun 30 05:13:08 PM PDT 24
Peak memory 199896 kb
Host smart-a936d45a-3c8e-4a21-add7-1e9aa49ee24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037223352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1037223352
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.753368984
Short name T325
Test name
Test status
Simulation time 144273175867 ps
CPU time 28.5 seconds
Started Jun 30 05:08:41 PM PDT 24
Finished Jun 30 05:09:10 PM PDT 24
Peak memory 199860 kb
Host smart-606af8a7-029f-4cc2-9456-223a45a0c41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753368984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.753368984
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.2370303426
Short name T339
Test name
Test status
Simulation time 8334699517 ps
CPU time 4.51 seconds
Started Jun 30 05:08:41 PM PDT 24
Finished Jun 30 05:08:46 PM PDT 24
Peak memory 197700 kb
Host smart-4d5bd6d0-8eef-48ff-93c9-87d6b0911890
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370303426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2370303426
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.3573855783
Short name T370
Test name
Test status
Simulation time 64520172011 ps
CPU time 162.43 seconds
Started Jun 30 05:08:38 PM PDT 24
Finished Jun 30 05:11:21 PM PDT 24
Peak memory 199852 kb
Host smart-43449b4d-bd16-45bc-9917-6e350e460ed3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3573855783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.3573855783
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.899450091
Short name T311
Test name
Test status
Simulation time 10368417918 ps
CPU time 20.14 seconds
Started Jun 30 05:08:40 PM PDT 24
Finished Jun 30 05:09:00 PM PDT 24
Peak memory 199456 kb
Host smart-a95fb011-fde5-46c1-9f3a-670f62432423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899450091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.899450091
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_perf.661444814
Short name T1056
Test name
Test status
Simulation time 14030163419 ps
CPU time 773.31 seconds
Started Jun 30 05:08:43 PM PDT 24
Finished Jun 30 05:21:36 PM PDT 24
Peak memory 199900 kb
Host smart-0142d405-1ff8-48a6-8b50-87bace98b648
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=661444814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.661444814
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.3042914708
Short name T894
Test name
Test status
Simulation time 4937340659 ps
CPU time 10.31 seconds
Started Jun 30 05:08:39 PM PDT 24
Finished Jun 30 05:08:49 PM PDT 24
Peak memory 198932 kb
Host smart-cc0fe3fd-6726-42cb-adc3-6a79e36092dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3042914708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3042914708
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.4257554301
Short name T1092
Test name
Test status
Simulation time 10840736882 ps
CPU time 15.29 seconds
Started Jun 30 05:08:40 PM PDT 24
Finished Jun 30 05:08:56 PM PDT 24
Peak memory 198744 kb
Host smart-285886a2-ba7d-46ed-80da-7a9c2bdef417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257554301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.4257554301
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1778340195
Short name T777
Test name
Test status
Simulation time 2384638850 ps
CPU time 1.76 seconds
Started Jun 30 05:08:39 PM PDT 24
Finished Jun 30 05:08:41 PM PDT 24
Peak memory 195608 kb
Host smart-650586a5-1212-41b9-bd58-2e23efd0889f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778340195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1778340195
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.620134310
Short name T380
Test name
Test status
Simulation time 991491326 ps
CPU time 1.41 seconds
Started Jun 30 05:08:40 PM PDT 24
Finished Jun 30 05:08:42 PM PDT 24
Peak memory 198188 kb
Host smart-e5d224ba-ec52-40a2-b796-f784c8e6e8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620134310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.620134310
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.2880242363
Short name T924
Test name
Test status
Simulation time 384997897226 ps
CPU time 646.02 seconds
Started Jun 30 05:08:39 PM PDT 24
Finished Jun 30 05:19:26 PM PDT 24
Peak memory 199772 kb
Host smart-e4d5ff24-1812-4085-9ebe-6a4398a89d21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880242363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2880242363
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.2726498058
Short name T289
Test name
Test status
Simulation time 113805297583 ps
CPU time 495.56 seconds
Started Jun 30 05:08:38 PM PDT 24
Finished Jun 30 05:16:54 PM PDT 24
Peak memory 216448 kb
Host smart-d96da83b-e882-40fc-9df3-6ed45c7cbfbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726498058 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.2726498058
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1326042481
Short name T395
Test name
Test status
Simulation time 712775279 ps
CPU time 2.37 seconds
Started Jun 30 05:08:40 PM PDT 24
Finished Jun 30 05:08:42 PM PDT 24
Peak memory 198628 kb
Host smart-c00c8ef0-a1b6-4cc8-b002-01addb196d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326042481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1326042481
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.3143818166
Short name T568
Test name
Test status
Simulation time 84926484086 ps
CPU time 102.88 seconds
Started Jun 30 05:08:40 PM PDT 24
Finished Jun 30 05:10:24 PM PDT 24
Peak memory 199860 kb
Host smart-7efe3a63-88eb-4365-a9c9-154952731624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143818166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3143818166
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.327755567
Short name T608
Test name
Test status
Simulation time 15008007 ps
CPU time 0.53 seconds
Started Jun 30 05:08:46 PM PDT 24
Finished Jun 30 05:08:47 PM PDT 24
Peak memory 195228 kb
Host smart-a57dcb11-bf4c-4a3c-a621-9823101cf378
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327755567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.327755567
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.2739552968
Short name T570
Test name
Test status
Simulation time 40591032210 ps
CPU time 31.49 seconds
Started Jun 30 05:08:40 PM PDT 24
Finished Jun 30 05:09:12 PM PDT 24
Peak memory 199784 kb
Host smart-38d0c09a-fd93-4eb1-97bb-c9fa2cd5f3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739552968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.2739552968
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.3005892452
Short name T527
Test name
Test status
Simulation time 78921648770 ps
CPU time 39.7 seconds
Started Jun 30 05:08:41 PM PDT 24
Finished Jun 30 05:09:21 PM PDT 24
Peak memory 199944 kb
Host smart-99f0597b-63b5-4e1e-b7c3-8e0ed4bc9a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005892452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.3005892452
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.3006364907
Short name T676
Test name
Test status
Simulation time 128124517523 ps
CPU time 114.25 seconds
Started Jun 30 05:08:40 PM PDT 24
Finished Jun 30 05:10:35 PM PDT 24
Peak memory 199916 kb
Host smart-95196901-6883-46f3-b0f6-69a5e3a39659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006364907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3006364907
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.3441683035
Short name T108
Test name
Test status
Simulation time 318956061044 ps
CPU time 103.4 seconds
Started Jun 30 05:08:46 PM PDT 24
Finished Jun 30 05:10:30 PM PDT 24
Peak memory 199772 kb
Host smart-bc659131-b9d7-4ef5-acd4-649a106d2633
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441683035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.3441683035
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.3746539418
Short name T344
Test name
Test status
Simulation time 133323190481 ps
CPU time 1006.7 seconds
Started Jun 30 05:08:50 PM PDT 24
Finished Jun 30 05:25:37 PM PDT 24
Peak memory 199456 kb
Host smart-0c82a0af-74b8-49b4-9194-45f362470c91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3746539418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.3746539418
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.733545007
Short name T375
Test name
Test status
Simulation time 4747987507 ps
CPU time 4.83 seconds
Started Jun 30 05:08:48 PM PDT 24
Finished Jun 30 05:08:53 PM PDT 24
Peak memory 199120 kb
Host smart-ab7c1b0f-91a1-4bcc-a757-d78229406d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733545007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.733545007
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1148097234
Short name T898
Test name
Test status
Simulation time 30488123446 ps
CPU time 12.35 seconds
Started Jun 30 05:08:47 PM PDT 24
Finished Jun 30 05:09:00 PM PDT 24
Peak memory 199708 kb
Host smart-80834fc0-b221-4d2a-bbfa-3d6071cef393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148097234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1148097234
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.2817823286
Short name T345
Test name
Test status
Simulation time 9375158951 ps
CPU time 237.29 seconds
Started Jun 30 05:08:47 PM PDT 24
Finished Jun 30 05:12:45 PM PDT 24
Peak memory 199784 kb
Host smart-c64d025b-989f-46ce-b848-0627694450d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2817823286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2817823286
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.684454074
Short name T1081
Test name
Test status
Simulation time 3616269190 ps
CPU time 6.71 seconds
Started Jun 30 05:08:43 PM PDT 24
Finished Jun 30 05:08:50 PM PDT 24
Peak memory 198008 kb
Host smart-dc6b8b39-7d7d-4332-b407-ac07170cec73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=684454074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.684454074
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.3055605078
Short name T549
Test name
Test status
Simulation time 97421474458 ps
CPU time 127.89 seconds
Started Jun 30 05:08:46 PM PDT 24
Finished Jun 30 05:10:54 PM PDT 24
Peak memory 199824 kb
Host smart-074c08f3-4dab-4033-9937-c6229d7a7bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055605078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.3055605078
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.3235119163
Short name T353
Test name
Test status
Simulation time 3114116408 ps
CPU time 1.65 seconds
Started Jun 30 05:08:47 PM PDT 24
Finished Jun 30 05:08:50 PM PDT 24
Peak memory 196676 kb
Host smart-3056ebe7-4871-4630-8079-832d3c4b1f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235119163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3235119163
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.231435191
Short name T643
Test name
Test status
Simulation time 11593854554 ps
CPU time 21.72 seconds
Started Jun 30 05:08:41 PM PDT 24
Finished Jun 30 05:09:04 PM PDT 24
Peak memory 199904 kb
Host smart-5795cad3-4041-4609-a300-cae85a2978f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231435191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.231435191
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.2661510834
Short name T418
Test name
Test status
Simulation time 4282807318 ps
CPU time 2.37 seconds
Started Jun 30 05:08:47 PM PDT 24
Finished Jun 30 05:08:50 PM PDT 24
Peak memory 199892 kb
Host smart-912a1fef-99b6-4436-b920-33e4df216122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661510834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2661510834
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.2260624723
Short name T674
Test name
Test status
Simulation time 135493341685 ps
CPU time 50.39 seconds
Started Jun 30 05:08:38 PM PDT 24
Finished Jun 30 05:09:29 PM PDT 24
Peak memory 199864 kb
Host smart-c58be03d-401a-4e87-b7f5-4c61a1f2f8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260624723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2260624723
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.3695522941
Short name T861
Test name
Test status
Simulation time 24982256 ps
CPU time 0.55 seconds
Started Jun 30 05:08:57 PM PDT 24
Finished Jun 30 05:08:58 PM PDT 24
Peak memory 195216 kb
Host smart-b3f6bbfa-7553-4c36-9851-c16a624fa538
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695522941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.3695522941
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.827740861
Short name T869
Test name
Test status
Simulation time 117165149345 ps
CPU time 87.39 seconds
Started Jun 30 05:08:47 PM PDT 24
Finished Jun 30 05:10:15 PM PDT 24
Peak memory 199808 kb
Host smart-49710277-5aca-4684-9269-665befdd344c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827740861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.827740861
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.3866343237
Short name T616
Test name
Test status
Simulation time 24180573094 ps
CPU time 34.09 seconds
Started Jun 30 05:08:50 PM PDT 24
Finished Jun 30 05:09:25 PM PDT 24
Peak memory 199424 kb
Host smart-3da7eaaa-71d0-49fb-bf81-7bbc4235ecec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866343237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3866343237
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.3316447429
Short name T810
Test name
Test status
Simulation time 17630987698 ps
CPU time 29.93 seconds
Started Jun 30 05:08:48 PM PDT 24
Finished Jun 30 05:09:19 PM PDT 24
Peak memory 199420 kb
Host smart-6d94b99b-ecd6-4e86-a466-dca8473ac907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316447429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3316447429
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.3688745172
Short name T928
Test name
Test status
Simulation time 209650379273 ps
CPU time 142.73 seconds
Started Jun 30 05:08:50 PM PDT 24
Finished Jun 30 05:11:13 PM PDT 24
Peak memory 197476 kb
Host smart-84361987-500d-43cc-8c52-c2f773cd1d79
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688745172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3688745172
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.831847493
Short name T860
Test name
Test status
Simulation time 140028200379 ps
CPU time 324.94 seconds
Started Jun 30 05:08:47 PM PDT 24
Finished Jun 30 05:14:13 PM PDT 24
Peak memory 199808 kb
Host smart-8dc19e29-7fc5-4963-ad1e-9c72e71efb21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=831847493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.831847493
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.1357213983
Short name T330
Test name
Test status
Simulation time 11791179377 ps
CPU time 22.66 seconds
Started Jun 30 05:08:47 PM PDT 24
Finished Jun 30 05:09:10 PM PDT 24
Peak memory 199876 kb
Host smart-af41df4b-ffdc-4dd3-be4f-20135995c457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357213983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1357213983
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_perf.1838676019
Short name T1100
Test name
Test status
Simulation time 17337462787 ps
CPU time 959.87 seconds
Started Jun 30 05:08:45 PM PDT 24
Finished Jun 30 05:24:46 PM PDT 24
Peak memory 200132 kb
Host smart-aeb32bf5-80d5-457f-a96f-809773a93189
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1838676019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1838676019
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3004291261
Short name T714
Test name
Test status
Simulation time 4729944512 ps
CPU time 10.15 seconds
Started Jun 30 05:08:47 PM PDT 24
Finished Jun 30 05:08:58 PM PDT 24
Peak memory 198048 kb
Host smart-c4110341-e53c-4cbf-9ebd-c3b696091d22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3004291261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3004291261
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.797282657
Short name T157
Test name
Test status
Simulation time 16127254954 ps
CPU time 39.41 seconds
Started Jun 30 05:08:46 PM PDT 24
Finished Jun 30 05:09:26 PM PDT 24
Peak memory 199920 kb
Host smart-ed614767-4218-475f-aed0-eb4071c3db7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797282657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.797282657
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.3899138964
Short name T814
Test name
Test status
Simulation time 4269144760 ps
CPU time 4.24 seconds
Started Jun 30 05:08:48 PM PDT 24
Finished Jun 30 05:08:53 PM PDT 24
Peak memory 196032 kb
Host smart-2a6437cb-820a-4c5c-82ca-7a870235b02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899138964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.3899138964
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.614913768
Short name T1070
Test name
Test status
Simulation time 467016228 ps
CPU time 1.26 seconds
Started Jun 30 05:08:49 PM PDT 24
Finished Jun 30 05:08:51 PM PDT 24
Peak memory 199384 kb
Host smart-6ac3ca7b-f9b4-44e8-994b-dfa1d3a5e313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614913768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.614913768
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.537084524
Short name T535
Test name
Test status
Simulation time 105882421379 ps
CPU time 183.28 seconds
Started Jun 30 05:08:46 PM PDT 24
Finished Jun 30 05:11:50 PM PDT 24
Peak memory 199892 kb
Host smart-13a4db42-077c-418b-985e-6f59b6a8525e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537084524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.537084524
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.988481178
Short name T467
Test name
Test status
Simulation time 2247078194 ps
CPU time 1.64 seconds
Started Jun 30 05:08:48 PM PDT 24
Finished Jun 30 05:08:50 PM PDT 24
Peak memory 198072 kb
Host smart-d275a3a1-fb55-4722-a471-44360c1e0a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988481178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.988481178
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.3480817233
Short name T1025
Test name
Test status
Simulation time 136583352195 ps
CPU time 259.69 seconds
Started Jun 30 05:08:47 PM PDT 24
Finished Jun 30 05:13:07 PM PDT 24
Peak memory 199888 kb
Host smart-6f2d04c2-98cf-4c15-8684-d105187876a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480817233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.3480817233
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.2013405185
Short name T565
Test name
Test status
Simulation time 13617530 ps
CPU time 0.57 seconds
Started Jun 30 05:09:08 PM PDT 24
Finished Jun 30 05:09:09 PM PDT 24
Peak memory 195212 kb
Host smart-60e8d265-3692-4573-a834-1a0985dfdd55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013405185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2013405185
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.3458064901
Short name T469
Test name
Test status
Simulation time 19951283466 ps
CPU time 33.66 seconds
Started Jun 30 05:08:56 PM PDT 24
Finished Jun 30 05:09:30 PM PDT 24
Peak memory 199924 kb
Host smart-b0ab7645-0457-4daf-9470-3e419d0e5b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458064901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3458064901
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3946356824
Short name T433
Test name
Test status
Simulation time 157000990077 ps
CPU time 271.94 seconds
Started Jun 30 05:08:57 PM PDT 24
Finished Jun 30 05:13:30 PM PDT 24
Peak memory 199912 kb
Host smart-3e5f3915-91f9-4992-b979-b0f0f6271a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946356824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3946356824
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.2353222248
Short name T196
Test name
Test status
Simulation time 36774750663 ps
CPU time 51.5 seconds
Started Jun 30 05:08:58 PM PDT 24
Finished Jun 30 05:09:50 PM PDT 24
Peak memory 199924 kb
Host smart-b477ea0a-0b5d-4d15-b95e-9c5793734864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353222248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2353222248
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.126214131
Short name T604
Test name
Test status
Simulation time 35680958339 ps
CPU time 67.78 seconds
Started Jun 30 05:08:59 PM PDT 24
Finished Jun 30 05:10:07 PM PDT 24
Peak memory 199860 kb
Host smart-34f502a7-4a2e-4cd5-96f2-b5ebf6c91c44
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126214131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.126214131
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_loopback.1022118638
Short name T410
Test name
Test status
Simulation time 8520926752 ps
CPU time 4.61 seconds
Started Jun 30 05:08:56 PM PDT 24
Finished Jun 30 05:09:02 PM PDT 24
Peak memory 199772 kb
Host smart-db65d9fd-fb5e-40fa-8e8e-2686dd302e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022118638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.1022118638
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_perf.2720791963
Short name T1077
Test name
Test status
Simulation time 17772347622 ps
CPU time 919.64 seconds
Started Jun 30 05:08:57 PM PDT 24
Finished Jun 30 05:24:17 PM PDT 24
Peak memory 199824 kb
Host smart-d14e31a6-35d6-4b7c-b24f-d245065d8062
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2720791963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.2720791963
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.1040824890
Short name T827
Test name
Test status
Simulation time 6761266607 ps
CPU time 65.12 seconds
Started Jun 30 05:08:56 PM PDT 24
Finished Jun 30 05:10:02 PM PDT 24
Peak memory 198232 kb
Host smart-909e8037-7c95-4507-9ef9-9ccb696f7851
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1040824890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1040824890
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1954290647
Short name T925
Test name
Test status
Simulation time 21951181169 ps
CPU time 10.37 seconds
Started Jun 30 05:08:56 PM PDT 24
Finished Jun 30 05:09:07 PM PDT 24
Peak memory 200192 kb
Host smart-6ac1303b-00f5-4964-8fc5-1d1471b11189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954290647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1954290647
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.2661072641
Short name T117
Test name
Test status
Simulation time 4097227070 ps
CPU time 2.47 seconds
Started Jun 30 05:08:56 PM PDT 24
Finished Jun 30 05:08:59 PM PDT 24
Peak memory 195972 kb
Host smart-606b7e75-c401-4834-8841-cc68739e7e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661072641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.2661072641
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3539200694
Short name T669
Test name
Test status
Simulation time 439535492 ps
CPU time 1.45 seconds
Started Jun 30 05:08:56 PM PDT 24
Finished Jun 30 05:08:58 PM PDT 24
Peak memory 198620 kb
Host smart-fe4b356e-f4f3-45d1-9368-7114135b506b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539200694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3539200694
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.2642552973
Short name T915
Test name
Test status
Simulation time 123485556498 ps
CPU time 768.08 seconds
Started Jun 30 05:09:03 PM PDT 24
Finished Jun 30 05:21:51 PM PDT 24
Peak memory 199780 kb
Host smart-8f452dcb-7e9e-432a-aa6f-a7fbb95244d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642552973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2642552973
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.4030672736
Short name T587
Test name
Test status
Simulation time 22362185042 ps
CPU time 113.46 seconds
Started Jun 30 05:08:58 PM PDT 24
Finished Jun 30 05:10:52 PM PDT 24
Peak memory 215980 kb
Host smart-f600ef00-54a6-42e9-b454-3b1bcadcb7b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030672736 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.4030672736
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1868161437
Short name T283
Test name
Test status
Simulation time 13556148711 ps
CPU time 16.35 seconds
Started Jun 30 05:08:58 PM PDT 24
Finished Jun 30 05:09:15 PM PDT 24
Peak memory 199784 kb
Host smart-91669597-2b2c-44ad-ba78-cf8b1811e67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868161437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1868161437
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.4222609101
Short name T695
Test name
Test status
Simulation time 17028682273 ps
CPU time 21.85 seconds
Started Jun 30 05:08:57 PM PDT 24
Finished Jun 30 05:09:19 PM PDT 24
Peak memory 199908 kb
Host smart-40fceaf7-5c08-4fc1-bb84-f43d400fb95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222609101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.4222609101
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.2597249444
Short name T1060
Test name
Test status
Simulation time 13644422 ps
CPU time 0.55 seconds
Started Jun 30 05:09:04 PM PDT 24
Finished Jun 30 05:09:06 PM PDT 24
Peak memory 194224 kb
Host smart-3d65260a-4e4e-4bb8-a6fb-144df4779556
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597249444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2597249444
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.3437031490
Short name T458
Test name
Test status
Simulation time 49715867208 ps
CPU time 26.76 seconds
Started Jun 30 05:09:04 PM PDT 24
Finished Jun 30 05:09:31 PM PDT 24
Peak memory 199800 kb
Host smart-609c99a6-77b9-4b37-8c58-538a8af57034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437031490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3437031490
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.2023386464
Short name T501
Test name
Test status
Simulation time 418087127233 ps
CPU time 335.05 seconds
Started Jun 30 05:09:06 PM PDT 24
Finished Jun 30 05:14:41 PM PDT 24
Peak memory 199836 kb
Host smart-606edf5e-c7d7-4d00-9189-34ebf19561e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023386464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2023386464
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.3661718879
Short name T273
Test name
Test status
Simulation time 56499549038 ps
CPU time 67.9 seconds
Started Jun 30 05:09:03 PM PDT 24
Finished Jun 30 05:10:12 PM PDT 24
Peak memory 199864 kb
Host smart-3cc6aa13-f16a-448d-a3ef-59acb9698ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661718879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.3661718879
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.65375970
Short name T788
Test name
Test status
Simulation time 71950227548 ps
CPU time 14.7 seconds
Started Jun 30 05:09:06 PM PDT 24
Finished Jun 30 05:09:21 PM PDT 24
Peak memory 199852 kb
Host smart-380a2463-eff2-4a27-b7de-96ae0b0c4ed1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65375970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.65375970
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.1510407422
Short name T272
Test name
Test status
Simulation time 120853409957 ps
CPU time 248.07 seconds
Started Jun 30 05:09:07 PM PDT 24
Finished Jun 30 05:13:16 PM PDT 24
Peak memory 199816 kb
Host smart-d3997310-199c-4e55-be8e-42457853e610
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1510407422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.1510407422
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.122331065
Short name T1072
Test name
Test status
Simulation time 2517400106 ps
CPU time 5.89 seconds
Started Jun 30 05:09:03 PM PDT 24
Finished Jun 30 05:09:09 PM PDT 24
Peak memory 198016 kb
Host smart-a26b1cb8-b2bd-43ce-bf4b-eff4b43c8bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122331065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.122331065
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_perf.1750069369
Short name T310
Test name
Test status
Simulation time 13543456667 ps
CPU time 362.87 seconds
Started Jun 30 05:09:04 PM PDT 24
Finished Jun 30 05:15:08 PM PDT 24
Peak memory 199908 kb
Host smart-d54dbcdc-9838-4531-b0a7-c478578c502b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1750069369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1750069369
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.337798573
Short name T385
Test name
Test status
Simulation time 4868707843 ps
CPU time 5 seconds
Started Jun 30 05:09:05 PM PDT 24
Finished Jun 30 05:09:10 PM PDT 24
Peak memory 199124 kb
Host smart-b03c2fc0-cf8b-45eb-8598-f385b9da5da7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=337798573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.337798573
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.2205114428
Short name T697
Test name
Test status
Simulation time 146336633838 ps
CPU time 30.05 seconds
Started Jun 30 05:09:04 PM PDT 24
Finished Jun 30 05:09:35 PM PDT 24
Peak memory 200252 kb
Host smart-bf61227d-b47f-4839-9bd2-241ab746dd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205114428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2205114428
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.2415816008
Short name T520
Test name
Test status
Simulation time 4449816527 ps
CPU time 1.86 seconds
Started Jun 30 05:09:04 PM PDT 24
Finished Jun 30 05:09:07 PM PDT 24
Peak memory 196004 kb
Host smart-98f01cda-da68-4c9d-881b-6f98a704bc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415816008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2415816008
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2042090674
Short name T746
Test name
Test status
Simulation time 247725209 ps
CPU time 2.05 seconds
Started Jun 30 05:09:04 PM PDT 24
Finished Jun 30 05:09:07 PM PDT 24
Peak memory 198180 kb
Host smart-5f67d4c3-f388-4c05-8760-066555943149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042090674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2042090674
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.2464409370
Short name T833
Test name
Test status
Simulation time 341826806911 ps
CPU time 646.71 seconds
Started Jun 30 05:09:03 PM PDT 24
Finished Jun 30 05:19:50 PM PDT 24
Peak memory 199836 kb
Host smart-3fb805db-0866-498e-a382-74a9a60e744f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464409370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2464409370
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.3450612622
Short name T600
Test name
Test status
Simulation time 4213420425 ps
CPU time 1.46 seconds
Started Jun 30 05:09:03 PM PDT 24
Finished Jun 30 05:09:06 PM PDT 24
Peak memory 198404 kb
Host smart-fdc98eb4-c735-4d9c-abbd-c5aa5a77f84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450612622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3450612622
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.1525777489
Short name T351
Test name
Test status
Simulation time 14196067914 ps
CPU time 21.89 seconds
Started Jun 30 05:09:04 PM PDT 24
Finished Jun 30 05:09:26 PM PDT 24
Peak memory 199676 kb
Host smart-f2dc101a-70b3-480f-988c-50eb54f2f04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525777489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.1525777489
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2749360568
Short name T580
Test name
Test status
Simulation time 22105768 ps
CPU time 0.56 seconds
Started Jun 30 05:09:15 PM PDT 24
Finished Jun 30 05:09:16 PM PDT 24
Peak memory 195228 kb
Host smart-26ce38ef-2960-4335-b028-5b455851af61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749360568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2749360568
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.1471269870
Short name T67
Test name
Test status
Simulation time 114899111671 ps
CPU time 79.25 seconds
Started Jun 30 05:09:04 PM PDT 24
Finished Jun 30 05:10:24 PM PDT 24
Peak memory 199900 kb
Host smart-3160c152-33b6-4d0e-b6bd-23803e705ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471269870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.1471269870
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.878445169
Short name T493
Test name
Test status
Simulation time 5073812665 ps
CPU time 6.36 seconds
Started Jun 30 05:09:03 PM PDT 24
Finished Jun 30 05:09:10 PM PDT 24
Peak memory 199920 kb
Host smart-eceb66fa-9276-4e52-988a-378132760d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878445169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.878445169
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.1159669681
Short name T198
Test name
Test status
Simulation time 78116600402 ps
CPU time 174.53 seconds
Started Jun 30 05:09:03 PM PDT 24
Finished Jun 30 05:11:58 PM PDT 24
Peak memory 199868 kb
Host smart-bd11e766-d218-41a4-ab41-3c9a9a18fae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159669681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1159669681
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.2689799418
Short name T945
Test name
Test status
Simulation time 45369557567 ps
CPU time 67.76 seconds
Started Jun 30 05:09:06 PM PDT 24
Finished Jun 30 05:10:14 PM PDT 24
Peak memory 199788 kb
Host smart-09667c5c-f506-4f68-8b09-8e55cf0a5a47
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689799418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2689799418
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.699189419
Short name T563
Test name
Test status
Simulation time 109953587080 ps
CPU time 723.45 seconds
Started Jun 30 05:09:12 PM PDT 24
Finished Jun 30 05:21:16 PM PDT 24
Peak memory 199860 kb
Host smart-c1ec329d-7251-4532-9482-afe043a1c5f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=699189419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.699189419
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.1650567957
Short name T421
Test name
Test status
Simulation time 3266338911 ps
CPU time 2.47 seconds
Started Jun 30 05:09:11 PM PDT 24
Finished Jun 30 05:09:14 PM PDT 24
Peak memory 199436 kb
Host smart-ef517875-1145-4191-ad26-e888243dbe0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650567957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1650567957
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.2755939717
Short name T633
Test name
Test status
Simulation time 30425760381 ps
CPU time 13.56 seconds
Started Jun 30 05:09:07 PM PDT 24
Finished Jun 30 05:09:22 PM PDT 24
Peak memory 199772 kb
Host smart-7bb44884-b696-499d-87e3-bc444435dc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755939717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2755939717
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.3067557135
Short name T481
Test name
Test status
Simulation time 16622443502 ps
CPU time 664.21 seconds
Started Jun 30 05:09:11 PM PDT 24
Finished Jun 30 05:20:16 PM PDT 24
Peak memory 199872 kb
Host smart-2b2db78a-8ac9-45c6-a65c-44df15f820d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3067557135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3067557135
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.1595932662
Short name T692
Test name
Test status
Simulation time 5033095086 ps
CPU time 10.56 seconds
Started Jun 30 05:09:07 PM PDT 24
Finished Jun 30 05:09:18 PM PDT 24
Peak memory 199844 kb
Host smart-48e4956b-9fce-47d5-ac19-001642bedd8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1595932662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.1595932662
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.1510159501
Short name T1082
Test name
Test status
Simulation time 35310894647 ps
CPU time 56.86 seconds
Started Jun 30 05:09:02 PM PDT 24
Finished Jun 30 05:09:59 PM PDT 24
Peak memory 199912 kb
Host smart-a46bb622-30dd-4257-a2b6-385d58d9869d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510159501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.1510159501
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.3250567934
Short name T613
Test name
Test status
Simulation time 3197601157 ps
CPU time 1.87 seconds
Started Jun 30 05:09:03 PM PDT 24
Finished Jun 30 05:09:06 PM PDT 24
Peak memory 196368 kb
Host smart-4e3f399b-a429-4f4a-bd88-f723fd903c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250567934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3250567934
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.421829344
Short name T398
Test name
Test status
Simulation time 698648803 ps
CPU time 1.2 seconds
Started Jun 30 05:09:03 PM PDT 24
Finished Jun 30 05:09:05 PM PDT 24
Peak memory 198292 kb
Host smart-e67f281c-0f81-42de-8a78-eed40fec9665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421829344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.421829344
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.3313248953
Short name T52
Test name
Test status
Simulation time 234068101955 ps
CPU time 763.76 seconds
Started Jun 30 05:09:13 PM PDT 24
Finished Jun 30 05:21:58 PM PDT 24
Peak memory 216500 kb
Host smart-3278bf63-601e-462e-a703-8fa7b4f547fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313248953 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.3313248953
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.2002587916
Short name T990
Test name
Test status
Simulation time 7899211080 ps
CPU time 14.63 seconds
Started Jun 30 05:09:06 PM PDT 24
Finished Jun 30 05:09:21 PM PDT 24
Peak memory 199464 kb
Host smart-dd3e3f18-0919-405b-b5dd-5fa2909a6ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002587916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2002587916
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.2530138236
Short name T522
Test name
Test status
Simulation time 44910995745 ps
CPU time 40.58 seconds
Started Jun 30 05:09:06 PM PDT 24
Finished Jun 30 05:09:47 PM PDT 24
Peak memory 199828 kb
Host smart-7063e1bb-926b-4916-8f77-d5be714ac97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530138236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.2530138236
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1782312323
Short name T97
Test name
Test status
Simulation time 20426923 ps
CPU time 0.55 seconds
Started Jun 30 05:09:12 PM PDT 24
Finished Jun 30 05:09:13 PM PDT 24
Peak memory 195520 kb
Host smart-23c09e4e-47e8-4dfe-8fb9-498afd7c656d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782312323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1782312323
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.219999515
Short name T429
Test name
Test status
Simulation time 59318104518 ps
CPU time 23.5 seconds
Started Jun 30 05:09:13 PM PDT 24
Finished Jun 30 05:09:37 PM PDT 24
Peak memory 199844 kb
Host smart-4d33c42f-198a-497f-94e8-6e7d63b8a581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219999515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.219999515
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.679475867
Short name T1095
Test name
Test status
Simulation time 94258594671 ps
CPU time 39.95 seconds
Started Jun 30 05:09:12 PM PDT 24
Finished Jun 30 05:09:52 PM PDT 24
Peak memory 199928 kb
Host smart-318d7eb3-b53b-4ffe-a8a6-27fdecc9ae96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679475867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.679475867
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.1986350048
Short name T1002
Test name
Test status
Simulation time 39425125103 ps
CPU time 12.56 seconds
Started Jun 30 05:09:13 PM PDT 24
Finished Jun 30 05:09:26 PM PDT 24
Peak memory 199832 kb
Host smart-397abfcc-afe3-43a8-94a2-c19a5aad73e1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986350048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1986350048
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2644918843
Short name T530
Test name
Test status
Simulation time 231157100117 ps
CPU time 231.08 seconds
Started Jun 30 05:09:15 PM PDT 24
Finished Jun 30 05:13:07 PM PDT 24
Peak memory 199884 kb
Host smart-3fe3b040-ebf3-43e6-bd4e-bfea3aa556d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2644918843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2644918843
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2796665950
Short name T1085
Test name
Test status
Simulation time 2756850482 ps
CPU time 1.77 seconds
Started Jun 30 05:09:14 PM PDT 24
Finished Jun 30 05:09:16 PM PDT 24
Peak memory 197344 kb
Host smart-2f471171-5c14-4d42-91d4-2ec9b4276d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796665950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2796665950
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_perf.13181861
Short name T399
Test name
Test status
Simulation time 4077460191 ps
CPU time 99.55 seconds
Started Jun 30 05:09:13 PM PDT 24
Finished Jun 30 05:10:53 PM PDT 24
Peak memory 199832 kb
Host smart-6eee18eb-f729-45de-a0e3-b0087ed4b237
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=13181861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.13181861
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.469852858
Short name T816
Test name
Test status
Simulation time 5285844969 ps
CPU time 11.24 seconds
Started Jun 30 05:09:12 PM PDT 24
Finished Jun 30 05:09:24 PM PDT 24
Peak memory 197772 kb
Host smart-29c71d6e-8b39-46a9-a3a2-3f1c46f545b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=469852858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.469852858
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.56817827
Short name T1049
Test name
Test status
Simulation time 50199393957 ps
CPU time 67.27 seconds
Started Jun 30 05:09:15 PM PDT 24
Finished Jun 30 05:10:23 PM PDT 24
Peak memory 199512 kb
Host smart-5850aa1e-9ae4-4a7b-9b39-5272cc5e3a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56817827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.56817827
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.284113078
Short name T548
Test name
Test status
Simulation time 3364674401 ps
CPU time 4.3 seconds
Started Jun 30 05:09:13 PM PDT 24
Finished Jun 30 05:09:18 PM PDT 24
Peak memory 196288 kb
Host smart-ae0bdd83-45e8-4c3d-b74c-62db5c884b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284113078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.284113078
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.2314878234
Short name T596
Test name
Test status
Simulation time 5895227008 ps
CPU time 18.16 seconds
Started Jun 30 05:09:12 PM PDT 24
Finished Jun 30 05:09:30 PM PDT 24
Peak memory 199408 kb
Host smart-ef1bcc24-ae30-403e-adac-03d95c1c14a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314878234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2314878234
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.3231358503
Short name T722
Test name
Test status
Simulation time 215121801154 ps
CPU time 565.1 seconds
Started Jun 30 05:09:12 PM PDT 24
Finished Jun 30 05:18:38 PM PDT 24
Peak memory 199812 kb
Host smart-0ca1746a-a888-4bec-9ffc-c079df00284a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231358503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3231358503
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.2898122619
Short name T663
Test name
Test status
Simulation time 17358461370 ps
CPU time 191.52 seconds
Started Jun 30 05:09:15 PM PDT 24
Finished Jun 30 05:12:27 PM PDT 24
Peak memory 215500 kb
Host smart-3dc953ce-5a15-442b-8856-1a589a596a8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898122619 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.2898122619
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.3561448242
Short name T557
Test name
Test status
Simulation time 2743401513 ps
CPU time 2.29 seconds
Started Jun 30 05:09:12 PM PDT 24
Finished Jun 30 05:09:15 PM PDT 24
Peak memory 198256 kb
Host smart-16013f7e-e3ed-4ebe-b54b-5a6f5f52ca2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561448242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3561448242
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.930637266
Short name T482
Test name
Test status
Simulation time 95247349764 ps
CPU time 38.07 seconds
Started Jun 30 05:09:14 PM PDT 24
Finished Jun 30 05:09:53 PM PDT 24
Peak memory 199864 kb
Host smart-7b0788cd-f4f0-4925-8439-cfe2b090cf8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930637266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.930637266
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.2368358637
Short name T906
Test name
Test status
Simulation time 35025237 ps
CPU time 0.54 seconds
Started Jun 30 05:09:21 PM PDT 24
Finished Jun 30 05:09:22 PM PDT 24
Peak memory 194632 kb
Host smart-9a789cfe-fcb1-4cca-9352-2c1776cc2beb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368358637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2368358637
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.2931797432
Short name T662
Test name
Test status
Simulation time 88375579744 ps
CPU time 34.85 seconds
Started Jun 30 05:09:18 PM PDT 24
Finished Jun 30 05:09:53 PM PDT 24
Peak memory 199812 kb
Host smart-4b8fb72d-bbac-48d8-8b3d-260bea412f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931797432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2931797432
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.1460851214
Short name T514
Test name
Test status
Simulation time 144628945880 ps
CPU time 57.44 seconds
Started Jun 30 05:09:20 PM PDT 24
Finished Jun 30 05:10:17 PM PDT 24
Peak memory 199924 kb
Host smart-43b018f8-39f2-41c3-84af-2c5c0d63b3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460851214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1460851214
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3929620688
Short name T422
Test name
Test status
Simulation time 14006376513 ps
CPU time 10.14 seconds
Started Jun 30 05:09:19 PM PDT 24
Finished Jun 30 05:09:29 PM PDT 24
Peak memory 197516 kb
Host smart-5bd03306-5d19-4865-92aa-4b7028db42ca
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929620688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3929620688
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.2856499334
Short name T550
Test name
Test status
Simulation time 101904015472 ps
CPU time 367.75 seconds
Started Jun 30 05:09:19 PM PDT 24
Finished Jun 30 05:15:28 PM PDT 24
Peak memory 199848 kb
Host smart-15f03e9b-347e-4694-a19c-feefd0bf4ed7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2856499334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.2856499334
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.24822957
Short name T377
Test name
Test status
Simulation time 4147839672 ps
CPU time 5.98 seconds
Started Jun 30 05:09:19 PM PDT 24
Finished Jun 30 05:09:26 PM PDT 24
Peak memory 199892 kb
Host smart-649970fb-2e71-4126-8da7-d2bc4bc9b444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24822957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.24822957
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_perf.370011057
Short name T691
Test name
Test status
Simulation time 6796754939 ps
CPU time 94.89 seconds
Started Jun 30 05:09:19 PM PDT 24
Finished Jun 30 05:10:55 PM PDT 24
Peak memory 199824 kb
Host smart-11414549-d098-48f5-a73e-6cb929809ab7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=370011057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.370011057
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.1302984425
Short name T2
Test name
Test status
Simulation time 5664916962 ps
CPU time 11.88 seconds
Started Jun 30 05:09:21 PM PDT 24
Finished Jun 30 05:09:33 PM PDT 24
Peak memory 198056 kb
Host smart-3913ed09-4124-40d5-a651-cc6b13ac9dea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1302984425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1302984425
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.476371402
Short name T759
Test name
Test status
Simulation time 117789834453 ps
CPU time 96.93 seconds
Started Jun 30 05:09:19 PM PDT 24
Finished Jun 30 05:10:57 PM PDT 24
Peak memory 199444 kb
Host smart-434d3f0f-62d6-4d40-a21e-ff138cb0e861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476371402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.476371402
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.841208183
Short name T1000
Test name
Test status
Simulation time 3431967034 ps
CPU time 5.66 seconds
Started Jun 30 05:09:20 PM PDT 24
Finished Jun 30 05:09:26 PM PDT 24
Peak memory 196136 kb
Host smart-d4a67162-eaa9-4710-a65b-314f6cc73924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841208183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.841208183
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.2118601519
Short name T436
Test name
Test status
Simulation time 496487762 ps
CPU time 1.75 seconds
Started Jun 30 05:09:13 PM PDT 24
Finished Jun 30 05:09:15 PM PDT 24
Peak memory 198248 kb
Host smart-6b61480a-073e-4ba1-9115-a505964e378d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118601519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2118601519
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.660857191
Short name T181
Test name
Test status
Simulation time 271407916854 ps
CPU time 1718.39 seconds
Started Jun 30 05:09:20 PM PDT 24
Finished Jun 30 05:38:00 PM PDT 24
Peak memory 225536 kb
Host smart-ef1a9e4b-4892-4acf-97c3-85a0ea22b68a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660857191 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.660857191
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.2031801438
Short name T104
Test name
Test status
Simulation time 590901898 ps
CPU time 1.13 seconds
Started Jun 30 05:09:18 PM PDT 24
Finished Jun 30 05:09:20 PM PDT 24
Peak memory 196848 kb
Host smart-c8a61b9d-4134-402b-a06b-3409db7d2bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031801438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2031801438
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.3523155017
Short name T293
Test name
Test status
Simulation time 42228947170 ps
CPU time 66.39 seconds
Started Jun 30 05:09:20 PM PDT 24
Finished Jun 30 05:10:27 PM PDT 24
Peak memory 199912 kb
Host smart-de53d597-e6a4-4174-8fac-bba3e7c56dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523155017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3523155017
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.2419551829
Short name T431
Test name
Test status
Simulation time 34851597 ps
CPU time 0.55 seconds
Started Jun 30 05:09:27 PM PDT 24
Finished Jun 30 05:09:29 PM PDT 24
Peak memory 195508 kb
Host smart-c416ea82-38f3-4300-a9b5-9a0ac10bf0df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419551829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2419551829
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.3950393403
Short name T1026
Test name
Test status
Simulation time 244558634517 ps
CPU time 178.73 seconds
Started Jun 30 05:09:21 PM PDT 24
Finished Jun 30 05:12:21 PM PDT 24
Peak memory 199624 kb
Host smart-2926837f-90d1-41dc-97c7-275213cdb250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950393403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.3950393403
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.1191310504
Short name T867
Test name
Test status
Simulation time 112140477668 ps
CPU time 83.86 seconds
Started Jun 30 05:09:20 PM PDT 24
Finished Jun 30 05:10:44 PM PDT 24
Peak memory 199912 kb
Host smart-a10c3d93-5f27-4f60-8222-c982bc2b801b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191310504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1191310504
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.1143863887
Short name T150
Test name
Test status
Simulation time 109223398420 ps
CPU time 86.27 seconds
Started Jun 30 05:09:20 PM PDT 24
Finished Jun 30 05:10:47 PM PDT 24
Peak memory 199756 kb
Host smart-8b2566b2-482a-4ac0-a9d9-2b2796f7bac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143863887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1143863887
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.1846060884
Short name T961
Test name
Test status
Simulation time 12939078915 ps
CPU time 11.43 seconds
Started Jun 30 05:09:21 PM PDT 24
Finished Jun 30 05:09:33 PM PDT 24
Peak memory 199900 kb
Host smart-63373602-9f81-43e2-8013-bc69e2f5c38a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846060884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1846060884
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.2435246174
Short name T1093
Test name
Test status
Simulation time 138845092909 ps
CPU time 353.59 seconds
Started Jun 30 05:09:27 PM PDT 24
Finished Jun 30 05:15:22 PM PDT 24
Peak memory 199752 kb
Host smart-e4500aaa-5a86-400c-9274-4d99178b58d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2435246174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2435246174
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.1186429567
Short name T371
Test name
Test status
Simulation time 5734791663 ps
CPU time 1.7 seconds
Started Jun 30 05:09:26 PM PDT 24
Finished Jun 30 05:09:28 PM PDT 24
Peak memory 199332 kb
Host smart-620e7721-4bb4-45d1-ad9f-82a746098260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186429567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.1186429567
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.3839486643
Short name T986
Test name
Test status
Simulation time 43861011290 ps
CPU time 15.87 seconds
Started Jun 30 05:09:21 PM PDT 24
Finished Jun 30 05:09:38 PM PDT 24
Peak memory 197752 kb
Host smart-49402146-9ce8-4511-96d4-a290a096c050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839486643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3839486643
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.1252200613
Short name T987
Test name
Test status
Simulation time 7978040453 ps
CPU time 121.4 seconds
Started Jun 30 05:09:25 PM PDT 24
Finished Jun 30 05:11:27 PM PDT 24
Peak memory 199868 kb
Host smart-76435f21-e93c-4d74-84a2-6823d1a834c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1252200613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1252200613
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.3805013482
Short name T556
Test name
Test status
Simulation time 6295266182 ps
CPU time 6.6 seconds
Started Jun 30 05:09:20 PM PDT 24
Finished Jun 30 05:09:28 PM PDT 24
Peak memory 199188 kb
Host smart-542ed284-a966-4e90-aef8-ac6fa9346ce4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3805013482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3805013482
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.360556153
Short name T864
Test name
Test status
Simulation time 39887598111 ps
CPU time 64.47 seconds
Started Jun 30 05:09:20 PM PDT 24
Finished Jun 30 05:10:25 PM PDT 24
Peak memory 199908 kb
Host smart-f5fbbd1d-282b-4c3f-9a4c-8c9bdea51eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360556153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.360556153
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.2429025841
Short name T863
Test name
Test status
Simulation time 2445338530 ps
CPU time 2.43 seconds
Started Jun 30 05:09:21 PM PDT 24
Finished Jun 30 05:09:24 PM PDT 24
Peak memory 196452 kb
Host smart-cde36542-403f-4a5b-badc-08e43ec4408f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429025841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2429025841
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.430782843
Short name T263
Test name
Test status
Simulation time 6245734747 ps
CPU time 25 seconds
Started Jun 30 05:09:17 PM PDT 24
Finished Jun 30 05:09:42 PM PDT 24
Peak memory 199580 kb
Host smart-80516475-09c7-41a6-b1ad-40c30126aff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430782843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.430782843
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.1504990741
Short name T996
Test name
Test status
Simulation time 135686566681 ps
CPU time 41.78 seconds
Started Jun 30 05:09:27 PM PDT 24
Finished Jun 30 05:10:09 PM PDT 24
Peak memory 199772 kb
Host smart-04e0a48f-8303-4e7a-bfdb-e6cac8f02c42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504990741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.1504990741
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.1329214369
Short name T551
Test name
Test status
Simulation time 36955141239 ps
CPU time 201.91 seconds
Started Jun 30 05:09:27 PM PDT 24
Finished Jun 30 05:12:49 PM PDT 24
Peak memory 215760 kb
Host smart-00d0c563-d72f-4925-a14f-d07e789cbfc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329214369 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.1329214369
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.2088687446
Short name T443
Test name
Test status
Simulation time 7009550569 ps
CPU time 22.34 seconds
Started Jun 30 05:09:20 PM PDT 24
Finished Jun 30 05:09:44 PM PDT 24
Peak memory 199904 kb
Host smart-7c1e852b-09fc-4495-a138-1ce8ae188e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088687446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.2088687446
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1245128341
Short name T922
Test name
Test status
Simulation time 35527655206 ps
CPU time 25.7 seconds
Started Jun 30 05:09:20 PM PDT 24
Finished Jun 30 05:09:46 PM PDT 24
Peak memory 199872 kb
Host smart-8a4d2a12-5c5e-442f-994a-3647bb6d6df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245128341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1245128341
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.1398772736
Short name T730
Test name
Test status
Simulation time 108035499 ps
CPU time 0.56 seconds
Started Jun 30 05:06:36 PM PDT 24
Finished Jun 30 05:06:38 PM PDT 24
Peak memory 194192 kb
Host smart-93e7e72c-2738-4d6d-bd67-55d31423d15e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398772736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1398772736
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.3499424272
Short name T253
Test name
Test status
Simulation time 50776669427 ps
CPU time 67.94 seconds
Started Jun 30 05:06:37 PM PDT 24
Finished Jun 30 05:07:46 PM PDT 24
Peak memory 199804 kb
Host smart-be648064-a4d8-4546-a59d-da59953bfbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499424272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.3499424272
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3827892863
Short name T637
Test name
Test status
Simulation time 44560216531 ps
CPU time 17.21 seconds
Started Jun 30 05:06:35 PM PDT 24
Finished Jun 30 05:06:53 PM PDT 24
Peak memory 199164 kb
Host smart-eeff5e83-df06-42a5-9b5e-bac9dc06966e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827892863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3827892863
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.785931342
Short name T1074
Test name
Test status
Simulation time 30213826480 ps
CPU time 42.53 seconds
Started Jun 30 05:06:38 PM PDT 24
Finished Jun 30 05:07:21 PM PDT 24
Peak memory 199836 kb
Host smart-8e9e88e1-b29c-41ac-a358-506feeb20f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785931342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.785931342
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.2475363817
Short name T13
Test name
Test status
Simulation time 55048825372 ps
CPU time 48.07 seconds
Started Jun 30 05:06:36 PM PDT 24
Finished Jun 30 05:07:25 PM PDT 24
Peak memory 199892 kb
Host smart-607d5068-b83c-4322-8a73-016b00246faf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475363817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2475363817
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.3949550873
Short name T569
Test name
Test status
Simulation time 70140212453 ps
CPU time 200.16 seconds
Started Jun 30 05:06:37 PM PDT 24
Finished Jun 30 05:09:58 PM PDT 24
Peak memory 199880 kb
Host smart-77f3ec3e-d93b-4b4b-93c7-3d32688ebe45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3949550873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3949550873
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.1926466911
Short name T709
Test name
Test status
Simulation time 3182319445 ps
CPU time 4.82 seconds
Started Jun 30 05:06:38 PM PDT 24
Finished Jun 30 05:06:44 PM PDT 24
Peak memory 198464 kb
Host smart-c0a8bbe0-0eb4-4fe4-8813-182d2ed67a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926466911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.1926466911
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_perf.279269994
Short name T962
Test name
Test status
Simulation time 19856265237 ps
CPU time 217.99 seconds
Started Jun 30 05:06:36 PM PDT 24
Finished Jun 30 05:10:15 PM PDT 24
Peak memory 199912 kb
Host smart-5c5a9218-caff-46ed-972a-b5cbe1524062
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=279269994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.279269994
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.3353181276
Short name T1071
Test name
Test status
Simulation time 6520095797 ps
CPU time 14.9 seconds
Started Jun 30 05:06:37 PM PDT 24
Finished Jun 30 05:06:53 PM PDT 24
Peak memory 198772 kb
Host smart-ab659d2e-67c3-4642-a0f3-9109870611e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3353181276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.3353181276
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2344170530
Short name T444
Test name
Test status
Simulation time 43905891326 ps
CPU time 25.19 seconds
Started Jun 30 05:06:36 PM PDT 24
Finished Jun 30 05:07:03 PM PDT 24
Peak memory 199872 kb
Host smart-434a0e56-cf7d-4a82-b6fd-057f776eb253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344170530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2344170530
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.3907617332
Short name T605
Test name
Test status
Simulation time 2456253770 ps
CPU time 4.16 seconds
Started Jun 30 05:06:37 PM PDT 24
Finished Jun 30 05:06:42 PM PDT 24
Peak memory 196328 kb
Host smart-189c8053-98c0-44b9-b723-814cfff968a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907617332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.3907617332
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.468578454
Short name T25
Test name
Test status
Simulation time 128416881 ps
CPU time 0.76 seconds
Started Jun 30 05:06:36 PM PDT 24
Finished Jun 30 05:06:37 PM PDT 24
Peak memory 218368 kb
Host smart-619f28b7-2cd8-4671-b711-215bb6db4610
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468578454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.468578454
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.3946313735
Short name T684
Test name
Test status
Simulation time 5778686941 ps
CPU time 7.95 seconds
Started Jun 30 05:06:35 PM PDT 24
Finished Jun 30 05:06:44 PM PDT 24
Peak memory 199656 kb
Host smart-3aa6513c-311b-4b5f-b1f7-bfae4724ffc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946313735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3946313735
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.122365988
Short name T974
Test name
Test status
Simulation time 209075929239 ps
CPU time 90.4 seconds
Started Jun 30 05:06:47 PM PDT 24
Finished Jun 30 05:08:19 PM PDT 24
Peak memory 199720 kb
Host smart-cd73236f-f66a-4331-80f1-c18fea8f98fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122365988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.122365988
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.4270503418
Short name T428
Test name
Test status
Simulation time 114873104720 ps
CPU time 875.91 seconds
Started Jun 30 05:06:36 PM PDT 24
Finished Jun 30 05:21:13 PM PDT 24
Peak memory 216492 kb
Host smart-a3d6a4ec-97c8-4e7a-8e56-7ca587dbe8c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270503418 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.4270503418
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.1700558120
Short name T340
Test name
Test status
Simulation time 1351476269 ps
CPU time 2.31 seconds
Started Jun 30 05:06:36 PM PDT 24
Finished Jun 30 05:06:40 PM PDT 24
Peak memory 199592 kb
Host smart-2af1e81d-8874-4d41-843f-8382bb202c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700558120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.1700558120
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.2713124491
Short name T262
Test name
Test status
Simulation time 18786567516 ps
CPU time 26.19 seconds
Started Jun 30 05:06:35 PM PDT 24
Finished Jun 30 05:07:02 PM PDT 24
Peak memory 199616 kb
Host smart-08ca468a-dc99-479d-8e57-a7dd5cbae579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713124491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.2713124491
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.1748644040
Short name T693
Test name
Test status
Simulation time 34708400 ps
CPU time 0.53 seconds
Started Jun 30 05:09:35 PM PDT 24
Finished Jun 30 05:09:36 PM PDT 24
Peak memory 194688 kb
Host smart-bcc82ddc-a44d-4223-a97a-6ae4c718ec94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748644040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.1748644040
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3406172581
Short name T71
Test name
Test status
Simulation time 111195335882 ps
CPU time 90.54 seconds
Started Jun 30 05:09:27 PM PDT 24
Finished Jun 30 05:10:58 PM PDT 24
Peak memory 199904 kb
Host smart-b299820c-840b-4a46-9994-6af00b50fc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406172581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3406172581
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.1229433186
Short name T635
Test name
Test status
Simulation time 32484622302 ps
CPU time 17.94 seconds
Started Jun 30 05:09:27 PM PDT 24
Finished Jun 30 05:09:45 PM PDT 24
Peak memory 199868 kb
Host smart-4729fab6-edaa-44ae-b86d-0634219191e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229433186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1229433186
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.333991502
Short name T790
Test name
Test status
Simulation time 19840114156 ps
CPU time 19.85 seconds
Started Jun 30 05:09:27 PM PDT 24
Finished Jun 30 05:09:47 PM PDT 24
Peak memory 199908 kb
Host smart-a5c2db36-87e7-423f-9d91-a026c7537bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333991502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.333991502
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.4020979566
Short name T427
Test name
Test status
Simulation time 2651747968 ps
CPU time 4.43 seconds
Started Jun 30 05:09:30 PM PDT 24
Finished Jun 30 05:09:34 PM PDT 24
Peak memory 195752 kb
Host smart-e1627941-2be6-4ce9-abc4-326965161dc2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020979566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.4020979566
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.1515656239
Short name T868
Test name
Test status
Simulation time 82397712164 ps
CPU time 249.54 seconds
Started Jun 30 05:09:34 PM PDT 24
Finished Jun 30 05:13:44 PM PDT 24
Peak memory 199916 kb
Host smart-9c80b014-c74a-4524-93de-90d2da8738a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1515656239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.1515656239
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.4141906038
Short name T747
Test name
Test status
Simulation time 2177307530 ps
CPU time 3.63 seconds
Started Jun 30 05:09:33 PM PDT 24
Finished Jun 30 05:09:38 PM PDT 24
Peak memory 198796 kb
Host smart-4ba32dd7-4a72-4aab-9500-a95526946944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141906038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.4141906038
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_perf.1326178842
Short name T503
Test name
Test status
Simulation time 2299599077 ps
CPU time 107.91 seconds
Started Jun 30 05:09:33 PM PDT 24
Finished Jun 30 05:11:22 PM PDT 24
Peak memory 199844 kb
Host smart-088b4ea3-b728-481c-b219-3eb91ccad46c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1326178842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1326178842
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.830522220
Short name T728
Test name
Test status
Simulation time 3581526427 ps
CPU time 5.89 seconds
Started Jun 30 05:09:27 PM PDT 24
Finished Jun 30 05:09:34 PM PDT 24
Peak memory 198008 kb
Host smart-84f220eb-4890-46ed-b587-2381aaf740f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=830522220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.830522220
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.1096012184
Short name T606
Test name
Test status
Simulation time 59747150036 ps
CPU time 27.19 seconds
Started Jun 30 05:09:26 PM PDT 24
Finished Jun 30 05:09:53 PM PDT 24
Peak memory 199856 kb
Host smart-ed887793-1e6c-4195-a065-8c6d054fdd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096012184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.1096012184
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.2211609785
Short name T390
Test name
Test status
Simulation time 3102847616 ps
CPU time 2.25 seconds
Started Jun 30 05:09:28 PM PDT 24
Finished Jun 30 05:09:30 PM PDT 24
Peak memory 195956 kb
Host smart-653f59ce-70e7-46fa-906b-12c4136ded2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211609785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2211609785
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.1564725139
Short name T1009
Test name
Test status
Simulation time 948488848 ps
CPU time 1.45 seconds
Started Jun 30 05:09:30 PM PDT 24
Finished Jun 30 05:09:31 PM PDT 24
Peak memory 198652 kb
Host smart-9cb30af5-6863-452f-bcce-142536c33b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564725139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.1564725139
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.1714708891
Short name T956
Test name
Test status
Simulation time 289241101566 ps
CPU time 455.37 seconds
Started Jun 30 05:09:32 PM PDT 24
Finished Jun 30 05:17:08 PM PDT 24
Peak memory 199872 kb
Host smart-f52faffd-378b-49c1-a745-1bd1dd48eea3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714708891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.1714708891
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.4086280907
Short name T893
Test name
Test status
Simulation time 1410133636 ps
CPU time 4.21 seconds
Started Jun 30 05:09:27 PM PDT 24
Finished Jun 30 05:09:32 PM PDT 24
Peak memory 199456 kb
Host smart-6ba373a8-8e43-471d-8c1c-f71f4f67736e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086280907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.4086280907
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.3908944136
Short name T292
Test name
Test status
Simulation time 35687571625 ps
CPU time 22.27 seconds
Started Jun 30 05:09:27 PM PDT 24
Finished Jun 30 05:09:50 PM PDT 24
Peak memory 199868 kb
Host smart-d0d657f7-b8da-4dbc-b60c-771f200c7940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908944136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.3908944136
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.3523693654
Short name T890
Test name
Test status
Simulation time 95287674 ps
CPU time 0.55 seconds
Started Jun 30 05:09:43 PM PDT 24
Finished Jun 30 05:09:44 PM PDT 24
Peak memory 195520 kb
Host smart-ccd0be66-cd8d-46d3-9842-d13e6e7365dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523693654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.3523693654
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.1931796638
Short name T690
Test name
Test status
Simulation time 50010271808 ps
CPU time 78.85 seconds
Started Jun 30 05:09:33 PM PDT 24
Finished Jun 30 05:10:53 PM PDT 24
Peak memory 199920 kb
Host smart-40edebe4-b07e-4a19-b004-d2dcbe6770c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931796638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1931796638
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2628915774
Short name T518
Test name
Test status
Simulation time 46155479582 ps
CPU time 23.33 seconds
Started Jun 30 05:09:33 PM PDT 24
Finished Jun 30 05:09:57 PM PDT 24
Peak memory 199916 kb
Host smart-0209ffdd-aba5-4a3f-855a-4b4445849bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628915774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2628915774
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.2058593909
Short name T1014
Test name
Test status
Simulation time 9502525731 ps
CPU time 16.74 seconds
Started Jun 30 05:09:35 PM PDT 24
Finished Jun 30 05:09:52 PM PDT 24
Peak memory 199868 kb
Host smart-8183fdd4-e491-4ad8-ba42-87e76fbc63c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058593909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2058593909
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.199579072
Short name T1083
Test name
Test status
Simulation time 8528962752 ps
CPU time 3.92 seconds
Started Jun 30 05:09:34 PM PDT 24
Finished Jun 30 05:09:38 PM PDT 24
Peak memory 196796 kb
Host smart-4e9848ad-d2a3-45c9-8598-92bc71289343
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199579072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.199579072
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.1978683761
Short name T638
Test name
Test status
Simulation time 62296950799 ps
CPU time 402.64 seconds
Started Jun 30 05:09:41 PM PDT 24
Finished Jun 30 05:16:24 PM PDT 24
Peak memory 199840 kb
Host smart-b2968f11-be46-4d25-bfe7-e404e89819fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1978683761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.1978683761
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.639998156
Short name T909
Test name
Test status
Simulation time 5954893584 ps
CPU time 7.52 seconds
Started Jun 30 05:09:41 PM PDT 24
Finished Jun 30 05:09:49 PM PDT 24
Peak memory 199744 kb
Host smart-f746c878-7a0d-4357-8542-60ccd8b21aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639998156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.639998156
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_perf.2711591105
Short name T673
Test name
Test status
Simulation time 13155371893 ps
CPU time 476.6 seconds
Started Jun 30 05:09:42 PM PDT 24
Finished Jun 30 05:17:39 PM PDT 24
Peak memory 199788 kb
Host smart-a63f42cd-3efe-428c-b77a-a0c8421b4847
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2711591105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2711591105
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.3508377678
Short name T331
Test name
Test status
Simulation time 4569949889 ps
CPU time 5.44 seconds
Started Jun 30 05:09:38 PM PDT 24
Finished Jun 30 05:09:44 PM PDT 24
Peak memory 197780 kb
Host smart-cd33aad4-af19-4f74-9cad-d76431e0c9cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3508377678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3508377678
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.3964700940
Short name T1094
Test name
Test status
Simulation time 16302784308 ps
CPU time 28.34 seconds
Started Jun 30 05:09:38 PM PDT 24
Finished Jun 30 05:10:07 PM PDT 24
Peak memory 199764 kb
Host smart-febc7b10-bb39-4495-9ecc-65019b23c345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964700940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.3964700940
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.3428180998
Short name T301
Test name
Test status
Simulation time 574653467 ps
CPU time 1.19 seconds
Started Jun 30 05:09:33 PM PDT 24
Finished Jun 30 05:09:35 PM PDT 24
Peak memory 195360 kb
Host smart-3f43d9e9-6271-4dfe-9af2-5ad451b6a0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428180998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3428180998
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2109625167
Short name T264
Test name
Test status
Simulation time 6092958936 ps
CPU time 12.17 seconds
Started Jun 30 05:09:35 PM PDT 24
Finished Jun 30 05:09:47 PM PDT 24
Peak memory 199268 kb
Host smart-99ae2289-4a17-464e-b075-ec785679a152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109625167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2109625167
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.795081874
Short name T602
Test name
Test status
Simulation time 92906809774 ps
CPU time 127.59 seconds
Started Jun 30 05:09:42 PM PDT 24
Finished Jun 30 05:11:50 PM PDT 24
Peak memory 199856 kb
Host smart-d521040c-cea7-4b2c-b0da-a15238b6d663
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795081874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.795081874
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.1616440969
Short name T415
Test name
Test status
Simulation time 13041542142 ps
CPU time 22 seconds
Started Jun 30 05:09:34 PM PDT 24
Finished Jun 30 05:09:57 PM PDT 24
Peak memory 199784 kb
Host smart-28798b57-4d26-46e1-85a5-2a74f9ae384a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616440969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1616440969
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.1155868604
Short name T811
Test name
Test status
Simulation time 90838695464 ps
CPU time 61.09 seconds
Started Jun 30 05:09:34 PM PDT 24
Finished Jun 30 05:10:35 PM PDT 24
Peak memory 199928 kb
Host smart-cead2d29-0428-46b8-80ae-8290002ed626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155868604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1155868604
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.2614407150
Short name T1063
Test name
Test status
Simulation time 30886033 ps
CPU time 0.56 seconds
Started Jun 30 05:09:51 PM PDT 24
Finished Jun 30 05:09:52 PM PDT 24
Peak memory 195228 kb
Host smart-dbd03409-7041-43d7-a64f-43cabecb02ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614407150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.2614407150
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.1663074950
Short name T877
Test name
Test status
Simulation time 19996086745 ps
CPU time 36.4 seconds
Started Jun 30 05:09:41 PM PDT 24
Finished Jun 30 05:10:18 PM PDT 24
Peak memory 199828 kb
Host smart-a8b78496-7258-4115-abcf-d7ca2569ee4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663074950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1663074950
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.737828377
Short name T715
Test name
Test status
Simulation time 26979612160 ps
CPU time 34.13 seconds
Started Jun 30 05:09:43 PM PDT 24
Finished Jun 30 05:10:18 PM PDT 24
Peak memory 199776 kb
Host smart-8405ff34-bc40-4612-a412-f24282a928b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737828377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.737828377
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.2440829668
Short name T476
Test name
Test status
Simulation time 11448323855 ps
CPU time 18.79 seconds
Started Jun 30 05:09:43 PM PDT 24
Finished Jun 30 05:10:02 PM PDT 24
Peak memory 199884 kb
Host smart-4bdebd98-87df-4dab-97e7-90503213e0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440829668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.2440829668
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.627741110
Short name T834
Test name
Test status
Simulation time 15753915631 ps
CPU time 23.97 seconds
Started Jun 30 05:09:42 PM PDT 24
Finished Jun 30 05:10:07 PM PDT 24
Peak memory 199020 kb
Host smart-f70b779e-5c3e-498a-bcda-1a23575b5aff
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627741110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.627741110
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.2769949955
Short name T250
Test name
Test status
Simulation time 111974948650 ps
CPU time 803.16 seconds
Started Jun 30 05:09:42 PM PDT 24
Finished Jun 30 05:23:06 PM PDT 24
Peak memory 199868 kb
Host smart-e5cb4f39-c7cb-4675-b7d8-e0a18eba0e4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2769949955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2769949955
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.7220070
Short name T776
Test name
Test status
Simulation time 12948899355 ps
CPU time 20.4 seconds
Started Jun 30 05:09:42 PM PDT 24
Finished Jun 30 05:10:03 PM PDT 24
Peak memory 199820 kb
Host smart-e53de796-e048-4d31-aa89-04d814ef484a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7220070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.7220070
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_perf.1151972103
Short name T769
Test name
Test status
Simulation time 13563748932 ps
CPU time 244.37 seconds
Started Jun 30 05:09:43 PM PDT 24
Finished Jun 30 05:13:48 PM PDT 24
Peak memory 199772 kb
Host smart-bf80801a-f85e-4cfc-9f09-fb84471f346e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1151972103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1151972103
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3772021083
Short name T623
Test name
Test status
Simulation time 5988923846 ps
CPU time 37.39 seconds
Started Jun 30 05:09:40 PM PDT 24
Finished Jun 30 05:10:18 PM PDT 24
Peak memory 199324 kb
Host smart-05682417-573b-48cc-a1f7-0897aa6cb127
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3772021083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3772021083
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.501694539
Short name T487
Test name
Test status
Simulation time 30728568744 ps
CPU time 21.32 seconds
Started Jun 30 05:09:43 PM PDT 24
Finished Jun 30 05:10:05 PM PDT 24
Peak memory 199820 kb
Host smart-940c6e41-347b-4241-90cf-ca74f00e1080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501694539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.501694539
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.2182535673
Short name T274
Test name
Test status
Simulation time 1640074448 ps
CPU time 1.3 seconds
Started Jun 30 05:09:39 PM PDT 24
Finished Jun 30 05:09:41 PM PDT 24
Peak memory 195320 kb
Host smart-73084fae-c463-4579-b326-47d668a86de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182535673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.2182535673
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.1586558520
Short name T617
Test name
Test status
Simulation time 707941610 ps
CPU time 1.08 seconds
Started Jun 30 05:09:41 PM PDT 24
Finished Jun 30 05:09:42 PM PDT 24
Peak memory 198160 kb
Host smart-656c566f-88fa-4952-af13-010a469fef09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586558520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1586558520
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.1985236827
Short name T641
Test name
Test status
Simulation time 30287803437 ps
CPU time 144.49 seconds
Started Jun 30 05:09:49 PM PDT 24
Finished Jun 30 05:12:14 PM PDT 24
Peak memory 200144 kb
Host smart-e22e9c9c-3fe6-4945-83c6-f1db2bcb8652
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985236827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1985236827
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.2498504463
Short name T50
Test name
Test status
Simulation time 174799753373 ps
CPU time 614.14 seconds
Started Jun 30 05:09:50 PM PDT 24
Finished Jun 30 05:20:05 PM PDT 24
Peak memory 216516 kb
Host smart-87bc375f-3010-4ab7-b2c0-70073457547f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498504463 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.2498504463
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.2695457833
Short name T254
Test name
Test status
Simulation time 6896054986 ps
CPU time 9.24 seconds
Started Jun 30 05:09:41 PM PDT 24
Finished Jun 30 05:09:51 PM PDT 24
Peak memory 199732 kb
Host smart-90353d6d-648e-4c44-888b-d6f96557e4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695457833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2695457833
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.1328586049
Short name T404
Test name
Test status
Simulation time 61221012514 ps
CPU time 94.7 seconds
Started Jun 30 05:09:41 PM PDT 24
Finished Jun 30 05:11:17 PM PDT 24
Peak memory 199824 kb
Host smart-e203c521-1ca0-4daf-8e06-8943f1c01c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328586049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1328586049
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.3284029541
Short name T655
Test name
Test status
Simulation time 14479336 ps
CPU time 0.58 seconds
Started Jun 30 05:09:51 PM PDT 24
Finished Jun 30 05:09:52 PM PDT 24
Peak memory 195520 kb
Host smart-f311e733-bbbc-4410-a0dc-26a30634a366
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284029541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3284029541
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.591497419
Short name T543
Test name
Test status
Simulation time 35074840028 ps
CPU time 29.82 seconds
Started Jun 30 05:09:56 PM PDT 24
Finished Jun 30 05:10:27 PM PDT 24
Peak memory 199864 kb
Host smart-7ba8bc69-dbf0-48c9-8d70-bc137fdd30ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591497419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.591497419
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.72773102
Short name T601
Test name
Test status
Simulation time 142908705707 ps
CPU time 212.14 seconds
Started Jun 30 05:09:48 PM PDT 24
Finished Jun 30 05:13:20 PM PDT 24
Peak memory 199588 kb
Host smart-882b9400-e0ea-4d8d-b39a-2bb8f420f4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72773102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.72773102
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.1869757071
Short name T763
Test name
Test status
Simulation time 155065214091 ps
CPU time 49.32 seconds
Started Jun 30 05:09:49 PM PDT 24
Finished Jun 30 05:10:39 PM PDT 24
Peak memory 199856 kb
Host smart-524db39c-6add-4512-ae9a-96ba24d1438d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869757071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.1869757071
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.1842405444
Short name T1018
Test name
Test status
Simulation time 19124234437 ps
CPU time 32.37 seconds
Started Jun 30 05:09:51 PM PDT 24
Finished Jun 30 05:10:24 PM PDT 24
Peak memory 199332 kb
Host smart-3c9b6cee-d0dd-4abf-a559-f87cc8accc01
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842405444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1842405444
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.3515405453
Short name T259
Test name
Test status
Simulation time 38351541536 ps
CPU time 156.29 seconds
Started Jun 30 05:09:49 PM PDT 24
Finished Jun 30 05:12:26 PM PDT 24
Peak memory 199840 kb
Host smart-6f309b0d-f288-4a3b-8ddb-e23050814529
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3515405453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3515405453
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.1953432779
Short name T460
Test name
Test status
Simulation time 14312471436 ps
CPU time 7.11 seconds
Started Jun 30 05:09:51 PM PDT 24
Finished Jun 30 05:09:59 PM PDT 24
Peak memory 199736 kb
Host smart-9e9fe2f7-bcce-4121-9d3c-23981583a275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953432779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.1953432779
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_perf.2824168992
Short name T1020
Test name
Test status
Simulation time 25104624267 ps
CPU time 99.41 seconds
Started Jun 30 05:09:49 PM PDT 24
Finished Jun 30 05:11:30 PM PDT 24
Peak memory 199884 kb
Host smart-e43d4090-e928-45eb-91cf-7a3297fbac59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2824168992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.2824168992
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.118968632
Short name T799
Test name
Test status
Simulation time 2902560276 ps
CPU time 2.36 seconds
Started Jun 30 05:09:50 PM PDT 24
Finished Jun 30 05:09:53 PM PDT 24
Peak memory 198400 kb
Host smart-f82d7f24-0f9a-45c0-93bd-71b56b6cc5d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=118968632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.118968632
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.2810809806
Short name T805
Test name
Test status
Simulation time 74722878560 ps
CPU time 35.29 seconds
Started Jun 30 05:09:49 PM PDT 24
Finished Jun 30 05:10:24 PM PDT 24
Peak memory 199828 kb
Host smart-6d2a54c5-0c92-4442-bdfc-ee6c38caa7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810809806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.2810809806
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.911317890
Short name T277
Test name
Test status
Simulation time 1449771045 ps
CPU time 1.69 seconds
Started Jun 30 05:09:49 PM PDT 24
Finished Jun 30 05:09:51 PM PDT 24
Peak memory 195296 kb
Host smart-f59030e3-f3af-483f-b626-527d41e3c33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911317890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.911317890
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.3520268021
Short name T994
Test name
Test status
Simulation time 487076990 ps
CPU time 1.26 seconds
Started Jun 30 05:09:50 PM PDT 24
Finished Jun 30 05:09:52 PM PDT 24
Peak memory 198496 kb
Host smart-bcb257d7-eb3c-4b9f-97c0-54f9073e21ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520268021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.3520268021
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.1001818810
Short name T113
Test name
Test status
Simulation time 50040898984 ps
CPU time 789.27 seconds
Started Jun 30 05:09:49 PM PDT 24
Finished Jun 30 05:22:58 PM PDT 24
Peak memory 213372 kb
Host smart-1ef884ef-39d2-433a-b773-a930450629f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001818810 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.1001818810
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.2720827002
Short name T582
Test name
Test status
Simulation time 748312910 ps
CPU time 2.48 seconds
Started Jun 30 05:09:56 PM PDT 24
Finished Jun 30 05:09:59 PM PDT 24
Peak memory 198340 kb
Host smart-337676f0-b319-4f35-93eb-30d8dcaeb8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720827002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.2720827002
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.285512801
Short name T320
Test name
Test status
Simulation time 18085652215 ps
CPU time 15.89 seconds
Started Jun 30 05:09:49 PM PDT 24
Finished Jun 30 05:10:05 PM PDT 24
Peak memory 198052 kb
Host smart-f0c61ac1-514e-402b-913a-b3b60a139053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285512801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.285512801
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.3780578950
Short name T23
Test name
Test status
Simulation time 11479163 ps
CPU time 0.54 seconds
Started Jun 30 05:09:56 PM PDT 24
Finished Jun 30 05:09:58 PM PDT 24
Peak memory 194456 kb
Host smart-faf9393e-5840-4437-a24c-ec2e4a148803
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780578950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3780578950
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.146098895
Short name T955
Test name
Test status
Simulation time 159585765054 ps
CPU time 88.9 seconds
Started Jun 30 05:09:56 PM PDT 24
Finished Jun 30 05:11:26 PM PDT 24
Peak memory 199864 kb
Host smart-4751b1e5-6abd-4ebd-b57a-d31d9fde2d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146098895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.146098895
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1548667907
Short name T640
Test name
Test status
Simulation time 20545803774 ps
CPU time 39.78 seconds
Started Jun 30 05:09:56 PM PDT 24
Finished Jun 30 05:10:37 PM PDT 24
Peak memory 199916 kb
Host smart-2cf273c2-7bec-4b00-ba45-b9c930064343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548667907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1548667907
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_intr.165609478
Short name T567
Test name
Test status
Simulation time 268841464084 ps
CPU time 221.98 seconds
Started Jun 30 05:09:57 PM PDT 24
Finished Jun 30 05:13:40 PM PDT 24
Peak memory 199812 kb
Host smart-8068687e-2a8e-48ee-b85c-5bc94f9845cb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165609478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.165609478
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.20666472
Short name T892
Test name
Test status
Simulation time 105857421076 ps
CPU time 538.83 seconds
Started Jun 30 05:09:58 PM PDT 24
Finished Jun 30 05:18:58 PM PDT 24
Peak memory 199828 kb
Host smart-c6b76ca2-89d9-40fe-9aa9-f9d03af66713
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=20666472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.20666472
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.451995380
Short name T324
Test name
Test status
Simulation time 4672788970 ps
CPU time 8.88 seconds
Started Jun 30 05:09:58 PM PDT 24
Finished Jun 30 05:10:07 PM PDT 24
Peak memory 198956 kb
Host smart-af3c3896-bfa8-4956-a4ee-ede2ed46bd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451995380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.451995380
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_perf.2321804797
Short name T739
Test name
Test status
Simulation time 17997876541 ps
CPU time 248.69 seconds
Started Jun 30 05:09:57 PM PDT 24
Finished Jun 30 05:14:07 PM PDT 24
Peak memory 199840 kb
Host smart-0d5b7c3a-e00f-48c4-b715-d591aa81c281
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2321804797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2321804797
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.269988197
Short name T1038
Test name
Test status
Simulation time 2823391062 ps
CPU time 7.49 seconds
Started Jun 30 05:09:58 PM PDT 24
Finished Jun 30 05:10:06 PM PDT 24
Peak memory 197724 kb
Host smart-3634548b-3c28-49f2-b458-9893a80e714e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=269988197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.269988197
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.3137576840
Short name T977
Test name
Test status
Simulation time 54682754635 ps
CPU time 86.28 seconds
Started Jun 30 05:09:56 PM PDT 24
Finished Jun 30 05:11:23 PM PDT 24
Peak memory 199776 kb
Host smart-2988df7a-2473-4f46-8370-6a6af953ab82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137576840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3137576840
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.2371085610
Short name T448
Test name
Test status
Simulation time 4004476721 ps
CPU time 4.37 seconds
Started Jun 30 05:09:59 PM PDT 24
Finished Jun 30 05:10:04 PM PDT 24
Peak memory 196344 kb
Host smart-d1b8176b-a7ff-45ac-8c8b-078b75b7f710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371085610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2371085610
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.93825221
Short name T369
Test name
Test status
Simulation time 448255983 ps
CPU time 2.08 seconds
Started Jun 30 05:09:50 PM PDT 24
Finished Jun 30 05:09:53 PM PDT 24
Peak memory 199760 kb
Host smart-649681b7-d93d-470d-b815-49d77e9ced02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93825221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.93825221
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.1391520896
Short name T498
Test name
Test status
Simulation time 2630018461 ps
CPU time 2.43 seconds
Started Jun 30 05:09:58 PM PDT 24
Finished Jun 30 05:10:01 PM PDT 24
Peak memory 198656 kb
Host smart-6ee42605-e772-49ec-bce2-7150ccf5d554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391520896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1391520896
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.3338984011
Short name T778
Test name
Test status
Simulation time 11314770182 ps
CPU time 11.22 seconds
Started Jun 30 05:09:49 PM PDT 24
Finished Jun 30 05:10:01 PM PDT 24
Peak memory 199664 kb
Host smart-3dbed87f-bf49-4406-9fb2-f841bebb579d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338984011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3338984011
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.2504755606
Short name T781
Test name
Test status
Simulation time 24793958 ps
CPU time 0.56 seconds
Started Jun 30 05:10:03 PM PDT 24
Finished Jun 30 05:10:05 PM PDT 24
Peak memory 195204 kb
Host smart-e7ac5e3a-b4e3-4863-9d4b-d5dda73b7164
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504755606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2504755606
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.1239843084
Short name T819
Test name
Test status
Simulation time 35804453697 ps
CPU time 55.72 seconds
Started Jun 30 05:09:57 PM PDT 24
Finished Jun 30 05:10:54 PM PDT 24
Peak memory 199844 kb
Host smart-0441c4ae-782d-4414-9f54-be8982c6462d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239843084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1239843084
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.1659278646
Short name T921
Test name
Test status
Simulation time 31792432707 ps
CPU time 52.16 seconds
Started Jun 30 05:09:59 PM PDT 24
Finished Jun 30 05:10:52 PM PDT 24
Peak memory 199880 kb
Host smart-ca4db5ab-d1cd-4723-9730-f77b1f53a337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659278646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.1659278646
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.3349510763
Short name T689
Test name
Test status
Simulation time 21204047023 ps
CPU time 28.02 seconds
Started Jun 30 05:09:58 PM PDT 24
Finished Jun 30 05:10:27 PM PDT 24
Peak memory 199852 kb
Host smart-7c17ba00-9f42-4c3e-ba74-7250969266a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349510763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3349510763
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.1494763330
Short name T668
Test name
Test status
Simulation time 49312009348 ps
CPU time 24.22 seconds
Started Jun 30 05:09:59 PM PDT 24
Finished Jun 30 05:10:23 PM PDT 24
Peak memory 199908 kb
Host smart-5b5b1c7b-3a2d-43b4-ba4b-789745a78940
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494763330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.1494763330
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.2654409450
Short name T511
Test name
Test status
Simulation time 170412854661 ps
CPU time 81.24 seconds
Started Jun 30 05:09:57 PM PDT 24
Finished Jun 30 05:11:19 PM PDT 24
Peak memory 200104 kb
Host smart-bd40ac6a-f5be-47c1-8a8b-185ba35e39f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2654409450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.2654409450
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.2479474725
Short name T607
Test name
Test status
Simulation time 3848419524 ps
CPU time 2.6 seconds
Started Jun 30 05:09:58 PM PDT 24
Finished Jun 30 05:10:01 PM PDT 24
Peak memory 198724 kb
Host smart-ab635ad2-18cb-4a3b-beb5-a6bedf689474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479474725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2479474725
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_perf.1975321202
Short name T391
Test name
Test status
Simulation time 5801909903 ps
CPU time 93.65 seconds
Started Jun 30 05:09:57 PM PDT 24
Finished Jun 30 05:11:32 PM PDT 24
Peak memory 199544 kb
Host smart-b0e32ec5-5fe4-4ba7-bc79-b791249e98a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1975321202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.1975321202
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.2482153868
Short name T354
Test name
Test status
Simulation time 5489765464 ps
CPU time 22.67 seconds
Started Jun 30 05:09:57 PM PDT 24
Finished Jun 30 05:10:20 PM PDT 24
Peak memory 198096 kb
Host smart-8975299e-44a2-48e4-ac31-4c36c4dc155a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2482153868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2482153868
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.1058804992
Short name T621
Test name
Test status
Simulation time 27885689108 ps
CPU time 33.15 seconds
Started Jun 30 05:09:57 PM PDT 24
Finished Jun 30 05:10:31 PM PDT 24
Peak memory 199820 kb
Host smart-0cc3a329-192b-4df4-9c98-67db6e3bbe45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058804992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.1058804992
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.2259477209
Short name T1008
Test name
Test status
Simulation time 5547190657 ps
CPU time 6.68 seconds
Started Jun 30 05:09:56 PM PDT 24
Finished Jun 30 05:10:03 PM PDT 24
Peak memory 196312 kb
Host smart-c72a45cc-5b10-42e7-a554-024db90e6d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259477209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2259477209
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.3451678608
Short name T280
Test name
Test status
Simulation time 577679859 ps
CPU time 1.26 seconds
Started Jun 30 05:10:00 PM PDT 24
Finished Jun 30 05:10:02 PM PDT 24
Peak memory 198764 kb
Host smart-a364e5a9-f2cf-4767-9e0a-35039d64f335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451678608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3451678608
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.862794045
Short name T688
Test name
Test status
Simulation time 7726785608 ps
CPU time 7.31 seconds
Started Jun 30 05:09:56 PM PDT 24
Finished Jun 30 05:10:04 PM PDT 24
Peak memory 199820 kb
Host smart-9c28f8c0-ba11-49f7-b2bf-f6fbf87e4e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862794045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.862794045
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.4249992955
Short name T971
Test name
Test status
Simulation time 138519289516 ps
CPU time 48.54 seconds
Started Jun 30 05:09:57 PM PDT 24
Finished Jun 30 05:10:47 PM PDT 24
Peak memory 199760 kb
Host smart-c64475db-b81a-4036-afb2-327668dd5fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249992955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.4249992955
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.2841872238
Short name T954
Test name
Test status
Simulation time 52725164 ps
CPU time 0.57 seconds
Started Jun 30 05:10:04 PM PDT 24
Finished Jun 30 05:10:05 PM PDT 24
Peak memory 195236 kb
Host smart-c33715f9-5a47-43d1-aecd-8e2c975e749d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841872238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2841872238
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.1599105084
Short name T598
Test name
Test status
Simulation time 122030576363 ps
CPU time 65.82 seconds
Started Jun 30 05:10:07 PM PDT 24
Finished Jun 30 05:11:13 PM PDT 24
Peak memory 199864 kb
Host smart-c599d2d5-8024-40a5-8c09-cada13069fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599105084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1599105084
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.3593991195
Short name T667
Test name
Test status
Simulation time 16306263773 ps
CPU time 9.33 seconds
Started Jun 30 05:10:04 PM PDT 24
Finished Jun 30 05:10:14 PM PDT 24
Peak memory 199876 kb
Host smart-c9543588-56af-4784-bec0-12df6e9faf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593991195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3593991195
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.2245078311
Short name T227
Test name
Test status
Simulation time 12180861430 ps
CPU time 19.2 seconds
Started Jun 30 05:10:05 PM PDT 24
Finished Jun 30 05:10:25 PM PDT 24
Peak memory 199944 kb
Host smart-a6a16b0e-ac3f-4285-83a1-5d341add024a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245078311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2245078311
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.1222203811
Short name T1066
Test name
Test status
Simulation time 48619736163 ps
CPU time 16 seconds
Started Jun 30 05:10:06 PM PDT 24
Finished Jun 30 05:10:22 PM PDT 24
Peak memory 198888 kb
Host smart-8956c812-bfea-4398-b5a1-202204db4bfd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222203811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.1222203811
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.4207744203
Short name T911
Test name
Test status
Simulation time 63941186782 ps
CPU time 244.3 seconds
Started Jun 30 05:10:06 PM PDT 24
Finished Jun 30 05:14:11 PM PDT 24
Peak memory 199816 kb
Host smart-8b2cf362-a026-4b3f-bf1a-ee2651710b43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4207744203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.4207744203
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2404287655
Short name T793
Test name
Test status
Simulation time 1476862625 ps
CPU time 3.12 seconds
Started Jun 30 05:10:03 PM PDT 24
Finished Jun 30 05:10:07 PM PDT 24
Peak memory 197952 kb
Host smart-b117e9c3-e327-4f3a-a4f9-06e11898842c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404287655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2404287655
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_perf.2771848096
Short name T664
Test name
Test status
Simulation time 4982790529 ps
CPU time 63.05 seconds
Started Jun 30 05:10:06 PM PDT 24
Finished Jun 30 05:11:09 PM PDT 24
Peak memory 199864 kb
Host smart-9119c5ba-eef9-4628-9b60-4e902dc56d09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2771848096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.2771848096
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.976736112
Short name T1048
Test name
Test status
Simulation time 4339427696 ps
CPU time 46.27 seconds
Started Jun 30 05:10:04 PM PDT 24
Finished Jun 30 05:10:51 PM PDT 24
Peak memory 197812 kb
Host smart-944274d8-ac79-419a-8221-d00dad6c9006
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=976736112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.976736112
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.3296989284
Short name T942
Test name
Test status
Simulation time 38286161038 ps
CPU time 12.5 seconds
Started Jun 30 05:10:03 PM PDT 24
Finished Jun 30 05:10:17 PM PDT 24
Peak memory 199844 kb
Host smart-79ac6558-44ce-423e-97b5-b41c0b1967fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296989284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.3296989284
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3653819937
Short name T817
Test name
Test status
Simulation time 1977041244 ps
CPU time 3.54 seconds
Started Jun 30 05:10:03 PM PDT 24
Finished Jun 30 05:10:08 PM PDT 24
Peak memory 195340 kb
Host smart-089c151a-0e94-405d-a8db-f3de76a23cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653819937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3653819937
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.387497616
Short name T449
Test name
Test status
Simulation time 667278475 ps
CPU time 2.53 seconds
Started Jun 30 05:10:06 PM PDT 24
Finished Jun 30 05:10:09 PM PDT 24
Peak memory 198680 kb
Host smart-06a29ccf-f443-446a-9327-c350c3600dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387497616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.387497616
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.1749177840
Short name T156
Test name
Test status
Simulation time 202108404678 ps
CPU time 180.38 seconds
Started Jun 30 05:10:05 PM PDT 24
Finished Jun 30 05:13:06 PM PDT 24
Peak memory 200124 kb
Host smart-dc08e8e0-23e3-4810-97ad-abb7e34197b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749177840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1749177840
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.1961189211
Short name T735
Test name
Test status
Simulation time 93179736366 ps
CPU time 1008.4 seconds
Started Jun 30 05:10:03 PM PDT 24
Finished Jun 30 05:26:52 PM PDT 24
Peak memory 224696 kb
Host smart-ecc11031-9f90-46ba-8c33-316631f0ebdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961189211 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.1961189211
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.2343491433
Short name T284
Test name
Test status
Simulation time 2887638788 ps
CPU time 2.37 seconds
Started Jun 30 05:10:02 PM PDT 24
Finished Jun 30 05:10:05 PM PDT 24
Peak memory 198928 kb
Host smart-416d533d-f139-423c-98f4-fac2c1e8163e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343491433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2343491433
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1950428146
Short name T297
Test name
Test status
Simulation time 60108764384 ps
CPU time 20.8 seconds
Started Jun 30 05:10:04 PM PDT 24
Finished Jun 30 05:10:25 PM PDT 24
Peak memory 199596 kb
Host smart-096156d1-fb9f-4347-b872-80d5c4dd01aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950428146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1950428146
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.1809473745
Short name T477
Test name
Test status
Simulation time 12652166 ps
CPU time 0.56 seconds
Started Jun 30 05:10:13 PM PDT 24
Finished Jun 30 05:10:15 PM PDT 24
Peak memory 195140 kb
Host smart-52a7fd60-7f9a-41bf-98cb-002151672e5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809473745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1809473745
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.1082075431
Short name T333
Test name
Test status
Simulation time 15869690826 ps
CPU time 26.05 seconds
Started Jun 30 05:10:04 PM PDT 24
Finished Jun 30 05:10:31 PM PDT 24
Peak memory 199844 kb
Host smart-7ffbe5eb-19e2-4134-892e-ec28d60e1a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082075431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1082075431
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.2272693239
Short name T800
Test name
Test status
Simulation time 202567310142 ps
CPU time 242.83 seconds
Started Jun 30 05:10:02 PM PDT 24
Finished Jun 30 05:14:05 PM PDT 24
Peak memory 199852 kb
Host smart-76ff9b21-6ec9-470b-9762-35d660f0eb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272693239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.2272693239
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.671906742
Short name T199
Test name
Test status
Simulation time 39776911076 ps
CPU time 30.8 seconds
Started Jun 30 05:10:03 PM PDT 24
Finished Jun 30 05:10:34 PM PDT 24
Peak memory 199908 kb
Host smart-ae3596e5-775d-42ef-92ef-5b83364ac823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671906742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.671906742
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.1293318789
Short name T346
Test name
Test status
Simulation time 8518810832 ps
CPU time 2.46 seconds
Started Jun 30 05:10:05 PM PDT 24
Finished Jun 30 05:10:08 PM PDT 24
Peak memory 196644 kb
Host smart-a24f12d1-6f0f-497b-84f6-aa9a966d000f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293318789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1293318789
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.3282375542
Short name T803
Test name
Test status
Simulation time 73319856398 ps
CPU time 322.36 seconds
Started Jun 30 05:10:13 PM PDT 24
Finished Jun 30 05:15:36 PM PDT 24
Peak memory 199908 kb
Host smart-8e4c4e64-4cfb-44e9-b8c5-86fb3e5c3156
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3282375542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.3282375542
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.860205786
Short name T373
Test name
Test status
Simulation time 9271687396 ps
CPU time 22.47 seconds
Started Jun 30 05:10:13 PM PDT 24
Finished Jun 30 05:10:36 PM PDT 24
Peak memory 199376 kb
Host smart-a881f073-2478-4997-bb7c-0e73859df58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860205786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.860205786
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_perf.4171855873
Short name T881
Test name
Test status
Simulation time 7121356337 ps
CPU time 85.94 seconds
Started Jun 30 05:10:12 PM PDT 24
Finished Jun 30 05:11:39 PM PDT 24
Peak memory 199824 kb
Host smart-88a8ffec-97ed-484b-9b3d-a8d3058dc13a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4171855873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.4171855873
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.1458722766
Short name T897
Test name
Test status
Simulation time 5646139645 ps
CPU time 27.27 seconds
Started Jun 30 05:10:03 PM PDT 24
Finished Jun 30 05:10:31 PM PDT 24
Peak memory 199696 kb
Host smart-b19973b0-589e-4b38-ae7f-86d544d0e348
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1458722766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1458722766
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3349269940
Short name T383
Test name
Test status
Simulation time 30564927220 ps
CPU time 21.13 seconds
Started Jun 30 05:10:10 PM PDT 24
Finished Jun 30 05:10:32 PM PDT 24
Peak memory 199784 kb
Host smart-d30a47d3-1c55-4145-8892-64de915ecb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349269940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3349269940
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.2289321220
Short name T1030
Test name
Test status
Simulation time 17757291525 ps
CPU time 5.42 seconds
Started Jun 30 05:10:03 PM PDT 24
Finished Jun 30 05:10:09 PM PDT 24
Peak memory 195972 kb
Host smart-485663a6-63d5-4ba9-9d1b-8c57ce59fd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289321220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.2289321220
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.830224612
Short name T537
Test name
Test status
Simulation time 503785485 ps
CPU time 1.29 seconds
Started Jun 30 05:10:03 PM PDT 24
Finished Jun 30 05:10:05 PM PDT 24
Peak memory 198352 kb
Host smart-8fdf9129-6790-4703-ba6a-e8d8b38e024f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830224612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.830224612
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.2119005481
Short name T923
Test name
Test status
Simulation time 326479764837 ps
CPU time 572.42 seconds
Started Jun 30 05:10:11 PM PDT 24
Finished Jun 30 05:19:44 PM PDT 24
Peak memory 200144 kb
Host smart-4cd0737f-1319-4a91-8196-547797663160
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119005481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2119005481
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2097849388
Short name T610
Test name
Test status
Simulation time 841834714 ps
CPU time 3.01 seconds
Started Jun 30 05:10:11 PM PDT 24
Finished Jun 30 05:10:15 PM PDT 24
Peak memory 199528 kb
Host smart-514b4e34-01f8-463e-ac1a-45579631e5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097849388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2097849388
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.921763594
Short name T502
Test name
Test status
Simulation time 31830314763 ps
CPU time 61.1 seconds
Started Jun 30 05:10:04 PM PDT 24
Finished Jun 30 05:11:06 PM PDT 24
Peak memory 199844 kb
Host smart-091b71f2-1471-4a2c-9bad-f71945114459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921763594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.921763594
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.1663483202
Short name T497
Test name
Test status
Simulation time 37849263 ps
CPU time 0.53 seconds
Started Jun 30 05:10:18 PM PDT 24
Finished Jun 30 05:10:19 PM PDT 24
Peak memory 194204 kb
Host smart-923a7ff2-135c-45a4-a669-cd7b3e3a4816
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663483202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.1663483202
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2600881031
Short name T999
Test name
Test status
Simulation time 67076884868 ps
CPU time 27.91 seconds
Started Jun 30 05:10:13 PM PDT 24
Finished Jun 30 05:10:42 PM PDT 24
Peak memory 199916 kb
Host smart-c3937319-6401-4307-8652-55281d303eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600881031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2600881031
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1508925514
Short name T547
Test name
Test status
Simulation time 76070970669 ps
CPU time 61.57 seconds
Started Jun 30 05:10:12 PM PDT 24
Finished Jun 30 05:11:14 PM PDT 24
Peak memory 199816 kb
Host smart-b41c58bb-e286-49c1-a162-486f83fd3487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508925514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1508925514
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.832861993
Short name T226
Test name
Test status
Simulation time 230527727725 ps
CPU time 81.43 seconds
Started Jun 30 05:10:16 PM PDT 24
Finished Jun 30 05:11:37 PM PDT 24
Peak memory 199864 kb
Host smart-9dbf0d51-4940-496b-a62c-66ff327610fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832861993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.832861993
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.62327674
Short name T1047
Test name
Test status
Simulation time 82923287914 ps
CPU time 54.07 seconds
Started Jun 30 05:10:12 PM PDT 24
Finished Jun 30 05:11:07 PM PDT 24
Peak memory 199848 kb
Host smart-0b1930f6-6058-43cc-83d4-39437c6ede9d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62327674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.62327674
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.219806871
Short name T878
Test name
Test status
Simulation time 84208041791 ps
CPU time 246.9 seconds
Started Jun 30 05:10:18 PM PDT 24
Finished Jun 30 05:14:25 PM PDT 24
Peak memory 199872 kb
Host smart-901e785a-618c-4204-922c-f917fae8528c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=219806871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.219806871
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.4197017121
Short name T694
Test name
Test status
Simulation time 2097430802 ps
CPU time 2.41 seconds
Started Jun 30 05:10:19 PM PDT 24
Finished Jun 30 05:10:22 PM PDT 24
Peak memory 198276 kb
Host smart-af850ffd-4c6a-41b1-bf0a-c6a006796a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197017121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.4197017121
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_perf.741942668
Short name T571
Test name
Test status
Simulation time 9758548056 ps
CPU time 151.2 seconds
Started Jun 30 05:10:18 PM PDT 24
Finished Jun 30 05:12:50 PM PDT 24
Peak memory 199832 kb
Host smart-ed08532a-0f9b-4dec-8858-f7f2a949863b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=741942668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.741942668
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2719486109
Short name T626
Test name
Test status
Simulation time 7397298570 ps
CPU time 34.08 seconds
Started Jun 30 05:10:12 PM PDT 24
Finished Jun 30 05:10:47 PM PDT 24
Peak memory 198100 kb
Host smart-c5cece7f-bbfc-4ed4-a130-650a63ae9d08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2719486109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2719486109
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.51525076
Short name T979
Test name
Test status
Simulation time 99416123212 ps
CPU time 124.4 seconds
Started Jun 30 05:10:11 PM PDT 24
Finished Jun 30 05:12:15 PM PDT 24
Peak memory 199768 kb
Host smart-57467f81-5d54-431b-98d4-5394fbde4783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51525076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.51525076
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1337827346
Short name T644
Test name
Test status
Simulation time 1823813420 ps
CPU time 1.89 seconds
Started Jun 30 05:10:12 PM PDT 24
Finished Jun 30 05:10:14 PM PDT 24
Peak memory 195536 kb
Host smart-a2a693de-9e43-4b8c-9ca9-639db5391b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337827346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1337827346
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.636180782
Short name T4
Test name
Test status
Simulation time 287641099 ps
CPU time 1.65 seconds
Started Jun 30 05:10:13 PM PDT 24
Finished Jun 30 05:10:16 PM PDT 24
Peak memory 199036 kb
Host smart-d5de90a4-24c0-4fe9-a40b-0ba7e20562d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636180782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.636180782
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.1193390299
Short name T484
Test name
Test status
Simulation time 36597697876 ps
CPU time 250.56 seconds
Started Jun 30 05:10:17 PM PDT 24
Finished Jun 30 05:14:29 PM PDT 24
Peak memory 208164 kb
Host smart-01bcebe3-2df6-497f-a46d-d844f16511b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193390299 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1193390299
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.4251198119
Short name T11
Test name
Test status
Simulation time 8840231419 ps
CPU time 4.72 seconds
Started Jun 30 05:10:18 PM PDT 24
Finished Jun 30 05:10:23 PM PDT 24
Peak memory 199776 kb
Host smart-170762f6-f245-4a8d-9aaf-080ede52d7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251198119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.4251198119
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.3046217361
Short name T992
Test name
Test status
Simulation time 10572005887 ps
CPU time 18.91 seconds
Started Jun 30 05:10:12 PM PDT 24
Finished Jun 30 05:10:31 PM PDT 24
Peak memory 198612 kb
Host smart-c522dce7-3565-4c4d-8170-82d5f60c1efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046217361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3046217361
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.3171432209
Short name T787
Test name
Test status
Simulation time 18705131 ps
CPU time 0.55 seconds
Started Jun 30 05:10:25 PM PDT 24
Finished Jun 30 05:10:27 PM PDT 24
Peak memory 195212 kb
Host smart-1dd22d29-6edd-4182-be3b-6a19f0bc8ad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171432209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.3171432209
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.2762520629
Short name T856
Test name
Test status
Simulation time 40941067835 ps
CPU time 60.32 seconds
Started Jun 30 05:10:20 PM PDT 24
Finished Jun 30 05:11:21 PM PDT 24
Peak memory 199668 kb
Host smart-d96e7345-24e4-44fa-a058-88050e374e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762520629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.2762520629
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.4057366051
Short name T1065
Test name
Test status
Simulation time 75975464580 ps
CPU time 113.61 seconds
Started Jun 30 05:10:18 PM PDT 24
Finished Jun 30 05:12:12 PM PDT 24
Peak memory 199672 kb
Host smart-7d6a95f1-2069-4bce-a1fe-49e8cec18c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057366051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.4057366051
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.2874781036
Short name T804
Test name
Test status
Simulation time 86489766953 ps
CPU time 117.42 seconds
Started Jun 30 05:10:18 PM PDT 24
Finished Jun 30 05:12:16 PM PDT 24
Peak memory 199856 kb
Host smart-cf6340a9-470d-4ce8-9f7d-6d03520067d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874781036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2874781036
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3410640638
Short name T445
Test name
Test status
Simulation time 27617769200 ps
CPU time 14.41 seconds
Started Jun 30 05:10:18 PM PDT 24
Finished Jun 30 05:10:32 PM PDT 24
Peak memory 199760 kb
Host smart-12e50f06-b4e8-4dd7-afef-587e1bc2757e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410640638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3410640638
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.4123318376
Short name T765
Test name
Test status
Simulation time 108724069733 ps
CPU time 146.37 seconds
Started Jun 30 05:10:25 PM PDT 24
Finished Jun 30 05:12:52 PM PDT 24
Peak memory 199840 kb
Host smart-79722015-1b6c-43a8-83d1-62277c9d8d3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4123318376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.4123318376
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.655815719
Short name T717
Test name
Test status
Simulation time 8697165531 ps
CPU time 14.71 seconds
Started Jun 30 05:10:24 PM PDT 24
Finished Jun 30 05:10:39 PM PDT 24
Peak memory 199828 kb
Host smart-4378dc65-eb24-49fa-8722-ac55f390ba1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655815719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.655815719
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.1206874472
Short name T343
Test name
Test status
Simulation time 7422859461 ps
CPU time 11.73 seconds
Started Jun 30 05:10:20 PM PDT 24
Finished Jun 30 05:10:32 PM PDT 24
Peak memory 199708 kb
Host smart-75cfc189-3a5c-4323-8586-100409a1f138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206874472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1206874472
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.3899373421
Short name T388
Test name
Test status
Simulation time 11054293311 ps
CPU time 455.98 seconds
Started Jun 30 05:10:27 PM PDT 24
Finished Jun 30 05:18:03 PM PDT 24
Peak memory 199884 kb
Host smart-34920aac-57b4-4947-b2a7-c32a17dc3060
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3899373421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3899373421
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.1150602346
Short name T328
Test name
Test status
Simulation time 6175611116 ps
CPU time 15.06 seconds
Started Jun 30 05:10:19 PM PDT 24
Finished Jun 30 05:10:35 PM PDT 24
Peak memory 198868 kb
Host smart-ee28fb86-3775-4150-ae77-9afbcfc2dc56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1150602346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1150602346
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.2054933310
Short name T939
Test name
Test status
Simulation time 62206608191 ps
CPU time 62.49 seconds
Started Jun 30 05:10:25 PM PDT 24
Finished Jun 30 05:11:28 PM PDT 24
Peak memory 199808 kb
Host smart-8542c7d9-fa3d-468d-8707-bb59eb18e063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054933310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2054933310
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.1807433280
Short name T703
Test name
Test status
Simulation time 3190946528 ps
CPU time 5.27 seconds
Started Jun 30 05:10:20 PM PDT 24
Finished Jun 30 05:10:25 PM PDT 24
Peak memory 195768 kb
Host smart-d1ef5978-5b14-403d-9180-50c82c391ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807433280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1807433280
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.177186325
Short name T944
Test name
Test status
Simulation time 105556782 ps
CPU time 0.99 seconds
Started Jun 30 05:10:19 PM PDT 24
Finished Jun 30 05:10:20 PM PDT 24
Peak memory 199608 kb
Host smart-6c3b4f4d-39db-4067-8205-dd65d13d07e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177186325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.177186325
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.2957361657
Short name T361
Test name
Test status
Simulation time 141618031532 ps
CPU time 396.19 seconds
Started Jun 30 05:10:26 PM PDT 24
Finished Jun 30 05:17:03 PM PDT 24
Peak memory 199892 kb
Host smart-78858738-5075-4b75-b551-b37882f83a97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957361657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2957361657
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.4289593054
Short name T624
Test name
Test status
Simulation time 67310225126 ps
CPU time 479.88 seconds
Started Jun 30 05:10:27 PM PDT 24
Finished Jun 30 05:18:27 PM PDT 24
Peak memory 215780 kb
Host smart-c2f4ef06-6ead-403c-a1dd-d0940f27732d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289593054 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.4289593054
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.933032200
Short name T660
Test name
Test status
Simulation time 395665818 ps
CPU time 1.59 seconds
Started Jun 30 05:10:25 PM PDT 24
Finished Jun 30 05:10:28 PM PDT 24
Peak memory 198584 kb
Host smart-15e2a0f6-ef14-4b1d-a15d-5ebbe0dc70e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933032200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.933032200
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.847839723
Short name T896
Test name
Test status
Simulation time 63679617675 ps
CPU time 48.23 seconds
Started Jun 30 05:10:20 PM PDT 24
Finished Jun 30 05:11:08 PM PDT 24
Peak memory 199920 kb
Host smart-4e521f0b-7971-4c22-96aa-3f83ad2b46e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847839723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.847839723
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.89510581
Short name T815
Test name
Test status
Simulation time 11842632 ps
CPU time 0.56 seconds
Started Jun 30 05:06:35 PM PDT 24
Finished Jun 30 05:06:36 PM PDT 24
Peak memory 195220 kb
Host smart-e161721b-8852-4f86-a70f-0fff9a280a5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89510581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.89510581
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.699057082
Short name T838
Test name
Test status
Simulation time 141929647730 ps
CPU time 29.43 seconds
Started Jun 30 05:06:37 PM PDT 24
Finished Jun 30 05:07:07 PM PDT 24
Peak memory 199920 kb
Host smart-1c41482b-1edd-4efe-998b-2c5efe09c98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699057082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.699057082
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.3692730971
Short name T118
Test name
Test status
Simulation time 34901928880 ps
CPU time 14.42 seconds
Started Jun 30 05:06:36 PM PDT 24
Finished Jun 30 05:06:51 PM PDT 24
Peak memory 199436 kb
Host smart-e23ba312-efbc-49ea-b263-d10750a8cea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692730971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.3692730971
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.1619362804
Short name T940
Test name
Test status
Simulation time 197045377490 ps
CPU time 62.24 seconds
Started Jun 30 05:06:37 PM PDT 24
Finished Jun 30 05:07:40 PM PDT 24
Peak memory 199832 kb
Host smart-0587109b-6053-4d87-8947-4f8340254480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619362804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1619362804
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.1491275070
Short name T859
Test name
Test status
Simulation time 4276874875 ps
CPU time 3.68 seconds
Started Jun 30 05:06:48 PM PDT 24
Finished Jun 30 05:06:53 PM PDT 24
Peak memory 196456 kb
Host smart-92d7e3c8-be69-436a-b835-5a0438e4bfb4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491275070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1491275070
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.1222474323
Short name T758
Test name
Test status
Simulation time 64974722107 ps
CPU time 110.9 seconds
Started Jun 30 05:06:47 PM PDT 24
Finished Jun 30 05:08:39 PM PDT 24
Peak memory 199688 kb
Host smart-ff839a38-959d-46bb-b2bc-567e63d7556d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1222474323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1222474323
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.3767590473
Short name T1053
Test name
Test status
Simulation time 10823888026 ps
CPU time 20.43 seconds
Started Jun 30 05:06:47 PM PDT 24
Finished Jun 30 05:07:08 PM PDT 24
Peak memory 199352 kb
Host smart-362d1f84-2c3f-4590-95e8-7f7e9aacdc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767590473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3767590473
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_perf.11004896
Short name T993
Test name
Test status
Simulation time 23119930512 ps
CPU time 509.49 seconds
Started Jun 30 05:06:37 PM PDT 24
Finished Jun 30 05:15:07 PM PDT 24
Peak memory 199904 kb
Host smart-8c941031-762a-4294-91df-72b1a3b4f81e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=11004896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.11004896
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.75357902
Short name T801
Test name
Test status
Simulation time 2986898446 ps
CPU time 2.66 seconds
Started Jun 30 05:06:37 PM PDT 24
Finished Jun 30 05:06:40 PM PDT 24
Peak memory 197796 kb
Host smart-0ab6aa56-e302-4dac-9f6b-debdfadc10ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=75357902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.75357902
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.3821879485
Short name T910
Test name
Test status
Simulation time 205800941775 ps
CPU time 208.26 seconds
Started Jun 30 05:06:48 PM PDT 24
Finished Jun 30 05:10:18 PM PDT 24
Peak memory 199672 kb
Host smart-f60be3e8-af7c-4d27-8b12-b13a47779308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821879485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3821879485
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.2769095347
Short name T1061
Test name
Test status
Simulation time 52289631912 ps
CPU time 76.58 seconds
Started Jun 30 05:06:34 PM PDT 24
Finished Jun 30 05:07:51 PM PDT 24
Peak memory 195960 kb
Host smart-023995e3-10b5-4292-b689-102871292901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769095347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.2769095347
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.2782098866
Short name T895
Test name
Test status
Simulation time 735628330 ps
CPU time 2.76 seconds
Started Jun 30 05:06:47 PM PDT 24
Finished Jun 30 05:06:51 PM PDT 24
Peak memory 199300 kb
Host smart-e14699ba-4cce-45bb-a633-8abf8a8600a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782098866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2782098866
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.2005644869
Short name T69
Test name
Test status
Simulation time 298403184506 ps
CPU time 239.43 seconds
Started Jun 30 05:06:36 PM PDT 24
Finished Jun 30 05:10:36 PM PDT 24
Peak memory 199860 kb
Host smart-4268f860-040c-41cf-aebb-70763ecee071
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005644869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.2005644869
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.3451903617
Short name T653
Test name
Test status
Simulation time 1419911318 ps
CPU time 1.8 seconds
Started Jun 30 05:06:35 PM PDT 24
Finished Jun 30 05:06:37 PM PDT 24
Peak memory 198292 kb
Host smart-b45d00a3-59be-4827-8850-29fddbad23af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451903617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.3451903617
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.2737613910
Short name T486
Test name
Test status
Simulation time 40860501463 ps
CPU time 78.47 seconds
Started Jun 30 05:06:35 PM PDT 24
Finished Jun 30 05:07:54 PM PDT 24
Peak memory 199876 kb
Host smart-9e869fb8-e643-4fb0-b858-32cfff5ed0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737613910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2737613910
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.1951818723
Short name T968
Test name
Test status
Simulation time 56288137778 ps
CPU time 80.81 seconds
Started Jun 30 05:10:25 PM PDT 24
Finished Jun 30 05:11:47 PM PDT 24
Peak memory 199812 kb
Host smart-8ec7fc10-d082-4d5f-8c6a-5eabbbe69467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951818723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1951818723
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.440945562
Short name T261
Test name
Test status
Simulation time 15204810307 ps
CPU time 21.69 seconds
Started Jun 30 05:10:25 PM PDT 24
Finished Jun 30 05:10:48 PM PDT 24
Peak memory 199924 kb
Host smart-cf570685-6b6a-43cd-a78c-0fa65b0080b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440945562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.440945562
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.2219135800
Short name T612
Test name
Test status
Simulation time 63739341129 ps
CPU time 75.63 seconds
Started Jun 30 05:10:26 PM PDT 24
Finished Jun 30 05:11:42 PM PDT 24
Peak memory 199892 kb
Host smart-c4128906-b222-4897-b8df-56e345c4237f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219135800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2219135800
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.2049101824
Short name T454
Test name
Test status
Simulation time 53789734896 ps
CPU time 62.29 seconds
Started Jun 30 05:10:33 PM PDT 24
Finished Jun 30 05:11:36 PM PDT 24
Peak memory 199840 kb
Host smart-5700140d-c6ae-467f-b796-a684b6bfc98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049101824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.2049101824
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.686519072
Short name T125
Test name
Test status
Simulation time 67668456625 ps
CPU time 783.35 seconds
Started Jun 30 05:10:33 PM PDT 24
Finished Jun 30 05:23:37 PM PDT 24
Peak memory 216000 kb
Host smart-7b8e9099-adc5-4f08-a587-1ad19ea9fbfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686519072 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.686519072
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.2819905275
Short name T124
Test name
Test status
Simulation time 44664834623 ps
CPU time 14.41 seconds
Started Jun 30 05:10:33 PM PDT 24
Finished Jun 30 05:10:48 PM PDT 24
Peak memory 199820 kb
Host smart-0fa29a2f-6699-4884-95ec-55638e49755c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819905275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2819905275
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3657096736
Short name T193
Test name
Test status
Simulation time 19223154682 ps
CPU time 37.48 seconds
Started Jun 30 05:10:32 PM PDT 24
Finished Jun 30 05:11:09 PM PDT 24
Peak memory 199948 kb
Host smart-70f70993-133b-44ab-aa02-78cb345aba83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657096736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3657096736
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.3003283714
Short name T1033
Test name
Test status
Simulation time 10630632821 ps
CPU time 14.95 seconds
Started Jun 30 05:10:34 PM PDT 24
Finished Jun 30 05:10:49 PM PDT 24
Peak memory 199912 kb
Host smart-b7474e44-e54b-48f9-8bb6-94d33e5b9ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003283714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.3003283714
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.1349650933
Short name T574
Test name
Test status
Simulation time 56884853444 ps
CPU time 53.27 seconds
Started Jun 30 05:10:33 PM PDT 24
Finished Jun 30 05:11:27 PM PDT 24
Peak memory 199904 kb
Host smart-b0c49964-dcd6-4924-b159-b9c41d00fdbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349650933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.1349650933
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.892248480
Short name T49
Test name
Test status
Simulation time 50967069941 ps
CPU time 932.17 seconds
Started Jun 30 05:10:33 PM PDT 24
Finished Jun 30 05:26:05 PM PDT 24
Peak memory 216480 kb
Host smart-e4c943ba-c2ea-46b7-bdcd-f399ab37dc3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892248480 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.892248480
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.429363776
Short name T200
Test name
Test status
Simulation time 59621796303 ps
CPU time 24.91 seconds
Started Jun 30 05:10:33 PM PDT 24
Finished Jun 30 05:10:58 PM PDT 24
Peak memory 199860 kb
Host smart-c2cc2835-b076-4eea-a472-1d84d17c8096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429363776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.429363776
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3641044990
Short name T281
Test name
Test status
Simulation time 27053253540 ps
CPU time 24.97 seconds
Started Jun 30 05:10:32 PM PDT 24
Finished Jun 30 05:10:58 PM PDT 24
Peak memory 199852 kb
Host smart-c37a51aa-fbc4-43c2-bafb-0dc248e64614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641044990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3641044990
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3576537663
Short name T622
Test name
Test status
Simulation time 155124084225 ps
CPU time 453.8 seconds
Started Jun 30 05:10:32 PM PDT 24
Finished Jun 30 05:18:07 PM PDT 24
Peak memory 216364 kb
Host smart-6c5e841f-d4ec-4d96-a945-3e8ca0662e25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576537663 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3576537663
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3961584045
Short name T853
Test name
Test status
Simulation time 14456800 ps
CPU time 0.57 seconds
Started Jun 30 05:06:41 PM PDT 24
Finished Jun 30 05:06:42 PM PDT 24
Peak memory 195484 kb
Host smart-f350f277-f8d1-49d5-b281-afb48951e75f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961584045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3961584045
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.1665421233
Short name T541
Test name
Test status
Simulation time 26017498747 ps
CPU time 43.95 seconds
Started Jun 30 05:06:43 PM PDT 24
Finished Jun 30 05:07:28 PM PDT 24
Peak memory 199784 kb
Host smart-b2bd999d-cf75-44a6-84df-102be68ae670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665421233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1665421233
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.176776491
Short name T865
Test name
Test status
Simulation time 43517719756 ps
CPU time 16.77 seconds
Started Jun 30 05:06:40 PM PDT 24
Finished Jun 30 05:06:58 PM PDT 24
Peak memory 199476 kb
Host smart-c8e341e5-656a-4471-9cf7-251e1d895a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176776491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.176776491
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.3294522859
Short name T211
Test name
Test status
Simulation time 44119769096 ps
CPU time 63.34 seconds
Started Jun 30 05:06:41 PM PDT 24
Finished Jun 30 05:07:45 PM PDT 24
Peak memory 199616 kb
Host smart-2a3d0e3d-c73c-4b78-8d5c-8f8be2426dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294522859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.3294522859
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.3845693733
Short name T725
Test name
Test status
Simulation time 36499550643 ps
CPU time 14.11 seconds
Started Jun 30 05:06:43 PM PDT 24
Finished Jun 30 05:06:58 PM PDT 24
Peak memory 198700 kb
Host smart-b3779e60-a1f9-48f9-8591-cbf38553bef3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845693733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3845693733
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.2814777214
Short name T237
Test name
Test status
Simulation time 306898439659 ps
CPU time 305.68 seconds
Started Jun 30 05:06:45 PM PDT 24
Finished Jun 30 05:11:52 PM PDT 24
Peak memory 199912 kb
Host smart-99602d64-8038-4ca9-b71c-489f37a153ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2814777214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2814777214
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.1720545326
Short name T768
Test name
Test status
Simulation time 11273654897 ps
CPU time 7.79 seconds
Started Jun 30 05:06:42 PM PDT 24
Finished Jun 30 05:06:50 PM PDT 24
Peak memory 198844 kb
Host smart-a8647a17-8cbe-4b0a-bff8-1890e1d67fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720545326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1720545326
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_perf.1016857516
Short name T564
Test name
Test status
Simulation time 24265479086 ps
CPU time 1456.9 seconds
Started Jun 30 05:06:47 PM PDT 24
Finished Jun 30 05:31:06 PM PDT 24
Peak memory 199832 kb
Host smart-e654e5c4-3e94-4f20-94ea-be3cab3337be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1016857516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1016857516
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.3757982729
Short name T348
Test name
Test status
Simulation time 3664166783 ps
CPU time 31.39 seconds
Started Jun 30 05:06:40 PM PDT 24
Finished Jun 30 05:07:12 PM PDT 24
Peak memory 198944 kb
Host smart-d5cb26c5-f762-4408-961c-2dbe007cb5f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3757982729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3757982729
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1568626618
Short name T139
Test name
Test status
Simulation time 30960769851 ps
CPU time 53.06 seconds
Started Jun 30 05:06:43 PM PDT 24
Finished Jun 30 05:07:37 PM PDT 24
Peak memory 199784 kb
Host smart-b21aaaf5-dfb5-4d69-9daa-e539f835a011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568626618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1568626618
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.437273038
Short name T73
Test name
Test status
Simulation time 1651138507 ps
CPU time 2.1 seconds
Started Jun 30 05:06:45 PM PDT 24
Finished Jun 30 05:06:48 PM PDT 24
Peak memory 195488 kb
Host smart-b2c5e1aa-2677-4c69-bb75-21eef851d423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437273038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.437273038
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.2746500608
Short name T988
Test name
Test status
Simulation time 5737943721 ps
CPU time 16.48 seconds
Started Jun 30 05:06:48 PM PDT 24
Finished Jun 30 05:07:06 PM PDT 24
Peak memory 199596 kb
Host smart-a9e7da16-1f6b-4f94-b348-74dd06f288d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746500608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.2746500608
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.799861616
Short name T1032
Test name
Test status
Simulation time 78211104184 ps
CPU time 361.42 seconds
Started Jun 30 05:06:48 PM PDT 24
Finished Jun 30 05:12:50 PM PDT 24
Peak memory 199816 kb
Host smart-4195c35b-aed4-49e9-ba4c-6ce447d3c9c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799861616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.799861616
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.1448463917
Short name T29
Test name
Test status
Simulation time 18988480429 ps
CPU time 305.04 seconds
Started Jun 30 05:06:43 PM PDT 24
Finished Jun 30 05:11:49 PM PDT 24
Peak memory 216360 kb
Host smart-5c6de9be-d8ff-4847-8b35-3064f2a373e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448463917 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.1448463917
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.1677971480
Short name T359
Test name
Test status
Simulation time 965843373 ps
CPU time 3.35 seconds
Started Jun 30 05:06:41 PM PDT 24
Finished Jun 30 05:06:45 PM PDT 24
Peak memory 199756 kb
Host smart-19b241ea-1ea1-41d4-afe9-63cb59c70e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677971480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.1677971480
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.437361357
Short name T440
Test name
Test status
Simulation time 26910551325 ps
CPU time 40.3 seconds
Started Jun 30 05:06:42 PM PDT 24
Finished Jun 30 05:07:23 PM PDT 24
Peak memory 199828 kb
Host smart-a2320cc5-3a7d-4b34-9734-b244525a6819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437361357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.437361357
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.2163681436
Short name T1091
Test name
Test status
Simulation time 76315700203 ps
CPU time 125.48 seconds
Started Jun 30 05:10:34 PM PDT 24
Finished Jun 30 05:12:40 PM PDT 24
Peak memory 199924 kb
Host smart-1c581198-1020-470d-b59e-180e62cca15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163681436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.2163681436
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.770504199
Short name T753
Test name
Test status
Simulation time 158435799724 ps
CPU time 47.79 seconds
Started Jun 30 05:10:36 PM PDT 24
Finished Jun 30 05:11:25 PM PDT 24
Peak memory 199864 kb
Host smart-7b1e6b4e-1b6c-42db-a698-c013b6e9e678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770504199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.770504199
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.85031600
Short name T562
Test name
Test status
Simulation time 26187678787 ps
CPU time 696.69 seconds
Started Jun 30 05:10:36 PM PDT 24
Finished Jun 30 05:22:13 PM PDT 24
Peak memory 216400 kb
Host smart-94ffd9b5-7a40-4ad8-8b9d-a422e49f06f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85031600 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.85031600
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.3585762030
Short name T378
Test name
Test status
Simulation time 19558574850 ps
CPU time 26.51 seconds
Started Jun 30 05:10:33 PM PDT 24
Finished Jun 30 05:11:00 PM PDT 24
Peak memory 199820 kb
Host smart-4df94e53-a5b4-4edc-ae73-15c5eaa5042c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585762030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3585762030
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.3542527656
Short name T991
Test name
Test status
Simulation time 20189394238 ps
CPU time 14.48 seconds
Started Jun 30 05:10:33 PM PDT 24
Finished Jun 30 05:10:48 PM PDT 24
Peak memory 199896 kb
Host smart-4f2b573f-a481-4b50-9a78-67c8c289a7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542527656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3542527656
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.1442480164
Short name T17
Test name
Test status
Simulation time 49826893852 ps
CPU time 518.74 seconds
Started Jun 30 05:10:33 PM PDT 24
Finished Jun 30 05:19:12 PM PDT 24
Peak memory 216456 kb
Host smart-84885f5b-5554-46c4-9f8f-b79f9f4923cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442480164 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.1442480164
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.4129736865
Short name T593
Test name
Test status
Simulation time 14954135220 ps
CPU time 36.54 seconds
Started Jun 30 05:10:33 PM PDT 24
Finished Jun 30 05:11:10 PM PDT 24
Peak memory 199840 kb
Host smart-335d4c8a-9246-4574-aa69-a525fe21836f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129736865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.4129736865
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.4212060839
Short name T107
Test name
Test status
Simulation time 105730584205 ps
CPU time 40.28 seconds
Started Jun 30 05:10:40 PM PDT 24
Finished Jun 30 05:11:21 PM PDT 24
Peak memory 199844 kb
Host smart-8298190f-c0b0-44ba-b449-f4203ce9b377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212060839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.4212060839
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.766678714
Short name T288
Test name
Test status
Simulation time 28715646824 ps
CPU time 45.53 seconds
Started Jun 30 05:10:42 PM PDT 24
Finished Jun 30 05:11:28 PM PDT 24
Peak memory 199924 kb
Host smart-d5f818f0-cfce-4ef2-9b72-4b2581b15f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766678714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.766678714
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.939057163
Short name T318
Test name
Test status
Simulation time 22193946651 ps
CPU time 30.26 seconds
Started Jun 30 05:10:41 PM PDT 24
Finished Jun 30 05:11:12 PM PDT 24
Peak memory 199564 kb
Host smart-2dcf7f2a-6743-4b21-8df7-18e6362fd753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939057163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.939057163
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.3339701222
Short name T700
Test name
Test status
Simulation time 37364524626 ps
CPU time 326.66 seconds
Started Jun 30 05:10:42 PM PDT 24
Finished Jun 30 05:16:10 PM PDT 24
Peak memory 216420 kb
Host smart-a79d30ba-e3f4-4c20-b248-fe8245f631cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339701222 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.3339701222
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.1381086590
Short name T760
Test name
Test status
Simulation time 18483541025 ps
CPU time 17.29 seconds
Started Jun 30 05:10:42 PM PDT 24
Finished Jun 30 05:10:59 PM PDT 24
Peak memory 199800 kb
Host smart-c189bcfe-5237-442e-8705-6856b9a6b56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381086590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.1381086590
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.2876257971
Short name T168
Test name
Test status
Simulation time 101196457280 ps
CPU time 53.25 seconds
Started Jun 30 05:10:39 PM PDT 24
Finished Jun 30 05:11:32 PM PDT 24
Peak memory 199764 kb
Host smart-af5c7f57-d5cd-45b0-ba3b-45e662628f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876257971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2876257971
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.2271549136
Short name T1007
Test name
Test status
Simulation time 33187673 ps
CPU time 0.56 seconds
Started Jun 30 05:06:42 PM PDT 24
Finished Jun 30 05:06:43 PM PDT 24
Peak memory 195132 kb
Host smart-925c54d3-7cb7-4133-84ff-efa39a097821
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271549136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2271549136
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.1139126874
Short name T851
Test name
Test status
Simulation time 149148424605 ps
CPU time 63 seconds
Started Jun 30 05:06:43 PM PDT 24
Finished Jun 30 05:07:47 PM PDT 24
Peak memory 199904 kb
Host smart-b0e1c116-03f9-4a4c-b140-e197f0a4a8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139126874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.1139126874
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.3492607967
Short name T809
Test name
Test status
Simulation time 34099754018 ps
CPU time 35.22 seconds
Started Jun 30 05:06:48 PM PDT 24
Finished Jun 30 05:07:25 PM PDT 24
Peak memory 199944 kb
Host smart-8e33f73e-823a-4dbc-b05c-98b2f2902dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492607967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3492607967
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.3043407474
Short name T235
Test name
Test status
Simulation time 46033284897 ps
CPU time 71.3 seconds
Started Jun 30 05:06:43 PM PDT 24
Finished Jun 30 05:07:55 PM PDT 24
Peak memory 199772 kb
Host smart-b33eabc1-e257-4537-a173-9a965ac3ae3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043407474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.3043407474
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.402343146
Short name T387
Test name
Test status
Simulation time 68470361256 ps
CPU time 114.8 seconds
Started Jun 30 05:06:47 PM PDT 24
Finished Jun 30 05:08:43 PM PDT 24
Peak memory 199884 kb
Host smart-c8216038-4e98-441c-9b95-3ca9ffc2ca7a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402343146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.402343146
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.3378844169
Short name T271
Test name
Test status
Simulation time 117240389018 ps
CPU time 939.79 seconds
Started Jun 30 05:06:43 PM PDT 24
Finished Jun 30 05:22:24 PM PDT 24
Peak memory 199880 kb
Host smart-cc853ffc-a4af-4f2a-843e-d6499e3185f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3378844169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3378844169
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.3771009866
Short name T919
Test name
Test status
Simulation time 4936797733 ps
CPU time 3.12 seconds
Started Jun 30 05:06:42 PM PDT 24
Finished Jun 30 05:06:45 PM PDT 24
Peak memory 199196 kb
Host smart-348cf620-04e7-4eed-baed-696af637182e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771009866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.3771009866
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_perf.2188209377
Short name T245
Test name
Test status
Simulation time 17773898448 ps
CPU time 935.9 seconds
Started Jun 30 05:06:41 PM PDT 24
Finished Jun 30 05:22:17 PM PDT 24
Peak memory 200176 kb
Host smart-e74efb73-2432-4730-b21e-cdf14c679e55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2188209377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2188209377
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.2770663960
Short name T347
Test name
Test status
Simulation time 4291046947 ps
CPU time 3.83 seconds
Started Jun 30 05:06:43 PM PDT 24
Finished Jun 30 05:06:48 PM PDT 24
Peak memory 198448 kb
Host smart-6ba48d6d-1f37-40ac-ad6c-57daeaff2e7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2770663960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.2770663960
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.2374298066
Short name T699
Test name
Test status
Simulation time 51446385773 ps
CPU time 21.95 seconds
Started Jun 30 05:06:47 PM PDT 24
Finished Jun 30 05:07:10 PM PDT 24
Peak memory 199852 kb
Host smart-7c906cba-9a22-42e2-bbd2-7ea4e1078df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374298066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.2374298066
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.4118991531
Short name T480
Test name
Test status
Simulation time 4396434849 ps
CPU time 2.3 seconds
Started Jun 30 05:06:48 PM PDT 24
Finished Jun 30 05:06:52 PM PDT 24
Peak memory 196144 kb
Host smart-76887a86-590e-4208-b9cf-9f64dd48d826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118991531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.4118991531
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.1392178637
Short name T453
Test name
Test status
Simulation time 250794918 ps
CPU time 1.48 seconds
Started Jun 30 05:06:40 PM PDT 24
Finished Jun 30 05:06:42 PM PDT 24
Peak memory 198420 kb
Host smart-9cfee88b-2c5a-48f5-a887-847d31054eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392178637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1392178637
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.233884094
Short name T115
Test name
Test status
Simulation time 136460346958 ps
CPU time 704.36 seconds
Started Jun 30 05:06:48 PM PDT 24
Finished Jun 30 05:18:33 PM PDT 24
Peak memory 213896 kb
Host smart-34a0300e-ce32-4c72-9717-281024a20ea0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233884094 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.233884094
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3340094559
Short name T1028
Test name
Test status
Simulation time 1116154754 ps
CPU time 3.62 seconds
Started Jun 30 05:06:47 PM PDT 24
Finished Jun 30 05:06:51 PM PDT 24
Peak memory 199284 kb
Host smart-d53fb943-3c3e-44a9-92a5-b390291fa851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340094559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3340094559
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.3240190790
Short name T595
Test name
Test status
Simulation time 80124510381 ps
CPU time 12.57 seconds
Started Jun 30 05:06:41 PM PDT 24
Finished Jun 30 05:06:54 PM PDT 24
Peak memory 199824 kb
Host smart-71e6a593-afe9-498d-bafe-4436a7ca9f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240190790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.3240190790
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.1995667516
Short name T680
Test name
Test status
Simulation time 105530846660 ps
CPU time 166.31 seconds
Started Jun 30 05:10:40 PM PDT 24
Finished Jun 30 05:13:27 PM PDT 24
Peak memory 199836 kb
Host smart-1089c736-e8df-45e4-93fb-1a835a5932d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995667516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1995667516
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.1277952334
Short name T126
Test name
Test status
Simulation time 45818841447 ps
CPU time 340.13 seconds
Started Jun 30 05:10:41 PM PDT 24
Finished Jun 30 05:16:22 PM PDT 24
Peak memory 215680 kb
Host smart-34ec2736-4d9f-4a71-b3cd-922868fa6f60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277952334 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.1277952334
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2469552215
Short name T109
Test name
Test status
Simulation time 29364502865 ps
CPU time 105.07 seconds
Started Jun 30 05:10:41 PM PDT 24
Finished Jun 30 05:12:27 PM PDT 24
Peak memory 216432 kb
Host smart-01488cb0-1762-4059-b8d5-ad3106b344ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469552215 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2469552215
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3599145404
Short name T447
Test name
Test status
Simulation time 242917551946 ps
CPU time 270.38 seconds
Started Jun 30 05:10:41 PM PDT 24
Finished Jun 30 05:15:12 PM PDT 24
Peak memory 199892 kb
Host smart-25f851b7-7523-42c5-93bc-32452b61e324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599145404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3599145404
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.1525989921
Short name T119
Test name
Test status
Simulation time 41554501494 ps
CPU time 16.36 seconds
Started Jun 30 05:10:43 PM PDT 24
Finished Jun 30 05:10:59 PM PDT 24
Peak memory 198808 kb
Host smart-5a509a0c-6a51-4040-843a-0d61f5b06684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525989921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.1525989921
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.2207124609
Short name T5
Test name
Test status
Simulation time 25444631288 ps
CPU time 42.84 seconds
Started Jun 30 05:10:39 PM PDT 24
Finished Jun 30 05:11:22 PM PDT 24
Peak memory 199840 kb
Host smart-f09d5d75-1379-4d2c-be21-7b5efcb93295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207124609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2207124609
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1698524262
Short name T216
Test name
Test status
Simulation time 435577883388 ps
CPU time 1649.85 seconds
Started Jun 30 05:10:39 PM PDT 24
Finished Jun 30 05:38:09 PM PDT 24
Peak memory 224656 kb
Host smart-721d2c18-5e43-48c1-ae49-e2747a139264
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698524262 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1698524262
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.1527903143
Short name T389
Test name
Test status
Simulation time 108516612611 ps
CPU time 90.51 seconds
Started Jun 30 05:10:42 PM PDT 24
Finished Jun 30 05:12:13 PM PDT 24
Peak memory 199828 kb
Host smart-1baf5fa6-cee1-40e1-8bf6-299435cd2357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527903143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1527903143
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.964092658
Short name T625
Test name
Test status
Simulation time 39834663473 ps
CPU time 172.11 seconds
Started Jun 30 05:10:41 PM PDT 24
Finished Jun 30 05:13:33 PM PDT 24
Peak memory 216404 kb
Host smart-4e595ee7-2af1-400e-9b4c-f85163972035
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964092658 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.964092658
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.2024453499
Short name T989
Test name
Test status
Simulation time 42474092189 ps
CPU time 31.13 seconds
Started Jun 30 05:10:40 PM PDT 24
Finished Jun 30 05:11:12 PM PDT 24
Peak memory 199852 kb
Host smart-06dbe13f-3005-4ebb-96fd-467d223cdc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024453499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2024453499
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1319329020
Short name T362
Test name
Test status
Simulation time 133625969714 ps
CPU time 916.83 seconds
Started Jun 30 05:10:48 PM PDT 24
Finished Jun 30 05:26:05 PM PDT 24
Peak memory 215060 kb
Host smart-a660520e-cf2e-4de5-acb0-30945d1389a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319329020 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1319329020
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.740689336
Short name T120
Test name
Test status
Simulation time 28172503812 ps
CPU time 16.12 seconds
Started Jun 30 05:10:49 PM PDT 24
Finished Jun 30 05:11:06 PM PDT 24
Peak memory 199628 kb
Host smart-1cdcfbd8-3821-4af4-ac76-76ca2f0b4621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740689336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.740689336
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.3847788938
Short name T727
Test name
Test status
Simulation time 6515527210 ps
CPU time 9.73 seconds
Started Jun 30 05:10:49 PM PDT 24
Finished Jun 30 05:10:59 PM PDT 24
Peak memory 199640 kb
Host smart-7a0b6bdd-d275-4a0a-9f7b-d614d4e7d980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847788938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3847788938
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.2560664306
Short name T101
Test name
Test status
Simulation time 84285124538 ps
CPU time 70.43 seconds
Started Jun 30 05:10:50 PM PDT 24
Finished Jun 30 05:12:01 PM PDT 24
Peak memory 199928 kb
Host smart-1784df46-7cfa-44f1-9f2d-0ce11d60fc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560664306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2560664306
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.3256922109
Short name T1031
Test name
Test status
Simulation time 12178538 ps
CPU time 0.57 seconds
Started Jun 30 05:06:53 PM PDT 24
Finished Jun 30 05:06:54 PM PDT 24
Peak memory 195180 kb
Host smart-5467ad04-d226-46e0-9d5f-1c561a454fa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256922109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.3256922109
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3302779827
Short name T1011
Test name
Test status
Simulation time 104493991746 ps
CPU time 187.41 seconds
Started Jun 30 05:06:43 PM PDT 24
Finished Jun 30 05:09:51 PM PDT 24
Peak memory 199800 kb
Host smart-126e9d74-1853-4252-968e-6943a0347845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302779827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3302779827
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.2312850505
Short name T519
Test name
Test status
Simulation time 12683664364 ps
CPU time 18.86 seconds
Started Jun 30 05:06:43 PM PDT 24
Finished Jun 30 05:07:02 PM PDT 24
Peak memory 199836 kb
Host smart-d355863e-f357-413c-b01b-63aae6e15502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312850505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2312850505
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3269423999
Short name T257
Test name
Test status
Simulation time 137704419134 ps
CPU time 49.36 seconds
Started Jun 30 05:06:47 PM PDT 24
Finished Jun 30 05:07:38 PM PDT 24
Peak memory 199876 kb
Host smart-64535f76-75f9-4f8e-82fc-f1c8f8756684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269423999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3269423999
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3685548710
Short name T766
Test name
Test status
Simulation time 66051890397 ps
CPU time 23.96 seconds
Started Jun 30 05:06:51 PM PDT 24
Finished Jun 30 05:07:16 PM PDT 24
Peak memory 199820 kb
Host smart-d1eac3da-041b-4f94-9f53-0197fd0e1210
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685548710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3685548710
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.1650723114
Short name T981
Test name
Test status
Simulation time 176479833696 ps
CPU time 477.13 seconds
Started Jun 30 05:06:53 PM PDT 24
Finished Jun 30 05:14:51 PM PDT 24
Peak memory 199796 kb
Host smart-c475ef86-15fe-479a-92a7-1adf2038012e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1650723114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.1650723114
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.845101049
Short name T452
Test name
Test status
Simulation time 2775731328 ps
CPU time 5.67 seconds
Started Jun 30 05:06:53 PM PDT 24
Finished Jun 30 05:06:59 PM PDT 24
Peak memory 197980 kb
Host smart-d25e587a-9fdf-4d71-9784-19a5eab492b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845101049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.845101049
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_perf.1252137874
Short name T685
Test name
Test status
Simulation time 27003517238 ps
CPU time 340.55 seconds
Started Jun 30 05:06:54 PM PDT 24
Finished Jun 30 05:12:35 PM PDT 24
Peak memory 199904 kb
Host smart-ca3228cb-025a-40a9-a141-07b9f37746d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1252137874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.1252137874
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.3415757168
Short name T475
Test name
Test status
Simulation time 3887715794 ps
CPU time 24.49 seconds
Started Jun 30 05:06:48 PM PDT 24
Finished Jun 30 05:07:14 PM PDT 24
Peak memory 198868 kb
Host smart-17a1db88-da13-40a8-872f-3aa19aad0b74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3415757168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3415757168
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.2108743393
Short name T430
Test name
Test status
Simulation time 48444544917 ps
CPU time 22.19 seconds
Started Jun 30 05:06:52 PM PDT 24
Finished Jun 30 05:07:15 PM PDT 24
Peak memory 199840 kb
Host smart-9d8e2fc7-0edf-4bb7-a82d-c2eb6ab031af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108743393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2108743393
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.2798829720
Short name T10
Test name
Test status
Simulation time 4893843500 ps
CPU time 2.26 seconds
Started Jun 30 05:06:52 PM PDT 24
Finished Jun 30 05:06:55 PM PDT 24
Peak memory 196156 kb
Host smart-e914a107-65ea-4c30-9ed8-7eeb91569a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798829720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2798829720
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.3191852453
Short name T295
Test name
Test status
Simulation time 5805254820 ps
CPU time 17.81 seconds
Started Jun 30 05:06:43 PM PDT 24
Finished Jun 30 05:07:01 PM PDT 24
Peak memory 199892 kb
Host smart-a5e8a301-b9ed-43ce-aa4d-27ddc7259092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191852453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3191852453
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.4078137433
Short name T121
Test name
Test status
Simulation time 271752459818 ps
CPU time 757.5 seconds
Started Jun 30 05:06:52 PM PDT 24
Finished Jun 30 05:19:30 PM PDT 24
Peak memory 199876 kb
Host smart-d22d2c38-4f02-4ac3-9d9f-51d6feb53a02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078137433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.4078137433
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.1283473770
Short name T1045
Test name
Test status
Simulation time 68697960165 ps
CPU time 143.59 seconds
Started Jun 30 05:06:51 PM PDT 24
Finished Jun 30 05:09:16 PM PDT 24
Peak memory 216244 kb
Host smart-c5a7246f-6375-4915-8ccf-5352c27be4b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283473770 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.1283473770
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.1491772270
Short name T290
Test name
Test status
Simulation time 10043339697 ps
CPU time 6.71 seconds
Started Jun 30 05:06:53 PM PDT 24
Finished Jun 30 05:07:00 PM PDT 24
Peak memory 199888 kb
Host smart-c91ce714-90e2-4fbe-ba31-268a0b3cdce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491772270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.1491772270
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.997308248
Short name T824
Test name
Test status
Simulation time 55498267050 ps
CPU time 117.63 seconds
Started Jun 30 05:06:41 PM PDT 24
Finished Jun 30 05:08:39 PM PDT 24
Peak memory 199852 kb
Host smart-3b265d55-b959-42c7-b69b-afbb2b17d038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997308248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.997308248
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.959840931
Short name T823
Test name
Test status
Simulation time 128353091837 ps
CPU time 253.77 seconds
Started Jun 30 05:10:49 PM PDT 24
Finished Jun 30 05:15:04 PM PDT 24
Peak memory 199924 kb
Host smart-6d895437-9801-40f3-ab3b-a284781e6292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959840931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.959840931
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.2657095015
Short name T959
Test name
Test status
Simulation time 31124426727 ps
CPU time 258.66 seconds
Started Jun 30 05:10:48 PM PDT 24
Finished Jun 30 05:15:08 PM PDT 24
Peak memory 208296 kb
Host smart-388b501a-d868-44a8-97a4-fd2f87217b9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657095015 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.2657095015
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.349533571
Short name T808
Test name
Test status
Simulation time 145018685853 ps
CPU time 223.93 seconds
Started Jun 30 05:10:48 PM PDT 24
Finished Jun 30 05:14:33 PM PDT 24
Peak memory 199836 kb
Host smart-6a6b70e3-a728-4655-b4b3-cd89930c46c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349533571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.349533571
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.4227737025
Short name T386
Test name
Test status
Simulation time 8684084404 ps
CPU time 113.9 seconds
Started Jun 30 05:10:50 PM PDT 24
Finished Jun 30 05:12:44 PM PDT 24
Peak memory 216468 kb
Host smart-c9e0da06-0679-4c11-a628-2784faeda623
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227737025 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.4227737025
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.217460291
Short name T628
Test name
Test status
Simulation time 284886996665 ps
CPU time 35.48 seconds
Started Jun 30 05:10:47 PM PDT 24
Finished Jun 30 05:11:23 PM PDT 24
Peak memory 199904 kb
Host smart-dadeb4f5-70eb-45c5-aa2a-5805fa97f5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217460291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.217460291
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3421596721
Short name T30
Test name
Test status
Simulation time 27891224452 ps
CPU time 48.64 seconds
Started Jun 30 05:10:49 PM PDT 24
Finished Jun 30 05:11:38 PM PDT 24
Peak memory 199920 kb
Host smart-42248fc9-9ff9-4343-9a3c-f6be50e978b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421596721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3421596721
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.2850549682
Short name T807
Test name
Test status
Simulation time 124642258155 ps
CPU time 41.55 seconds
Started Jun 30 05:10:47 PM PDT 24
Finished Jun 30 05:11:30 PM PDT 24
Peak memory 199828 kb
Host smart-d4bd767b-0ba7-4c20-9001-8ed05ef8ca26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850549682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2850549682
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2728343148
Short name T976
Test name
Test status
Simulation time 41047312743 ps
CPU time 298.32 seconds
Started Jun 30 05:10:48 PM PDT 24
Finished Jun 30 05:15:47 PM PDT 24
Peak memory 216120 kb
Host smart-5b88ce5a-600a-4863-af7c-1b68b5757ce7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728343148 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2728343148
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.2449000037
Short name T183
Test name
Test status
Simulation time 130814892677 ps
CPU time 80.62 seconds
Started Jun 30 05:10:47 PM PDT 24
Finished Jun 30 05:12:09 PM PDT 24
Peak memory 199864 kb
Host smart-8a1ae6c7-b7d9-48da-8b7e-2e99c3f3a976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449000037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2449000037
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.436676664
Short name T176
Test name
Test status
Simulation time 104760192186 ps
CPU time 1670.9 seconds
Started Jun 30 05:10:51 PM PDT 24
Finished Jun 30 05:38:43 PM PDT 24
Peak memory 226632 kb
Host smart-8910a2d0-3c78-4aee-9ec3-c8a0df1e2dc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436676664 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.436676664
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.1465070483
Short name T372
Test name
Test status
Simulation time 49979664896 ps
CPU time 909.25 seconds
Started Jun 30 05:10:49 PM PDT 24
Finished Jun 30 05:25:59 PM PDT 24
Peak memory 213948 kb
Host smart-66e5adf7-cf79-498c-8344-7aef12b91190
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465070483 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1465070483
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.1425425890
Short name T130
Test name
Test status
Simulation time 23774439467 ps
CPU time 50.25 seconds
Started Jun 30 05:10:47 PM PDT 24
Finished Jun 30 05:11:38 PM PDT 24
Peak memory 199916 kb
Host smart-5ba994b9-272e-4ebd-be0c-d5bb5ad7a886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425425890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1425425890
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.3198491910
Short name T473
Test name
Test status
Simulation time 180329911256 ps
CPU time 466.74 seconds
Started Jun 30 05:10:48 PM PDT 24
Finished Jun 30 05:18:36 PM PDT 24
Peak memory 216372 kb
Host smart-dcc36cb8-216d-4b09-8a1f-895fa8957ab8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198491910 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.3198491910
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.593185613
Short name T1086
Test name
Test status
Simulation time 51534268017 ps
CPU time 39.1 seconds
Started Jun 30 05:10:51 PM PDT 24
Finished Jun 30 05:11:31 PM PDT 24
Peak memory 199312 kb
Host smart-2cbab511-7ef2-456b-b708-23bf5ef8f412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593185613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.593185613
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.2678446501
Short name T818
Test name
Test status
Simulation time 68876373935 ps
CPU time 281.64 seconds
Started Jun 30 05:10:47 PM PDT 24
Finished Jun 30 05:15:29 PM PDT 24
Peak memory 216520 kb
Host smart-24ebcdcc-001b-46fc-af42-b93b6903b61b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678446501 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.2678446501
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.2033444800
Short name T457
Test name
Test status
Simulation time 38187695 ps
CPU time 0.57 seconds
Started Jun 30 05:06:51 PM PDT 24
Finished Jun 30 05:06:52 PM PDT 24
Peak memory 195516 kb
Host smart-723ba77b-99ff-4efe-912f-29fcaed704f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033444800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2033444800
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.1836106074
Short name T585
Test name
Test status
Simulation time 55454947221 ps
CPU time 23.7 seconds
Started Jun 30 05:06:52 PM PDT 24
Finished Jun 30 05:07:17 PM PDT 24
Peak memory 199904 kb
Host smart-0bf20f79-c0c4-41f7-adcc-c0be4d7cc008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836106074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.1836106074
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.458146652
Short name T413
Test name
Test status
Simulation time 17084173857 ps
CPU time 13.89 seconds
Started Jun 30 05:06:54 PM PDT 24
Finished Jun 30 05:07:08 PM PDT 24
Peak memory 199864 kb
Host smart-a0860d4d-a3db-4213-a202-b13321132043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458146652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.458146652
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_intr.1084430439
Short name T305
Test name
Test status
Simulation time 10151664994 ps
CPU time 4.4 seconds
Started Jun 30 05:06:54 PM PDT 24
Finished Jun 30 05:06:59 PM PDT 24
Peak memory 197024 kb
Host smart-f51d0325-cc45-49d5-a10b-764f21a19db3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084430439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.1084430439
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.1233476074
Short name T752
Test name
Test status
Simulation time 64566012162 ps
CPU time 96.88 seconds
Started Jun 30 05:06:52 PM PDT 24
Finished Jun 30 05:08:29 PM PDT 24
Peak memory 199852 kb
Host smart-a8fd6165-bec5-42c7-85e9-41657e67656c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1233476074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1233476074
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.4241123183
Short name T500
Test name
Test status
Simulation time 3475826638 ps
CPU time 6.77 seconds
Started Jun 30 05:06:53 PM PDT 24
Finished Jun 30 05:07:01 PM PDT 24
Peak memory 199420 kb
Host smart-b1d357f1-5a9c-4895-a04e-601a0587ffae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241123183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.4241123183
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_perf.194649600
Short name T243
Test name
Test status
Simulation time 16450105654 ps
CPU time 257.97 seconds
Started Jun 30 05:06:52 PM PDT 24
Finished Jun 30 05:11:11 PM PDT 24
Peak memory 199868 kb
Host smart-28448ae9-5441-413e-903c-01f3e88463e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=194649600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.194649600
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.3865544562
Short name T998
Test name
Test status
Simulation time 4647953028 ps
CPU time 37.38 seconds
Started Jun 30 05:06:56 PM PDT 24
Finished Jun 30 05:07:33 PM PDT 24
Peak memory 199112 kb
Host smart-fa0b021d-e8b6-4552-b44e-3d6329fd0857
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3865544562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.3865544562
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.298658531
Short name T536
Test name
Test status
Simulation time 219146624295 ps
CPU time 318.9 seconds
Started Jun 30 05:06:52 PM PDT 24
Finished Jun 30 05:12:11 PM PDT 24
Peak memory 200224 kb
Host smart-e9e23ef3-e8e2-4289-9865-d00e0bd84fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298658531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.298658531
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.2547475699
Short name T614
Test name
Test status
Simulation time 3275746430 ps
CPU time 4.85 seconds
Started Jun 30 05:06:52 PM PDT 24
Finished Jun 30 05:06:57 PM PDT 24
Peak memory 195764 kb
Host smart-70e749ae-cb90-477d-a538-592b675924bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547475699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2547475699
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.857491334
Short name T1068
Test name
Test status
Simulation time 865981428 ps
CPU time 1.8 seconds
Started Jun 30 05:06:53 PM PDT 24
Finished Jun 30 05:06:55 PM PDT 24
Peak memory 199468 kb
Host smart-8a925544-0e2f-4c5d-8523-65bc56912701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857491334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.857491334
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.3092486399
Short name T166
Test name
Test status
Simulation time 515411506754 ps
CPU time 506.93 seconds
Started Jun 30 05:06:51 PM PDT 24
Finished Jun 30 05:15:19 PM PDT 24
Peak memory 199936 kb
Host smart-60faff9e-2ead-4a78-9159-9ad38f28c00d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092486399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3092486399
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.1858064787
Short name T751
Test name
Test status
Simulation time 136908962673 ps
CPU time 1703.93 seconds
Started Jun 30 05:06:51 PM PDT 24
Finished Jun 30 05:35:16 PM PDT 24
Peak memory 228000 kb
Host smart-d2bd07a8-9ccf-478b-94b4-58f8e5deaae2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858064787 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.1858064787
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.4039026535
Short name T39
Test name
Test status
Simulation time 823828435 ps
CPU time 3.68 seconds
Started Jun 30 05:06:54 PM PDT 24
Finished Jun 30 05:06:58 PM PDT 24
Peak memory 198628 kb
Host smart-c9d22021-fce7-4bfc-9e57-9cd4635d4ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039026535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.4039026535
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.599901836
Short name T103
Test name
Test status
Simulation time 60116954989 ps
CPU time 96.67 seconds
Started Jun 30 05:06:53 PM PDT 24
Finished Jun 30 05:08:31 PM PDT 24
Peak memory 199912 kb
Host smart-cad56765-557e-4c87-bc0e-9ed823274d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599901836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.599901836
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.1421883701
Short name T116
Test name
Test status
Simulation time 136229983774 ps
CPU time 407.91 seconds
Started Jun 30 05:10:48 PM PDT 24
Finished Jun 30 05:17:37 PM PDT 24
Peak memory 216464 kb
Host smart-6df50580-dfe2-434b-a30a-3528b85f1a87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421883701 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.1421883701
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.1116798595
Short name T771
Test name
Test status
Simulation time 130437859466 ps
CPU time 71.87 seconds
Started Jun 30 05:10:59 PM PDT 24
Finished Jun 30 05:12:11 PM PDT 24
Peak memory 199856 kb
Host smart-71a21973-d89b-45a0-847d-b8ee8d48e14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116798595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.1116798595
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.3604411559
Short name T544
Test name
Test status
Simulation time 92461876535 ps
CPU time 1055.97 seconds
Started Jun 30 05:10:58 PM PDT 24
Finished Jun 30 05:28:34 PM PDT 24
Peak memory 224596 kb
Host smart-37f324de-cd88-4a29-a7c9-f2b43d1cf6ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604411559 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.3604411559
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.725182079
Short name T719
Test name
Test status
Simulation time 76726475204 ps
CPU time 35.99 seconds
Started Jun 30 05:10:57 PM PDT 24
Finished Jun 30 05:11:33 PM PDT 24
Peak memory 199844 kb
Host smart-cb9439aa-5fc1-4f1b-aeb5-d15ed740094f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725182079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.725182079
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3225735201
Short name T841
Test name
Test status
Simulation time 8608558471 ps
CPU time 16.55 seconds
Started Jun 30 05:11:00 PM PDT 24
Finished Jun 30 05:11:17 PM PDT 24
Peak memory 199780 kb
Host smart-d0e6f611-b660-4c2f-be8d-2515a5ccadba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225735201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3225735201
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.473243172
Short name T654
Test name
Test status
Simulation time 19628933275 ps
CPU time 31.17 seconds
Started Jun 30 05:10:57 PM PDT 24
Finished Jun 30 05:11:29 PM PDT 24
Peak memory 199768 kb
Host smart-51e9d9ff-dfb8-48d5-b618-24bca507b894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473243172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.473243172
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3444197878
Short name T184
Test name
Test status
Simulation time 52479099974 ps
CPU time 79.58 seconds
Started Jun 30 05:10:58 PM PDT 24
Finished Jun 30 05:12:18 PM PDT 24
Peak memory 199756 kb
Host smart-7be6d77b-ab8d-4b49-853d-d1c7d32fd7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444197878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3444197878
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.2001955220
Short name T114
Test name
Test status
Simulation time 45756923619 ps
CPU time 195.27 seconds
Started Jun 30 05:10:56 PM PDT 24
Finished Jun 30 05:14:12 PM PDT 24
Peak memory 215788 kb
Host smart-93929444-187b-456b-9e11-65ef98d365c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001955220 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.2001955220
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3716275440
Short name T931
Test name
Test status
Simulation time 209998594089 ps
CPU time 86.66 seconds
Started Jun 30 05:10:58 PM PDT 24
Finished Jun 30 05:12:25 PM PDT 24
Peak memory 199920 kb
Host smart-f02bf2a2-4d4c-4560-8c23-7fa796621cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716275440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3716275440
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.931196609
Short name T645
Test name
Test status
Simulation time 131766961559 ps
CPU time 923.56 seconds
Started Jun 30 05:11:01 PM PDT 24
Finished Jun 30 05:26:25 PM PDT 24
Peak memory 216332 kb
Host smart-96c508e1-72dc-405f-a0f0-d43a68f339ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931196609 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.931196609
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2908200065
Short name T459
Test name
Test status
Simulation time 80841177064 ps
CPU time 41.46 seconds
Started Jun 30 05:10:59 PM PDT 24
Finished Jun 30 05:11:41 PM PDT 24
Peak memory 199852 kb
Host smart-b5c3e472-9a64-4a9e-949b-bbae0517565f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908200065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2908200065
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.2751162262
Short name T368
Test name
Test status
Simulation time 20823334001 ps
CPU time 262.4 seconds
Started Jun 30 05:10:57 PM PDT 24
Finished Jun 30 05:15:20 PM PDT 24
Peak memory 209360 kb
Host smart-e7ed2952-0b71-486f-9264-036f794e6da9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751162262 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.2751162262
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.4102261890
Short name T555
Test name
Test status
Simulation time 20519935015 ps
CPU time 40.49 seconds
Started Jun 30 05:10:57 PM PDT 24
Finished Jun 30 05:11:38 PM PDT 24
Peak memory 199904 kb
Host smart-e18eef46-a0e8-47d6-bf9b-a7411eb2842c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102261890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.4102261890
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1778120417
Short name T952
Test name
Test status
Simulation time 57133779152 ps
CPU time 651.96 seconds
Started Jun 30 05:10:57 PM PDT 24
Finished Jun 30 05:21:49 PM PDT 24
Peak memory 216448 kb
Host smart-2fc03e41-c117-4e6c-a354-51e8ebe8c4b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778120417 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1778120417
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.94863486
Short name T158
Test name
Test status
Simulation time 78379930207 ps
CPU time 214.27 seconds
Started Jun 30 05:10:57 PM PDT 24
Finished Jun 30 05:14:32 PM PDT 24
Peak memory 199868 kb
Host smart-cf0d6a96-7fb2-4668-8c17-fb1e71922686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94863486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.94863486
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.3340211473
Short name T36
Test name
Test status
Simulation time 59753724966 ps
CPU time 186.4 seconds
Started Jun 30 05:10:58 PM PDT 24
Finished Jun 30 05:14:05 PM PDT 24
Peak memory 216028 kb
Host smart-85600798-0f2c-4514-975c-8e709183ca0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340211473 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3340211473
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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