Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	111738	1			T1	2		T2	1503		T3	2
all_values[1]	111738	1			T1	2		T2	1503		T3	2
all_values[2]	111738	1			T1	2		T2	1503		T3	2
all_values[3]	111738	1			T1	2		T2	1503		T3	2
all_values[4]	111738	1			T1	2		T2	1503		T3	2
all_values[5]	111738	1			T1	2		T2	1503		T3	2
all_values[6]	111738	1			T1	2		T2	1503		T3	2
all_values[7]	111738	1			T1	2		T2	1503		T3	2
all_values[8]	111738	1			T1	2		T2	1503		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

505118

1

T1

18

T2

6915

T3

18

auto[1]

500524

1

T2

6612

T4

280

T5

12

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

926482

1

T1

13

T2

11929

T3

13

auto[1]

79160

1

T1

5

T2

1598

T3

5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	37150	1			T2	524		T4	1		T9	39
all_values[0]	auto[0]	auto[1]	20777	1			T1	2		T2	657		T3	2
all_values[0]	auto[1]	auto[0]	34671	1			T2	161		T9	70		T16	24
all_values[0]	auto[1]	auto[1]	19140	1			T2	161		T4	21		T5	3
all_values[1]	auto[0]	auto[0]	50936	1			T1	2		T2	234		T3	2
all_values[1]	auto[0]	auto[1]	1477	1			T16	3		T132	2		T121	2
all_values[1]	auto[1]	auto[0]	57628	1			T2	1256		T4	21		T6	7
all_values[1]	auto[1]	auto[1]	1697	1			T2	13		T16	2		T36	3
all_values[2]	auto[0]	auto[0]	51254	1			T1	1		T2	332		T3	1
all_values[2]	auto[0]	auto[1]	2465	1			T1	1		T2	1		T3	1
all_values[2]	auto[1]	auto[0]	55902	1			T2	1166		T6	2		T8	1
all_values[2]	auto[1]	auto[1]	2117	1			T2	4		T6	4		T9	3
all_values[3]	auto[0]	auto[0]	57415	1			T1	2		T2	1033		T3	2
all_values[3]	auto[0]	auto[1]	259	1			T16	5		T12	2		T17	1
all_values[3]	auto[1]	auto[0]	53812	1			T2	470		T4	48		T6	3
all_values[3]	auto[1]	auto[1]	252	1			T16	4		T13	1		T15	1
all_values[4]	auto[0]	auto[0]	58016	1			T1	2		T2	656		T3	2
all_values[4]	auto[0]	auto[1]	282	1			T16	1		T17	1		T20	1
all_values[4]	auto[1]	auto[0]	53085	1			T2	847		T4	46		T5	3
all_values[4]	auto[1]	auto[1]	355	1			T16	8		T17	2		T20	1
all_values[5]	auto[0]	auto[0]	55388	1			T1	2		T2	744		T3	2
all_values[5]	auto[0]	auto[1]	144	1			T16	6		T20	2		T37	2
all_values[5]	auto[1]	auto[0]	56043	1			T2	759		T4	48		T5	3
all_values[5]	auto[1]	auto[1]	163	1			T16	3		T17	2		T37	2
all_values[6]	auto[0]	auto[0]	57820	1			T1	2		T2	1327		T3	2
all_values[6]	auto[0]	auto[1]	138	1			T16	2		T17	1		T20	2
all_values[6]	auto[1]	auto[0]	53605	1			T2	176		T4	21		T6	1
all_values[6]	auto[1]	auto[1]	175	1			T16	4		T17	4		T20	1
all_values[7]	auto[0]	auto[0]	55904	1			T1	2		T2	531		T3	2
all_values[7]	auto[0]	auto[1]	269	1			T16	3		T17	1		T37	4
all_values[7]	auto[1]	auto[0]	55231	1			T2	972		T4	27		T5	3
all_values[7]	auto[1]	auto[1]	334	1			T16	6		T21	1		T17	5
all_values[8]	auto[0]	auto[0]	40477	1			T2	220		T4	1		T9	78
all_values[8]	auto[0]	auto[1]	14947	1			T1	2		T2	656		T3	2
all_values[8]	auto[1]	auto[0]	42145	1			T2	521		T6	2		T9	31
all_values[8]	auto[1]	auto[1]	14169	1			T2	106		T4	48		T6	5