Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2245

1

T1

1

T2

1

T3

1

auto[UartRx]

2245

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4084	1			T1	2		T2	2		T3	2
values[1]	28	1			T41	1		T124	1		T310	2
values[2]	36	1			T40	1		T108	2		T283	2
values[3]	40	1			T15	1		T37	2		T41	2
values[4]	43	1			T16	1		T38	1		T39	4
values[5]	26	1			T16	1		T29	1		T124	2
values[6]	36	1			T16	2		T29	1		T20	1
values[7]	44	1			T29	1		T20	1		T15	1
values[8]	32	1			T17	1		T20	1		T15	1
values[9]	46	1			T16	1		T17	1		T15	1
values[10]	51	1			T16	3		T29	2		T17	2

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2104	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	5	1			T311	1		T312	1		T313	2
auto[UartTx]	values[2]	14	1			T108	1		T99	2		T310	1
auto[UartTx]	values[3]	16	1			T15	1		T37	1		T41	1
auto[UartTx]	values[4]	11	1			T38	1		T39	2		T314	1
auto[UartTx]	values[5]	10	1			T16	1		T29	1		T124	1
auto[UartTx]	values[6]	13	1			T39	1		T315	1		T159	1
auto[UartTx]	values[7]	15	1			T38	1		T283	1		T230	1
auto[UartTx]	values[8]	11	1			T37	1		T315	1		T316	1
auto[UartTx]	values[9]	16	1			T16	1		T17	1		T15	1
auto[UartTx]	values[10]	19	1			T29	1		T15	1		T283	1
auto[UartRx]	values[0]	1980	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	23	1			T41	1		T124	1		T310	2
auto[UartRx]	values[2]	22	1			T40	1		T108	1		T283	2
auto[UartRx]	values[3]	24	1			T37	1		T41	1		T108	1
auto[UartRx]	values[4]	32	1			T16	1		T39	2		T40	1
auto[UartRx]	values[5]	16	1			T124	1		T316	1		T314	1
auto[UartRx]	values[6]	23	1			T16	2		T29	1		T20	1
auto[UartRx]	values[7]	29	1			T29	1		T20	1		T15	1
auto[UartRx]	values[8]	21	1			T17	1		T20	1		T15	1
auto[UartRx]	values[9]	30	1			T37	1		T38	1		T41	1
auto[UartRx]	values[10]	32	1			T16	3		T29	1		T17	2