Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2027	1			T3	1		T6	1		T7	1
auto[BaudRate115200]	1592	1			T1	1		T2	2		T4	2
auto[BaudRate230400]	1597	1			T2	2		T4	1		T5	2
auto[BaudRate128Kbps]	1678	1			T2	1		T5	1		T6	1
auto[BaudRate256Kbps]	1872	1			T2	1		T5	1		T6	1
auto[BaudRate1Mbps]	1526	1			T1	1		T2	1		T3	1
auto[BaudRate1p5Mbps]	1113	1			T8	3		T10	15		T16	5

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1297	1			T1	2		T6	7		T28	18
freqs[25]	1071	1			T21	18		T24	2		T139	58
freqs[48]	609	1			T10	36		T135	5		T280	2
freqs[50]	340	1			T132	9		T98	7		T284	5
freqs[100]	1070	1			T22	2		T19	18		T23	2

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	186	1			T6	1		T28	3		T17	4
auto[BaudRate9600]	freqs[25]	141	1			T21	2		T139	7		T261	3
auto[BaudRate9600]	freqs[48]	75	1			T10	6		T54	1		T67	2
auto[BaudRate9600]	freqs[50]	58	1			T132	2		T98	2		T133	1
auto[BaudRate9600]	freqs[100]	205	1			T19	18		T55	1		T71	1
auto[BaudRate115200]	freqs[24]	201	1			T1	1		T6	1		T28	6
auto[BaudRate115200]	freqs[25]	165	1			T21	6		T139	9		T261	1
auto[BaudRate115200]	freqs[48]	60	1			T10	6		T135	2		T54	1
auto[BaudRate115200]	freqs[50]	37	1			T133	1		T262	2		T142	2
auto[BaudRate115200]	freqs[100]	145	1			T22	1		T20	6		T297	2
auto[BaudRate230400]	freqs[24]	166	1			T29	3		T13	2		T48	1
auto[BaudRate230400]	freqs[25]	157	1			T21	1		T24	1		T139	7
auto[BaudRate230400]	freqs[48]	84	1			T10	3		T135	2		T280	2
auto[BaudRate230400]	freqs[50]	38	1			T132	1		T98	1		T133	1
auto[BaudRate230400]	freqs[100]	118	1			T20	3		T50	2		T55	1
auto[BaudRate128Kbps]	freqs[24]	222	1			T6	1		T28	6		T29	6
auto[BaudRate128Kbps]	freqs[25]	174	1			T21	4		T24	1		T139	18
auto[BaudRate128Kbps]	freqs[48]	88	1			T67	1		T37	6		T153	2
auto[BaudRate128Kbps]	freqs[50]	44	1			T132	3		T98	1		T133	2
auto[BaudRate128Kbps]	freqs[100]	132	1			T23	2		T20	5		T68	1
auto[BaudRate256Kbps]	freqs[24]	202	1			T6	1		T29	2		T17	3
auto[BaudRate256Kbps]	freqs[25]	168	1			T21	2		T139	7		T261	1
auto[BaudRate256Kbps]	freqs[48]	112	1			T10	3		T135	1		T54	4
auto[BaudRate256Kbps]	freqs[50]	60	1			T132	1		T98	1		T284	2
auto[BaudRate256Kbps]	freqs[100]	168	1			T22	1		T20	4		T260	2
auto[BaudRate1Mbps]	freqs[24]	196	1			T1	1		T6	3		T28	3
auto[BaudRate1Mbps]	freqs[25]	183	1			T21	1		T139	10		T261	1
auto[BaudRate1Mbps]	freqs[48]	76	1			T10	3		T54	1		T37	10
auto[BaudRate1Mbps]	freqs[50]	61	1			T98	1		T284	2		T133	3
auto[BaudRate1Mbps]	freqs[100]	150	1			T20	4		T50	1		T68	1
auto[BaudRate1p5Mbps]	freqs[25]	83	1			T21	2		T109	6		T317	2
auto[BaudRate1p5Mbps]	freqs[48]	114	1			T10	15		T54	3		T37	16
auto[BaudRate1p5Mbps]	freqs[50]	42	1			T132	2		T98	1		T284	1
auto[BaudRate1p5Mbps]	freqs[100]	152	1			T20	4		T50	3		T260	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded