Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.91	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	12	118	90.77

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	12	118	90.77	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	31565867	1			T2	640639		T4	33		T5	12
all_levels[1]	186269	1			T2	162		T9	67		T16	25
all_levels[2]	2304	1			T6	4		T9	26		T43	1
all_levels[3]	957	1			T9	11		T16	1		T45	2
all_levels[4]	680	1			T9	9		T16	6		T45	2
all_levels[5]	544	1			T9	12		T131	3		T119	2
all_levels[6]	395	1			T9	3		T120	1		T132	3
all_levels[7]	323	1			T9	1		T45	1		T120	2
all_levels[8]	258	1			T119	1		T17	1		T49	2
all_levels[9]	255	1			T16	2		T45	1		T131	1
all_levels[10]	203	1			T16	2		T119	2		T132	1
all_levels[11]	179	1			T21	1		T132	3		T20	1
all_levels[12]	166	1			T21	1		T13	3		T49	1
all_levels[13]	144	1			T45	1		T132	1		T50	1
all_levels[14]	118	1			T120	2		T132	1		T15	1
all_levels[15]	119	1			T121	1		T52	1		T133	1
all_levels[16]	113	1			T45	1		T120	1		T20	1
all_levels[17]	108	1			T121	2		T69	1		T134	1
all_levels[18]	103	1			T21	2		T20	1		T15	1
all_levels[19]	96	1			T43	1		T45	2		T14	1
all_levels[20]	67	1			T135	2		T20	2		T15	1
all_levels[21]	73	1			T9	1		T122	1		T136	3
all_levels[22]	59	1			T9	1		T137	2		T138	1
all_levels[23]	54	1			T9	1		T36	1		T132	1
all_levels[24]	48	1			T139	1		T37	1		T140	1
all_levels[25]	53	1			T131	1		T70	1		T141	1
all_levels[26]	50	1			T132	1		T134	1		T141	1
all_levels[27]	34	1			T16	1		T37	1		T26	1
all_levels[28]	39	1			T13	1		T140	1		T142	1
all_levels[29]	33	1			T131	1		T132	2		T134	1
all_levels[30]	41	1			T50	2		T15	2		T70	1
all_levels[31]	21	1			T143	1		T144	3		T145	1
all_levels[32]	30	1			T15	1		T146	4		T143	1
all_levels[33]	23	1			T131	1		T54	2		T128	1
all_levels[34]	25	1			T131	1		T121	1		T26	1
all_levels[35]	22	1			T134	2		T141	1		T147	2
all_levels[36]	34	1			T131	1		T50	1		T128	1
all_levels[37]	33	1			T131	2		T15	1		T134	1
all_levels[38]	22	1			T54	1		T148	1		T149	1
all_levels[39]	20	1			T17	1		T54	1		T133	1
all_levels[40]	23	1			T150	1		T151	1		T152	2
all_levels[41]	12	1			T21	1		T54	1		T125	1
all_levels[42]	22	1			T54	2		T15	1		T108	2
all_levels[43]	17	1			T131	1		T134	1		T153	1
all_levels[44]	14	1			T15	2		T154	1		T155	1
all_levels[45]	13	1			T69	1		T156	1		T157	1
all_levels[46]	15	1			T121	1		T158	1		T159	1
all_levels[47]	7	1			T21	1		T142	1		T160	1
all_levels[48]	16	1			T161	1		T162	1		T163	1
all_levels[49]	15	1			T149	1		T164	2		T165	3
all_levels[50]	13	1			T121	1		T126	1		T166	1
all_levels[51]	10	1			T131	1		T127	1		T167	1
all_levels[52]	26	1			T17	1		T69	1		T160	1
all_levels[53]	14	1			T139	2		T168	1		T156	1
all_levels[54]	29	1			T5	1		T120	4		T134	2
all_levels[55]	7	1			T169	1		T170	1		T171	1
all_levels[56]	9	1			T9	1		T172	1		T173	1
all_levels[57]	10	1			T14	1		T15	1		T41	2
all_levels[58]	7	1			T174	1		T175	2		T176	1
all_levels[59]	7	1			T15	1		T177	1		T178	1
all_levels[60]	10	1			T6	2		T121	1		T179	1
all_levels[61]	5	1			T180	2		T181	2		T103	1
all_levels[62]	7	1			T17	1		T172	1		T182	1
all_levels[63]	9	1			T14	1		T142	1		T39	1
all_levels[64]	111	1			T12	1		T14	2		T15	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31755966

1

T2

640801

T5

9

T6

4

auto[1]

4444

1

T4

33

T5

4

T6

6

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	12	118	90.77	12

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[39]]	[auto[1]]	0	1	1
[all_levels[44] , all_levels[45] , all_levels[46] , all_levels[47]]	[auto[1]]	--	--	4
[all_levels[51]]	[auto[1]]	0	1	1
[all_levels[55] , all_levels[56] , all_levels[57] , all_levels[58]]	[auto[1]]	--	--	4
[all_levels[62] , all_levels[63]]	[auto[1]]	--	--	2

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	31561871	1			T2	640639		T5	8		T6	2
all_levels[0]	auto[1]	3996	1			T4	33		T5	4		T6	2
all_levels[1]	auto[0]	186203	1			T2	162		T9	67		T16	25
all_levels[1]	auto[1]	66	1			T72	1		T146	1		T183	2
all_levels[2]	auto[0]	2277	1			T6	1		T9	26		T43	1
all_levels[2]	auto[1]	27	1			T6	3		T50	1		T69	1
all_levels[3]	auto[0]	937	1			T9	11		T16	1		T45	2
all_levels[3]	auto[1]	20	1			T52	5		T184	1		T185	1
all_levels[4]	auto[0]	665	1			T9	9		T16	6		T45	2
all_levels[4]	auto[1]	15	1			T48	1		T186	3		T187	1
all_levels[5]	auto[0]	515	1			T9	12		T131	3		T119	2
all_levels[5]	auto[1]	29	1			T188	1		T169	1		T152	2
all_levels[6]	auto[0]	378	1			T9	3		T120	1		T132	3
all_levels[6]	auto[1]	17	1			T52	1		T40	1		T189	1
all_levels[7]	auto[0]	310	1			T9	1		T45	1		T120	2
all_levels[7]	auto[1]	13	1			T188	1		T190	2		T116	1
all_levels[8]	auto[0]	250	1			T119	1		T17	1		T49	2
all_levels[8]	auto[1]	8	1			T191	4		T192	1		T193	2
all_levels[9]	auto[0]	240	1			T16	2		T45	1		T131	1
all_levels[9]	auto[1]	15	1			T166	1		T194	1		T195	3
all_levels[10]	auto[0]	192	1			T16	2		T119	2		T132	1
all_levels[10]	auto[1]	11	1			T108	2		T129	2		T162	1
all_levels[11]	auto[0]	171	1			T21	1		T132	3		T20	1
all_levels[11]	auto[1]	8	1			T158	1		T196	2		T197	2
all_levels[12]	auto[0]	158	1			T21	1		T13	1		T49	1
all_levels[12]	auto[1]	8	1			T13	2		T198	1		T40	1
all_levels[13]	auto[0]	134	1			T45	1		T132	1		T50	1
all_levels[13]	auto[1]	10	1			T165	2		T199	1		T200	1
all_levels[14]	auto[0]	113	1			T120	1		T132	1		T15	1
all_levels[14]	auto[1]	5	1			T120	1		T108	1		T201	2
all_levels[15]	auto[0]	115	1			T121	1		T52	1		T133	1
all_levels[15]	auto[1]	4	1			T184	1		T190	2		T202	1
all_levels[16]	auto[0]	102	1			T45	1		T120	1		T20	1
all_levels[16]	auto[1]	11	1			T41	2		T185	1		T157	2
all_levels[17]	auto[0]	94	1			T121	1		T69	1		T134	1
all_levels[17]	auto[1]	14	1			T121	1		T168	1		T203	2
all_levels[18]	auto[0]	91	1			T21	2		T20	1		T15	1
all_levels[18]	auto[1]	12	1			T186	3		T108	2		T204	1
all_levels[19]	auto[0]	83	1			T43	1		T45	1		T14	1
all_levels[19]	auto[1]	13	1			T45	1		T205	2		T177	2
all_levels[20]	auto[0]	59	1			T135	1		T20	2		T15	1
all_levels[20]	auto[1]	8	1			T135	1		T206	1		T207	1
all_levels[21]	auto[0]	70	1			T9	1		T122	1		T136	1
all_levels[21]	auto[1]	3	1			T136	2		T129	1		-	-
all_levels[22]	auto[0]	54	1			T9	1		T137	1		T138	1
all_levels[22]	auto[1]	5	1			T137	1		T208	1		T197	2
all_levels[23]	auto[0]	52	1			T9	1		T36	1		T132	1
all_levels[23]	auto[1]	2	1			T209	2		-	-		-	-
all_levels[24]	auto[0]	47	1			T139	1		T37	1		T140	1
all_levels[24]	auto[1]	1	1			T210	1		-	-		-	-
all_levels[25]	auto[0]	50	1			T131	1		T70	1		T141	1
all_levels[25]	auto[1]	3	1			T211	1		T212	1		T213	1
all_levels[26]	auto[0]	43	1			T132	1		T134	1		T141	1
all_levels[26]	auto[1]	7	1			T185	1		T214	1		T215	1
all_levels[27]	auto[0]	31	1			T16	1		T37	1		T26	1
all_levels[27]	auto[1]	3	1			T216	2		T217	1		-	-
all_levels[28]	auto[0]	36	1			T13	1		T140	1		T142	1
all_levels[28]	auto[1]	3	1			T218	1		T219	1		T220	1
all_levels[29]	auto[0]	30	1			T131	1		T132	2		T134	1
all_levels[29]	auto[1]	3	1			T113	1		T221	1		T214	1
all_levels[30]	auto[0]	40	1			T50	2		T15	2		T70	1
all_levels[30]	auto[1]	1	1			T222	1		-	-		-	-
all_levels[31]	auto[0]	18	1			T143	1		T144	1		T145	1
all_levels[31]	auto[1]	3	1			T144	2		T223	1		-	-
all_levels[32]	auto[0]	25	1			T15	1		T146	3		T143	1
all_levels[32]	auto[1]	5	1			T146	1		T224	1		T225	2
all_levels[33]	auto[0]	21	1			T131	1		T54	2		T128	1
all_levels[33]	auto[1]	2	1			T157	1		T226	1		-	-
all_levels[34]	auto[0]	21	1			T131	1		T121	1		T26	1
all_levels[34]	auto[1]	4	1			T227	1		T228	3		-	-
all_levels[35]	auto[0]	18	1			T134	2		T141	1		T147	1
all_levels[35]	auto[1]	4	1			T147	1		T229	2		T219	1
all_levels[36]	auto[0]	27	1			T131	1		T50	1		T128	1
all_levels[36]	auto[1]	7	1			T230	1		T193	1		T231	1
all_levels[37]	auto[0]	27	1			T131	2		T15	1		T134	1
all_levels[37]	auto[1]	6	1			T169	1		T127	1		T232	2
all_levels[38]	auto[0]	21	1			T54	1		T148	1		T149	1
all_levels[38]	auto[1]	1	1			T233	1		-	-		-	-
all_levels[39]	auto[0]	20	1			T17	1		T54	1		T133	1
all_levels[40]	auto[0]	19	1			T150	1		T151	1		T152	1
all_levels[40]	auto[1]	4	1			T152	1		T180	2		T234	1
all_levels[41]	auto[0]	10	1			T21	1		T54	1		T125	1
all_levels[41]	auto[1]	2	1			T235	1		T236	1		-	-
all_levels[42]	auto[0]	19	1			T54	1		T15	1		T108	1
all_levels[42]	auto[1]	3	1			T54	1		T108	1		T237	1
all_levels[43]	auto[0]	16	1			T131	1		T134	1		T153	1
all_levels[43]	auto[1]	1	1			T176	1		-	-		-	-
all_levels[44]	auto[0]	14	1			T15	2		T154	1		T155	1
all_levels[45]	auto[0]	13	1			T69	1		T156	1		T157	1
all_levels[46]	auto[0]	15	1			T121	1		T158	1		T159	1
all_levels[47]	auto[0]	7	1			T21	1		T142	1		T160	1
all_levels[48]	auto[0]	13	1			T161	1		T162	1		T163	1
all_levels[48]	auto[1]	3	1			T218	3		-	-		-	-
all_levels[49]	auto[0]	13	1			T149	1		T164	2		T165	1
all_levels[49]	auto[1]	2	1			T165	2		-	-		-	-
all_levels[50]	auto[0]	9	1			T121	1		T126	1		T166	1
all_levels[50]	auto[1]	4	1			T236	1		T238	3		-	-
all_levels[51]	auto[0]	10	1			T131	1		T127	1		T167	1
all_levels[52]	auto[0]	17	1			T17	1		T69	1		T160	1
all_levels[52]	auto[1]	9	1			T239	1		T240	4		T241	1
all_levels[53]	auto[0]	13	1			T139	1		T168	1		T156	1
all_levels[53]	auto[1]	1	1			T139	1		-	-		-	-
all_levels[54]	auto[0]	16	1			T5	1		T120	1		T134	1
all_levels[54]	auto[1]	13	1			T120	3		T134	1		T234	5
all_levels[55]	auto[0]	7	1			T169	1		T170	1		T171	1
all_levels[56]	auto[0]	9	1			T9	1		T172	1		T173	1
all_levels[57]	auto[0]	10	1			T14	1		T15	1		T41	2
all_levels[58]	auto[0]	7	1			T174	1		T175	2		T176	1
all_levels[59]	auto[0]	6	1			T15	1		T177	1		T178	1
all_levels[59]	auto[1]	1	1			T242	1		-	-		-	-
all_levels[60]	auto[0]	8	1			T6	1		T121	1		T179	1
all_levels[60]	auto[1]	2	1			T6	1		T243	1		-	-
all_levels[61]	auto[0]	3	1			T180	1		T181	1		T103	1
all_levels[61]	auto[1]	2	1			T180	1		T181	1		-	-
all_levels[62]	auto[0]	7	1			T17	1		T172	1		T182	1
all_levels[63]	auto[0]	9	1			T14	1		T142	1		T39	1
all_levels[64]	auto[0]	87	1			T12	1		T14	2		T15	2
all_levels[64]	auto[1]	24	1			T244	3		T245	1		T246	1