Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
8 |
1 |
7 |
87.50 |
Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_watermark_lvl |
8 |
1 |
7 |
87.50 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_watermark_lvl
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
1 |
7 |
87.50 |
User Defined Bins for cp_watermark_lvl
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
all_levels[7] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_levels[0] |
1343 |
1 |
|
|
T2 |
13 |
|
T16 |
5 |
|
T119 |
12 |
all_levels[1] |
641 |
1 |
|
|
T120 |
6 |
|
T49 |
3 |
|
T52 |
27 |
all_levels[2] |
449 |
1 |
|
|
T20 |
3 |
|
T50 |
1 |
|
T52 |
3 |
all_levels[3] |
361 |
1 |
|
|
T36 |
3 |
|
T121 |
2 |
|
T122 |
3 |
all_levels[4] |
219 |
1 |
|
|
T123 |
2 |
|
T124 |
4 |
|
T125 |
2 |
all_levels[5] |
98 |
1 |
|
|
T24 |
4 |
|
T26 |
6 |
|
T126 |
2 |
all_levels[6] |
57 |
1 |
|
|
T26 |
6 |
|
T117 |
3 |
|
T127 |
3 |
0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |