Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	111738	1			T1	2		T2	1503		T3	2
all_pins[1]	111738	1			T1	2		T2	1503		T3	2
all_pins[2]	111738	1			T1	2		T2	1503		T3	2
all_pins[3]	111738	1			T1	2		T2	1503		T3	2
all_pins[4]	111738	1			T1	2		T2	1503		T3	2
all_pins[5]	111738	1			T1	2		T2	1503		T3	2
all_pins[6]	111738	1			T1	2		T2	1503		T3	2
all_pins[7]	111738	1			T1	2		T2	1503		T3	2
all_pins[8]	111738	1			T1	2		T2	1503		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	966478	1			T1	18		T2	13243		T3	18
values[0x1]	39164	1			T2	284		T4	69		T5	3
transitions[0x0=>0x1]	30467	1			T2	179		T4	48		T5	3
transitions[0x1=>0x0]	30200	1			T2	179		T4	48		T5	2

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	92528	1			T1	2		T2	1342		T3	2
all_pins[0]	values[0x1]	19210	1			T2	161		T4	21		T5	3
all_pins[0]	transitions[0x0=>0x1]	18712	1			T2	161		T4	21		T5	3
all_pins[0]	transitions[0x1=>0x0]	1192	1			T2	13		T16	1		T36	3
all_pins[1]	values[0x0]	110048	1			T1	2		T2	1490		T3	2
all_pins[1]	values[0x1]	1690	1			T2	13		T16	2		T36	3
all_pins[1]	transitions[0x0=>0x1]	1596	1			T2	13		T16	2		T36	3
all_pins[1]	transitions[0x1=>0x0]	2094	1			T2	4		T6	4		T9	3
all_pins[2]	values[0x0]	109550	1			T1	2		T2	1499		T3	2
all_pins[2]	values[0x1]	2188	1			T2	4		T6	4		T9	3
all_pins[2]	transitions[0x0=>0x1]	2126	1			T2	4		T6	4		T9	3
all_pins[2]	transitions[0x1=>0x0]	190	1			T16	4		T13	1		T247	1
all_pins[3]	values[0x0]	111486	1			T1	2		T2	1503		T3	2
all_pins[3]	values[0x1]	252	1			T16	4		T13	1		T15	1
all_pins[3]	transitions[0x0=>0x1]	209	1			T16	1		T13	1		T15	1
all_pins[3]	transitions[0x1=>0x0]	312	1			T16	5		T17	2		T20	1
all_pins[4]	values[0x0]	111383	1			T1	2		T2	1503		T3	2
all_pins[4]	values[0x1]	355	1			T16	8		T17	2		T20	1
all_pins[4]	transitions[0x0=>0x1]	293	1			T16	7		T17	2		T20	1
all_pins[4]	transitions[0x1=>0x0]	140	1			T16	2		T17	2		T37	2
all_pins[5]	values[0x0]	111536	1			T1	2		T2	1503		T3	2
all_pins[5]	values[0x1]	202	1			T16	3		T17	2		T24	2
all_pins[5]	transitions[0x0=>0x1]	136	1			T16	3		T17	1		T24	2
all_pins[5]	transitions[0x1=>0x0]	638	1			T9	2		T16	4		T36	7
all_pins[6]	values[0x0]	111034	1			T1	2		T2	1503		T3	2
all_pins[6]	values[0x1]	704	1			T9	2		T16	4		T36	7
all_pins[6]	transitions[0x0=>0x1]	639	1			T9	2		T16	2		T36	7
all_pins[6]	transitions[0x1=>0x0]	269	1			T16	4		T21	1		T17	4
all_pins[7]	values[0x0]	111404	1			T1	2		T2	1503		T3	2
all_pins[7]	values[0x1]	334	1			T16	6		T21	1		T17	5
all_pins[7]	transitions[0x0=>0x1]	213	1			T16	3		T17	4		T15	3
all_pins[7]	transitions[0x1=>0x0]	14108	1			T2	106		T4	48		T6	5
all_pins[8]	values[0x0]	97509	1			T1	2		T2	1397		T3	2
all_pins[8]	values[0x1]	14229	1			T2	106		T4	48		T6	5
all_pins[8]	transitions[0x0=>0x1]	6543	1			T2	1		T4	27		T6	5
all_pins[8]	transitions[0x1=>0x0]	11257	1			T2	56		T5	2		T9	1