Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	6813949	1			T2	331225		T4	27		T5	8
all_levels[1]	1745806	1			T2	2926		T16	13387		T21	17329
all_levels[2]	678770	1			T2	2931		T5	2		T9	3
all_levels[3]	476701	1			T2	2935		T9	4		T16	958
all_levels[4]	397466	1			T2	2897		T9	2		T16	1114
all_levels[5]	544278	1			T2	2929		T9	8		T16	1250
all_levels[6]	301273	1			T2	2889		T9	4		T16	865
all_levels[7]	355343	1			T2	2917		T9	10		T16	1147
all_levels[8]	349592	1			T2	2919		T9	8		T16	919
all_levels[9]	505435	1			T2	2909		T9	2		T16	1069
all_levels[10]	317693	1			T2	2924		T9	8		T16	1033
all_levels[11]	490019	1			T2	2861		T9	11		T16	1245
all_levels[12]	265182	1			T2	1145		T9	3		T16	1258
all_levels[13]	311258	1			T2	1148		T9	4		T16	866
all_levels[14]	433093	1			T2	1147		T6	4		T9	4
all_levels[15]	632810	1			T2	1138		T9	8		T16	1238
all_levels[16]	324510	1			T2	1148		T9	6		T16	973
all_levels[17]	631596	1			T2	1144		T9	1		T16	1105
all_levels[18]	392760	1			T2	1146		T9	3		T16	1130
all_levels[19]	240318	1			T2	1136		T9	3		T16	713
all_levels[20]	238611	1			T2	1138		T9	2		T16	1242
all_levels[21]	438976	1			T2	1148		T9	1		T16	856
all_levels[22]	240241	1			T2	1140		T6	4		T9	2
all_levels[23]	297754	1			T2	1148		T9	6		T16	1100
all_levels[24]	241010	1			T2	1146		T9	3		T16	1026
all_levels[25]	293346	1			T2	1148		T5	5		T9	1
all_levels[26]	248770	1			T2	1145		T9	2		T16	920
all_levels[27]	221362	1			T2	1137		T16	1227		T21	1296
all_levels[28]	297513	1			T2	1136		T9	3		T16	1244
all_levels[29]	349231	1			T2	1136		T9	5		T16	973
all_levels[30]	427465	1			T2	1137		T9	7		T16	1043
all_levels[31]	627197	1			T2	1176		T9	10		T16	2108
all_levels[32]	11630787	1			T2	254653		T9	164		T16	15019

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31755966

1

T2

640801

T5

9

T6

4

auto[1]

4149

1

T2

1

T4

27

T5

6

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	6811595	1			T2	331225		T5	5		T6	1
all_levels[0]	auto[1]	2354	1			T4	27		T5	3		T6	3
all_levels[1]	auto[0]	1745524	1			T2	2926		T16	13387		T21	17329
all_levels[1]	auto[1]	282	1			T57	2		T98	2		T14	1
all_levels[2]	auto[0]	678731	1			T2	2931		T5	2		T9	3
all_levels[2]	auto[1]	39	1			T29	1		T69	1		T41	1
all_levels[3]	auto[0]	476535	1			T2	2935		T9	4		T16	958
all_levels[3]	auto[1]	166	1			T264	8		T72	3		T282	15
all_levels[4]	auto[0]	397427	1			T2	2897		T9	2		T16	1114
all_levels[4]	auto[1]	39	1			T184	1		T108	2		T204	5
all_levels[5]	auto[0]	544251	1			T2	2929		T9	8		T16	1250
all_levels[5]	auto[1]	27	1			T54	1		T133	1		T266	2
all_levels[6]	auto[0]	301242	1			T2	2889		T9	4		T16	865
all_levels[6]	auto[1]	31	1			T198	1		T149	1		T278	4
all_levels[7]	auto[0]	355217	1			T2	2917		T9	10		T16	1147
all_levels[7]	auto[1]	126	1			T264	1		T24	1		T73	1
all_levels[8]	auto[0]	349563	1			T2	2919		T9	8		T16	919
all_levels[8]	auto[1]	29	1			T135	1		T137	2		T149	1
all_levels[9]	auto[0]	505412	1			T2	2909		T9	2		T16	1069
all_levels[9]	auto[1]	23	1			T49	1		T260	1		T291	1
all_levels[10]	auto[0]	317664	1			T2	2924		T9	8		T16	1033
all_levels[10]	auto[1]	29	1			T136	1		T244	3		T113	1
all_levels[11]	auto[0]	489996	1			T2	2861		T9	11		T16	1245
all_levels[11]	auto[1]	23	1			T40	1		T166	1		T165	1
all_levels[12]	auto[0]	265158	1			T2	1145		T9	3		T16	1258
all_levels[12]	auto[1]	24	1			T121	1		T139	3		T26	1
all_levels[13]	auto[0]	311229	1			T2	1148		T9	4		T16	866
all_levels[13]	auto[1]	29	1			T13	3		T48	1		T168	1
all_levels[14]	auto[0]	433060	1			T2	1147		T6	1		T9	4
all_levels[14]	auto[1]	33	1			T6	3		T266	4		T320	2
all_levels[15]	auto[0]	632739	1			T2	1138		T9	8		T16	1238
all_levels[15]	auto[1]	71	1			T266	1		T147	1		T318	1
all_levels[16]	auto[0]	324487	1			T2	1148		T9	6		T16	973
all_levels[16]	auto[1]	23	1			T168	1		T203	1		T189	2
all_levels[17]	auto[0]	631582	1			T2	1144		T9	1		T16	1105
all_levels[17]	auto[1]	14	1			T321	1		T322	1		T192	1
all_levels[18]	auto[0]	392737	1			T2	1146		T9	3		T16	1130
all_levels[18]	auto[1]	23	1			T15	1		T139	1		T198	1
all_levels[19]	auto[0]	240295	1			T2	1136		T9	3		T16	713
all_levels[19]	auto[1]	23	1			T190	2		T278	5		T323	2
all_levels[20]	auto[0]	238594	1			T2	1138		T9	2		T16	1242
all_levels[20]	auto[1]	17	1			T153	1		T142	2		T299	1
all_levels[21]	auto[0]	438963	1			T2	1148		T9	1		T16	856
all_levels[21]	auto[1]	13	1			T120	3		T199	1		T324	2
all_levels[22]	auto[0]	240217	1			T2	1140		T6	2		T9	2
all_levels[22]	auto[1]	24	1			T6	2		T36	1		T188	1
all_levels[23]	auto[0]	297735	1			T2	1148		T9	6		T16	1100
all_levels[23]	auto[1]	19	1			T48	2		T153	1		T111	1
all_levels[24]	auto[0]	240992	1			T2	1146		T9	3		T16	1026
all_levels[24]	auto[1]	18	1			T121	1		T325	1		T324	2
all_levels[25]	auto[0]	293325	1			T2	1148		T5	2		T9	1
all_levels[25]	auto[1]	21	1			T5	3		T260	3		T186	2
all_levels[26]	auto[0]	248743	1			T2	1145		T9	2		T16	920
all_levels[26]	auto[1]	27	1			T50	1		T148	1		T263	1
all_levels[27]	auto[0]	221346	1			T2	1137		T16	1227		T21	1296
all_levels[27]	auto[1]	16	1			T13	2		T245	2		T151	1
all_levels[28]	auto[0]	297499	1			T2	1136		T9	3		T16	1244
all_levels[28]	auto[1]	14	1			T153	1		T246	1		T326	2
all_levels[29]	auto[0]	349209	1			T2	1136		T9	5		T16	973
all_levels[29]	auto[1]	22	1			T121	2		T190	2		T299	3
all_levels[30]	auto[0]	427433	1			T2	1137		T9	7		T16	1043
all_levels[30]	auto[1]	32	1			T139	1		T37	1		T41	1
all_levels[31]	auto[0]	627177	1			T2	1176		T9	10		T16	2108
all_levels[31]	auto[1]	20	1			T73	2		T146	1		T187	2
all_levels[32]	auto[0]	11630289	1			T2	254652		T9	163		T16	15019
all_levels[32]	auto[1]	498	1			T2	1		T9	1		T21	1