Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	623	1			T16	14		T17	7		T20	4
all_values[1]	623	1			T16	14		T17	7		T20	4
all_values[2]	623	1			T16	14		T17	7		T20	4
all_values[3]	623	1			T16	14		T17	7		T20	4
all_values[4]	623	1			T16	14		T17	7		T20	4
all_values[5]	623	1			T16	14		T17	7		T20	4
all_values[6]	623	1			T16	14		T17	7		T20	4
all_values[7]	623	1			T16	14		T17	7		T20	4
all_values[8]	623	1			T16	14		T17	7		T20	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2958

1

T16

67

T17

32

T20

22

auto[1]

2649

1

T16

59

T17

31

T20

14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1870

1

T16

39

T17

18

T20

14

auto[1]

3737

1

T16

87

T17

45

T20

22

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3381

1

T16

72

T17

31

T20

20

auto[1]

2226

1

T16

54

T17

32

T20

16

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	205	1			T16	2		T17	2		T37	2
all_values[0]	auto[0]	auto[1]	auto[1]	178	1			T16	4		T17	1		T20	3
all_values[0]	auto[1]	auto[0]	auto[1]	138	1			T16	3		T17	2		T20	1
all_values[0]	auto[1]	auto[1]	auto[1]	102	1			T16	5		T17	2		T37	1
all_values[1]	auto[0]	auto[0]	auto[0]	187	1			T16	8		T17	2		T20	1
all_values[1]	auto[0]	auto[1]	auto[0]	191	1			T16	1		T17	2		T37	3
all_values[1]	auto[1]	auto[0]	auto[1]	137	1			T16	2		T17	1		T20	1
all_values[1]	auto[1]	auto[1]	auto[1]	108	1			T16	3		T17	2		T20	2
all_values[2]	auto[0]	auto[0]	auto[0]	146	1			T16	8		T20	2		T37	2
all_values[2]	auto[0]	auto[0]	auto[1]	58	1			T16	1		T37	1		T128	1
all_values[2]	auto[0]	auto[1]	auto[0]	106	1			T16	3		T20	1		T128	2
all_values[2]	auto[0]	auto[1]	auto[1]	74	1			T17	1		T37	1		T41	3
all_values[2]	auto[1]	auto[0]	auto[1]	114	1			T16	2		T17	5		T37	1
all_values[2]	auto[1]	auto[1]	auto[1]	125	1			T17	1		T20	1		T37	2
all_values[3]	auto[0]	auto[0]	auto[0]	160	1			T16	1		T17	2		T20	2
all_values[3]	auto[0]	auto[0]	auto[1]	57	1			T16	2		T17	1		T128	1
all_values[3]	auto[0]	auto[1]	auto[0]	98	1			T16	2		T17	3		T20	1
all_values[3]	auto[0]	auto[1]	auto[1]	59	1			T41	5		T108	1		T117	2
all_values[3]	auto[1]	auto[0]	auto[1]	139	1			T16	4		T20	1		T128	1
all_values[3]	auto[1]	auto[1]	auto[1]	110	1			T16	5		T17	1		T37	4
all_values[4]	auto[0]	auto[0]	auto[0]	139	1			T16	2		T17	1		T37	2
all_values[4]	auto[0]	auto[0]	auto[1]	45	1			T37	1		T41	4		T129	1
all_values[4]	auto[0]	auto[1]	auto[0]	130	1			T16	1		T17	1		T20	1
all_values[4]	auto[0]	auto[1]	auto[1]	65	1			T16	6		T17	1		T38	3
all_values[4]	auto[1]	auto[0]	auto[1]	130	1			T16	2		T17	2		T20	1
all_values[4]	auto[1]	auto[1]	auto[1]	114	1			T16	3		T17	2		T20	2
all_values[5]	auto[0]	auto[0]	auto[0]	133	1			T16	2		T17	1		T20	1
all_values[5]	auto[0]	auto[0]	auto[1]	59	1			T16	2		T20	1		T39	1
all_values[5]	auto[0]	auto[1]	auto[0]	97	1			T16	1		T17	3		T37	1
all_values[5]	auto[0]	auto[1]	auto[1]	75	1			T16	1		T17	1		T37	1
all_values[5]	auto[1]	auto[0]	auto[1]	141	1			T16	6		T17	1		T20	2
all_values[5]	auto[1]	auto[1]	auto[1]	118	1			T16	2		T17	1		T37	1
all_values[6]	auto[0]	auto[0]	auto[0]	121	1			T16	4		T17	1		T20	1
all_values[6]	auto[0]	auto[0]	auto[1]	70	1			T17	1		T20	1		T37	1
all_values[6]	auto[0]	auto[1]	auto[0]	107	1			T16	2		T37	2		T128	1
all_values[6]	auto[0]	auto[1]	auto[1]	72	1			T16	3		T17	2		T38	2
all_values[6]	auto[1]	auto[0]	auto[1]	114	1			T16	1		T20	1		T37	2
all_values[6]	auto[1]	auto[1]	auto[1]	139	1			T16	4		T17	3		T20	1
all_values[7]	auto[0]	auto[0]	auto[0]	153	1			T16	1		T17	1		T20	4
all_values[7]	auto[0]	auto[0]	auto[1]	56	1			T16	2		T17	1		T37	2
all_values[7]	auto[0]	auto[1]	auto[0]	102	1			T16	3		T17	1		T128	1
all_values[7]	auto[0]	auto[1]	auto[1]	68	1			T16	2		T38	1		T41	2
all_values[7]	auto[1]	auto[0]	auto[1]	115	1			T16	2		T17	3		T37	2
all_values[7]	auto[1]	auto[1]	auto[1]	129	1			T16	4		T17	1		T37	2
all_values[8]	auto[0]	auto[0]	auto[1]	191	1			T16	5		T17	1		T20	1
all_values[8]	auto[0]	auto[1]	auto[1]	179	1			T16	3		T17	1		T128	2
all_values[8]	auto[1]	auto[0]	auto[1]	150	1			T16	5		T17	4		T20	1
all_values[8]	auto[1]	auto[1]	auto[1]	103	1			T16	1		T17	1		T20	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal